Silicon carbide semiconductor equipment

Abstract

Compared to conventional methods that simply provide a JTE region, the area can be reduced, and the active area within the silicon carbide semiconductor device can be increased. [Solution] The silicon carbide semiconductor device 100 includes a source region 40 provided in a well region 30, a first termination region 50 provided outside the source region 40 and having a high-concentration second conductivity region 51 with a higher impurity concentration than the well region 30, a gate metal 140 provided above the first termination region 50, and a source metal 130 provided above the source region 40 and the source region 40 side end of the first termination region 50. The high-concentration second conductivity region 51 extends below the area between the source contact region 130a of the source metal 130 and the gate contact region 140a of the gate metal 140.

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide semiconductor device having a JTE region. [Background technology]

[0002] Silicon carbide semiconductor devices, which are power semiconductor devices, have been known for some time. In silicon carbide semiconductor devices such as SiC-MOSFETs, a JTE (Junction Termination Extension) region may be provided. For example, Patent Document 1 (Japanese Patent Application Publication No. 2023-043833,

[0038] ) shows that the termination region has an annular structure that extends along each side of a rectangular semiconductor chip, and that a JTE region, which is a p-type semiconductor region formed on the upper surface of the drift layer, is provided in this termination region.

[0003] When such a JTE region is established, its area becomes larger, which reduces the active area within the silicon carbide semiconductor device. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2023-043833 [Overview of the project] [Problems that the invention aims to solve]

[0005] The present invention provides a silicon carbide semiconductor device that can reduce the area compared to the conventional method of simply providing a JTE region, thereby increasing the active area within the silicon carbide semiconductor device. [Means for solving the problem]

[0006] [Concept 1] The silicon carbide semiconductor device according to the present invention is a silicon carbide layer of a first conductivity type; a well region of a second conductivity type provided in said silicon carbide layer; a source region of a first conductivity type provided in said well region; a first termination region provided outward of said source region and having a high-concentration second conductivity type region with an impurity concentration higher than that of said well region; a gate metal provided above said first termination region; a source metal provided above said source region and an end portion on the source region side of said first termination region; comprising: said high-concentration second conductivity type region may extend below between a source contact region of said source metal and a gate contact region of said gate metal.

[0007] [Concept 2] In the silicon carbide semiconductor device according to Concept 1, said first termination region may have a JTE region provided below said high-concentration second conductivity type region.

[0008] [Concept 3] In the silicon carbide semiconductor device according to Concept 2, said high-concentration second conductivity type region may have a depth of 60% or less of the depth of said first termination region.

[0009] [Concept 4] The silicon carbide semiconductor device according to any one of Concepts 1 to 3, comprising a second termination region provided outward of said first termination region, said second termination region may include a guard ring region.

[0010] [Concept 5] In the silicon carbide semiconductor device according to Concept 4, a width of said guard ring region may be 35 µm or less.

[0011] [Concept 6] The silicon carbide semiconductor device according to Concept 4 or 5, The guard ring region may also include a high-concentration first conductivity region with a higher impurity concentration than the silicon carbide layer, located outside the guard ring region.

[0012] [Concept 7] In a silicon carbide semiconductor device according to any one of concepts 1 to 6, A field oxide film is provided on the upper surface of the first terminal region. A polysilicon layer is provided on the upper surface of the field oxide film. The gate contact region may be formed by the contact between the polysilicon layer and the gate metal. [Effects of the Invention]

[0013] A first termination region is provided outside the source region, having a high-concentration second conductivity region with a higher impurity concentration than the well region, and a JTE region provided below the high-concentration second conductivity region. By adopting a configuration in which the high-concentration second conductivity region extends below the area between the source contact region of the source metal and the gate contact region of the gate metal, sufficient breakdown voltage can be achieved while reducing the area of ​​the termination region compared to the conventional configuration in which a JTE region is simply provided, thereby increasing the active area within the silicon carbide semiconductor device. [Brief explanation of the drawing]

[0014] [Figure 1] A side cross-sectional view of a silicon carbide semiconductor device according to the first embodiment of the present invention. [Figure 2] A side cross-sectional view of a silicon carbide semiconductor device according to a modified example of the first embodiment of the present invention. [Figure 3] A side cross-sectional view of a silicon carbide semiconductor device according to a second embodiment of the present invention. [Modes for carrying out the invention]

[0015] First Embodiment In this embodiment, "one side" refers to the upper side of Figure 1, and "the other side" refers to the lower side of Figure 1.

[0016] The silicon carbide semiconductor device 100 of this embodiment may consist of a MOSFET or the like. The silicon carbide semiconductor device 100 includes, for example, a first conductivity type silicon carbide substrate 10 which is n-type, a first conductivity type silicon carbide layer 20 provided on the upper surface of the silicon carbide substrate 10, a second conductivity type well region 30 which is, for example, p-type, provided on the silicon carbide layer 20, a first conductivity type source region 40 provided in the well region 30, and a first termination region 50 provided on the outer peripheral side (right side in Figure 1) of the source region 40. A gate metal 140 is provided above (on one side of) the first termination region 50, and a source metal 130 is provided above the source region 40 and the end of the first termination region 50 on the source region 40 side (the left end in Figure 1). The first termination region 50 may have a high-concentration second conductivity region 51 with a higher impurity concentration than the well region 30, and a JTE region 55 provided below (on the other side of) the high-concentration second conductivity region 51. However, it is not limited to this configuration, and the high-concentration second conductivity region 51 may be formed in the first termination region 50 so as to penetrate the JTE region 55. In this case, the first termination region 50 may have a high-concentration second conductivity region 51 with a higher impurity concentration than the well region 30, but may not have a JTE region 55 (see Figure 2).

[0017] The high-concentration second conductivity region 51 extends continuously below the source contact region 130a (source contact region 130 of the source metal 130) where the source metal 130 contacts the well region 30 via the contact metal 115, and the gate contact region 140a (gate contact region 140 of the gate metal 140) where the gate metal 140 contacts the polysilicon layer 120.

[0018] As shown in Figure 1, a drain metal 90 may be provided on the lower surface (or other surface, back surface) of the silicon carbide substrate 10.

[0019] The side where the source region 40 is provided is the active region (cell region), and the side where the JTE region 55 is provided is the termination region. The JTE region 55 side corresponds to the end side of a semiconductor device such as a chip. In Figure 1, a high-concentration second conductivity region 52 is provided to the left of the source region 40, but another source region 40 may be provided to the left adjacent to the high-concentration second conductivity region 52, and the active region may be formed in the left region not shown in Figure 1.

[0020] A gate electrode 180 is provided above the source region 40 via an interlayer insulating film 185. The gate electrode 180 and the gate metal 140 are electrically connected and may be at the same potential. The gate electrode 180 and the gate metal 140 may be made of polysilicon or the like. The gate electrode 180 and the polysilicon layer 120 may be made of the same polysilicon and may be formed at the same time in the manufacturing process.

[0021] In the vertical cross-sectional view shown in Figure 1, a low-concentration second conductivity type region 45 is provided between the source regions 40, and a first conductivity type region 25 is provided between the low-concentration second conductivity type regions 45.

[0022] Although Figure 1 shows a vertical cross-sectional view, when shown in a plan view, the terminal region is provided so as to surround the active region (cell region) (see Figure 1 of Patent Document 1). The same applies to the first conductivity type region 25, the low-concentration second conductivity type region 45, and the source region 40; when shown in a plan view, the low-concentration second conductivity type region 45 is provided so as to surround the first conductivity type region 25, and the source region 40 is provided so as to surround the low-concentration second conductivity type region 45.

[0023] In this embodiment, n-type is used as the first conductivity type and p-type as the second conductivity type in the explanation, but the invention is not limited to this, and p-type may be used as the first conductivity type and n-type as the second conductivity type.

[0024] In this embodiment, n - The impurity concentration is, for example, 0.5 to 2.0 × 10 16 cm-3 , and the impurity concentration of n is, for example, 2.0 to 3.0×10 16 cm -3 , and n + has an impurity concentration of, for example, 0.5 to 50.0×10 18 cm -3 , and n ++ has an impurity concentration of, for example, 1.0 to 50.0×10 19 cm -3 . p - has an impurity concentration of, for example, 0.5 to 50.0×10 17 cm -3 , and the impurity concentration of p is, for example, 2.0×10 17 to 1.0×10 19 cm -3 , and p ++ has an impurity concentration of, for example, 1.0 to 50.0×10 19 cm -3 .

[0025] Therefore, as an example, the impurity concentration of the source region 40 is 1.0 to 50.0×10 19 cm -3 , the impurity concentration of the silicon carbide layer 20 is 0.5 to 2.0×10 16 cm -3 , the impurity concentration of the silicon carbide substrate 10 is 0.5 to 50.0×10 18 cm -3 , and the impurity concentration of the first conductivity type region 25 is 2.0 to 3.0×10 16 cm -3 .

[0026] Further, as an example, the impurity concentration of the well region 30 is 2.0×10 17 to 1.0×10 19 cm -3 , and the high-concentration second conductivity type regions 51 and 52 have an impurity concentration of 1.0 to 50.0×10 19 cm -3 . The impurity concentration of the JTE region 55 and the low-concentration second conductivity type region 45 is 0.5 to 50.0×10 17 cm -3 .

[0027] In one aspect of this embodiment, a first termination region 50 is provided, having a high-concentration second conductivity region 51 and a JTE region 55 provided below the high-concentration second conductivity region 51. A gate metal 140 is provided above the first termination region 50, and a source metal 130 is provided above the source region 40 and the source region 40 side end of the first termination region 50. The high-concentration second conductivity region 51 extends continuously below the area between the source contact region 130a of the source metal 130 and the gate contact region 140a of the gate metal 140. By providing the high-concentration second conductivity region 51 directly below the wiring of the gate metal 140 in this way, the Hall current is able to escape from the high-concentration second conductivity region 51 on the active region (cell region) side, eliminating the need to provide a separate structure for extracting the source current. Furthermore, while achieving sufficient withstand voltage, the area can be reduced compared to the conventional method of simply providing a JTE region 55 with a low impurity concentration, thereby increasing the active area within the silicon carbide semiconductor device 100. In particular, by providing a JTE region 55 with a low impurity concentration below the high-concentration second conductivity region 51 with a high impurity concentration, high stability of the termination region breakdown voltage with respect to the impurity concentration of the JTE region 55 can be achieved.

[0028] The end of the high-concentration second conductivity region 51 on the source region 40 side is positioned below the source contact region 130a of the source metal 130, thereby enabling contact with the source metal 130. In this embodiment, the high-concentration second conductivity region 51, positioned below the source contact region 130a in this manner, is extended in the peripheral direction to extend at least below the gate contact region 140a.

[0029] The high-concentration second conductivity region 51 may be 60% or less in depth of the first termination region 50. By setting the depth of the high-concentration second conductivity region 51 with a high impurity concentration to 60% or less, and configuring the JTE region 55 with a low impurity concentration located below the high-concentration second conductivity region 51 to occupy 40% or more of the depth of the first termination region 50, it is possible to more reliably achieve high stability of the termination region breakdown voltage with respect to the impurity concentration of the JTE region 55. The upper limit of the depth of the high-concentration second conductivity region 51 may be 50% of the depth of the first termination region 50, or it may be further reduced to 40% of the depth of the first termination region 50. The high-concentration second conductivity region 51 may be 10% or more of the depth of the first termination region 50, or it may be 20% or more of the depth of the first termination region 50.

[0030] A second termination region 70 consisting of a second conductivity type may be provided outside the periphery of the first termination region 50 (on the end side of the semiconductor device, which is the right side in Figure 1). The second termination region 70 may include a guard ring region. Providing such a second termination region 70 consisting of a guard ring region, etc., is beneficial in that it can achieve a higher withstand voltage. In this embodiment, the second termination region 70 is provided within the JTE region 55. The second termination region 70 is, for example, p ++ It consists of, for example, 1.0 to 50.0 × 10⁻⁶ 19 cm -3 In the guard ring region, for example, 8 to 15 guard rings with a width of 0.5 to 2 μm may be provided. However, the width and number of guard rings are merely examples and are not limited to these.

[0031] In the embodiment shown in Figure 2, a guard ring region is provided in the second termination region 70, extending through the JTE region 55. As shown in Figure 2, in the generated silicon carbide semiconductor device, the JTE region 55 is not provided in the first termination region 50, but the JTE region 55 may be provided in the second termination region 70, which is located outward in the peripheral direction of the high-concentration second conductivity region 51 (towards the end of the semiconductor device, on the right side in Figure 1).

[0032] A contact metal 115 made of Ti or the like may be provided between the source metal 130 and the high-concentration second conductivity region 51, source region 40, etc., in the vertical direction. A barrier metal 110 made of TiN or the like may be provided on the upper surface (front surface) of the interlayer insulating film 160, etc. Annealing is necessary to make contact between the contact metal 115 and the semiconductor layer made of silicon carbide, but the annealing temperature for silicon carbide is high, around 1000 degrees. Because annealing is performed at such high temperatures, there is a possibility that the metal Ti or the like that constituting the contact metal 115 may reach the interlayer insulating film 160. In this regard, by providing a barrier metal 110, it is possible to prevent such metals Ti or the like from reaching the interlayer insulating film 160 and protect the interlayer insulating film 160.

[0033] The depth of the high-concentration second conductivity region 51 and the depth of the second termination region 70 may be approximately the same. By adopting this configuration, the high-concentration second conductivity region 51 and the second termination region 70 can be formed simultaneously, simplifying the manufacturing process. In this embodiment, "approximately the same depth" means that the difference between the depth D1 of the high-concentration second conductivity region 51 and the depth D2 of the second termination region 70 is 10% or less of the larger of the two depths, D1 and D2. If D1 > D2, then D1 × 10% ≥ D1 - D2.

[0034] By adopting the first termination region 50 of this embodiment, a sufficiently high pressure resistance can be achieved, and the width W of the guard ring region G The width can be reduced, for example, the width of the guard ring region (the width from the active region end of the guard ring located on the most active region side (far left in Figure 1) to the outermost peripheral end of the guard ring located on the far right in Figure 1) W G The width W of the guard ring region may be 35 μm or less. G Reducing this size is beneficial because it allows for a larger active area within the silicon carbide semiconductor device 100.

[0035] A high-concentration first conductivity type region 80 with a higher impurity concentration than the silicon carbide layer 20, which functions as a channel stopper, may be provided outside the periphery of the second termination region 70, which consists of a guard ring region, etc. (the end side of the semiconductor device, and the right side in Figure 1). The high-concentration first conductivity type region 80 may be, for example, n ++ It consists of, for example, 1.0 to 50.0 × 10⁻⁶ 19 cm -3 That is the case.

[0036] A field oxide film 60 may be provided on the upper surface of the first terminal region 50. A polysilicon layer 120 may be provided on the upper surface of the field oxide film 60. As described above, a gate contact region 140a may be formed by the contact between the polysilicon layer 120 and the gate metal 140.

[0037] Second Embodiment Next, a second embodiment of the present invention will be described.

[0038] In this embodiment, as shown in Figure 3, the depth of the high-concentration second conductivity region 51 and the depth of the second termination region 70 are not substantially the same, which is different from the first embodiment. More specifically, the depth of the second termination region 70 is greater than the depth of the high-concentration second conductivity region 51, and the depth of the second termination region 70 reaches the lower end of the JTE region 55. The other configurations are the same as in the first embodiment, and any configuration described in the first embodiment can be adopted. The same reference numerals are used to describe the components described in the first embodiment.

[0039] This embodiment can also obtain the same effects as the first embodiment. However, because the depth of the high-concentration second conductivity region 51 and the depth of the second termination region 70 are different, it is not possible to form the high-concentration second conductivity region 51 and the second termination region 70 simultaneously. For this reason, it is inferior to the first embodiment in this respect.

[0040] The descriptions of the embodiments and the disclosure of the drawings described above are merely examples for illustrating the invention described in the claims, and the invention described in the claims is not limited by the descriptions of the embodiments or the disclosure of the drawings described above. Furthermore, the description of the claims at the time of filing is merely an example, and the description of the claims can be modified as appropriate based on the description in the specification, drawings, etc. [Explanation of Symbols]

[0041] 20 Silicon Carbide Layer 30-well area 40 Source Area 50 1st termination area 51 High concentration second conductivity type region 55 JTE area 60 Field Oxide Film 70 Second termination area 80 High concentration first conductivity type region 100 Silicon Carbide Semiconductor Devices 120 Polysilicon layer 130 Source Metal 130a Source Contact Area 140 Gate Metal 140a Gate contact area

Claims

1. A first-type conductive silicon carbide layer, A second conductivity type well region provided in the silicon carbide layer, A first conductivity type source region provided in the well region, A first termination region is provided outside the source region and has a high-concentration second conductivity type region with a higher impurity concentration than the well region, A gate metal provided above the first termination region, A source metal provided above the source region and the source region side end of the first terminal region, Equipped with, The silicon carbide semiconductor device wherein the high-concentration second conductivity region extends below the area between the source contact region of the source metal and the gate contact region of the gate metal.

2. The silicon carbide semiconductor device according to claim 1, wherein the first termination region has a JTE region provided below the high-concentration second conductivity type region.

3. The silicon carbide semiconductor device according to claim 2, wherein the high-concentration second conductivity type region has a depth of 60% or less of the depth of the first termination region.

4. A second terminal region is provided outside the first terminal region, The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the second termination region includes a guard ring region.

5. The silicon carbide semiconductor device according to claim 4, wherein the width of the guard ring region is 35 μm or less.

6. The silicon carbide semiconductor device according to claim 4, further comprising a high-concentration first conductivity type region having a higher impurity concentration than the silicon carbide layer provided outside the guard ring region.

7. A field oxide film is provided on the upper surface of the first terminal region. A polysilicon layer is provided on the upper surface of the field oxide film. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the gate contact region is formed by contact between the polysilicon layer and the gate metal.

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