Memory system

Abstract

To provide a memory system with high performance in response to host access. [Solution] The memory system according to the embodiment includes a non-volatile memory containing a plurality of storage areas, each having a plurality of memory cells, and a controller electrically connected to the non-volatile memory. The controller is configured to receive a query command from a host at a first time step, which includes first information that can identify at least a first logical address, to determine whether or not the internal movement of the first data corresponding to the first logical address is scheduled to begin within one hour from the first time step, and if the internal movement of the first data is scheduled to begin within one hour from the first time step, to send second information to the host indicating the scheduled time for the internal movement of the first data to begin.

Description

[[Technical Field]]

[0001] Embodiments of the present invention relate to a memory system including a nonvolatile memory. [[Background Art]]

[0002] In recent years, memory systems including nonvolatile memories have been widely spread. As one of such memory systems, a solid-state drive (SSD) including a NAND flash memory is known. SSDs are used as storage devices for various hosts such as servers in data centers.

[0003] A host may recognize that data corresponding to a certain logical address is unnecessary. In this case, the host transmits a deallocation command related to the unnecessary data to the memory system. The deallocation command is also referred to as a trim command or an unmap command.

[0004] A memory system may move data stored in a certain storage location to another storage location. This movement is referred to as internal movement. The memory system performs internal movement independently of requests from the host. That is, the host does not grasp when internal movement occurs. Therefore, the host may transmit a deallocation command related to internally moved data to the memory system. In this case, the internal movement performed by the memory system before receiving the deallocation command becomes wasted. Wasted internal movement excessively increases the Write Amplification Factor (WAF). Further, if the timing of internal movement overlaps with the timing of operation in response to an I / O command from the host, the performance of the memory system decreases. [[Prior Art Literature]] [[Patent Literature]]

[0005] [[Patent Literature 1]] U.S. Patent Application Publication No. 2021 / 0216239 [Patent Document 2] U.S. Patent Application Publication No. 2019 / 0095123 [Patent Document 3] U.S. Patent Application Publication No. 2016 / 0246713 [Patent Document 4] U.S. Patent Application Publication No. 2016 / 0188459 [Patent Document 5] U.S. Patent Application Publication No. 2016 / 0313943 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] Embodiments of the present invention aim to provide a memory system with high performance in terms of access from a host. [Means for solving the problem]

[0007] The memory system according to the embodiment includes a non-volatile memory containing a plurality of storage areas, each having a plurality of memory cells, and a controller electrically connected to the non-volatile memory. The controller is configured to receive a query command from a host at a first time step, which includes first information that can identify at least a first logical address, to determine whether the internal movement of the first data corresponding to the first logical address is scheduled to begin within one hour from the first time step, and if the internal movement of the first data is scheduled to begin within one hour from the first time step, to send second information to the host indicating the scheduled time for the internal movement of the first data to begin. [Brief explanation of the drawing]

[0008] [Figure 1] A block diagram showing an example configuration of an information processing system including a memory system according to the embodiment. [Figure 2] A diagram illustrating an example of an L2P table used in the memory system according to this embodiment. [Figure 3] A diagram illustrating multiple namespaces managed in a memory system according to this embodiment. [Figure 4] A diagram showing an example configuration of a memory chip included in the memory system according to the embodiment. [Figure 5] A diagram showing an example of the superblock configuration in a memory system according to this embodiment. [Figure 6] A diagram illustrating an example of processing when a memory system according to this embodiment receives a setting command. [Figure 7] A diagram illustrating an example of a notification management table used in the memory system according to this embodiment. [Figure 8] A diagram illustrating an example of processing when a memory system according to this embodiment receives a write command. [Figure 9] A diagram illustrating an example of a non-volatile memory on which data has been written in a memory system according to the embodiment. [Figure 10] A diagram illustrating an example of a forced refresh management table used in the memory system according to this embodiment. [Figure 11] A diagram illustrating an example of processing when a memory system according to this embodiment receives a query command. [Figure 12] A diagram illustrating an example of a notification sent by a memory system according to this embodiment. [Figure 13] A diagram illustrating another example of a forced refresh management table used in the memory system according to this embodiment. [Figure 14] A diagram illustrating another example of a notification sent by the memory system according to this embodiment. [Figure 15] A diagram illustrating an example of the timing at which a host sends a deallocate command to a memory system according to an embodiment. [Figure 16] A diagram illustrating an example of the timing at which a host sends a deallocate command to a memory system related to a comparative example. [Figure 17] FIG. 1 is a diagram for explaining an example of processing when the memory system according to an embodiment receives a reservation command. [Figure 18] FIG. 4 is a diagram for explaining still another example of a forced refresh management table used in the memory system according to an embodiment. [Figure 19] FIG. 7 is a diagram for explaining still another example of a forced refresh management table used in the memory system according to an embodiment. [Figure 20] FIG. 10 is a flowchart for explaining an example of a forced refresh procedure executed in the memory system according to an embodiment. [Figure 21] FIG. 13 is a diagram for explaining an example of a forced refresh list used in the memory system according to an embodiment. DESCRIPTION OF EMBODIMENTS

[0009] Hereinafter, embodiments will be described with reference to the accompanying drawings. The following description exemplifies apparatuses and methods for embodying the technical idea of the embodiments, and the technical idea of the embodiments is not limited to the structure, shape, arrangement, material, or other aspects of constituent elements described below. Modifications that can be easily conceived by those skilled in the art are naturally included in the scope of the present disclosure. To make the description clearer, in the drawings, the size, thickness, planar dimension, shape, and the like of each element may be changed from actual elements and schematically illustrated. A plurality of drawings may include elements having different dimensional relationships and ratios from each other. In a plurality of drawings, corresponding elements are denoted by the same reference numerals, and overlapping descriptions may be omitted. Some elements may be given a plurality of names, but these names are merely examples, and do not preclude other names from being given to these elements. This does not preclude other names from being given to elements that are not given a plurality of names. Connection may include not only direct connection but also connection via other elements. Unless it is explicitly stated that the number of an element is plural, the element may be a single element or a plurality of elements.

[0010] The configuration of the memory system according to the embodiment will be described below with reference to the drawings. Figure 1 is a block diagram showing an example configuration of an information processing system 1 including the memory system 3 according to the embodiment.

[0011] The information processing system 1 includes a host (host device) 2 and a memory system 3.

[0012] Host 2 is an information processing device configured to control memory system 3. Examples of Host 2 include personal computers, server computers, mobile terminals, or in-vehicle devices.

[0013] Memory system 3 is a semiconductor storage device configured to write data to and read data from non-volatile memory 5. Memory system 3 can be implemented, for example, as an SD card, a universal flash storage (UFS) device, or a solid-state drive (SSD).

[0014] Communication between host 2 and memory system 3 is performed via bus 7. Bus 7 is, for example, PCI Express. TM (PCIe TM ) is a bus. A standard for the logical interface connecting host 2 and memory system 3 is, for example, NVM express. TM (NVMe TM The ) standard is used.

[0015] Host 2 sends data and input / output (I / O) commands to memory system 3 via bus 7. Memory system 3 sends data and responses to host 2 via bus 7. I / O commands are commands for writing data to or reading data from non-volatile memory 5. I / O commands are, for example, write commands or read commands.

[0016] A write command is a command that requests the memory system 3 to write user data (write data) to non-volatile memory 5. A write command includes information such as a namespace identifier, a starting logical address, the size of the write data, and a data pointer. The namespace identifier is an identifier that identifies the namespace to which the data is written. The starting logical address is the logical address of the beginning of the write destination within this namespace. The size is the size of the write data associated with this write command. The data pointer represents the location in memory 22 of host 2 where the write data is stored.

[0017] A logical address is an address used by host 2 to access memory system 3. For example, a logical block address (LBA) is used as a logical address. An LBA is a logical address used to refer to a unit of data called a sector. Possible sector sizes specified by an LBA are, for example, 512 bytes (B), 4 kilobytes (KiB), 8 KiB, or 16 KiB.

[0018] The size of the write data can be expressed, for example, by the number of LBAs (number of sectors).

[0019] A read command is a command that requests to read data from memory system 3. A read command includes information representing a namespace identifier, a starting logical address, the size of the data to be read, and a data pointer. The namespace identifier is an identifier that identifies the namespace to be read. The starting logical address is the starting logical address of the data to be read within this namespace. The size is the size of the data to be read requested by this read command. The data pointer represents the location in memory 22 of host 2 to which the read data should be transferred.

[0020] The size of read data is expressed, for example, by the number of LBAs (number of sectors).

[0021] Next, an example configuration of host 2 will be described. Host 2 includes a processor 21 and memory 22. The processor 21 and memory 22 are connected via a bus 20.

[0022] The processor 21 is, for example, a Central Processing Unit (CPU). The processor 21 executes software (host software) loaded into memory 22. The host software is loaded into memory 22 from memory system 3 or other storage devices connected to host 2. The host software includes an operating system, file system, device drivers, or application programs. The processor 21 can run multiple applications.

[0023] Memory 22 is, for example, volatile memory. Memory 22 is also called main memory, system memory, or host memory. Memory 22 is, for example, random access memory such as Dynamic Random Access Memory (DRAM). A portion of the memory area of ​​memory 22 is used as a data buffer. The data buffer stores write data to be written to memory system 3 by host 2, or read data transferred from memory system 3.

[0024] Next, an example configuration of memory system 3 will be described. Memory system 3 includes a controller 4, non-volatile memory 5, and volatile memory 6.

[0025] Controller 4 is a memory controller that controls the non-volatile memory 5. Controller 4 may be implemented by a circuit such as a system-on-a-chip (SoC). The functions of each part within Controller 4 are implemented by dedicated hardware circuits, a processor that runs a program (firmware), or a combination of these. Controller 4 is electrically connected to the non-volatile memory 5.

[0026] An example of non-volatile memory 5 is NAND flash memory. Non-volatile memory 5 includes one or more memory chips. Memory chips are also called, for example, flash dies or memory dies. Each memory chip includes a memory cell array. A memory cell array has multiple memory cells arranged in a matrix. Non-volatile memory 5 may be a two-dimensional memory or a three-dimensional memory.

[0027] An example of volatile memory 6 is DRAM. The storage area of ​​volatile memory 6 is used, for example, to store information for managing the memory system 3. In addition, a portion of the storage area of ​​volatile memory 6 may be used to temporarily store write data to be written to non-volatile memory 5, or read data read from non-volatile memory 5.

[0028] The controller 4 includes a host interface circuit (host I / F) 41, a CPU 42, static RAM (SRAM) 43, a direct memory access controller (DMAC) 44, an ECC circuit 45, a non-volatile memory interface circuit (non-volatile memory I / F) 46, and a volatile memory interface circuit (volatile memory I / F) 47. The host I / F 41, CPU 42, SRAM 43, DMAC 44, ECC circuit 45, non-volatile memory I / F 46, and volatile memory I / F 47 are interconnected via an internal bus 40.

[0029] Host I / F41 is configured to communicate with Host 2. Host I / F41 is, for example, a PCIe controller. Host I / F41 receives various commands from Host 2. These commands are, for example, NVMe commands defined in the NVMe standard.

[0030] The CPU 42 is a processor. The CPU 42 controls the host I / F 41, SRAM 43, DMAC 44, ECC circuit 45, non-volatile memory I / F 46, and volatile memory I / F 47. When the memory system 3 is started, the CPU 42 loads a control program (firmware) from the non-volatile memory 5 or a ROM (not shown) into the SRAM 43. The CPU 42 then performs various processes by executing the loaded firmware. This firmware may also be loaded into the volatile memory 6 instead of the SRAM 43. The CPU 42 can perform command processing to handle various commands from the host 2.

[0031] The CPU 42, for example, as the flash translation layer (FTL), manages the data stored in the non-volatile memory 5 and the blocks contained within the non-volatile memory 5. Managing the data stored in the non-volatile memory 5 includes, for example, managing mapping information. The CPU 42 manages the mapping information using a logical-to-physical address translation table (L2P table) 61. The mapping information represents the mapping between each logical address and each physical address in the non-volatile memory 5. A physical address is an address that represents the physical storage location within the non-volatile memory 5.

[0032] Figure 2 is a diagram illustrating an example of an L2P table 61. The L2P table 61 manages the mapping between each logical address and each physical address. The L2P table 61 manages the mapping, for example, on a sector-by-sector basis. A physical address mapped to a given logical address represents the physical storage location in the non-volatile memory 5 where the data for that logical address is written. The L2P table 61 may be loaded from the non-volatile memory 5 to the volatile memory 6 when the memory system 3 is powered on (boot-up).

[0033] Furthermore, CPU42 creates and manages multiple namespaces. Each of these namespaces is a set of logical addresses. Multiple namespaces are used to make a single memory system behave as if it were multiple memory systems. Each of these namespaces is used by host2 to access memory system 3. Each of these namespaces is identified by a namespace identifier.

[0034] The block management performed by CPU42 includes managing bad blocks contained in non-volatile memory5, wear leveling, and garbage collection.

[0035] Figure 3 is a diagram illustrating the multiple namespaces managed in memory system 3.

[0036] Figure 3 illustrates a case where Controller 4 manages Namespace 0, Namespace 1, and Namespace 2. Each namespace is identified by a Namespace Identifier (NSID). Each namespace contains a set of consecutive Logical Addresses (LBAs). The minimum value of an LBA in the logical address space corresponding to each namespace is 0. The size of each namespace can be arbitrarily set. The size of a given namespace is represented by the value obtained by multiplying the number of LBAs contained in that namespace by the data size per LBA. The data size per LBA can be set individually for each namespace. In the following, the value of an LBA being n may be denoted as LBAn, where n is a non-negative integer.

[0037] In the example shown in Figure 3, namespace 0 contains multiple consecutive LBAs from LBA0 to LBA(x-1). Namespace 1 contains multiple consecutive LBAs from LBA0 to LBA(y-1). Namespace 2 contains multiple consecutive LBAs from LBA0 to LBA(z-1).

[0038] Returning to Figure 1, SRAM 43 is volatile memory. Part of the memory area of ​​SRAM 43 is used as a work area for the CPU 42. Another part of the memory area of ​​SRAM 43 can be used as a data buffer to temporarily store data to be written to or read from non-volatile memory 5.

[0039] The DMAC44 is configured to perform direct memory access (DMA). The DMAC44 performs data transfer between the host 2's memory 22 and the SRAM 43 or volatile memory 6.

[0040] The ECC circuit 45 is configured to perform encoding or decoding. The ECC circuit 45 performs encoding when data is written to the non-volatile memory 5. During encoding, the ECC circuit 45 adds redundant code (parity) to the data written to the non-volatile memory 5. The redundant code is, for example, an error correction code (ECC). Also, when data is read from the non-volatile memory 5, the ECC circuit 45 performs decoding. During decoding, the ECC circuit 45 performs error correction on the data read from the non-volatile memory 5. When performing error correction, the ECC circuit 45 uses the ECC added to this data.

[0041] The non-volatile memory interface 46 is configured to control the non-volatile memory 5. The non-volatile memory interface 46 is electrically connected to multiple memory chips included in the non-volatile memory 5.

[0042] Multiple memory chips can operate independently; that is, memory chips function as parallel-operating units. The non-volatile memory interface (I / F) 46 is connected to channels ch1 and ch2, respectively. The non-volatile memory interface (I / F) 46 is connected to one or more memory chips via the corresponding channels. Figure 1 illustrates the case where one memory chip is connected to each of channels ch1 and ch2. In this case, the non-volatile memory interface (I / F) 46 is connected to memory chip #1 via channel ch1. The non-volatile memory interface (I / F) 46 is connected to memory chip #2 via channel ch2. Here, we have described a case where there are two memory chips in the non-volatile memory 5 and two channels to which the non-volatile memory interface (I / F) 46 is connected, but each channel may have three or more. Also, two or more memory chips may be connected to a single channel.

[0043] In the configuration of the non-volatile memory 5 shown in Figure 1, the controller 4 can access memory chips #1 and #2 in parallel via two channels. That is, the controller 4 can perform parallel write or read operations on the two memory chips #1 and #2. In this case, the number of parallel accesses is 2. Note that each of memory chips #1 and #2 may have a multi-plane configuration with multiple planes. For example, if each of memory chips #1 and #2 contains four planes, the controller 4 can perform parallel write or read operations on up to eight planes. In this case, the number of parallel accesses is 8.

[0044] The volatile memory interface 47 is configured to control the volatile memory 6.

[0045] A portion of the storage area of ​​the volatile memory 6 may be used to store information for managing the memory system 3. For example, the volatile memory 6 stores an L2P table 61, a block management table 62, an active block list 63, a free block list 64, a notification management table 65, a forced refresh management table 66, and a forced refresh list 67.

[0046] The block management table 62 is a table that manages physical blocks and superblocks in the memory system 3. The configuration of superblocks will be described later. The block management table 62 includes, for example, information on bad blocks among the physical blocks in the memory system 3, and information on the multiple physical blocks that make up each superblock. A bad block is a block that cannot be read from or written to successfully. Bad blocks may also be called faulty blocks.

[0047] The active block list 63 is a list of superblocks that contain at least active data. Active data is data stored in storage locations indicated by physical addresses mapped to logical addresses. For example, data stored in storage locations represented by physical addresses referenced by the L2P table 61 is active data. Active data is also data that may be read by host 2.

[0048] The free block list 64 is a list of superblocks that store only invalid data. Invalid data is data stored at storage locations indicated by physical addresses that are not mapped to logical addresses. For example, data stored at storage locations represented by physical addresses not referenced by the L2P table 61 is invalid data. Invalid data is also data that can no longer be read from host 2.

[0049] The notification management table 65, the forced refresh management table 66, and the forced refresh list 67 are used for the notification function of the memory system 3. The notification function is a function that allows the memory system 3 to send information to host 2 regarding whether a forced refresh is scheduled and its start time. Details of the notification function will be described later.

[0050] Next, we will describe examples of the internal configurations of memory chips #1 and #2. Figure 4 shows an example of the configuration of memory chips #1 and #2 included in the memory system 3 according to the embodiment. In Figure 4, memory chip #1 is used as an example for explanation, but memory chip #2 may have a similar configuration to memory chip #1.

[0051] Memory chip #1 includes four planes (plane PLN1, plane PLN2, plane PLN3, and plane PLN4) and four peripheral circuits corresponding to each of the four planes (peripheral circuit 50-1, peripheral circuit 50-2, peripheral circuit 50-3, and peripheral circuit 50-4).

[0052] Each of the planes PLN1 to PLN4 contains a memory cell array. Each memory cell array in planes PLN1 to PLN4 contains multiple physical blocks (physical blocks BLK1 to BLKx). Each of the multiple physical blocks is a unit of erase operation. Each of the multiple physical blocks is also called a flash block or memory block. Each of the multiple physical blocks contains multiple physical pages (pages P1 to Py). Each of the multiple physical pages is a unit of write and read operations. Each of the multiple physical pages contains, for example, multiple memory cells connected to the same word line.

[0053] Each of peripheral circuits 50-1 to 50-4 is a circuit that controls the memory cell array of the corresponding plane. Each of peripheral circuits 50-1 to 50-4 includes, for example, a row decoder, a column decoder, a sense amplifier, and a page buffer. Each of peripheral circuits 50-1 to 50-4 performs a write, read, or erase operation on the memory cell array of the corresponding plane, depending on the address and command received from the non-volatile memory I / F 46.

[0054] Next, we will explain superblocks and superpages.

[0055] Figure 5 shows an example of the configuration of a superblock in the memory system 3 according to this embodiment. The controller 4 manages a set of physical blocks as a superblock. A superblock is, for example, a set of physical blocks selected one by one from each of the parallel-operating planes. A superblock is also called a logical block or block group. The controller 4 also manages a set of physical pages for each of the multiple physical blocks that make up the superblock as a superpage. A superpage is also called a logical page or page group. Here, we will describe the case in which a superblock is made up of physical blocks selected one by one from each of the four planes PLN1 to PLN4 included in memory chip #1.

[0056] One superblock SB includes a total of four physical blocks, one selected from each plane of memory chip #1. If the non-volatile memory 5 has multiple memory chips capable of parallel operation, a single superblock may also include physical blocks selected from each plane of the other memory chips.

[0057] Figure 5 illustrates a single superblock SB5 containing four physical blocks BLK5. Here, the superblock SB5 is composed of physical blocks BLK5 from each of the planes PLN1 to PLN4 of memory chip #1.

[0058] Controller 4 may perform an erasure process on a superblock basis. In other words, Controller 4 performs an erasure process on superblock SB5 if all data stored in superblock SB5 is invalid data. In the erasure process on superblock SB5, the erasure operation is performed on each of the four physical blocks BLK5 contained within superblock SB5.

[0059] Furthermore, the controller 4 can perform write operations in parallel on multiple physical blocks that constitute the superblock. In this write operation, the controller 4 writes data to the superpage, which is a set of physical pages, one selected from each of the multiple physical blocks. At this time, the controller 4 can write redundant code (parity) to at least one of the multiple physical pages that constitute the superpage.

[0060] In Figure 5, the set of physical pages P2 of each physical block BLK5 that make up the superblock SB5 constitutes the superpage SP2. For example, parity data can be written to the physical page P2 of physical block BLK5 of plane PLN4 to restore the data stored in the superpage SP2.

[0061] Next, we will explain the notification function of memory system 3.

[0062] Memory system 3 may move data stored in blocks of non-volatile memory 5 to other blocks. These blocks can be physical blocks or superblocks. This move is called an internal move. Memory system 3 performs internal moves independently of commands from host 2.

[0063] One example of internal movement is a forced refresh to prevent data retention errors. Each of the multiple memory cells contained in the non-volatile memory 5 stores data according to its threshold voltage by accumulating charge in a floating gate. Over time, the charge escapes from the floating gate, and the amount of charge accumulated in the floating gate decreases. If the amount of charge decreases below a certain level, data cannot be read correctly from the memory cell. The time until the amount of charge decreases below a certain level is called the retention limit time. The memory system 3 moves the data to another block before the retention limit time has elapsed from the start of data writing. This prevents read errors.

[0064] Another example of internal movement is wear leveling. The floating gates of the multiple memory cells contained in the non-volatile memory 5 decrease in charge storage capacity as the number of erase operations performed increases. The controller 4 reads data from blocks with fewer erase operations and writes the read data to blocks with more erase operations in order to equalize the number of erase operations across all blocks.

[0065] On the other hand, host 2 may recognize that data corresponding to a certain logical address is unnecessary. In this case, host 2 sends a deallocate command specifying that logical address to the memory system. Controller 4 resolves the mapping between that logical address and the physical address representing the physical storage location where the data is stored, and manages the data as invalid data.

[0066] Host 2 is unaware of when internal data movement occurs. Therefore, Host 2 may send a deallocate command for data immediately after memory system 3 has performed an internal data movement. In this case, the internal movement becomes wasted.

[0067] If host 2 knows the timing of internal movement in advance, host 2 can send a deallocate command to memory system 3 before the internal movement. This allows memory system 3 to avoid executing unnecessary internal movements. In this embodiment, controller 4 sends the schedule of internal movement to host 2 using a notification function.

[0068] The following example illustrates a case where the internal movement is a forced refresh. The embodiment is also applicable when the internal movement is wear leveling.

[0069] Host 2 sends a query to memory system 3 regarding the scheduled forced refresh. Upon receiving the query, memory system 3 sends the scheduled forced refresh to Host 2. The scheduled forced refresh is the start time of the forced refresh. The start time can be expressed as a specific time, or as elapsed time with the current time as 0. In the following explanation, the start time is expressed as elapsed time with the current time as 0. The schedule indicates, for example, how many hours from the current time the forced refresh will begin.

[0070] If the memory system 3 sends a notification to host 2 for all scheduled forced refreshes of all data, it increases traffic between the memory system 3 and host 2, which is undesirable. To address this, in this embodiment, only scheduled forced refreshes that start within a specific time frame from the current time are sent for data corresponding to a certain notification setting range. This specific time frame is also called the notification setting time. Host 2 sends a setting command to the memory system 3 to set the notification setting range and the notification setting time corresponding to this range. If host 2 wants to know all scheduled forced refreshes within a certain notification setting range, it sets the notification setting time corresponding to this range to a very long time. Alternatively, host 2 may disable the setting of the notification setting time.

[0071] Figure 6 illustrates an example of the processing performed by the memory system 3 when it receives a configuration command from the host 2.

[0072] Host 2 sends a configuration command (ST2) to memory system 3. The configuration command requests memory system 3 to create notification management data, which includes the notification setting range and notification setting time. The notification management data is the data used by memory system 3 to create the notification that it will send to host 2. Details of the notification management data will be described later.

[0073] The configuration command includes information representing the mode, information representing the notification setting range, and information representing the notification setting time. The mode can be add, edit, or delete. Adding means creating new notification management data. Editing means combining multiple notification management data into one notification management data. Deleting means deleting notification management data that is no longer needed.

[0074] The notification range is an identifier used to indicate the logical address range to which notification will be sent. For example, the notification range includes namespace identification information (NSID) and LBA range. The LBA range includes the start LBA and end LBA.

[0075] If memory system 3 supports multi-stream functionality or Flexible Data Placement functionality, the notification setting range may further include stream identifiers or reclaim unit handlers (RUHs). In this case, the information representing the notification setting range may include a bitmap representing the stream identifier or RUH. The bitmap is, for example, 16 bits of data. For example, if a bit in the bitmap is set to "1", the stream identifier or RUH data corresponding to that bit will be subject to notification. If a bit in the bitmap is set to "0", the stream identifier or RUH data corresponding to that bit will not be subject to notification.

[0076] Host 2 determines the notification time for each notification setting range.

[0077] Controller 4 (specifically, CPU 42, for example) creates notification management data to manage the settings specified by the configuration command. Controller 4 writes the notification management data to one entry in the notification management table 65 (ST4).

[0078] Figure 7 is a diagram illustrating an example of the notification management table 65. The notification management table 65 has entries for each namespace. Notification management data is created for each namespace corresponding to the namespace identifier specified in the configuration command. A single entry may contain multiple notification management data. The notification management data includes the LBA range and notification setting time specified in the configuration command. The notification management data may also include bitmap information. The CPU 42 assigns a configuration ID to the notification management data created in response to the configuration command. The CPU 42 writes the notification management data with the configuration ID to the notification management table 65.

[0079] In the example shown in Figure 7, the notification management data with setting ID 1 contains information about data stored in the LBA range from LBA0 to LBA99 in the namespace whose namespace identifier is NS0. The notification setting time for this notification management data specified by host 2 is 168 hours (7 days).

[0080] Return to Figure 6. Controller 4 sends a completion notification to Host 2 (ST6). The completion notification includes the configuration ID attached to the notification management data. Host 2 manages the notification management data specified in the configuration command using the configuration ID.

[0081] Figure 8 illustrates an example of the processing performed by the memory system 3 when it receives a write command. Host 2 sends a write command to the memory system 3 (ST12).

[0082] In response to receiving a write command, controller 4 writes the write data to non-volatile memory 5 (ST14). Here, the namespace identifier included in the write command is NS0, the starting LBA is LBA0, and the size of the write data is 100 sectors (i.e., the LBA range specified in the write command is LBA0 to LBA99).

[0083] Figure 9 illustrates an example of non-volatile memory 5 after data has been written in response to this write command. Before receiving this write command, assume that in superblock SB0, some memory areas have already been written with data, and the remaining memory areas are free, and in superblock SB1, all memory areas are free. Controller 4 sequentially writes the data LBA0 to LBA49 to the free areas of superblock SB0. Assume that the free areas of superblock SB0 have been filled after the data LBA49 has been written to superblock SB0. Subsequently, controller 4 sequentially writes the data LBA50 to LBA99 to superblock SB1.

[0084] Figure 10 is a diagram illustrating an example of a forced refresh management table 66. The forced refresh management table 66 stores the remaining time until a forced refresh is initiated for each superblock. The CPU 42 sets an initial value for the remaining time in the forced refresh management table 66 when the first write operation to each superblock is initiated. Here, the first write operation to a particular superblock refers to the first write operation performed after an erase operation has been performed on that superblock. The controller 4 is equipped with a timer (not shown). The remaining time is managed by the timer and decreases over time. The CPU 42 initiates a forced refresh of a superblock when the remaining time reaches 0.

[0085] A forced refresh of a superblock must be completed before the retention limit time expires, starting from the initial write to that superblock. Therefore, the initial value of the remaining time is shorter than the retention limit time. However, if the initial value of the remaining time is significantly shorter than the retention limit time, the number of forced refreshes will increase, which is undesirable.

[0086] The start time for data writing differs for each superblock. Therefore, multiple superblocks will not reach their retention limit time simultaneously. However, since forced refresh takes a certain amount of time, the remaining time for one or more other superblocks continues to decrease even while a forced refresh is in progress for one superblock. The start of forced refreshes for other superblocks will be delayed until the currently running forced refresh is complete. In this way, even if the start of a forced refresh is delayed, all superblocks must complete their forced refresh before the retention limit time elapses from the start of writing.

[0087] For example, if it takes 1 minute to force refresh one superblock, and controller 4 manages 1024 superblocks, then it takes approximately 17 hours to force refresh all superblocks. Therefore, if the initial value of the remaining time is set to the retention limit time minus 17 hours, it is guaranteed that the forced refresh of all superblocks will be completed before the retention limit time elapses from the start of writing. CPU 42 may also set the initial value of the remaining time to a small margin, for example, the retention limit time minus 24 hours. For example, if the retention limit time is 360 hours (15 days) and a small margin is set, the initial value of the remaining time would be 336 hours (14 days).

[0088] Figure 10 shows the state of the forced refresh management table 66 immediately after the data for LBA50 is written to superblock SB1. The remaining time for superblock SB1 is set to the initial value (336 hours). It is also assumed that the initial write to superblock SB0 started 6 hours before the initial write to superblock SB1. Therefore, the remaining time for superblock SB0 is 330 hours, which is 6 hours less than the initial value.

[0089] Returning to Figure 8, the controller 4, having written the write data to the non-volatile memory 5, sets the remaining time of the superblock from which the initial write began in the forced refresh management table 66, as explained with reference to Figure 10 (ST16). Then, the controller 4 sends a completion notification to the host 2 (ST18).

[0090] Figure 11 illustrates an example of how the memory system 3 processes an inquiry command. When the memory system 3 receives an inquiry command from host 2, it sends a notification to host 2 indicating that a forced refresh is scheduled.

[0091] Host 2 sends a query command to memory system 3 at any time (ST22). Host 2 may also send query commands to memory system 3 periodically at regular intervals. Alternatively, Host 2 may send query commands to memory system 3 when traffic to memory system 3 is low. The query command specifies one or more setting IDs of the notification management data sent to Host 2 as a completion notification for the setting command.

[0092] Controller 4 reads one notification management data corresponding to the setting ID specified in the query command from the notification management table 65 (ST24). Controller 4 determines one or more superblocks corresponding to the notification setting range of the notification management data using the L2P table 61 (ST26). Controller 4 reads the remaining time of that superblock from the forced refresh management table 66 (ST28).

[0093] Host 2 requests to know about scheduled forced refreshes that will start between the time the query command is sent and the notification setting time has elapsed. Therefore, Controller 4 determines whether the remaining time is less than or equal to the notification setting time (ST30). If the remaining time is less than or equal to the notification setting time (Yes in ST30), it is expected that a forced refresh will start between the time the query command is received and the notification setting time has elapsed. Therefore, Controller 4 generates an announcement notification that includes information indicating that a forced refresh (internal movement) is scheduled and information indicating the scheduled time of the internal movement (ST32). The scheduled time of the internal movement is set to the remaining time of the target superblock. Note that if it is expected that a forced refresh will start for two or more superblocks, the announcement notification may include two or more scheduled times for internal movement.

[0094] If the remaining time is longer than the notification setting time (No in ST30), it is assumed that a forced refresh will not be initiated between the time the query command is received and the notification setting time has elapsed. Therefore, controller 4 generates an announcement notification that includes information indicating that there are no plans for internal movement (ST34).

[0095] After processing in step ST32 or step ST34, the controller 4 determines whether there is any unread notification management data (i.e., unprocessed notification management data) corresponding to one or more configuration IDs specified in the query command (ST36). If there is unprocessed notification management data (Yes in ST36), the controller 4 reads the following notification management data from the notification management table 65 (ST24).

[0096] If there is no unprocessed notification management data (No in ST36), controller 4 sends the notification generated in step ST32 or step ST34 to host 2 (ST38).

[0097] The remaining time in the forced refresh management table 66 decreases over time. Therefore, the timing of when host 2 sends a query command may change whether or not an internal movement is scheduled in the notification.

[0098] First, let's explain the case where, in response to the write command described with reference to Figures 8 to 10, Host 2 sends a query command specifying 1 for the setting ID when writing data from LBA50 to superblock SB1 begins. In this case, assume that the forced refresh management table 66 is in the state shown in Figure 10. Also, assume that the notification management table 65 is in the state shown in Figure 7. That is, the notification management data with setting ID 1 includes NS0 and LBA0 to LBA99 as the notification setting range. The remaining time (330 hours) of superblock SB0, where the data from LBA0 to LBA49 is written, is longer than the notification setting time (168 hours). The remaining time (336 hours) of superblock SB1, where the data from LBA50 to LBA99 is written, is also longer than the notification setting time (168 hours). Therefore, the forced refresh for the notification setting range specified by this query command will not start until the notification setting time has elapsed.

[0099] Figure 12 illustrates an example of a notification sent to host 2 in this situation. This notification includes a configuration ID and information indicating that there are no planned internal movements.

[0100] Next, we will explain the case where, in response to the write command described with reference to Figures 8 to 10, Host 2 sends a query command specifying 1 for the setting ID after 7 days (168 hours) have elapsed since the start of writing data from LBA50 to superblock SB1. In this case, the forced refresh management table 66 is in the state shown in Figure 13. That is, the remaining time for superblock SB0 is 162 hours, which is 330 hours minus 168 hours as shown in Figure 10. The remaining time for superblock SB1 is 168 hours, which is 336 hours minus 168 hours as shown in Figure 10.

[0101] In this case, the remaining time (162 hours) for superblock SB0, where the data for LBA0 to LBA49 is written, is shorter than the notification setting time (168 hours). Also, the remaining time (168 hours) for superblock SB1, where the data for LBA50 to LBA99 is written, is equal to the notification setting time (168 hours). Therefore, the forced refresh for the notification setting range specified by this query command will start after 162 hours for LBA0 to LBA49 and after 168 hours for LBA50 to LBA99.

[0102] Figure 14 illustrates an example of a notification sent to host 2 in this situation. This notification includes a configuration ID and information indicating that internal migration is scheduled to begin in 162 hours for LBA0-LBA49 and in 168 hours for LBA50-LBA99.

[0103] In this way, when memory system 3 receives a query command from host 2, it notifies host 2 of the identifier of the data to be moved internally within the notification setting time from the time the command is received, and the scheduled start time. Upon receiving this notification, if the data scheduled to be moved internally is unnecessary data, host 2 can send a deallocate command for that data earlier than the scheduled start time of the internal movement.

[0104] Figure 15 is a diagram illustrating an example of the timing at which the host 2 sends a deallocate command to the memory system 3 according to this embodiment.

[0105] Host 2 sends a write command for data D0 to memory system 3 (ST52). Controller 4 writes data D0 to non-volatile memory 5, as explained with reference to Figures 8 to 10. Here, it is assumed that controller 4 writes data D0 to superblock SB0. Although not shown in Figure 15, when writing to superblock SB0 begins, controller 4 sets an initial value for the remaining time of superblock SB0 in the forced refresh management table 66. The initial value is, for example, 336 hours (14 days). Controller 4 sends a write completion notification to host 2.

[0106] Host 2 sends a configuration command to memory system 3 (ST54). Controller 4 writes notification management data to notification management table 65, as explained with reference to Figures 6 and 7. Controller 4 sends a configuration completion notification to Host 2. Host 2 may send the configuration command first and then the write command.

[0107] Host 2 sends a query command to memory system 3 at any time (ST56). Here, the query command is assumed to have been sent 174 hours (7 days and 6 hours) after the start of writing data D0 to superblock SB0. That is, the query command is assumed to have been sent when the remaining time for superblock SB0 was 162 hours. Controller 4 compares the remaining time in the forced refresh management table 66 with the notification setting time for the notification management data, as explained with reference to Figures 11 to 13, to determine whether an internal move is scheduled. In the example shown in Figure 15, the notification includes information indicating that data D0 will be moved internally after 162 hours. Controller 4 sends the notification including the scheduled internal move to Host 2 (ST58).

[0108] If host 2 already recognizes that data D0 is no longer needed upon receiving this notification, it can send a deallocate command for data D0 to memory system 3 within 162 hours of receiving the notification (ST60). If controller 4 receives a deallocate command for data D0, it will deallocate data D0 (ST62). As a result, controller 4 will not perform the internal move to data D0 that was scheduled to occur 336 hours after the start of writing to superblock SB0.

[0109] As explained above, the memory system 3 according to this embodiment can prevent the host 2 from moving data that it no longer needs internally. Since the number of unnecessary internal movements does not increase, the WAF does not become excessively high, and the performance of the memory system 3 does not deteriorate.

[0110] Figure 16 illustrates an example of the timing at which the host sends a deallocate command to the memory system in the comparative example. In the comparative example, the memory system does not send a scheduled internal move to the host.

[0111] The host sends a write command for data D0 to the memory system (ST72). The memory system controller writes data D0 to superblock SB0, as in the embodiment described with reference to Figure 15. In the forced refresh management table, the remaining time for superblock SB0 is set to an initial value (336 hours).

[0112] If 336 hours have elapsed since the start of writing data D0 to superblock SB0, the memory system will initiate a forced refresh of data D0 (ST74). That is, data D0 will be moved from superblock SB0 to superblock SB1.

[0113] As described above, the memory system in the comparative example does not send a scheduled internal move to the host. Here, the host was aware that data D0 was unnecessary before processing in step ST74, but the deallocate command for data D0 was sent to the memory system afterward (ST76).

[0114] Upon receiving the deallocate command, the memory system deals with data D0, which has been moved to superblock SB1 (ST78).

[0115] Thus, the memory system in the comparative example moves unnecessary data D0 internally, causing the WAF to become excessively high and degrading performance.

[0116] During a forced refresh, the memory system's response performance to I / O commands from the host is reduced. As described above, the host 2 connected to the memory system 3 in this embodiment can be aware of the scheduled forced refresh when it receives a notification. Therefore, the host 2 may send a request to the memory system 3 to change the timing of the forced refresh, which would otherwise reduce performance. This request is referred to as a reservation command.

[0117] Figure 17 is a diagram illustrating an example of processing when the memory system 3 according to this embodiment receives a reservation command.

[0118] Host 2 sends a query command to memory system 3 at any time (ST82). Controller 4, upon receiving the query command, sends a notification to host 2 (ST84).

[0119] Host 2 recognizes the period when memory system 3's performance will degrade based on the internal movement schedule of notification alerts. Host 2 also knows when access to memory system 3 is likely to be concentrated. If the performance degradation period coincides with this period of concentrated access, Host 2 sends a reservation command (ST86) to advance the start time of a forced refresh in memory system 3. The reservation command includes a configuration ID and information representing the reservation time. The reservation time indicates how many hours later Host 2 wants the forced refresh to start.

[0120] Upon receiving the reservation command, controller 4 adds a reservation time item to the forced refresh management table 66 and writes the reservation time specified in the reservation command to the forced refresh management table 66 (ST88).

[0121] Figure 18 illustrates an example of a forced refresh management table 66 in which the reservation time is written. Here, the reservation time is 24 hours, the remaining time for superblock SB0 is 162 hours, the remaining time for superblock SB1 is 168 hours, and the remaining time for superblock SB2 is 24 hours. Furthermore, it is assumed that the only superblocks corresponding to the notification setting range of the setting ID specified in the reservation command are superblock SB0 and superblock SB1. In this case, 24 hours is written to the reservation time of superblock SB0, and 24 hours is written to the reservation time of superblock SB1. Since the reservation command does not include the reservation time for superblock SB2, N (no reservation) is written to the reservation time item for superblock SB2. The reservation time, like the remaining time, is managed by a timer and decreases over time.

[0122] Return to Figure 17. After setting the reservation time, Controller 4 sends a reservation completion notification to Host 2 (ST90).

[0123] Figure 19 illustrates an example of the state of the forced refresh management table 66 24 hours after the reservation time was written. The remaining time for superblock SB0 is 138 hours, the remaining time for superblock SB1 is 144 hours, and the remaining time for superblock SB2 is 0 hours. The reservation time for superblocks SB0 and SB1 is 0 hours, and the reservation time for superblock SB2 is N.

[0124] Memory system 3 initiates a forced refresh based on the forced refresh management table 66. Figure 20 is a flowchart illustrating an example of the forced refresh procedure performed by memory system 3.

[0125] CPU42 examines the contents of the forced refresh management table 66 (ST102). CPU42 periodically executes the process in step ST102.

[0126] CPU42 determines whether there is a superblock with a remaining time of 0 in the forced refresh management table 66 (ST104).

[0127] If there is a superblock with a remaining time of 0 (Yes in ST104), CPU 42 writes the identification information of that superblock to the regular execution list of the forced refresh list 67 (ST106). If there is no superblock with a remaining time of 0 (No in ST104), the processing in step ST106 is not executed, and the CPU 42 proceeds to step ST108.

[0128] CPU42 determines whether there is a superblock with a reservation time of 0 in the forced refresh management table 66 (ST108).

[0129] If there is a superblock with a reservation time of 0 (Yes in ST108), CPU42 writes the identification information of that superblock to the reserved execution list of the forced refresh list 67 (ST110). If there is no superblock with a reservation time of 0 (No in ST108), the processing in step ST110 is not executed, and the CPU42 proceeds to step ST112.

[0130] Figure 21 is a diagram illustrating an example of a forced refresh list 67. The forced refresh list 67 stores identification information for superblocks that should be subjected to a forced refresh. The forced refresh list 67 includes a normal execution list and a reserved execution list. The normal execution list stores identification information for superblocks whose remaining time has reached zero. The reserved execution list stores identification information for superblocks whose reserved time has reached zero.

[0131] Returning to Figure 20, the CPU 42 determines whether the normal execution list and the reserved execution list in the forced refresh list 67 contain the same superblock identification information (ST112).

[0132] If the normal execution list and the reserved execution list contain the same superblock identification information (Yes in ST112), CPU 42 removes the superblock identification information from the normal execution list (ST114). This superblock identification information is then stored only in the reserved execution list. If the normal execution list and the reserved execution list do not contain the same superblock identification information (No in ST112), the process in step ST114 is not executed, and CPU 42 proceeds to step ST116.

[0133] CPU42 moves the data of the identification information stored in the reserved execution list from one superblock to another superblock (ST116). The process in step ST116 is executed sequentially for all superblocks in which the identification information is stored in the reserved execution list.

[0134] CPU42 moves the data of the identification information superblock stored in the normal execution list to another superblock (ST118). The process in step ST118 is executed sequentially for all superblocks in which the identification information is stored in the normal execution list.

[0135] According to this embodiment, the memory system 3 notifies the host 2 of the scheduled forced refresh. Therefore, the host 2 can know in advance when the performance of the memory system 3 will degrade. If the period of performance degradation coincides with a time when access to the memory system 3 is likely to be concentrated, the host 2 can send a reservation command to the memory system 3 to bring forward the scheduled forced refresh. Therefore, the memory system 3 can perform a forced refresh at a time when access from the host 2 is not concentrated.

[0136] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0137] 1... Information processing system, 2... Host, 3... Memory system, 4... Controller, 5... Non-volatile memory, 6... Volatile memory, 21... Processor, 22... Memory, 41... Host interface circuit, 42... CPU, 43... Static RAM, 44... Direct memory access controller, 45... ECC circuit, 46... Non-volatile memory interface circuit, 47... Volatile memory interface circuit, 50... Peripheral circuit, 61... Logical-physical address translation table, 62... Block management table, 63... Active block list, 64... Free block list, 65... Notification management table, 66... ​​Forced refresh management table, 67... Forced refresh list

Claims

1. A non-volatile memory comprising multiple storage areas, each having multiple memory cells, The non-volatile memory is electrically connected to the aforementioned non-volatile memory, At the first time step, a query command is received from the host that includes at least first information that can identify the first logical address. It is determined whether or not the internal movement of the first data corresponding to the first logical address is scheduled to begin between the first time and the first hour, If the internal movement of the first data is scheduled to begin between the first time and the first hour, second information indicating the scheduled start date of the internal movement of the first data is transmitted to the host. A controller configured as follows, A memory system equipped with the following features.

2. The internal movement of the first data is The controller reads the first data from a first storage area, which is one of the plurality of storage areas. The controller includes writing the read first data to a second storage area, which is another storage area among the plurality of storage areas. The memory system according to claim 1.

3. The aforementioned controller further, Upon receiving a configuration command from the host that includes at least third information capable of identifying the first logical address and fourth information representing the first time, data representing the correspondence between the first logical address and the first time is written to the first table. The memory system according to claim 2, configured as described above.

4. The aforementioned controller further, For each of the aforementioned multiple storage areas, the remaining time until the start time of internal data movement stored in each storage area is managed using the second table. In response to the remaining time in the first memory area becoming zero, the internal movement of the first data is initiated. The memory system according to claim 3, configured as described above.

5. The controller further responds to receiving a write command from the host, The data associated with the write command is written to the destination storage area among the plurality of storage areas. In the second table, the remaining time for the memory area to be written to is set to the second time. The memory system according to claim 4, configured as described above.

6. The controller further responds to receiving the query command from the host, From the first table, read the first time corresponding to the first logical address, Based on the first information included in the query command, the first storage area is identified. From the second table, read the remaining time in the first storage area. If the remaining time in the read first storage area is shorter than the first time corresponding to the read first logical address, it is determined that the internal movement of the first data is scheduled to begin. The memory system according to claim 5, configured as described above.

7. The aforementioned controller further, At the start of the first write to each of the plurality of memory areas, the remaining time for each memory area is set to an initial value in the second table. As time passes, the remaining time is updated to reflect the elapsed time. The memory system according to claim 4, configured as described above.

8. The aforementioned controller further, For each of the aforementioned multiple memory areas, the time limit from the start of the initial write to each memory area until the internal movement is executed is managed. The initial value of the remaining time for each of the aforementioned storage areas is set to the time obtained by subtracting the total time required for the internal movements performed for each of the plurality of storage areas from the limit time. The memory system according to claim 7, configured as described above.

9. The aforementioned controller further, For each of the aforementioned multiple storage areas, the reservation time until the start time of the internal movement of data stored in each storage area is managed using the second table. Upon receiving a reservation command from the host, which includes at least fifth information that can identify the first logical address and sixth information representing the third time which is the reserved time for the internal movement of the first data, In the second table, the third time is set to the reserved time of the first storage area, As time progresses, the remaining time in the first storage area and the reserved time in the first storage area are updated to times corresponding to the elapsed time, In response to the remaining time in the first storage area or the reserved time in the first storage area becoming zero, the internal movement of the first data is initiated. The memory system according to claim 4, configured as described above.

10. The aforementioned controller further, When the remaining time of the third storage area among the plurality of storage areas becomes zero, the identification information representing the third storage area is written to the first list, and when the reserved time of the fourth storage area among the plurality of storage areas becomes zero, the identification information of the fourth storage area is written to the second list. The internal movement of the fourth storage area having the identification information written in the second list is initiated, and then the internal movement of the third storage area having the identification information written in the first list is initiated. The memory system according to claim 9, configured as described above.

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