Indication device

Abstract

To provide a display device that can improve the quality of the display. [Solution] According to the embodiment, the display device comprises: an organic insulating layer arranged over a display area and a peripheral area above a substrate; a plurality of lower electrodes arranged above the organic insulating layer in the display area; an inorganic insulating layer having a plurality of pixel apertures that overlap each of the plurality of lower electrodes; a first partition wall arranged above the inorganic insulating layer, including a conductive first lower part and a first upper part having an end protruding from the side surface of the first lower part, each surrounding a plurality of pixel apertures; a plurality of laminated films covering the lower electrodes through the pixel apertures and including an organic layer that emits light in response to the application of voltage; a first sealing layer formed of an inorganic insulating material and covering the plurality of laminated films; a dam structure arranged above the organic insulating layer in the peripheral area, surrounding the first partition wall and protruding beyond the first partition wall; and a first resin layer arranged inside the dam structure and covering the first sealing layer.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a display device. [Background Art]

[0002] In recent years, display devices using organic light-emitting diodes (OLED) as display elements have been put into practical use. In this type of display device, a technique for improving display quality is required. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. WO 2018 / 179308 [Patent Document 7] United States Patent Application Publication No. 2022 / 0077251 Specification [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] An object of the present invention is to provide a display device capable of improving display quality. [Means for Solving the Problem]

[0005] Generally, according to the embodiment, the display device comprises a substrate having a display area and a peripheral area surrounding the display area; an organic insulating layer disposed above the substrate, extending across the display area and the peripheral area; a plurality of lower electrodes disposed above the organic insulating layer in the display area; an inorganic insulating layer having a plurality of pixel apertures overlapping each of the plurality of lower electrodes; a first partition wall disposed above the inorganic insulating layer, including a conductive first lower part and a first upper part having an end protruding from the side surface of the first lower part, each surrounding the plurality of pixel apertures; a plurality of laminated films covering the lower electrodes through the pixel apertures and including an organic layer that emits light in response to the application of voltage; a first sealing layer formed of an inorganic insulating material and covering the plurality of laminated films; a dam structure disposed above the organic insulating layer in the peripheral area, surrounding the first partition wall and protruding beyond the first partition wall; and a first resin layer disposed inside the dam structure and covering the first sealing layer.

[0006] In another embodiment, the display device includes a substrate having a display area and a peripheral area surrounding the display area; an organic insulating layer disposed above the substrate, extending across the display area and the peripheral area; a plurality of lower electrodes disposed above the organic insulating layer in the display area; an inorganic insulating layer having a plurality of pixel apertures that overlap each of the plurality of lower electrodes; a first partition wall disposed above the inorganic insulating layer, including a conductive first lower part and a first upper part having an end protruding from the side surface of the first lower part, each surrounding the plurality of pixel apertures in the display area and extending from the display area to the peripheral area; a plurality of laminated films covering the lower electrodes through the pixel apertures and including an organic layer that emits light in response to the application of voltage; a first sealing layer formed of an inorganic insulating material and covering the plurality of laminated films; a dam structure disposed above the first partition wall in the peripheral area; and a first resin layer disposed inside the dam structure and covering the first sealing layer. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of the configuration of a display device according to the first embodiment. [Figure 2] Figure 2 is a schematic plan view showing an example of the layout of subpixels that make up a single pixel. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic plan view of the motherboard according to the first embodiment. [Figure 5] Figure 5 is a schematic plan view of the panel section. [Figure 6A] Figure 6A is a schematic cross-sectional view of the panel along the line VI-VI in Figure 5. [Figure 6B] Figure 6B is an enlarged view of the vicinity of the dam structure in Figure 6A. [Figure 7] Figure 7 is a flowchart showing an example of a method for manufacturing a display device. [Figure 8A] Figure 8A is a schematic cross-sectional view showing the manufacturing process of a display device. [Figure 8B] Figure 8B is a schematic cross-sectional view showing the process following Figure 8A. [Figure 8C] Figure 8C is a schematic cross-sectional view showing the process following Figure 8B. [Figure 8D] Figure 8D is a schematic cross-sectional view showing the process following Figure 8C. [Figure 8E] Figure 8E is a schematic cross-sectional view showing the process following Figure 8D. [Figure 8F] Figure 8F is a schematic cross-sectional view showing the process following Figure 8E. [Figure 8G] Figure 8G is a schematic cross-sectional view showing the process following Figure 8F. [Figure 8H] Figure 8H is a schematic cross-sectional view showing the process following Figure 8G. [Figure 8I] Figure 8I is a schematic cross-sectional view showing the process following Figure 8H. [Figure 8J] Figure 8J is a schematic cross-sectional view showing the process following Figure 8I. [Figure 9A] Figure 9A is a schematic cross-sectional view showing the manufacturing process of a display device. [Figure 9B] FIG. 9B is a schematic cross-sectional view showing a step subsequent to FIG. 9A. [Figure 9C] FIG. 9C is a schematic cross-sectional view showing a step subsequent to FIG. 9B. [Figure 10] FIG. 10 is a flowchart illustrating an example of a method for manufacturing a resin layer. [Figure 11A] FIG. 11A is a diagram for explaining the manufacturing steps of the resin layer. [Figure 11B] FIG. 11B is a schematic cross-sectional view showing a step subsequent to FIG. 11A. [Figure 11C] FIG. 11C is a schematic cross-sectional view showing a step subsequent to FIG. 11B. [Figure 12] FIG. 12 is a schematic cross-sectional view of a panel unit according to a second embodiment. [Figure 13A] FIG. 13A is a schematic cross-sectional view of a panel unit according to a third embodiment. [Figure 13B] FIG. 13B is an enlarged view of the vicinity of a dam in FIG. 13A. [Figure 14A] FIG. 14A is a diagram for explaining an example of an arrangement mode of dams. [Figure 14B] FIG. 14B is a diagram for explaining another example of an arrangement mode of dams. [Figure 14C] FIG. 14C is a diagram for explaining still another example of an arrangement mode of dams. [Figure 14D] FIG. 14D is a diagram for explaining still another example of an arrangement mode of dams. [Figure 15] FIG. 15 is a flowchart illustrating an example of a method for manufacturing a display device according to the third embodiment. [Figure 16A] FIG. 16A is a schematic cross-sectional view of a panel unit according to a fourth embodiment. [Figure 16B] FIG. 16B is an enlarged view of the vicinity of a dam in FIG. 16A. [Figure 17A] FIG. 17A is a schematic cross-sectional view of a panel unit according to the fourth embodiment. [Figure 17B] FIG. 17B is an enlarged view of the vicinity of a dam in FIG. 17A. [Figure 18A] Figure 18A is a schematic cross-sectional view of the panel portion in the fifth embodiment. [Figure 18B] Figure 18B is an enlarged view of the area near the dam in Figure 18A. [Figure 19A] Figure 19A is a flowchart showing an example of a method for manufacturing a display device according to the fifth embodiment. [Figure 19B] Figure 19B is a flowchart showing another example of a method for manufacturing a display device according to the fifth embodiment. [Figure 19C] Figure 19C is a flowchart showing yet another example of a method for manufacturing a display device according to the fifth embodiment. [Figure 20A] Figure 20A is a schematic cross-sectional view of the panel portion in the sixth embodiment. [Figure 20B] Figure 20B is an enlarged view of the area near the dam in Figure 20A. [Figure 21] Figure 21 is a flowchart showing an example of a method for manufacturing a display device according to the sixth embodiment. [Figure 22] Figure 22 is a schematic cross-sectional view of the panel portion in the seventh embodiment. [Modes for carrying out the invention]

[0008] Embodiments will be described below with reference to the drawings. It should be noted that the disclosure is merely an example, and modifications that can be easily conceived by those skilled in the art while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation; however, these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and in each drawing, components that perform the same or similar functions as those described above with respect to previously shown drawings are denoted by the same reference numerals, and redundant detailed explanations may be omitted as appropriate.

[0009] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X-axis is referred to as the X-direction, the direction along the Y-axis as the Y-direction, and the direction along the Z-axis as the Z-direction. Viewing various elements parallel to the Z-direction is called a plan view.

[0010] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] [First Embodiment] Figure 1 shows an example configuration of a display device DSP according to this embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 and the display area DA in plan view is circular. Note that the term "circular" includes not only perfect circles, but also oblong, elliptical, and partially cut-off shapes. Furthermore, the shape of the substrate 10 and the display area DA in plan view is not limited to circular; it may be other shapes such as rectangles, squares, or ellipses.

[0013] The display area DA comprises a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of sub-pixels SP that display different colors. In this embodiment, it is assumed that each pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. Each pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0014] The display device DSP further includes a terminal section T located in the peripheral region SA. A flexible circuit board, for example, that supplies voltage and signals for driving the display device DSP, is connected to the terminal section T.

[0015] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0016] The display area DA is arranged with multiple scan lines GL that supply scan signals to the pixel circuit 1 of each sub-pixel SP, multiple signal lines SL that supply video signals to the pixel circuit 1 of each sub-pixel SP, and multiple power lines PL. In the example in Figure 1, the scan lines GL and power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0017] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element DE.

[0018] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0019] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3 that constitute a single pixel PX. In the example in Figure 2, sub-pixels SP1 and SP3 are aligned in the Y direction. Also, sub-pixels SP1 and SP3 are aligned with sub-pixel SP2 in the X direction.

[0020] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP3 are alternately arranged in the Y direction, and columns in which multiple sub-pixels SP2 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0021] A rib layer 5 (inorganic insulating layer) is arranged in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, pixel apertures AP1 and AP3 are rectangles of equivalent area. On the other hand, pixel aperture AP2 is a rectangle that is longer in the Y direction than pixel apertures AP1 and AP3. However, the shapes of pixel apertures AP1, AP2, and AP3 are not limited to this example.

[0022] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3.

[0023] The portion of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlaps with the pixel aperture AP1 constitutes the display element DE1 of the sub-pixel SP1. The portion of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlaps with the pixel aperture AP2 constitutes the display element DE2 of the sub-pixel SP2. The portion of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlaps with the pixel aperture AP3 constitutes the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0024] A conductive partition wall 6A (first partition wall) is positioned above the rib layer 5. The partition wall 6A serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition wall 6A overlaps with the rib layer 5 overall and has a similar planar shape to the rib layer 5. The partition wall 6A surrounds each of the pixel apertures AP1, AP2, and AP3.

[0025] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring, such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.

[0026] The lower electrodes LE1, LE2, and LE3 are positioned on top of the organic insulating layer 12. The rib layer 5 is positioned on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross-section of Figure 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12.

[0027] The partition wall 6A includes a conductive lower part 61 (first lower part) positioned on the rib layer 5 and an upper part 62 (first upper part) positioned on the lower part 61. The upper part 62 has a greater width than the lower part 61. That is, the partition wall 6A is in an overhanging shape, with both ends of the upper part 62 protruding beyond the sides of the lower part 61.

[0028] In the example shown in Figure 3, the lower section 61 has a bottom layer 63 positioned on top of the rib layer 5 and an axial layer 64 positioned on top of the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the axial layer 64. In the example shown in Figure 3, both ends of the bottom layer 63 protrude from the sides of the axial layer 64.

[0029] Furthermore, in the example shown in Figure 3, the upper section 62 comprises a first top layer 65 and a second top layer 66 positioned on top of the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, it is not limited to this, and the first top layer 65 and the second top layer 66 may have equivalent widths.

[0030] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6A.

[0031] Display element DE1 includes a cap layer CP1 covering the upper electrode UE1. Display element DE2 includes a cap layer CP2 covering the upper electrode UE2. Display element DE3 includes a cap layer CP3 covering the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0032] In the following description, a multilayer containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is referred to as the multilayer film FL1, a multilayer containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 is referred to as the multilayer film FL2, and a multilayer containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 is referred to as the multilayer film FL3. The multilayer films FL1, FL2, and FL3 are arranged in the pixel apertures AP1, AP2, and AP3, respectively.

[0033] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE11, SE12, and SE13 (first sealing layers). Sealing layer SE11 continuously covers the display element DE1 and the surrounding partition wall 6A. Sealing layer SE12 continuously covers the display element DE2 and the surrounding partition wall 6A. Sealing layer SE13 continuously covers the display element DE3 and the surrounding partition wall 6A.

[0034] In the example shown in Figure 3, the sealing layer SE11 on the partition wall 6A between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition wall 6A. Also, the sealing layer SE11 on the partition wall 6A between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition wall 6A. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact above the partition wall 6A.

[0035] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6A. The laminated films FL1, FL2, FL3 may be placed in at least a portion of these gaps.

[0036] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1 (first resin layer). The resin layer RS1 is covered by the sealing layer SE2 (second sealing layer). The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0037] A cover component, such as a polarizing plate, touch panel, protective film, or cover glass, may be further placed on top of the resin layer RS2. Such a cover component may be bonded to the resin layer RS2 via an adhesive layer, such as OCA (Optical Clear Adhesive).

[0038] The electrodes constituting the touch panel described above may be placed on top of the sealing layer SE2. In addition, color filters corresponding to the colors of the sub-pixels SP1, SP2, and SP3 may be placed above the display elements DE1, DE2, and DE3, respectively.

[0039] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0040] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of this reflective layer, respectively. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0041] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0042] The organic layers OR1, OR2, and OR3 are composed of multiple thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked sequentially in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including multiple emissive layers.

[0043] The cap layers CP1, CP2, and CP3 have a laminated structure in which multiple transparent layers are stacked, for example. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The bottom layer 63 and axial layer 64 of the partition wall 6A are formed of a metallic material. For example, the metallic material for the bottom layer 63 can be molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb). For example, the metallic material for the axial layer 64 can be aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). The axial layer 64 may also be formed of an insulating material.

[0045] The first top layer 65 of the partition wall 6A is formed of, for example, a metallic material. The second top layer 66 of the partition wall 6A is formed of, for example, a conductive oxide. As the metallic material forming the first top layer 65, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide forming the second top layer 66, for example, ITO or IZO can be used. The upper part 62 may consist of three or more layers, or it may be formed as a single layer. Furthermore, the upper part 62 may include a layer formed of an insulating material.

[0046] A common voltage is supplied to the partition wall 6A. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the video signal on the signal line SL through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0047] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the red wavelength range.

[0048] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0049] During the manufacturing of a display device DSP, a large motherboard is created in which multiple areas (panel sections) corresponding to the display device DSP are formed. The following describes the configurations that can be applied to this motherboard.

[0050] Figure 4 is a schematic plan view of the motherboard MB (display device motherboard) according to this embodiment. The motherboard MB has, for example, a rectangular shape as shown, but may have other shapes such as a circle.

[0051] The motherboard MB has multiple panel sections PP arranged in a matrix, and a marginal area BA surrounding these panel sections PP. In the example in Figure 4, each panel section PP is arranged in the X and Y directions with the marginal area BA in between. However, the arrangement of the multiple panel sections PP on the motherboard MB is not limited to this example. In other examples, some panel sections PP may be arranged without the marginal area BA in between.

[0052] Figure 5 is a schematic plan view of the panel section PP. The outline of the panel section PP corresponds to the cut line CL1 used to cut out each panel section PP from the motherboard MB. The panel section PP has the display area DA and the peripheral area SA described above. The peripheral area SA in the panel section PP corresponds to the area between the display area DA and the cut line CL1.

[0053] The peripheral region SA further includes a cut line CL2 that forms the outline of the substrate 10 of the display device DSP. The peripheral region SA includes an inspection region TA between the cut lines CL1 and CL2. Multiple inspection pads TD for inspecting the operation of the display device DSP are arranged in the inspection region TA. Each inspection pad TD is connected to a terminal section T via wiring WL.

[0054] During the manufacturing of the display device DSP, the panel portion PP is cut out from the motherboard MB along the cut line CL1. Furthermore, after inspection is performed on the cut-out panel portion PP, the inspection area TA is separated from the panel portion PP along the cut line CL2.

[0055] The panel section PP includes dam structures DS1 and DS2. Both dam structures DS1 and DS2 are formed in an annular shape. Dam structure DS1 is located in the peripheral region SA between the cut line CL2 and the display region DA, and surrounds the display region DA. Dam structure DS2 is formed to surround dam structure DS1 and is spaced apart from it. Dam structure DS2 is located in the inspection region TA.

[0056] The cut line CL2 is mostly located between the dam structures DS1 and DS2. However, in the example in Figure 5, the cut line CL2 is located outside the dam structures DS1 and DS2 near terminal T. In other words, the cut line CL2 crosses the dam structure DS2 near terminal T.

[0057] Figure 6A is a schematic cross-sectional view of the panel section PP along the line VI-VI in Figure 5. Figure 6B is an enlarged view of the vicinity of the dam structure DS1 in Figure 6A. In Figure 6A, the cross-sectional structure of the panel section PP is shown, and the structure inside the cut line CL2 corresponds to the cross-sectional structure of the region containing the dam structure DS1 in the display device DSP.

[0058] As shown in Figure 6A, the circuit layer 11 is located above the substrate 10, extending from the display area DA to the peripheral area SA. Within the peripheral area SA, the circuit layer 11 is located between cut line CL1 and cut line CL2.

[0059] The circuit layer 11 shown in Figure 3 includes inorganic insulating layers 31, 32, and 33 made of inorganic insulating material, an organic insulating layer 34 made of organic insulating material, and metal layers 41, 42, and 43. The inorganic insulating layer 31 covers the upper surface of the substrate 10.

[0060] The metal layer 41 is located on top of the inorganic insulating layer 31. The metal layer 41 is, for example, a layer containing a scan line GL. The inorganic insulating layer 32 covers the metal layer 41. The metal layer 42 is located on top of the inorganic insulating layer 32. The inorganic insulating layer 33 covers the metal layer 42. The metal layer 42 is, for example, a layer containing a signal line SL.

[0061] The organic insulating layer 34 covers the inorganic insulating layer 33. The metal layer 43 is placed on top of the organic insulating layer 34 and is covered by the organic insulating layer 12. The metal layer 43 is electrically connected to the metal layer 42 via a contact portion CT1 formed on the organic insulating layer 34.

[0062] The organic insulating layers 34 and 12 are partially formed in the peripheral region SA. The organic insulating layers 34 and 12 are continuously arranged across the display region DA and the peripheral region SA. Organic insulating layer 12 covers the edge of organic insulating layer 34. An additional organic insulating layer 13 is arranged in the peripheral region SA. Organic insulating layer 13 is formed of an organic insulating material such as polyimide.

[0063] As described above, the PP panel section is equipped with dam structures DS1 and DS2. Dam structure DS1 plays the role of blocking the resin layer RS1 before it hardens during the manufacturing of the display device DSP. Dam structure DS2 plays the role of blocking the resin layer RS2 before it hardens.

[0064] The dam structure DS1 is located in the peripheral region SA between the cut line CL2 and the display region DA. The dam structure DS1 includes dams DM1 and DM2 placed on the organic insulating layer 12, and dam DM3 placed on the circuit layer 11 (inorganic insulating layer 33).

[0065] Dams DM1 and DM2 are formed by the organic insulating layer 13. In this embodiment, dams DM1 and DM2 are made of the same material as the organic insulating layer 13 and are formed in the same layer as the organic insulating layer 13.

[0066] Dams DM1 and DM2 surround bulkhead 6A and protrude above bulkhead 6A. Below dams DM1 and DM2, a portion of metal layers 41 and 42 (a circuit including metal layers 41 and 42) may be located.

[0067] Dam structure DS2 is located in the surrounding region SA between cut line CL2 and cut line CL1. Dam structure DS2 includes dams DM4, DM5, and DM6 which are placed on top of the circuit layer 11 (inorganic insulating layer 33).

[0068] Dams DM1 to DM6 all protrude above the substrate 10. Dams DM1 and DM2 are located higher than the other dams DM3 to DM6. Dams DM1 and DM2 are formed by a different process than, for example, dams DM3 to DM6.

[0069] Dams DM3 to DM6 are formed from organic insulating layers 34 and 12. In this embodiment, dams DM3 to DM6 are made of the same material as organic insulating layers 34 and 12 and are formed in the same layer as organic insulating layers 34 and 12. Furthermore, dams DM3 to DM6 are covered by organic insulating layer 13.

[0070] In the display area DA, the lower electrode LEx is positioned on the organic insulating layer 12. The lower electrode LEx corresponds to one of the lower electrodes LE1, LE2, or LE3 shown in Figure 3. The lower electrode LEx is electrically connected to the metal layer 43 via a contact portion CT2 (shown in Figure 6B) formed on the organic insulating layer 12.

[0071] Furthermore, a portion of the lower electrode LEx (shown as the relay layer RL in Figure 6B) extends to the surrounding region SA. The relay layer RL is located on the display region DA side of the dam DM1 and covers the organic insulating layer 12.

[0072] The relay layer RL is electrically connected to the metal layer 43 via a contact portion CT21 formed on the organic insulating layer 12. The contact portion CT21 is located between the display area DA and the dam DM1. By connecting the relay layer RL and the metal layer 43 at this location, the risk of the relay layer RL becoming disconnected can be reduced.

[0073] In the display area DA, a rib layer 5 is positioned above the lower electrode LEx. The rib layer 5 has a pixel aperture APx. The pixel aperture APx corresponds to one of the pixel apertures AP1, AP2, or AP3 shown in Figures 2 and 3. The rib layer 5 also covers the peripheral area SA. Specifically, as shown in Figure 6A, the rib layer 5 continuously covers the relay layer RL and dams DM1 to DM6.

[0074] In the display area DA, a partition wall 6A is positioned above the rib layer 5. As described above, the partition wall 6A includes a lower section 61 (bottom layer 63, axial layer 64) and an upper section 62 (first top layer 65, second top layer 66).

[0075] A portion of the partition wall 6A is positioned above the relay layer RL in the surrounding region SA. The end of the partition wall 6A has the shape shown in the enlarged view below Figure 6A. Furthermore, the partition wall 6A is electrically connected to the relay layer RL via a contact portion CT3 (shown in Figure 6B) formed in the rib layer 5. Specifically, the lower part 61 of the partition wall 6A (specifically the bottom layer 63) is in contact with the relay layer RL.

[0076] Furthermore, bulkheads 6B (second bulkhead) and 6C are located in the surrounding area SA. Bulkheads 6B and 6C are located outside the dam structure DS1. Bulkhead 6B is located between dam DM3 and dam DM4, between dam DM4 and dam DM5, and between dam DM5 and dam DM6. Between dam DM3 and dam DM4, multiple (e.g., two) bulkheads 6B are lined up on either side of the cut line CL2. Bulkhead 6B is formed along the dam structures DS1 and DS2 and the cut line CL2.

[0077] The partition wall 6B is positioned on top of the rib layer 5. As shown in the enlarged view below Figure 6A, the partition wall 6B includes a lower section 61 (bottom layer 63, axial layer 64) and an upper section 62 (first top layer 65, second top layer 66). In this embodiment, the lower section 61 of the partition wall 6B corresponds to the second lower section, and the upper section 62 of the partition wall 6B corresponds to the second upper section.

[0078] The partition wall 6C covers dams DM4 to dam DM6, respectively. Specifically, the partition wall 6C covers dams DM4 to dam DM6, respectively, via the rib layer 5. As shown in the enlarged view below Figure 6A, the partition wall 6C includes a lower section 61 (bottom layer 63, axial layer 64) and an upper section 62 (first top layer 65, second top layer 66).

[0079] In the display area DA, the multilayer film FLx is positioned on top of the lower electrode LEx. The multilayer film FLx and the partition wall 6A are covered by the sealing layer SE1x (first sealing layer). The shapes of the partition wall 6A, the multilayer film FLx, and the sealing layer SE1x in the display area DA are as described with reference to Figure 3. The multilayer film FLx may also be positioned between the partition wall 6A and the sealing layer SE1x.

[0080] The multilayer film FLx is formed using the same process and materials as any of the multilayer films FL1, FL2, or FL3 shown in Figure 3. The sealing layer SE1x is formed using the same process and materials as any of the sealing layers SE11, SE12, or SE13 shown in Figure 3.

[0081] Focusing on dams DM1 and DM2, dams DM1 and DM2 are not covered by the laminated film FLx and the sealing layer SE1x. The end Ex (second end) of the sealing layer SE1x is located closer to the display area DA than dam DM1.

[0082] Above the sealing layer SE1x, the resin layer RS1 and sealing layer SE2, as shown in Figure 3, are positioned. The resin layer RS1 covers the sealing layer SE1x and the rib layer 5. The resin layer RS1 is located inside the dam structure DS1.

[0083] In the example shown in Figure 6B, the end portion Er1 of the resin layer RS1 is located above the dam DM1. That is, the resin layer RS1 covers a portion of the dam DM1. However, the position of the end portion Er1 is not limited to this example. The resin layer RS1 is surrounded by the sealing layer SE1x, the rib layer 5, and the sealing layer SE2. This prevents moisture from penetrating the resin layer RS1.

[0084] The sealing layer SE2 covers the end portion Er1 of the resin layer RS1. The sealing layer SE2 is in contact with the rib layer 5 in the region outside the end portion Er1. Specifically, as shown in Figure 6A, the sealing layer SE2 covers dams DM2 to DM6, and partitions 6B and 6C. In the surrounding region SA, the area where the sealing layer SE2 and the rib layer 5 are in contact corresponds to a moisture-blocking region that suppresses moisture penetration into the resin layer RS1.

[0085] Furthermore, in the example shown in Figure 6A, a polarizing plate 15 is positioned above the sealing layer SE2. The end 15E of the polarizing plate 15 is located, for example, between cut line CL2 and cut line CL1.

[0086] Here, we focus on the relationship between dams DM1 and DM2 and other elements. The upper surfaces 13S of dams DM1 and DM2 are located above the upper surface SES of the sealing layer SE1x, as shown in Figure 6B. In the example in Figure 6A, the height of dam DM1 is equal to the height of dam DM2, but the height of dam DM1 may be different from the height of dam DM2. For example, the height of dam DM1 may be greater than the height of dam DM2, or the height of dam DM1 may be less than the height of dam DM2.

[0087] Here, the heights of dams DM1 and DM2 correspond to the distance in the Z direction from, for example, the upper surface of the organic insulating layer 12 to the upper surface 13S of dams DM1 and DM2. The height of the resin layer RS1 is shown as height HR (shown in Figure 6B). Height HR is the distance from the upper surface SES of the sealing layer SE1x to the apex of the resin layer RS1. The apex is the position of the resin layer RS1 with the greatest film thickness, and overlaps with, for example, the region where the resin layer RS11 described later is formed.

[0088] The heights of the dams DM1 and DM2 are preferably greater than the height HR of the resin layer RS1. However, due to manufacturing constraints, it may be difficult to make the heights of the dams DM1 and DM2 greater than the height HR of the resin layer RS1. In such cases, the height HR of the resin layer RS1 is preferably, for example, approximately 3 to 5 times the height of the dams DM1 and DM2. This allows the resin layer RS1 to be dammed before it hardens.

[0089] The cross-sectional structure shown in Figure 6A can be applied to any location in the peripheral region SA, except for the area near the terminal T. However, the structure of the peripheral region SA is not necessarily limited to that shown in Figure 6A.

[0090] Next, an example of a manufacturing method for a DSP display device will be described. When manufacturing a DSP display device, a large motherboard is created in which multiple regions (panel sections) are formed, each containing a portion corresponding to the DSP display device.

[0091] Next, an example of a method for manufacturing a display device DSP will be described. Figure 7 is a flowchart of an example of a method for manufacturing a display device DSP. Figures 8A to 8J are schematic cross-sectional views showing the manufacturing process of a display device DSP. In Figures 8A to 8J, the focus is mainly on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0092] In forming the panel portion PP, first, a circuit layer 11 including the inorganic insulating layers 31, 32, 33, an organic insulating layer 34, a plurality of metal layers, and a semiconductor layer is formed on top of the substrate 10 of the mother board MB (step PR1 in Figure 7). In step PR1, an organic insulating layer 34 is formed in the peripheral region SA to form dams DM3 to dams DM6.

[0093] Next, the organic insulating layer 12 is formed (step PR2 in Figure 7). In step PR2, the organic insulating layer 12 covering the organic insulating layer 34 is formed in the peripheral region SA. Thus, after steps PR2 and PR3, dams DM3 to dams DM6 shown in Figure 6A are formed in the peripheral region SA. After step PR2, as shown in Figure 8A, the lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR3 in Figure 7).

[0094] Next, as shown in Figure 8B, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed over the entire motherboard MB (step PR4 in Figure 7). At this point, the pixel apertures AP1, AP2, and AP3 are not yet provided on the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0095] After the formation of the rib layer 5, a process is carried out to form the partition walls 6A, 6B, and 6C (process PR5 in Figure 7). In process PR5, as shown in Figure 8C, a first layer L1 for processing into the bottom layer 63, a second layer L2 for processing into the axial layer 64, a third layer L3 for processing into the first top layer 65, and a fourth layer L4 for processing into the second top layer 66 are sequentially formed over the entire motherboard MB.

[0096] Furthermore, a resist R1 is placed on top of the fourth layer L4. The resist R1 is patterned to match the shape of the partitions 6A, 6B, and 6C. The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can be formed, for example, by sputtering.

[0097] Subsequently, the first layer L1, second layer L2, third layer L3, and fourth layer L4 are patterned using the resist R1 as a mask. In one example, the first layer L1 is formed of titanium nitride, the second layer L2 is formed of aluminum, the third layer L3 is formed of titanium, and the fourth layer L4 is formed of ITO. In this case, the patterning may include wet etching to remove the portion of the fourth layer L4 exposed from the resist R1, dry etching to remove the portions of the first layer L1, second layer L2, and third layer L3 exposed from the resist R1, and wet etching to reduce the width of the second layer L2.

[0098] After step PR5, partition wall 6A is formed in the display area DA, as shown in Figure 8D. Partition walls 6B and 6C are also formed in the surrounding area SA. After the formation of partition walls 6A, 6B, and 6C, the resist R1 is removed (peeled off).

[0099] Next, a process is carried out to create pixel apertures AP1, AP2, and AP3 (process PR6 in Figure 7). In this process PR6, a resist R2 is formed to cover the partition wall 6A, as shown in Figure 8E. Furthermore, dry etching is performed on the rib layer 5 using the resist R2 as a mask. As a result, pixel apertures AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed on the rib layer 5, as shown in Figure 8F. After the dry etching, the resist R2 is removed (peeled off). Note that the pixel apertures AP1, AP2, and AP3 may be formed in front of the partition walls 6A, 6B, and 6C.

[0100] After step PR6, a process is carried out to remove the rib layer 5 from the inspection pad TD shown in Figure 5 (step PR7 in Figure 7). In step PR7, the resist that has been opened in the inspection pad TD is placed on top of the rib layer 5, and dry etching is performed on the rib layer 5.

[0101] After step PR7, a process for forming the display element DE1 is carried out (step PR8 in Figure 7). In forming the display element DE1, first, as shown in Figure 8G, a multilayer film FL1 and a sealing layer SE11 are formed. As shown in Figure 3, the multilayer film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel aperture AP1, an upper electrode UE1 that covers the organic layer OR1, and a cap layer CP1 that covers the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed, for example, by vapor deposition. The sealing layer SE11 can be formed, for example, by CVD.

[0102] The laminated film FL1 and the sealing layer SE11 are formed on the entire motherboard MB, including not only the display area DA of each panel section PP, but also the peripheral area SA and the margin area BA. The laminated film FL1 is divided into multiple parts by overhanging partition walls 6A. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6A.

[0103] Next, the multilayer film FL1 and the sealing layer SE11 are patterned. In this patterning process, as shown in Figure 8G, a resist R3 is placed on top of the sealing layer SE11. The resist R3 covers the subpixel SP1 and a portion of the surrounding partition wall 6A.

[0104] Subsequently, an etching process is performed using resist R3 as a mask. As a result, as shown in Figure 8H, the portions of the multilayer film FL1 and the sealing layer SE11 that are exposed from resist R3 are removed. In other words, the portions of the multilayer film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 are left, and the other portions are removed. This forms the display element DE1 on the sub-pixel SP1. For example, in the peripheral region SA and the margin region BA (shown in Figure 4), the multilayer film FL1 and the sealing layer SE11 are removed by this etching process. This etching process may include wet etching or dry etching performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, resist R3 is removed (peeled off).

[0105] After step PR8, a process for forming the display element DE2 is carried out (step PR9 in Figure 7). The display element DE2 can be formed using the same procedure as the display element DE1. That is, in forming the display element DE2, the multilayer film FL2 and the sealing layer SE12 are formed over the entire mother substrate MB. As shown in Figure 3, the multilayer film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel aperture AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0106] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed, for example, by vapor deposition. The sealing layer SE12 can be formed, for example, by CVD. By patterning such a multilayer film FL2 and sealing layer SE2, a display element DE2 is formed on the sub-pixel SP2, as shown in Figure 8I. For example, in the peripheral region SA and the margin region BA, the multilayer film FL2 and sealing layer SE12 are removed by etching during the patterning process.

[0107] After process PR9, a process for forming the display element DE3 is carried out (process PR10 in Figure 7). The display element DE3 can be formed using the same procedure as for the display elements DE1 and DE2. That is, in forming the display element DE3, the multilayer film FL3 and the sealing layer SE13 are formed over the entire mother substrate MB. As shown in Figure 3, the multilayer film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel aperture AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.

[0108] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed, for example, by vapor deposition. The sealing layer SE13 can be formed, for example, by CVD. By patterning such a multilayer film FL3 and sealing layer SE13, a display element DE3 is formed on the sub-pixel SP3, as shown in Figure 8J. For example, in the peripheral region SA and the blank region BA, the multilayer film FL3 and sealing layer SE13 are removed by etching during the patterning process.

[0109] Note that, while this example assumes that the display elements DE1, DE2, and DE3 are formed in this order, they may be formed in any other order.

[0110] The laminated films FL1, FL2, and FL3 formed by vapor deposition in steps PR8 to PR10 may have poor adhesion to the substrate. Therefore, during the manufacturing of the DSP display device, the laminated films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 covering them may peel off from the substrate.

[0111] The above delamination is likely to occur when the laminated films FL1, FL2, and FL3 are formed continuously over a wide area. In the display area DA, the partition wall 6A finely divides the laminated films FL1, FL2, and FL3. Therefore, the above delamination is suppressed.

[0112] Furthermore, in this embodiment, partition walls 6B and 6C are arranged in the peripheral region SA. As a result, the laminated films FL1, FL2, and FL3 are separated by partition walls 6B and 6C in the peripheral region SA as well, thereby suppressing the peeling described above.

[0113] After step PR10, a resin layer RS1 is formed (step PR11 in Figure 7). The resin layer RS1 can be formed inside the dam structure DS1, for example, by an inkjet method. After step PR11, a sealing layer SE2 is formed over the entire motherboard MB, for example, by CVD (step PR12 in Figure 7).

[0114] After step PR12, etching is performed to remove the rib layer 5 and sealing layer SE2 covering the terminal portion T (step PR13 in Figure 7). This etching is, for example, dry etching.

[0115] After step PR13, the resin layer RS2 is formed (step PR14 in Figure 7). The resin layer RS2 can be formed inside the dam structure DS2, for example, by an inkjet method.

[0116] After step PR14, the polarizing plate 15 is placed on the resin layer RS2 (step PR15 in Figure 7). After step PR15, the motherboard MB is cut along the cut line CL1 (step PR16 in Figure 7).

[0117] Subsequently, the inspection area TA is cut along the cut line CL2 after an inspection process using the inspection pad TD (process PR17 in Figure 7). In process PR17, for example, the polarizing plate 15 is also cut along the cut line CL2.

[0118] This completes the DSP display device. For cutting in steps PR16 and PR17, laser cutting can be used, for example, by irradiating an infrared laser along the cut lines CL1 and CL2. However, cutting in steps PR16 and PR17 may be carried out by other methods such as scribe cutting.

[0119] Next, we will explain the area within the surrounding region SA that includes the dam structure DS1.

[0120] Figures 9A to 9C are schematic cross-sectional views showing the manufacturing process of the DSP display device. In Figures 9A to 9C, we mainly focus on the dams DM1 and DM2 of the dam structure DS1, and omit the elements below the organic insulating layer 12.

[0121] The manufacturing method of the display device DSP according to this embodiment further includes a step of forming the organic insulating layer 13 (step PR20 in Figure 7). In other words, step PR20 corresponds to the step of forming the dams DM1 and DM2 of the dam structure DS1. In this embodiment, step PR20 is performed after the organic insulating layer 12 is formed and before the lower electrodes LE1, LE2, and LE3 are formed.

[0122] Specifically, after step PR2, an organic insulating layer 13 is formed on the organic insulating layer 12, as shown in Figure 9A. The organic insulating layer 13 is formed into a predetermined shape, for example, by photolithography.

[0123] As a result, dams DM1 and DM2 (dam structure DS1) are formed on the organic insulating layer 12 to block the resin layer RS1 before curing. Furthermore, in dams DM3 to DM6, the organic insulating layer 13 covers the organic insulating layer 12, as shown in Figure 6A.

[0124] Next, in step PR4 shown in Figure 7, as shown in Figure 9B, dams DM1 and DM2 are covered by the rib layer 5. The organic insulating layer 13 is placed between the organic insulating layer 12 and the rib layer 5. In other words, dams DM1 and DM2 are not exposed from the rib layer 5.

[0125] Subsequently, through processes PR4 to PR10, a resin layer RS1 is formed inside the dam structure DS1 (process PR11 in Figure 7), and as shown in Figure 9C, the resin layer RS1 and the rib layer 5 are covered with a sealing layer SE2 (process PR12 in Figure 7).

[0126] Here, we will describe an example of the process PR11 for forming the resin layer RS1.

[0127] Figure 10 is a flowchart showing an example of the manufacturing process for the resin layer RS1. Figures 11A to 11C are diagrams illustrating the manufacturing process for the resin layer RS1.

[0128] Process PR11 includes multiple coating steps to form the resin layer RS1. First, as shown in Figure 11A, the material is applied to the outer periphery of the region where the resin layer RS1 will be formed (process PR111 in Figure 10). In Figure 11A, the layer formed by process PR111 is shown as the resin layer RS11. The width of the resin layer RS11 is changed as appropriate.

[0129] Subsequently, the resin layer RS11 is cured by UV irradiation or the like (step PR112 in Figure 10). In step PR112, for example, only the surface of the resin layer RS11 is cured. In Figure 11B, the cured portion is shown as layer H11.

[0130] Next, the material is further applied to the entire region where the resin layer RS1 is formed (step PR113 in Figure 10). In Figure 11C, the layer formed by step PR113 is shown as the resin layer RS12.

[0131] Then, in step PR113, the resin layers RS11 and RS12 are cured. Thus, the resin layer RS1 includes multiple layers (resin layer RS11 and resin layer RS12). Note that step PR113 may include multiple coating steps.

[0132] A portion of the resin layer RS12 is formed on top of layer H11 of the resin layer RS11. Layer H11 has a different surface wettability than the uncured resin layer RS11. Specifically, compared to the uncured resin layer RS11, layer H11 is more susceptible to surface tension acting on the uncured resin layer RS12 applied on top of it.

[0133] As a result, in step PR113, the uncured resin layer RS12 is less likely to overflow outwards from the resin layer RS11. Furthermore, in this embodiment, the uncured resin layer RS1 is dammed up by the dam structure DS1, further suppressing the spreading of the resin layer RS1.

[0134] A display device DSP configured as in this embodiment can improve display quality. In this embodiment, the dams DM1 and DM2 of the dam structure DS1 are arranged above the organic insulating layer 12.

[0135] As a comparative example, we consider the case where dams DM1 and DM2 are formed in the same position as dam DM3. Specifically, we consider the case where dams DM1 and DM2 are placed on top of the circuit layer 11 (inorganic insulating layer 33). Here, the upper surface of the resin layer RS1 in the comparative example is shown as surface S100 by a dashed line in Figure 6B.

[0136] In the comparative example, the film thickness of the resin layer RS1 changes abruptly at the edge WP (shown in Figure 6B). Here, the edge WP is the vicinity region including the edge of the display area DA. For example, the edge WP is the region from the vertex of the resin layer RS1 to the edge of the display area DA.

[0137] A sharp change in the thickness of the resin layer RS1 at the edge WP can cause a decrease in display quality. In Figure 6B, the difference H1 is shown as the difference in the Z direction between the position of the vertex of the resin layer RS1 and the surface S100 of the resin layer RS1 at the edge of the display area DA in the comparative example. In particular, if the width from the display area DA to the cut line CL2 (frame portion) becomes small, it becomes impossible to secure sufficient thickness of the resin layer RS1 placed in the peripheral area SA. This width is, for example, 0.7 to 1 mm.

[0138] Therefore, at the edge WP, the difference H1 increases, and the thickness of the resin layer RS1 tends to change abruptly. Such abrupt changes in thickness can cause changes in brightness at the edge WP. As a result, a brightness difference occurs between the edge WP and the center of the display area DA, which can degrade the display quality of the display device. For example, a frame-shaped brightness unevenness may occur in the display area DA.

[0139] In contrast, in this embodiment, as described above, the dams DM1 and DM2 are placed on the organic insulating layer 12. In other words, compared to the case where the dams DM1 and DM2 are placed on the circuit layer 11, the dams DM1 and DM2 can be placed higher. Therefore, the dams DM1 and DM2 can dam the resin layer RS1 higher than in the comparative example.

[0140] As a result, as shown in Figure 6B, the thickness of the resin layer RS1 at the edge WP is less likely to change abruptly. In this embodiment, the difference in the Z direction between the position of the vertex of the resin layer RS1 and the surface S10 of the resin layer RS1 at the edge of the display area DA is shown as the difference H2.

[0141] In this embodiment, the change in film thickness at the edge WP is smaller than in the comparative example. Specifically, the difference H2 is smaller than the difference H1 (difference H1 > difference H2). In this embodiment, the film thickness of the resin layer RS1 is easier to control.

[0142] As a result, a difference in brightness is less likely to occur between the edge WP and the central part of the display area DA, thereby suppressing a decrease in display quality. In this embodiment, display quality can be improved in particular in narrow-bezel display devices (DSPs). Furthermore, by positioning the resin layer RS1 higher, the amount of resin layer RS1 applied can be increased compared to the comparative example. This further suppresses the difference H2 of the resin layer RS1.

[0143] In addition to those described herein, various other desirable effects can be obtained from this embodiment.

[0144] Next, other embodiments will be described. In the other embodiments described below, components similar to those in the first embodiment described above will be given the same reference numerals as in the first embodiment, and their detailed descriptions may be omitted or simplified. The configurations of the display device DSP, motherboard MB, and panel PP, which are not specifically mentioned, can be the same as in the first embodiment.

[0145] [Second Embodiment] Figure 12 is a schematic cross-sectional view of the panel portion PP in this embodiment. In this embodiment, the configuration of the resin layer RS1 differs from that of the first embodiment. Specifically, the resin layer RS1 does not have the resin layer RS11 shown in Figure 7. The resin layer RS1 is composed of resin layer RS12. In other respects, the film thickness of the resin layer RS1 in this embodiment is smaller than that of the resin layer RS1 in the first embodiment. In this case, the height HR of the resin layer RS1 is also smaller than that of the first embodiment.

[0146] Focusing on the manufacturing process, step PR11 in this embodiment does not include steps PR111 and PR112 in Figure 10. If the thickness of the resin layer RS1 is less than or equal to a predetermined value, it is not necessary to form the resin layer RS11 in advance.

[0147] For example, in the display area DA, if the area of ​​the openings in the partition wall 6A is large, the uncured resin layer RS1 can easily flow into each opening, and the thickness of the resin layer RS1 can be reduced. In other words, if the area of ​​the openings in the partition wall 6A is large, it is less likely that the uncured resin layer RS1 will not flow into the openings, so-called coating gaps will occur.

[0148] Furthermore, the thickness of the resin layer RS1 can be appropriately changed depending on the acceptable size of foreign matter in the manufacturing process. Specifically, by making the thickness of the resin layer RS1 greater than the size of the foreign matter, damage to the sealing layer SE2 by the foreign matter can be suppressed.

[0149] In this embodiment, the same effects as in the first embodiment can be obtained. In this embodiment, the height of the dam can be reduced by reducing the thickness of the resin layer RS1. In addition, in the manufacturing process, steps PR111 and PR112 in step PR20 can be omitted.

[0150] In the first and second embodiments, examples were disclosed in which the dams DM1 and DM2 are formed by an organic insulating layer 13. However, the dams DM1 and DM2 may also be formed by an organic insulating layer 12. In this case, the organic insulating layer 12 and the dams DM1 and DM2 are formed integrally. For example, instead of step PR20, the dams DM1 and DM2 may be formed in step PR1 by applying a halftone mask when forming the organic insulating layer 12.

[0151] Next, the third to seventh embodiments will be described. In the third to seventh embodiments, the process of forming the organic insulating layer 13 and the arrangement of the dams DM1 and DM2 differ from the embodiments described above.

[0152] [Third Embodiment] Figure 13A is a schematic cross-sectional view of the panel section PP in this embodiment. Figure 13B is an enlarged view of the vicinity of dams DM1 and DM2 in Figure 13A. In this embodiment, the lower electrode LEx and the partition wall 6A are arranged continuously from the display area DA to the surrounding area SA.

[0153] As shown in Figures 13A and 13B, the dams DM1 and DM2 are positioned above the partition wall 6A. In this embodiment, a sealing layer SE1x is located between the partition wall 6A and the dams DM1 and DM2. The organic insulating layer 13 is in contact with the sealing layer SE1x. Furthermore, a laminated film FLx may be positioned between the partition wall 6A and the sealing layer SE1x, as shown in Figure 13B.

[0154] Below dams DM1 and DM2, the organic insulating layer 34, organic insulating layer 12, lower electrode LEx (intermediate layer RL), rib layer 5, partition wall 6A, multilayer film FLx, and sealing layer SE1x are stacked in this order.

[0155] In the examples in Figures 13A and 13B, the dam DM1 is in contact with both the resin layer RS11 and the resin layer RS12. The resin layer RS1 is surrounded by the sealing layer SE1x, the dam DM1 (organic insulating layer 13), and the sealing layer SE2. This suppresses the penetration of moisture into the resin layer RS1.

[0156] The end Ex of sealing layer SE1x is located on the cut line CL2 side of dams DM1 and DM2, as shown in Figure 13B. The end Ex of sealing layer SE1x covers the end 6E (first end) of bulkhead 6A. End 6E is located above rib layer 5. Sealing layer SE2 covers the end Ex of sealing layer SE1x. Furthermore, sealing layer SE2 covers dams DM3 and bulkheads 6B and 6C, as shown in Figure 13A.

[0157] Focusing on dam DM3, the rib layer 5, organic insulating layer 13, and sealing layer SE2 are stacked on top of dam DM3 in this order. Also, focusing on dams DM4 through DM6, the rib layer 5, partition wall 6C, organic insulating layer 13, and sealing layer SE2 are stacked on top of dams DM4 through DM6 in this order.

[0158] Next, we will describe the arrangement of dams DM1 and DM2 in a plan view relative to bulkhead 6A.

[0159] Figures 14A to 14D are diagrams illustrating examples of the arrangement of dams DM1 and DM2. In Figures 14A to 14D, the bulkhead 6A and dams DM1 and DM2 are shown, while other elements are omitted. In Figures 14A to 14D, the bulkhead 6A is marked with a dot.

[0160] The partition wall 6A has a plurality of openings 71 (partition wall openings) in the surrounding region SA. The openings 71 are arranged in a matrix in the X and Y directions. The openings 71 have, for example, an elongated shape in the Y direction.

[0161] The partition wall 6A may further have slits 73. Adjacent openings 71 in the X direction may be connected via slits 73. Two or more openings 71 may be connected via slits 73. Also, the widths of the openings 71 in the X direction may differ, as shown in Figures 14A to 14D. Note that the widths of the openings 71 in the X direction and the Y direction can be changed as appropriate. The shape of the openings 71 is not limited to the illustrated examples.

[0162] In the examples in Figures 14A to 14D, dams DM1 and DM2 extend in the Y direction. Dams DM1 and DM2 are positioned between adjacent openings 71 in the X direction. In the example in Figure 14A, dam DM1 does not overlap with slit 73, but dam DM2 does. In other words, dam DM2 intersects with slit 73. In contrast, as in the example in Figure 14B, both dams DM1 and DM2 may overlap with slit 73.

[0163] Furthermore, as shown in the examples in Figures 14C and 14D, both dams DM1 and DM2 do not necessarily overlap the slit 73. In addition, as shown in the example in Figure 14C, dam DM2 may be formed in a zigzag shape. Specifically, dam DM2 may include a portion extending in the X direction and a portion extending in the Y direction.

[0164] Figure 14A discloses an example in which dam DM2 overlaps with slit 73, but dam DM1 may overlap with slit 73 and dam DM2 may not overlap with slit 73. Figure 14C discloses an example in which dam DM2 is formed in a zigzag shape, but dam DM1 may be formed in a zigzag shape, or both dams DM1 and DM2 may be formed in a zigzag shape. In addition, at least one of dams DM1 and DM2 may overlap with opening 71. As described above, various arrangements can be applied to dams DM1 and DM2 depending on the shape and position of opening 71 in the partition wall 6A.

[0165] Next, an example of the manufacturing process for the DSP display device according to this embodiment will be described. Figure 15 is a flowchart of an example of a manufacturing method for the DSP display device. Figure 15 shows a part of the manufacturing process.

[0166] In this embodiment, step PR20 is performed after the step in which the display element DE3 is formed (step PR10 in Figure 15) and before the step in which the resin layer RS1 is formed (step PR11 in Figure 15). This forms dams DM1 and DM2 (dam structure DS1) above the partition wall 6A to block the resin layer RS1 before it hardens. Specifically, dams DM1 and DM2 are formed on the sealing layer SE1x.

[0167] Step PR20 may include a step for baking the organic insulating layer 13. This step removes any moisture that may be present in the organic insulating layer 13. In this embodiment, the resin layer RS1 is in contact with the dam DM1 (organic insulating layer 13). Therefore, by sufficiently removing any moisture that may be present in the organic insulating layer 13, the penetration of moisture into the resin layer RS1 can be further suppressed. This improves the reliability of the display device DSP.

[0168] In this embodiment as well, the same effects as in the first embodiment can be obtained. In this embodiment, the dams DM1 and DM2 are placed on the sealing layer SE1x. As a result, the position of the dams DM1 and DM2 (for example, the distance from the top surface of the substrate 10 to the bottom surface of the dams DM1 and DM2) can be raised compared to the first embodiment.

[0169] In other words, in this embodiment, the positions of dams DM1 and DM2 can be raised without increasing the burden on the manufacturing process. As a result, when the amount of material applied to form the resin layer RS1 is the same, the difference H2 (shown in Figure 6B) can be made smaller than in the first embodiment. Furthermore, in this embodiment, compared to the first embodiment, the area in which the partition wall 6A is formed is wider, so peeling of the laminated film FLx formed in subsequent processes is further suppressed.

[0170] In this embodiment as well, a portion of the metal layers 41 and 42 (the circuit formed by the metal layers 41 and 42) of the circuit layer 11 may be placed below the dams DM1 and DM2.

[0171] [Fourth Embodiment] Figure 16A is a schematic cross-sectional view of the panel section PP in this embodiment. Figure 16B is an enlarged view of the vicinity of dams DM1 and DM2 in Figure 16A. Figure 17A is a schematic cross-sectional view of the panel section PP in this embodiment. Figure 17B is an enlarged view of the vicinity of dams DM1 and DM2 in Figure 17A.

[0172] In this embodiment, the dam structure DS1 differs from the dam structure DS1 in the third embodiment. Specifically, the shape of the dam DM2 differs from the shape of the dam DM2 in the third embodiment.

[0173] Dam DM2 has an extension 131, as shown in Figures 16A and 17A. The extension 131 extends further toward the cut line CL2 than dam DM2. The extension 131 has a smaller thickness than the rest of dam DM2. In the example in Figure 16B, the extension 131 covers the end Ex of the sealing layer SE1x.

[0174] The extension 131 may extend further toward the cut line CL2, as in the example in Figure 17B. Specifically, the extension 131 further covers the end 121 (third end) of the organic insulating layer 12 via the rib layer 5. The end 121 is located outside the end Ex of the sealing layer SE1x. In this case, the extension 131 is in contact with the rib layer 5 between the end 121 and the dam DM3.

[0175] Furthermore, in the example shown in Figure 17, the extension portion 131 is connected to the organic insulating layer 13 that covers the dam DM3. In other words, a portion of the organic insulating layer 13 that forms the dam DM2 covers the dam DM3.

[0176] In this embodiment, step PR20 includes the step of forming the extension portion 131. For example, the extension portion 131 is formed in step PR20 of Figure 15 by, for example, applying a halftone mask.

[0177] In this embodiment as well, the same effects as in the third embodiment can be obtained. In this embodiment, the dam DM2 has an extension portion 131. By covering the end portion Ex with the extension portion 131, the step difference at the end portion Ex can be reduced. In other words, the inclination angle due to the step difference can be reduced.

[0178] This reduces the likelihood of problems such as cracks occurring in the sealing layer SE2 located above the end plate Ex, or disconnections occurring when wiring (e.g., wiring for a touch panel) placed on top of the sealing layer SE2 crosses over the end plate Ex. As a result, the reliability of the display device DSP can be improved.

[0179] Furthermore, in the example shown in Figure 17B, the extension portion 131 is positioned above the end portion 121 of the organic insulating layer 12. This reduces the step at the end portion 121, thereby making defects less likely to occur.

[0180] In the example shown in Figure 17B, the extension portion 131 is shown to be connected to the organic insulating layer 13 covering the dam DM3, but the extension portion 131 does not have to be connected to the organic insulating layer 13 covering the dam DM3. Also, in this embodiment, an example is shown in which the dam DM2 has an extension portion 131, but if only the dam DM1 is placed above the sealing layer SE1x, the dam DM1 may also have an extension portion 131.

[0181] [Fifth Embodiment] Figure 18A is a schematic cross-sectional view of the panel section PP in this embodiment. Figure 18B is an enlarged view of the vicinity of dams DM1 and DM2 in Figure 18A. In this embodiment, dams DM1 and DM2 are positioned on the partition wall 6A, as shown in Figures 18A and 18B. Specifically, dams DM1 and DM2 are in contact with the second top layer 66 (shown in Figure 3) of the upper part 62 of the partition wall 6A.

[0182] Below dams DM1 and DM2, the organic insulating layer 34, organic insulating layer 12, lower electrode LEx (intermediate layer RL), rib layer 5, and partition wall 6A are stacked in this order. Above dams DM1 and DM2, the multilayer film FLx and sealing layer SE1x are stacked in this order. As described above, the multilayer film FLx includes an organic layer containing an emissive layer, an upper electrode, and a cap layer.

[0183] In the example shown in Figure 18A, the resin layer RS1 is surrounded by sealing layers SE1x and SE2. This suppresses the intrusion of moisture into the resin layer RS1. Furthermore, since the dam DM1 is covered by sealing layer SE1x, the intrusion of moisture that may be contained in the organic insulating layer 13 is suppressed.

[0184] As shown in Figure 18B, the end portion Ex of sealing layer SE1x is located on the cut line CL2 side of dams DM1 and DM2 and covers the end portion of partition wall 6A. Sealing layer SE2 covers the end portion Ex of sealing layer SE1x. Sealing layer SE2 is in contact with rib layer 5 in the region outside of end portion Ex. Specifically, sealing layer SE2 covers dam DM3 and partition walls 6B and 6C.

[0185] Focusing on dam DM3, the rib layer 5, organic insulating layer 13, and sealing layer SE2 are stacked on top of dam DM3 in this order. Also, focusing on dams DM4 through DM6, the rib layer 5, partition wall 6C, organic insulating layer 13, and sealing layer SE2 are stacked on top of dams DM4 through DM6 in this order.

[0186] Next, an example of the manufacturing process for the DSP display device according to this embodiment will be described. Figures 19A to 19C are flowcharts showing an example of a manufacturing method for the DSP display device. Figures 19A to 19C show a part of the manufacturing process. In this embodiment, process PR20 is performed before the process in which the display element DE3 is formed (process PR10 in Figure 15).

[0187] In the example in Figure 19A, this is performed after process PR7 and before process PR8. In the example in Figure 19B, this is performed after process PR8 and before process PR9. In the example in Figure 19C, this is performed after process PR9 and before process PR10. As a result, dams DM1 and DM2 (dam structure DS1) are formed on the partition wall 6A. In addition, the laminated film FLx and sealing layer SE1x are laminated on the dams DM1 and DM2.

[0188] In this embodiment as well, the same effects as in the first embodiment can be obtained. In this embodiment, the dams DM1 and DM2 are arranged on the partition wall 6A. As a result, the position of the dams DM1 and DM2 (for example, the distance from the top surface of the substrate 10 to the bottom surface of the dams DM1 and DM2) can be raised compared to the first embodiment.

[0189] Furthermore, in this embodiment, compared to the first embodiment, the area in which the partition wall 6A is formed is wider, which further suppresses delamination of the laminated film FLx formed in subsequent processes.

[0190] Furthermore, in this embodiment, the dams DM1 and DM2 are covered with a sealing layer SE1x. In this embodiment, the sealing layer SE1x can suppress the penetration of moisture that may be contained in the organic insulating layer 13 into the resin layer RS1. This improves the reliability of the display device DSP.

[0191] [Sixth Embodiment] Figure 20A is a schematic cross-sectional view of the panel section PP in this embodiment. Figure 20B is an enlarged view of the vicinity of dams DM1 and DM2 in Figure 20A. This embodiment differs from the third embodiment in that the panel section PP (display device DSP) further comprises a sealing layer 14 (third sealing layer).

[0192] The sealing layer 14 is formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the sealing layer 14 is formed of silicon nitride.

[0193] The sealing layer 14 is located on the dam structures DS1 and DS2, respectively. Specifically, the sealing layer 14 covers dams DM1 through DM6, respectively. Dams DM1 and DM2 are further covered by the sealing layer SE2. In other words, the sealing layer SE2 overlaps the sealing layer 14.

[0194] Focusing on dam DM3, the rib layer 5, organic insulating layer 13, sealing layer 14, and sealing layer SE2 are stacked on top of dam DM3 in this order. Similarly, focusing on dams DM4 through DM6, the rib layer 5, partition wall 6C, organic insulating layer 13, sealing layer 14, and sealing layer SE2 are stacked on top of dams DM4 through DM6 in this order. In other words, the sealing layer 14 is also located outside the dam structure DS1 in the surrounding region SA.

[0195] Next, an example of the manufacturing process for the DSP display device according to this embodiment will be described. Figure 21 is a flowchart of an example of a manufacturing method for the DSP display device. Figure 21 shows a part of the manufacturing process.

[0196] The manufacturing method of the display device DSP according to this embodiment further includes a step of forming a sealing layer 14 (step PR30 in Figure 21). Step PR30 is performed, for example, after the step of forming the organic insulating layer 13 (step PR20) and before the step of forming the resin layer RS1 (step PR11). In step PR30, after the sealing layer 14 is formed in the display area DA and the peripheral area SA, it is patterned to cover dams DM1 to dams DM6.

[0197] In this embodiment, the same effects as in the third embodiment can be obtained. In this embodiment, the dams DM1 and DM2 are covered with a sealing layer 14. In this embodiment, the penetration of moisture that may be contained in the organic insulating layer 13 into the resin layer RS1 is suppressed by the sealing layer 14. This improves the reliability of the display device DSP.

[0198] [Seventh Embodiment] Figure 22 is a schematic cross-sectional view of the panel portion PP in this embodiment. In this embodiment, the arrangement of the sealing layer 14 differs from that of the sixth embodiment. Specifically, the sealing layer 14 is arranged over the entire display area DA and the peripheral area SA. In this embodiment, step PR30 (shown in Figure 21) does not include a step of patterning the sealing layer 14.

[0199] Focusing on the display area DA, the sealing layer 14 is positioned between the sealing layer SE1x and the resin layer RS1. Focusing on the partition wall 6B, the sealing layer 14 and the sealing layer SE2 are stacked on top of the partition wall 6B in that order. Furthermore, the sealing layer 14 is positioned to cover the edges Ex of the sealing layer SE1x.

[0200] In this embodiment as well, the same effects as in the sixth embodiment can be obtained.

[0201] With a display device DSP configured according to the above embodiment, the display quality can be improved. In addition, various other desirable effects can be obtained from each of the above embodiments.

[0202] In the embodiments described above, examples were disclosed in which the dam structure DS1 includes dams DM1 to DM3, but the dam structure DS1 only needs to include dam DM1 and does not need to include at least one of dams DM2 and DM3. In the embodiments disclosed in which the dam structure DS2 includes dams DM4 to DM6, but the dam structure DS2 only needs to include dam DM6 and does not need to include at least one of dams DM4 and DM5.

[0203] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention. Within the scope of the idea of ​​the present invention, a person skilled in the art can conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or modify components, or to add, omit, or change the conditions of the above-described embodiments, are also included within the scope of the present invention insofar as they retain the gist of the present invention.

[0204] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention.

[0205] Hereinafter, an example of a method for manufacturing a display device obtained from the configuration disclosed herein is provided. [Note 1] An organic insulating layer is formed on a substrate having a display area and a peripheral area surrounding the display area, extending across the display area and the peripheral area. In the aforementioned peripheral region, a dam structure is formed above the organic insulating layer. In the display area, a plurality of lower electrodes are formed above the organic insulating layer. Each of the aforementioned multiple lower electrodes has multiple pixel apertures that overlap them, and an inorganic insulating layer is formed to cover the dam structure. It includes a conductive first lower portion disposed above the inorganic insulating layer, and a first upper portion having an end protruding from the side surface of the first lower portion, forming a first partition wall that surrounds each of the plurality of pixel apertures. A plurality of laminated films are formed, each containing an organic layer that covers the lower electrode through the pixel aperture and emits light in response to the application of a voltage. A first sealing layer is formed from an inorganic insulating material and covers the plurality of laminated films. It is positioned inside the dam structure and forms a first resin layer that covers the first sealing layer. A method for manufacturing a display device, including the following. [Note 2] The invention further includes forming a second sealing layer, which is made of an inorganic insulating material and covers the first resin layer, The second sealing layer is in contact with the inorganic insulating layer outside of the first resin layer. A method for manufacturing the display device described in Appendix 1. [Note 3] An organic insulating layer is formed on a substrate having a display area and a peripheral area surrounding the display area, extending across the display area and the peripheral area. In the display area, a plurality of lower electrodes are formed above the organic insulating layer. An inorganic insulating layer having multiple pixel apertures that overlap each of the multiple lower electrodes is formed. It includes a conductive first lower portion disposed above the inorganic insulating layer, and a first upper portion having an end protruding from the side surface of the first lower portion, and each of the multiple pixel apertures in the display area and forms a first partition wall extending from the display area to the peripheral area. A plurality of laminated films are formed, each containing an organic layer that covers the lower electrode through the pixel aperture and emits light in response to the application of a voltage. A first sealing layer is formed from an inorganic insulating material and covers the plurality of laminated films. In the aforementioned surrounding region, a dam structure is formed above the first bulkhead. It is positioned inside the dam structure and forms a first resin layer that covers the first sealing layer. A method for manufacturing a display device, including the following. [Note 4] The formation of the dam structure is carried out after the formation of the first sealing layer. The dam structure is in contact with the first sealing layer. A method for manufacturing the display device described in Appendix 3. [Note 5] The first partition wall has a first end located above the inorganic insulating layer in the peripheral region, The first sealing layer has a second end that covers the first end, Forming the dam structure includes forming an extension that covers the second end. A method for manufacturing the display device described in Appendix 4. [Note 6] The organic insulating layer has a third end located outside the first sealing layer in the peripheral region, Forming the dam structure includes forming the extension that covers the third end, A method for manufacturing the display device described in Appendix 5. [Note 7] The formation of the dam structure is carried out after the formation of the first bulkhead. The dam structure is in contact with the first bulkhead. A method for manufacturing the display device described in Appendix 3. [Note 8] A second sealing layer is formed from an inorganic insulating material and covers the first resin layer. The further step includes forming a third sealing layer, which is made of an inorganic insulating material and covers the dam structure, after forming the dam structure and before forming the second sealing layer. A method for manufacturing the display device described in Appendix 4. [Explanation of Symbols]

[0206] 5…Rib layer, 6A,6B,6C…Partition wall, 10…Substrate, 11…Circuit layer, 12,13,34…Organic insulating layer, 14…Sealing layer, 15…Polarizing plate, 31,32,33…Inorganic insulating layer, 61…Bottom, 62…Top, 71…Aperture, 73…Slit, AP1,AP2,AP3,APx…Pixel aperture, DA…Display area, DE,DE1,DE2,DE3…Display element, DM1,DM2,DM3,D M4, DM5, DM6...dam, DS1, DS2...dam structure, DSP...display device, FL1, FL2, FL3, FLx...multilayer film, LE1, LE2, LE3, LEx...lower electrode, OR1, OR2, OR3...organic layer, RS1, RS2...resin layer, SA...peripheral region, SE11, SE12, SE13, SE1x, SE2...encapsulation layer, SP...sub-pixel, UE1, UE2, UE3...upper electrode.

Claims

1. A substrate having a display area and a peripheral area surrounding the display area, An organic insulating layer is arranged above the substrate, extending over the display area and the peripheral area, In the display area, a plurality of lower electrodes are arranged above the organic insulating layer, An inorganic insulating layer having multiple pixel apertures that overlap each of the multiple lower electrodes, A first partition wall, which surrounds each of the multiple pixel apertures, includes a conductive first lower portion disposed above the inorganic insulating layer and a first upper portion having an end protruding from the side surface of the first lower portion, A plurality of laminated films comprising an organic layer that covers the lower electrode through the pixel aperture and emits light in response to the application of a voltage, A first sealing layer formed of an inorganic insulating material and covering the plurality of laminated films, In the aforementioned peripheral region, a dam structure is provided, which is positioned above the organic insulating layer, surrounds the first partition wall, and protrudes beyond the first partition wall. The dam structure is located inside the dam structure and comprises a first resin layer that covers the first sealing layer. Display device.

2. The dam structure is covered with the inorganic insulating layer. The display device according to claim 1.

3. The upper surface of the dam structure is located above the upper surface of the first sealing layer. The display device according to claim 2.

4. It further comprises a second sealing layer formed of an inorganic insulating material and covering the first resin layer, The second sealing layer is in contact with the inorganic insulating layer outside of the first resin layer. The display device according to claim 2.

5. The second partition wall further includes a second lower portion disposed above the inorganic insulating layer in the peripheral region, and a second upper portion having an end portion protruding from the side surface of the second lower portion. The second sealing layer covers the second partition wall. The display device according to claim 4.

6. A substrate having a display area and a peripheral area surrounding the display area, An organic insulating layer is arranged above the substrate, extending over the display area and the peripheral area, In the display area, a plurality of lower electrodes are arranged above the organic insulating layer, An inorganic insulating layer having multiple pixel apertures that overlap each of the multiple lower electrodes, The first partition wall includes a conductive first lower portion positioned above the inorganic insulating layer, and a first upper portion having an end protruding from the side surface of the first lower portion, each of which surrounds a plurality of the pixel apertures in the display area, and which extends from the display area to the peripheral area. A plurality of laminated films comprising an organic layer that covers the lower electrode through the pixel aperture and emits light in response to the application of a voltage, A first sealing layer formed of an inorganic insulating material and covering the plurality of laminated films, In the aforementioned surrounding region, a dam structure is positioned above the first bulkhead, The dam structure is located inside the dam structure and comprises a first resin layer that covers the first sealing layer. Display device.

7. The laminated film and the first sealing layer are located between the first partition wall and the dam structure. The display device according to claim 6.

8. The first partition wall has a first end located above the inorganic insulating layer in the peripheral region, The first sealing layer has a second end that covers the first end, The dam structure has an extension that covers the second end. The display device according to claim 7.

9. The organic insulating layer has a third end located outside the first sealing layer in the peripheral region, The extension covers both the second end and the third end. The display device according to claim 8.

10. The dam structure is in contact with the first upper part of the first bulkhead. The display device according to claim 6.

11. Above the dam structure, the laminated film and the first sealing layer are stacked in this order. The display device according to claim 10.

12. A second sealing layer formed of an inorganic insulating material and covering the first resin layer, The second partition wall further includes a second lower portion disposed above the inorganic insulating layer in the peripheral region, and a second upper portion having an end portion protruding from the side surface of the second lower portion. The second sealing layer covers the second partition wall. The display device according to claim 11.

13. A second sealing layer formed of an inorganic insulating material and covering the first resin layer, It further comprises a third sealing layer made of an inorganic insulating material that covers the dam structure, The second sealing layer overlaps the third sealing layer. The display device according to claim 7.

14. The third sealing layer is positioned outside the dam structure in the surrounding region. The display device according to claim 13.

15. The third sealing layer is positioned between the first sealing layer and the first resin layer in the display area. The display device according to claim 14.

16. The second partition wall further includes a second lower portion disposed above the inorganic insulating layer in the peripheral region, and a second upper portion having an end portion protruding from the side surface of the second lower portion. The second sealing layer covers the second partition wall. The display device according to claim 13.

17. The first partition wall further has a plurality of partition wall openings in the surrounding region, The dam structure is positioned between the adjacent partition wall openings. The display device according to claim 6.

18. The first partition wall further has slits connecting the multiple adjacent partition wall openings, The dam structure overlaps the slit, The display device according to claim 17.

19. The first partition wall further has slits connecting the multiple adjacent partition wall openings, The dam structure does not overlap the slit. The display device according to claim 17.

20. The dam structure further comprises a metal layer disposed between the substrate and the organic insulating layer below the dam structure. The display device according to any one of claims 1 to 19.

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