Silicon carbide semiconductor equipment

Abstract

To provide a silicon carbide semiconductor device that achieves good connection reliability between a source electrode and a silicon carbide substrate. 【Solution】A silicon carbide semiconductor device 100 includes: a silicon carbide substrate 20 having a first main surface 1 and a second main surface 2 opposing the first main surface 1; a first ohmic electrode 41 containing Ti or Mg; a second ohmic electrode 42 containing nickel; a source electrode 44; and a drain electrode 45. The silicon carbide substrate has an n-type source region and drift region 11, and p-type body region 12 and contact region 14. The first ohmic electrode is in contact with the source region, the second ohmic electrode is in contact with the contact region, and the source electrode is connected to the first ohmic electrode and the second ohmic electrode. The source region contains an n-type impurity at 5×10 18 cm -3 to 1×10 21 cm -3 in concentration, and the contact region contains a p-type impurity at 1×10 19 cm -3 to 5×10 21 cm -3 in concentration.

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide semiconductor device.

Background Art

[0002] A silicon carbide semiconductor device having an ohmic electrode between a source electrode and a silicon carbide substrate is disclosed.

Prior Art Literature

Patent Literature

[0003]

Patent Literature 1

Patent Literature 2

Summary of Invention

Problem to be Solved by the Invention

[0004] In recent years, there has been an increasing demand for improving connection reliability between a source electrode and a silicon carbide substrate.

[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device that can achieve excellent connection reliability between a source electrode and a silicon carbide substrate.

Means for Solving the Problem

[0006] The silicon carbide semiconductor device of this disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, a first ohmic electrode containing titanium or magnesium, a second ohmic electrode containing nickel, a source electrode, and a drain electrode, wherein the silicon carbide substrate has an n-type conductivity and a source region having the first main surface, an n-type conductivity and a drift region provided between the source region and the second main surface, a p-type conductivity and a body region provided between the source region and the drift region, and a p-type conductivity and a contact region having the first main surface and contacting the body region, the first ohmic electrode making ohmic contact with the source region, the second ohmic electrode making ohmic contact with the contact region, the source electrode being electrically connected to the first and second ohmic electrodes, the drain electrode being electrically connected to the drift region, and the source region containing 5 × 10 n-type impurities. 18 cm -3 The above 1 x 10 21 cm -3 The following effective concentrations are contained, and the contact region contains 1 × 10⁻⁶ p-type impurities. 19 cm -3 The above 5 x 10 21 cm -3 It contains the following effective concentrations. [Effects of the Invention]

[0007] According to this disclosure, good connection reliability can be obtained between the source electrode and the silicon carbide substrate. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows the configuration of the interlayer insulating film and the first main surface in a silicon carbide semiconductor device according to an embodiment. [Figure 2] Figure 2 is a cross-sectional view (part 1) showing the configuration of a silicon carbide semiconductor device according to the embodiment. [Figure 3] Figure 3 is a cross-sectional view (part 2) showing the configuration of a silicon carbide semiconductor device according to the embodiment. [Figure 4]Figure 4 shows the first ohmic electrode and its vicinity above the source region. [Figure 5] Figure 5 shows the silicon concentration distribution in and around the first ohmic electrode above the source region. [Figure 6] Figure 6 shows the second ohmic electrode and its vicinity above the contact area. [Figure 7] Figure 7 shows the silicon concentration distribution in and around the second ohmic electrode above the contact region. [Figure 8] Figure 8 is a cross-sectional view (part 1) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 9] Figure 9 is a cross-sectional view (part 2) showing a method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 10] Figure 10 is a cross-sectional view (part 3) showing a method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 11] Figure 11 is a cross-sectional view (part 4) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 12] Figure 12 is a cross-sectional view (part 5) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 13] Figure 13 is a cross-sectional view (part 6) showing a method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 14] Figure 14 is a cross-sectional view (part 7) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 15] Figure 15 is a cross-sectional view (part 8) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 16] Figure 16 is a cross-sectional view (part 9) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 17] Figure 17 is a cross-sectional view (part 10) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 18] Figure 18 is a cross-sectional view (part 11) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 19] Figure 19 is a cross-sectional view (part 12) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 20] Figure 20 is a top view showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Modes for carrying out the invention]

[0009] The implementation methods are described below.

[0010] [Description of Embodiments in this Disclosure] The embodiments of this disclosure are listed and described below. In the following description, the same or corresponding elements are denoted by the same reference numeral, and the same description is not repeated. In the crystallographic descriptions herein, individual orientations are indicated by [], collective orientations by <>, individual planes by () and collective planes by {}. Also, while negative crystallographic exponents are usually indicated by placing a "-" (bar) above the number, in this disclosure a negative sign is placed before the number. Also, the following description uses the XYZ Cartesian coordinate system, but this coordinate system is defined for illustrative purposes and is not limited to the orientation of the silicon carbide semiconductor device. Also, from any point, the +Z direction may be referred to as upward, upper side, or up, and the -Z direction may be referred to as downward, lower side, or down.

[0011] [(1) A silicon carbide semiconductor device according to one aspect of the present disclosure comprises: a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface; a first ohmic electrode containing titanium or magnesium; a second ohmic electrode containing nickel; a source electrode; and a drain electrode, wherein the silicon carbide substrate comprises: a source region having n-type conductivity and having the first main surface; a drift region having n-type conductivity and provided between the source region and the second main surface; a body region having p-type conductivity and provided between the source region and the drift region; and a contact region having p-type conductivity, having the first main surface and being in contact with the body region, the first ohmic electrode is in ohmic contact with the source region, the second ohmic electrode is in ohmic contact with the contact region, the source electrode is electrically connected to the first ohmic electrode and the second ohmic electrode, the drain electrode is electrically connected to the drift region, and the source region contains n-type impurities at 5×10 18 cm -3 to 1×10 21 cm -3 inclusive in terms of effective concentration, and the contact region contains p-type impurities at 1×10 19 cm -3 to 5×10 21 cm -3 inclusive in terms of effective concentration.

[0012] The source region contains n-type impurities at an effective concentration of 5×10 18 cm -3 or higher, and the first ohmic electrode contains titanium or magnesium. Further, the contact region contains p-type impurities at 1×10 19 cm -3The material contains the above effective concentration, and the second ohmic electrode contains nickel. Therefore, during the manufacturing of silicon carbide semiconductor devices, alloying annealing of the first and second ohmic electrodes is not required, and the first ohmic electrode can be made to make ohmic contact with the source region, and the second ohmic electrode can be made to make ohmic contact with the contact region. Consequently, deformation of the first and second ohmic electrodes due to alloying annealing is avoided, and a decrease in connection reliability between the source electrode and the source region and the contact region due to deformation is avoided. In other words, good connection reliability can be obtained. Note that the source region contains 1 × 10⁻⁶ n-type impurities. 21 cm -3 It contains in an effective concentration of more than 5 × 10⁻⁶, or the contact area contains p-type impurities. 21 cm -3 When contained at ultra-high effective concentrations, numerous crystal defects may be present in the source or contact region, potentially leading to increased leakage between the source electrode and the drain electrode.

[0013] [2] In [1], the source region contains the n-type impurities, 5 × 10 19 cm -3 The above 1 x 10 20 cm -3 The following effective concentrations are contained, and the contact region contains the p-type impurities at 1 × 10⁻⁶ concentrations. 20 cm -3 The above 1 x 10 21 cm -3 It may be included at the following effective concentrations. In this case, better connection reliability is easier to obtain, and leakage is less likely to occur.

[0014] [3] In [1] or [2], the first ohmic electrode may cover the second ohmic electrode. In this case, the first ohmic electrode can make it less likely for interdiffusion to occur between the second ohmic electrode and the source electrode. In addition, since etching or other processing of the first ohmic electrode is unnecessary, an increase in processing time and cost can be avoided.

[0015] [4] In [3], a barrier film containing titanium nitride may be provided between the first ohmic electrode and the second ohmic electrode and the source electrode. In this case, interdiffusion between the source electrode and the first and second ohmic electrodes can be made less likely. In addition, deformation of the first and second ohmic electrodes due to alloying annealing can be avoided, so the shape of the barrier film is stable and good barrier properties can be obtained.

[0016] [5] In any of [1] to [4], the source electrode may contain aluminum. In this case, a low electrical resistance is obtained in the source electrode in the contact region having a p-type conductivity.

[0017] [6] In any of [1] to [5], the first ohmic electrode and the second ohmic electrode do not need to contain aluminum. In this case, a low contact resistance is obtained in the source region having an n-type conductivity.

[0018] [7] In any of [1] to [6], the first ohmic electrode has a first surface facing the first main surface and a second surface opposite to the first surface, and the second ohmic electrode has a third surface facing the first main surface and a fourth surface opposite to the third surface, and the arithmetic mean roughness of each of the first, second, third, and fourth surfaces may be 10 nm or less. If alloying annealing of the first and second ohmic electrodes is not performed, the arithmetic mean roughness Ra of each of the first, second, third, and fourth surfaces tends to be 10 nm or less, and good connection reliability is easily obtained.

[0019] [8] In any of [1] to [7], the first ohmic electrode has a first transition layer in contact with the first main surface, the first transition layer contains silicon at a concentration of 0.1 to 0.9 times the maximum silicon concentration in the silicon carbide substrate, the second ohmic electrode has a second transition layer in contact with the first main surface, the second transition layer contains silicon at a concentration of 0.1 to 0.9 times the maximum silicon concentration in the silicon carbide substrate, and the thickness of the first transition layer and the second transition layer may be 20 nm or less. If alloying annealing of the first ohmic electrode and the second ohmic electrode is not performed, the thickness of the first transition layer and the second transition layer tend to be 20 nm or less, making it easy to obtain low contact resistance.

[0020] [9] In any of [1] to [8], the device has a gate insulating film that contacts the body region, a gate electrode that sandwiches the gate insulating film between itself and the body region, and an interlayer insulating film that covers the gate electrode, wherein contact holes reaching the source region and the contact region are formed in the interlayer insulating film. In this case, the source electrode can be electrically connected to the source region and the contact region through the contact holes.

[0021]

[10] In [9], the interlayer insulating film may include a first insulating film containing undoped silicon oxide and covering the gate electrode, and a second insulating film containing boric phosphate glass and covering the first insulating film. In this case, the shape of the contact hole can be stabilized while a curved surface can be provided on the second insulating film to improve the coverage of the source electrode. Furthermore, the boric phosphate glass has a gettering effect on light metals such as sodium and potassium from the outside.

[0022]

[11] In [9] or

[10] , the first main surface is provided with a gate trench having a side surface that penetrates the source region and the body region and reaches at least the drift region, and a bottom surface connected to the side surface, and the gate insulating film may be in contact with the side surface and the bottom surface. In this case, the transistor can be easily integrated.

[0023]

[12] In any of [9] to

[11] , the first ohmic electrode and the second ohmic electrode may cover the interlayer insulating film. In this case, the precision required for processing the first ohmic electrode and the second ohmic electrode can be relaxed, and it is possible to form elements with a narrow cell pitch.

[0024] [Embodiments of this Disclosure] The embodiment relates to a so-called vertical MOS (metal oxide semiconductor) type field-effect transistor (FET) using silicon carbide. This MOS type FET is an example of a silicon carbide semiconductor device. Figure 1 is a diagram showing the configuration of the interlayer insulating film and the first main surface in the silicon carbide semiconductor device according to the embodiment. Figures 2 and 3 are cross-sectional views showing the configuration of the silicon carbide semiconductor device according to the embodiment. Figure 2 corresponds to a cross-sectional view along the line II-II in Figure 1. Figure 3 corresponds to a cross-sectional view along the line III-III in Figure 1.

[0025] As shown in Figures 1 to 3, the silicon carbide semiconductor device 100 according to the embodiment includes a silicon carbide substrate 20, a gate insulating film 31, a gate electrode 32, a first ohmic electrode 41, a second ohmic electrode 42, a barrier film 43, a source electrode 44, a drain electrode 45, and an interlayer insulating film 35.

[0026] The silicon carbide substrate 20 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is on the +Z side with respect to the second main surface 2. The silicon carbide substrate 20 includes a silicon carbide single crystal substrate 21 and a silicon carbide epitaxial layer 10. The silicon carbide epitaxial layer 10 is on the silicon carbide single crystal substrate 21. The first main surface 1 is on the silicon carbide epitaxial layer 10, and the second main surface 2 is on the silicon carbide single crystal substrate 21. The silicon carbide single crystal substrate 21 and the silicon carbide epitaxial layer 10 are formed of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 21 contains n-type impurities such as nitrogen (N) and has an n-type conductivity type (first conductivity type). Hereafter, a plan view perpendicular to the first principal plane 1 will simply be referred to as a plan view.

[0027] The first main surface 1 is the {0001} surface or a surface inclined by an off-angle of 8° or less in the off-direction. Preferably, the first main surface 1 is the (000-1) surface or a surface inclined by an off-angle of 8° or less in the off-direction. The first main surface 1 may also be the (0001) surface or a surface inclined by an off-angle of 8° or less in the off-direction. The off-direction may be, for example, the <11-20> direction or the <1-100> direction. The off-angle may be, for example, 1° or more or 2° or more. The off-angle may be 6° or less or 4° or less.

[0028] The silicon carbide epitaxial layer 10 has a drift region 11, a body region 12, a source region 13, a contact region 14, and an electric field relaxation region 15. The drift region 11 has a first drift region 11A and a second drift region 11B. The source region 13 and the contact region 14 have a first main surface 1.

[0029] The source region 13 has a first main surface 1. The source region 13 extends along the X axis. The source region 13 contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity. The source region 13 contains n-type impurities in 5 × 10⁻⁶ units. 18 cm -3 The above 1 x 1021 cm -3 The following effective concentrations are present. Source region 13 contains n-type impurities at 3 × 10⁻⁶ concentrations. 19 cm -3 The above 3 x 10 20 cm -3 It may be contained in the following effective concentrations: 5 × 10 19 cm -3 The above 1 x 10 20 cm -3 It may be contained at the following effective concentrations.

[0030] The contact region 14 has a first main surface 1. The contact region 14 extends along the X-axis. The contact region 14 is in contact with the source region 13. The source region 13 and the contact region 14 are arranged alternately along the Y-axis. The contact region 14 contains p-type impurities such as aluminum (Al) and has a p-type conductivity. The contact region 14 contains p-type impurities in a quantity of 1 × 10⁻¹⁶ 19 cm -3 The above 5 x 10 21 cm -3 It contains the following effective concentrations. Contact region 14 contains p-type impurities at 1 × 10⁻⁶ levels. 20 cm -3 The above 5 x 10 21 cm -3 It may be contained at the following effective concentrations: 1 × 10 20 cm -3 The above 1 x 10 21 cm -3 It may be contained in the following effective concentrations: 3 × 10 20 cm -3 The above 8 x 10 20 cm -3 It may be contained at the following effective concentrations.

[0031] In this disclosure, the effective concentration of n-type impurities is the concentration obtained by subtracting the concentration of p-type impurities from the concentration of n-type impurities, and the effective concentration of p-type impurities is the concentration obtained by subtracting the concentration of n-type impurities from the concentration of p-type impurities. The effective concentrations can be measured, for example, using a scanning capacitance microscope (SCM). Furthermore, the effective concentration of impurities contained in each region is the average value of the effective concentrations of impurities contained in that region.

[0032] The body region 12 is located between the source region 13 and the contact region 14 and the second main surface 2. The body region 12 is in contact with the source region 13 and the contact region 14. The lower end surfaces of the source region 13 and the contact region 14 are in contact with the upper end surface of the body region 12. The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type conductivity (second conductivity).

[0033] The first drift region 11A is located between the body region 12 and the second main surface 2. The first drift region 11A is in contact with the body region 12. The lower end surface of the body region 12 and the upper end surface of the first drift region 11A are in contact with each other. The first drift region 11A extends along the Y-axis. Multiple first drift regions 11A are provided along the X-axis at regular intervals (first pitch P1). The first drift region 11A contains n-type impurities such as nitrogen (N) or phosphorus (P) and has an n-type conductivity. The source region 13 and the first drift regions 11A are separated from each other by the body region 12.

[0034] The electric field relaxation region 15 is located between the body region 12 and the second main surface 2. The electric field relaxation region 15 is in contact with the body region 12 and the first drift region 11A. The lower end surface of the body region 12 and the upper end surface of the electric field relaxation region 15 are in contact with each other. The electric field relaxation region 15 extends along the Y-axis. Multiple electric field relaxation regions 15 are provided along the X-axis at regular intervals (first pitch P1). The first drift region 11A and the electric field relaxation region 15 are arranged alternately along the X-axis. The lower end surface of the first drift region 11A and the lower end surface of the electric field relaxation region 15 may or may not be flush. The electric field relaxation region 15 contains p-type impurities such as aluminum (Al) and has a p-type conductivity. The contact region 14, the body region 12, and the electric field relaxation region 15 are electrically connected to each other. The contact region 14 may be in contact with the electric field relaxation region 15.

[0035] The second drift region 11B is located between the first drift region 11A and the field relaxation region 15 and the second main surface 2. The second drift region 11B is in contact with the first drift region 11A and the field relaxation region 15. The lower end surfaces of the first drift region 11A and the lower end surfaces of the field relaxation region 15 are in contact with the upper end surface of the second drift region 11B. The second drift region 11B contains n-type impurities such as nitrogen (N) or phosphorus (P) at a lower concentration than the first drift region 11A and has an n-type conductivity. The second drift region 11B may be in contact with the silicon carbide single crystal substrate 21. A buffer layer containing n-type impurities such as nitrogen (N) and having an n-type conductivity may be present between the second drift region 11B and the silicon carbide single crystal substrate 21.

[0036] A gate trench 5 is located on the first main surface 1. The gate trench 5 comprises a side surface 3 that penetrates the source region 13 and the body region 12 and reaches the first drift region 11A, and a bottom surface 4 connected to the side surface 3. The gate trench 5 is defined by the side surface 3 and the bottom surface 4. The bottom surface 4 is located in the first drift region 11A. In plan view, the gate trench 5 overlaps with the first drift region 11A. The gate trench 5 extends along the Y-axis. Multiple gate trenches 5 are provided along the X-axis at regular intervals (first pitch P1). The electric field relaxation region 15 is separated from the gate trench 5. For example, the bottom surface 4 is parallel to the first main surface 1 and the second main surface 2. In a cross-sectional view perpendicular to the Y-axis, the angle θ1 of the side surface 3 with respect to the virtual plane 9 containing the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. Side surface 3 has, for example, a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent electron mobility. The angle θ1 may be, for example, 80° or more and 90° or less.

[0037] Along the Z-axis, there is a silicon carbide single crystal substrate 21, a second drift region 11B, and a first drift region 11A between the bottom surface 4 and the second main surface 2, and the conductivity type of the silicon carbide substrate 20 between the bottom surface 4 and the second main surface 2 is n-type.

[0038] Multiple gate trenches 5 may be arranged at regular intervals along the Y-axis. If multiple gate trenches 5 are arranged at regular intervals along the Y-axis, a portion of the contact area 14 may be located between adjacent gate trenches 5 along the Y-axis. Multiple gate trenches 5 may be arranged in an array in a plan view.

[0039] The gate insulating film 31 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 31 is, for example, an oxide film. The gate insulating film 31 contains, for example, silicon dioxide (SiO2). The gate insulating film 31 is in contact with the first drift region 11A at the bottom surface 4. The gate insulating film 31 is in contact with the source region 13, the body region 12 and the first drift region 11A at the side surface 3. The gate insulating film 31 may also be in contact with the source region 13 at the first main surface 1.

[0040] The gate electrode 32 has a gate insulating film 31 sandwiched between it and the body region 12. The gate electrode 32 rests on the gate insulating film 31, and the gate insulating film 31 is sandwiched between it and the silicon carbide substrate 20. The gate electrode 32 contains, for example, polycrystalline silicon containing conductive impurities. The gate electrode 32 faces the side surface 3 and the bottom surface 4. The gate electrode 32 extends along the Y axis. In a plan view, the gate electrode 32 may overlap with a plurality of gate trenches 5 aligned along the Y axis.

[0041] The interlayer insulating film 35 covers the gate electrode 32. The interlayer insulating film 35 has insulating films 33 and 34. Insulating film 33 is in contact with the upper surface of the gate electrode 32 and the upper surface of the gate insulating film 31. Insulating film 34 is on top of insulating film 33. Insulating films 33 and 34 are, for example, oxide films. Insulating film 33 is, for example, a non-doped silicate glass (NSG) film. Insulating film 34 is, for example, a borophosphosilicate glass (BPSG) film. Insulating film 34 has a curved surface that is convex when viewed from the gate electrode 32. Insulating film 33 is an example of a first insulating film, and insulating film 34 is an example of a second insulating film.

[0042] Contact holes 39 are formed in the interlayer insulating film 35 and the gate insulating film 31 at regular intervals (first pitch P1) along the X-axis. The contact holes 39 are arranged such that the gate electrode 32 is positioned between adjacent contact holes 39 along the X-axis. The contact holes 39 extend along the Y-axis. The contact holes 39 reach the source region 13 and the contact region 14.

[0043] As shown in Figure 3, the second ohmic electrode 42 is located on the contact region 14. The second ohmic electrode 42 contains nickel (Ni) and makes ohmic contact with the contact region 14. The second ohmic electrode 42 is, for example, a Ni layer. The second ohmic electrode 42 also contacts the gate insulating film 31 and the interlayer insulating film 35. The second ohmic electrode 42 extends along the X-axis. The second ohmic electrode 42 covers the contact region 14 and a portion of the gate insulating film 31 and the interlayer insulating film 35.

[0044] As shown in Figures 2 and 3, the first ohmic electrode 41 is located on the source region 13 and the second ohmic electrode 42. The first ohmic electrode 41 contains titanium (Ti) or magnesium (Mg) and makes ohmic contact with the source region 13. The first ohmic electrode 41 is, for example, a titanium layer or a magnesium layer. The first ohmic electrode 41 also contacts the gate insulating film 31 and the interlayer insulating film 35. The first ohmic electrode 41 covers the source region 13, the second ohmic electrode 42, and the portions of the gate insulating film 31 and the interlayer insulating film 35 exposed from the second ohmic electrode 42.

[0045] The barrier film 43 is located on the first ohmic electrode 41. The barrier film 43 contains titanium nitride (TiN), for example, a TiN layer. The barrier film 43 covers the first ohmic electrode 41 and is in contact with the first ohmic electrode 41.

[0046] The source electrode 44 is located on the barrier film 43. The source electrode 44 contains aluminum (Al) and is, for example, an aluminum layer or an aluminum alloy layer. The source electrode 44 covers the barrier film 43 and is in contact with the barrier film 43. The source electrode 44 is electrically connected to the first ohmic electrode 41 and the second ohmic electrode 42. The barrier film 43 is provided between the first ohmic electrode 41 and the second ohmic electrode 42 and the source electrode 44. The gate electrode 32 and the source electrode 44 are electrically insulated from each other by the interlayer insulating film 35.

[0047] A passivation film may be present, covering a portion of the source electrode 44.

[0048] Here, the first ohmic electrode 41 and the second ohmic electrode 42 will be described in detail. Figure 4 shows the first ohmic electrode 41 and its vicinity on the source region 13. Figure 5 shows the silicon concentration distribution on the first ohmic electrode 41 and its vicinity on the source region 13. Figure 6 shows the second ohmic electrode 42 and its vicinity on the contact region 14. Figure 7 shows the silicon concentration distribution on the second ohmic electrode 42 and its vicinity on the contact region 14. In Figures 5 and 7, the silicon concentration on the vertical axis is normalized by the maximum silicon concentration in the silicon carbide substrate 20.

[0049] As shown in Figure 4, the first ohmic electrode 41 has a first surface 411 facing the first main surface 1 and a second surface 412 opposite to the first surface 411. For example, the first surface 411 is in contact with the first main surface 1. The arithmetic mean roughness Ra of each of the first surface 411 and the second surface 412 is 10 nm or less. The arithmetic mean roughness Ra can be measured using a transmission electron microscope (TEM).

[0050] The first ohmic electrode 41 has a first transition layer 415 that contacts the first main surface 1. As shown in Figure 5, the first transition layer 415 is a layer containing silicon at a concentration of 0.1 to 0.9 times the maximum silicon concentration in the silicon carbide substrate 20. The thickness T1 of the first transition layer 415 is, for example, 20 nm or less. The thickness T1 may be 10 nm or less, or 5 nm or less. The thickness T1 is the dimension of the first transition layer 415 along the Z axis and can be measured using a TEM.

[0051] As shown in Figure 6, the second ohmic electrode 42 has a third surface 421 facing the first main surface 1 and a fourth surface 422 opposite to the third surface 421. For example, the third surface 421 is in contact with the first main surface 1. The arithmetic mean roughness Ra of the third surface 421 and the fourth surface 422 is 10 nm or less. The arithmetic mean roughness Ra can be measured using a TEM.

[0052] The second ohmic electrode 42 has a second transition layer 425 that contacts the first main surface 1. As shown in Figure 7, the second transition layer 425 is a layer containing silicon at a concentration of 0.1 to 0.9 times the maximum silicon concentration in the silicon carbide substrate 20. The thickness T2 of the second transition layer 425 is, for example, 20 nm or less. The thickness T2 may be 10 nm or less, or 5 nm or less. The thickness T2 is the dimension of the second transition layer 425 along the Z axis and can be measured using a TEM.

[0053] The drain electrode 45 is in contact with the second main surface 2. The drain electrode 45 is in contact with the silicon carbide single crystal substrate 21 on the second main surface 2. The drain electrode 45 is electrically connected to the drift region 11. The drain electrode 45 includes, for example, nickel silicide (NiSi). The drain electrode 45 may also include titanium (Ti), aluminum (Al), and silicon (Si). The drain electrode 45 is in ohmic contact with the silicon carbide single crystal substrate 21.

[0054] Next, a method for manufacturing the silicon carbide semiconductor device 100 will be described. Figures 8 to 19 are cross-sectional views showing the manufacturing method of the silicon carbide semiconductor device 100 according to an embodiment. Figures 8 to 16 show the changes in the cross-section shown in Figure 2, and Figures 17 to 19 show the changes in the cross-section shown in Figure 3. Figure 20 is a top view showing the manufacturing method of the silicon carbide semiconductor device 100 according to an embodiment.

[0055] First, as shown in Figure 8, a silicon carbide single crystal substrate 21 is prepared, and an n-type semiconductor layer 71 and an n-type semiconductor layer 72 are formed on the silicon carbide single crystal substrate 21 as a second drift region 11B. The n-type semiconductor layer 71 contains n-type impurities at the same concentration as the second drift region 11B, and the n-type semiconductor layer 72 contains n-type impurities at the same concentration as the first drift region 11A.

[0056] Next, as shown in Figure 9, an electric field relaxation region 15 is formed in the n-type semiconductor layer 72. In forming the electric field relaxation region 15, for example, channeling and random implantation of p-type impurities are performed.

[0057] Next, as shown in Figures 10 and 17, a body region 12, a source region 13, and a contact region 14 are formed in the n-type semiconductor layer 72. Ion implantation of p-type impurities is performed during the formation of the body region 12 and the contact region 14, and ion implantation of n-type impurities is performed during the formation of the source region 13. The remaining portion of the n-type semiconductor layer 72 becomes the first drift region 11A.

[0058] Next, as shown in Figure 11, a gate trench 5 is formed on the first main surface 1, and a gate insulating film 31 and a gate electrode 32 are formed.

[0059] Next, as shown in Figure 12, an interlayer insulating film 35 having insulating films 33 and 34 is formed, and contact holes 39 are formed in the interlayer insulating film 35 and the gate insulating film 31. For example, insulating film 33 is an NSG film, and insulating film 34 is a BPSG film.

[0060] Next, as shown in Figure 13, annealing is performed at a temperature at which the gate insulating film 31 and insulating film 33 do not soften, but the insulating film 34 softens, for example, a temperature between 800°C and 1000°C. As a result, the insulating film 34 flows, and a curved surface is formed on the insulating film 34 that is convex when viewed from the gate electrode 32.

[0061] Next, as shown in Figures 14 and 18, a second ohmic electrode 42 is formed on the source region 13, the contact region 14, and the interlayer insulating film 35. The second ohmic electrode 42 covers the source region 13, the contact region 14, the gate insulating film 31, and the interlayer insulating film 35.

[0062] Next, as shown in Figures 15 and 20, the second ohmic electrode 42 is etched along the X-axis so that the source region 13 is exposed from the second ohmic electrode 42. After etching, the second ohmic electrode 42 covers the contact region 14 and a portion of the gate insulating film 31 and interlayer insulating film 35, and makes ohmic contact with the contact region 14, as shown in Figure 18. The etching of the second ohmic electrode 42 is performed by, for example, wet etching. Figure 15 corresponds to a cross-sectional view along the line XV-XV in Figure 20. Figure 18 corresponds to a cross-sectional view along the line XVIII-XVIII in Figure 20.

[0063] Next, as shown in Figures 16 and 19, a first ohmic electrode 41 is formed on the source region 13, the second ohmic electrode 42, and the interlayer insulating film 35. The first ohmic electrode 41 covers the source region 13, the second ohmic electrode 42, and the portions of the gate insulating film 31 and the interlayer insulating film 35 exposed from the second ohmic electrode 42, and makes ohmic contact with the source region 13. Next, a barrier film 43 is formed on the first ohmic electrode 41, and a source electrode 44 is formed on the barrier film 43. For example, from the start of the formation of the second ohmic electrode 42 (see Figures 14 and 18) until the completion of the formation of the source electrode 44, the temperature of the second ohmic electrode 42 is kept below 500°C.

[0064] Next, the drain electrode 45 is formed (see Figure 2). In this way, the silicon carbide semiconductor device 100 according to the embodiment can be manufactured.

[0065] In the silicon carbide semiconductor device 100, the source region 13 contains 3 × 10 n-type impurities. 19 cm -3 The above effective concentrations are contained, and the first ohmic electrode 41 contains titanium (Ti) or magnesium (Mg). In addition, the contact area 14 contains p-type impurities at a concentration of 1 × 10⁻⁶. 20 cm -3 The silicon carbide semiconductor device 100 contains the above effective concentration, and the second ohmic electrode 42 contains nickel (Ni). Therefore, even without performing alloying annealing of the first ohmic electrode 41 and the second ohmic electrode 42 during the manufacturing of the silicon carbide semiconductor device 100, the first ohmic electrode 41 can be made to ohmic contact with the source region 13, and the second ohmic electrode 42 can be made to ohmic contact with the contact region 14. Thus, deformation of the first ohmic electrode 41 and the second ohmic electrode 42 due to alloying annealing can be avoided, and a decrease in connection reliability between the source electrode 44 and the source region 13 and the contact region 14 due to deformation can be avoided. In other words, good connection reliability can be obtained with the silicon carbide semiconductor device 100. Note that the source region 13 contains 3 × 10 n-type impurities. 20 cm -3 It contains in an effective concentration of 1 × 10⁻¹⁶ or the contact area 14 contains p-type impurities. 21 cm -3 When contained at an effective concentration exceeding the limit, many crystal defects may be present in the source region 13 or contact region 14, which may increase the likelihood of leakage between the source electrode 44 and the drain electrode 45.

[0066] If alloying annealing is not performed on the first ohmic electrode 41 and the second ohmic electrode 42, the arithmetic mean roughness Ra of each of the first surface 411, second surface 412, third surface 421, and fourth surface 422 tends to be 10 nm or less, making it easier to obtain good connection reliability. In addition, the thickness of the first transition layer 415 and the thickness of the second transition layer 425 tend to be 20 nm or less, making it easier to obtain low contact resistance.

[0067] When the first ohmic electrode 41 covers the second ohmic electrode 42, the first ohmic electrode 41 can reduce the likelihood of interdiffusion between the second ohmic electrode 42 and the source electrode 44. Furthermore, since etching or other processing of the first ohmic electrode 41 is unnecessary, an increase in processing time and cost can be avoided.

[0068] When the silicon carbide semiconductor device 100 has a barrier film 43 containing titanium nitride, interdiffusion between the source electrode 44 and the first ohmic electrode 41 and the second ohmic electrode 42 can be made less likely. In addition, deformation of the first ohmic electrode 41 and the second ohmic electrode 42 due to alloying annealing can be avoided, so the shape of the barrier film 43 is stable and good barrier properties can be obtained.

[0069] When the source electrode 44 contains aluminum, a low electrical resistance is obtained in the source electrode 44 in the p-type contact region 14. The first ohmic electrode 41 and the second ohmic electrode 42 do not need to contain aluminum. When the first ohmic electrode 41 and the second ohmic electrode 42 do not contain aluminum, a low contact resistance is obtained in the n-type source region 13. In addition, diffusion of aluminum into the interlayer insulating film 35 due to heat generation during short-circuit operation can be avoided.

[0070] If contact holes 39 are formed in the interlayer insulating film 35, the source electrode 44 can be electrically connected to the source region 13 and the contact region 14 through the contact holes 39. Furthermore, if the interlayer insulating film 35 has an insulating film 33 containing undoped silicon oxide and an insulating film 34 containing borosilicate glass, the shape of the contact holes 39 can be stabilized while a curved surface can be provided in the insulating film 34 to improve the coverage of the source electrode 44. This makes it easier to integrate transistors to a high degree. In addition, borosilicate glass has a gettering effect against light metals such as sodium (Na) and potassium (K) from the outside.

[0071] When a gate trench 5 is provided on the first main surface 1, and the gate insulating film 31 is in contact with the side surface 3 and bottom surface 4 of the gate trench 5, it is easier to integrate transistors to a high degree.

[0072] When the first ohmic electrode 41 and the second ohmic electrode 42 cover the interlayer insulating film 35, the precision required for processing the first ohmic electrode 41 and the second ohmic electrode 42 can be relaxed, and it is possible to form elements with a narrow cell pitch.

[0073] Furthermore, a portion of the first ohmic electrode 41 may be in contact with the contact region 14, and a portion of the second ohmic electrode 42 may be in contact with the source region 13.

[0074] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims. [Explanation of Symbols]

[0075] 1. First main surface 2. Second main surface 3 Sides 4. Bottom 5 Gate Trench 9. Virtual Plane 10 Silicon carbide epitaxial layer 11. Drift Region 11A First drift region 11B Second drift region 12 Body Region 13 Source Area 14 Contact Area 15. Electric field relaxation region 20 Silicon carbide substrate 21 Silicon carbide single crystal substrate 31 Gate insulating film 32 gates 33, 34 Insulating film 35 Interlayer insulating film 39 Contact Holes 41 First ohmic electrode 42 Second Ohmic Electrode 43 Barrier film 44 Source electrodes 45 Drain electrode 71, 72 n-type semiconductor layer 100 Silicon Carbide Semiconductor Devices 411 Page 1 412 2nd page 415 1st transition layer 421 3rd page 422 Page 4 425 2nd transition layer P1 First Pitch θ1 angle

Claims

1. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, A first ohmic electrode containing titanium or magnesium, A second ohmic electrode containing nickel, Source electrode and, Drain electrode and It has, The silicon carbide substrate is A source region having an n-type conductivity and the first main surface, It has an n-type conductivity, and a drift region is provided between the source region and the second main surface, Having a p-type conductivity, a body region provided between the source region and the drift region, Having a p-type conductive pattern, having the first main surface, and a contact area that contacts the body area, It has, The first ohmic electrode makes ohmic contact with the source region, The second ohmic electrode makes ohmic contact with the contact region, The source electrode is electrically connected to the first ohmic electrode and the second ohmic electrode, The drain electrode is electrically connected to the drift region, The aforementioned source region contains 5 × 10 n-type impurities. １８ cm －３ The above 1 x 10 ２１ cm －３ It contains the following effective concentrations: The aforementioned contact region contains 1 × 10 p-type impurities. １９ cm －３ The above 5 x 10 ２１ cm －３ A silicon carbide semiconductor device containing the following effective concentrations.

2. The source region contains the n-type impurity at 5×10 １９ cm －３ or more and 1×10 ２０ cm －３ or less as an effective concentration, The contact region contains 1 × 10⁻⁶ p-type impurities. ２０ cm －３ The above 1 x 10 ２１ cm －３ A silicon carbide semiconductor device according to claim 1, containing the following effective concentrations.

3. The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the first ohmic electrode covers the second ohmic electrode.

4. The silicon carbide semiconductor device according to claim 3, comprising titanium nitride and having a barrier film provided between the first ohmic electrode, the second ohmic electrode and the source electrode.

5. The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the source electrode contains aluminum.

6. The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the first ohmic electrode and the second ohmic electrode do not contain aluminum.

7. The first ohmic electrode is A first surface facing the first main surface, The second side is opposite to the first side, It has, The second ohmic electrode is A third surface opposite to the first main surface, The fourth surface is opposite to the third surface mentioned above, It has, The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the arithmetic mean roughness of each of the first, second, third, and fourth surfaces is 10 nm or less.

8. The first ohmic electrode has a first transition layer that contacts the first main surface, The first transition layer contains silicon at a concentration of 0.1 to 0.9 times the maximum silicon concentration in the silicon carbide substrate. The second ohmic electrode has a second transition layer that contacts the first main surface, The second transition layer contains silicon at a concentration of 0.1 to 0.9 times the maximum silicon concentration in the silicon carbide substrate. The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the thickness of the first transition layer and the thickness of the second transition layer are 20 nm or less.

9. A gate insulating film that contacts the body region, A gate electrode sandwiching the gate insulating film between itself and the body region, The interlayer insulating film covering the gate electrode, It has, The silicon carbide semiconductor device according to claim 1 or claim 2, wherein contact holes reaching the source region and the contact region are formed in the interlayer insulating film.

10. The interlayer insulating film is A first insulating film containing undoped silicon oxide covering the gate electrode, A second insulating film containing borosilicate glass and covering the first insulating film, A silicon carbide semiconductor device according to claim 9, having the features described.

11. The first main surface is provided with a gate trench having a side surface that penetrates the source region and the body region and reaches at least the drift region, and a bottom surface that is connected to the side surface. The silicon carbide semiconductor device according to claim 9, wherein the gate insulating film is in contact with the side surface and the bottom surface.

12. The silicon carbide semiconductor device according to claim 9, wherein the first ohmic electrode and the second ohmic electrode cover the interlayer insulating film.

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