Semiconductor equipment

Abstract

To provide a semiconductor device capable of improving high-frequency characteristics. [Solution] The semiconductor device comprises a conductive base, a substrate, an amplifier provided on the substrate for amplifying high-frequency signals, a reference potential pad provided on the upper surface of the substrate to which the reference potential terminal of the amplifier is electrically connected, and via wiring that penetrates the substrate and electrically connects the reference potential pad and the base; a semiconductor chip mounted on the base; a first insulating layer provided on the base so as to cover the semiconductor chip; a first wiring layer provided on the first insulating layer; a first through electrode that penetrates the first insulating layer and electrically connects the first wiring layer and the reference potential pad; and a second through electrode that penetrates the first insulating layer and electrically connects the first wiring layer and the base.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] It is known to provide a circuit module on a transistor die, and provide a passive electronic component electrically coupled between a gate and a lead or between a drain and a lead on a surface of the circuit module (for example, Patent Document 1) Prior Art Documents Patent Documents

[0003] Patent Document 1 Japanese Unexamined Patent Publication No. 2023-159434 Summary of Invention Problem to be Solved by Invention

[0004] In some cases, a reference potential terminal of a semiconductor chip such as a transistor die is connected to ground via a via penetrating the semiconductor chip. However, when the reference potential terminal is connected to ground via a via, the inductance component and resistance component increase. This deteriorates high-frequency characteristics such as gain.

[0005] An object of the present disclosure is to provide a semiconductor device capable of improving high-frequency characteristics. Means for Solving the Problem

[0006] Embodiments of the present disclosure are semiconductor devices comprising: a conductive base; a substrate; an amplifier provided on the substrate for amplifying high-frequency signals; a reference potential pad provided on the upper surface of the substrate to which the reference potential terminal of the amplifier is electrically connected; a via wiring that penetrates the substrate and electrically connects the reference potential pad and the base; a semiconductor chip mounted on the base; a first insulating layer provided on the base so as to cover the semiconductor chip; a first wiring layer provided on the first insulating layer; a first through-electrode that penetrates the first insulating layer and electrically connects the first wiring layer and the reference potential pad; and a second through-electrode that penetrates the first insulating layer and electrically connects the first wiring layer and the base. [Effects of the Invention]

[0007] According to this disclosure, it is possible to provide a semiconductor device capable of improving high-frequency characteristics. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a cross-sectional view of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a plan view of the area around the semiconductor chip of the semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a plan view of the area around the semiconductor chip of the semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a cross-sectional view of AA in Figures 2 and 3. [Figure 5] Figure 5 is a cross-sectional view of BB in Figures 2 and 3. [Figure 6] Figure 6 is a perspective view of the area around the semiconductor chip of the semiconductor device according to the first embodiment. [Figure 7] Figure 7 is a circuit diagram showing the equivalent circuit of the semiconductor device according to the first embodiment. [Figure 8] Figure 8 is a plan view of the semiconductor device relating to comparative form 1. [Figure 9] Figure 9 is a plan view of the semiconductor device relating to comparative form 2. [Figure 10] Fig. 10 is a cross-sectional view taken along line A-A in Fig. 8. [Figure 11] Fig. 11 is a circuit diagram showing an equivalent circuit of a semiconductor device according to Comparative Example 2. [Figure 12] Fig. 12 is a schematic diagram showing maximum gain versus frequency in Comparative Examples 1 and 2. [Figure 13] Fig. 13 is a schematic diagram showing a turning point frequency fk and the maximum gain at fk. [Figure 14] Fig. 14 is a cross-sectional view of a semiconductor device according to Comparative Example 3. [Figure 15] Fig. 15 is a circuit diagram showing an equivalent circuit of a semiconductor device according to Comparative Example 3. [Figure 16] Fig. 16 is a cross-sectional view of a semiconductor device according to Comparative Example 4. [Figure 17] Fig. 17 is a circuit diagram showing an equivalent circuit of a semiconductor device according to Comparative Example 4. [Figure 18] Fig. 18 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 19] Fig. 19 is a cross-sectional view taken along line A-A in Fig. 18. [Figure 20] Fig. 20 is a circuit diagram showing an equivalent circuit of a semiconductor device according to the second embodiment. [Figure 21] Fig. 21 is a schematic diagram showing maximum gain versus frequency in the embodiment and comparative examples. [Figure 22] Fig. 22 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 23] Fig. 23 is a cross-sectional view of a semiconductor device according to Comparative Example 5. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] (1) Embodiments of the present disclosure are semiconductor devices comprising: a conductive base; a substrate; an amplifier provided on the substrate for amplifying high-frequency signals; a reference potential pad provided on the upper surface of the substrate to which the reference potential terminal of the amplifier is electrically connected; a via wiring that penetrates the substrate and electrically connects the reference potential pad and the base; a semiconductor chip mounted on the base; a first insulating layer provided on the base so as to cover the semiconductor chip; a first wiring layer provided on the first insulating layer; a first through electrode that penetrates the first insulating layer and electrically connects the first wiring layer and the reference potential pad; and a second through electrode that penetrates the first insulating layer and electrically connects the first wiring layer and the base. This makes it possible to reduce the inductance and resistance connected to the reference potential, thereby improving high-frequency characteristics. (2) In (1) above, the semiconductor chip has an input pad electrically connected to the input terminal of the amplifier and provided on the upper surface of the substrate, and an output pad electrically connected to the output terminal of the amplifier and provided on the upper surface of the substrate, and the semiconductor device may also include a second wiring layer provided on the first insulating layer, a third wiring layer provided on the first insulating layer, a third through electrode that penetrates the first insulating layer and electrically connects the second wiring layer and the input pad, and a fourth through electrode that penetrates the first insulating layer and electrically connects the third wiring layer and the output pad. This simplifies the manufacturing process for forming the first wiring layer. (3) In (2) above, a fourth wiring layer may be provided which is electrically connected to the first wiring layer and is located on the first insulating layer between the second wiring layer and the third wiring layer. This reduces the feedback capacitance and improves the high-frequency characteristics. (4) In (3) above, the distance between the fourth wiring layer and the second wiring layer may be shorter than the distance between the fourth wiring layer and the third wiring layer. This can improve high-frequency characteristics. (5) In (3) or (4) above, the alignment direction is from the second wiring layer to the third wiring layer, and the distance the first wiring layer protrudes from the fourth wiring layer in the alignment direction may be shorter than the distance the first wiring layer protrudes from the fourth wiring layer in the opposite direction to the alignment direction. This can improve high-frequency characteristics. (6) In any of (2) to (5) above, the reference potential pad, the first wiring layer, the first through electrode, and the second through electrode may each be provided in multiple quantities so as to sandwich the amplifier. This can improve high-frequency characteristics. (7) In any of (1) to (6) above, the amplifier may include a transistor, the reference potential terminal may be the source of the transistor, the input terminal may be the gate of the transistor, and the output terminal may be the drain of the transistor. This can improve high-frequency characteristics. (8) In any of (1) to (7) above, the shortest distance between the first through electrode and the second through electrode may be smaller than the minimum width of the semiconductor chip. This can improve high-frequency characteristics. (9) In any of (1) to (8) above, the lower surface of the base may be a reference potential surface to which a reference potential is supplied. This can improve high-frequency characteristics. (1) In any of (1) to (8) above, the device may include a second insulating layer provided on the first insulating layer so as to cover the first wiring layer, a metal layer provided on the second insulating layer, and a fifth through-electrode that penetrates the second insulating layer and electrically connects the metal layer and the first wiring layer. This improves high-frequency characteristics. (11) In (10) above, the upper surface of the metal layer may be a reference potential surface to which a reference potential is supplied. This can improve high-frequency characteristics.

[0011] [Details of the embodiments of this disclosure] Specific examples of semiconductor devices according to embodiments of this disclosure will be described below with reference to the drawings. However, this disclosure is not limited to these examples, and all modifications within the meaning and scope of the claims are intended to be included.

[0012] (First Embodiment) Figure 1 is a cross-sectional view of a semiconductor device according to the first embodiment. The thickness direction of the base 10 is the Z direction, the arrangement direction of the input pads 22 and output pads 23 on the semiconductor chip 20 is the X direction, and the direction perpendicular to the X and Z directions is the Y direction.

[0013] As shown in Figure 1, the semiconductor device 100 of the first embodiment includes a base 10, terminals 11A and 11B, insulating layers 12 and 16, through-electrodes 13, wiring layers 14, semiconductor chips 20A and 20B, and electronic components 18.

[0014] The base 10, terminals 11A and 11B are conductive and have electrical conductivity. The semiconductor chips 20A and 20B are mounted on the base 10. A reference potential, such as the ground potential, is supplied to the base 10. The semiconductor chips 20A and 20B each have amplifiers 30A and 30B, respectively. The semiconductor chips 20A and 20B each have a substrate 24, a reference potential pad 21, an input pad 22, and an output pad 23, respectively. The reference potential pad 21, the input pad 22, and the output pad 23 are provided on the upper surface of the substrate 24.

[0015] The base 10, terminals 11A and 11B are metal plates such as copper plates, for example, lead frames. The insulating layer 12 (first insulating layer) is provided on the base 10, terminals 11A and 11B so as to cover the semiconductor chips 20A and 20B. The through-electrode 13 penetrates the insulating layer 12 and is electrically connected to terminals 11A and 11B, input pads 22 and output pads 23. The wiring layer 14 is provided on the insulating layer 12. A portion of the wiring layer 14 functions as a signal line of a microstrip line that transmits high-frequency signals. The wiring layer 14 is electrically connected to terminals 11A and 11B, input pads 22 and output pads 23 via the through-electrode 13. The electronic component 18 is mounted on the wiring layer 14. The electronic component 18 has a body 18A and electrodes 18B. The electrodes 18B are provided on the surface of the body 18A. The electrodes 18B are bonded to the wiring layer 14, for example, using a conductive bonding layer. The electronic component 18 is, for example, a discrete passive component, such as a chip capacitor, chip inductor, or chip resistor. The insulating layer 16 is provided on the insulating layer 12 so as to cover the electronic component 18 and the wiring layer 14. The insulating layers 12 and 16 are made of resin, such as epoxy resin. The through-electrode 13 and the wiring layer 14 are made of metal, such as a copper layer.

[0016] Passive circuit 31A has a wiring layer 14 and electronic components 18 connected between terminal 11A and semiconductor chip 20A. Passive circuit 31B has a wiring layer 14 and electronic components 18 connected between semiconductor chips 20A and 20B. Passive circuit 31C has a wiring layer 14 and electronic components 18 connected between semiconductor chip 20B and terminal 11B. Passive circuits 31A, 31B, and 31C include, for example, impedance matching circuits. Passive circuit 31A matches the impedance seen from terminal 11A to passive circuit 31A with the impedance seen from passive circuit 31A to amplifier 30A. Passive circuit 31B matches the impedance seen from amplifier 30A to passive circuit 31B with the impedance seen from passive circuit 31B to amplifier 30B. Passive circuit 31C matches the impedance seen from amplifier 30B to passive circuit 31C with the impedance seen from passive circuit 31C to terminal 11B.

[0017] A high-frequency signal is input to terminal 11A. When the semiconductor device 100 is used as a base station for mobile communications, the frequency of the high-frequency signal is, for example, between 0.5 GHz and 20 GHz. The high-frequency signal is input to the input pad 22 of the semiconductor chip 20A via the passive circuit 31A. Amplifier 30A amplifies the high-frequency signal input to the input pad 22 and outputs the amplified high-frequency signal to the output pad 23. The high-frequency signal amplified in amplifier 30A is input to the input pad 22 of the semiconductor chip 20B via the passive circuit 31B. Amplifier 30B amplifies the high-frequency signal input to the input pad 22 and outputs the amplified high-frequency signal to the output pad 23. The high-frequency signal amplified in amplifier 30B is output from terminal 11B via the passive circuit 31C.

[0018] Figure 1 illustrates an example with two amplifiers, 30A and 30B, but one amplifier or three or more amplifiers are also acceptable.

[0019] Figures 2 and 3 are plan views of the area around the semiconductor chip of a semiconductor device according to the first embodiment. Figure 2 mainly illustrates the semiconductor chip 20, and Figure 3 mainly illustrates the wiring layer 14. Figure 4 is a cross-sectional view of AA in Figures 2 and 3. Figure 5 is a cross-sectional view of BB in Figures 2 and 3. Figure 6 is a perspective view of the area around the semiconductor chip of a semiconductor device according to the first embodiment. Semiconductor chips 20A and 20B in Figure 1 will be described as semiconductor chip 20.

[0020] As shown in Figures 2, 4, and 5, the semiconductor chip 20 includes a substrate 24, a reference potential pad 21, an input pad 22, an output pad 23, via wiring 25, an amplifier 30, and electrodes 34. The reference potential pad 21, input pad 22, and output pad 23 are provided on the upper surface of the substrate 24. The electrodes 34 are provided across the entire lower surface of the substrate 24. The via wiring 25 penetrates the substrate 24 and electrically connects the reference potential pad 21 and the electrodes 34, creating a short circuit. The electrodes 34 are joined to the base 10 by a conductive bonding member 36. As a result, the via wiring 25 electrically connects the reference potential pad 21 and the base 10.

[0021] The amplifier 30 includes a transistor 32. The transistor 32 has a plurality of source electrodes 26, a plurality of gate electrodes 27, and a plurality of drain electrodes 28. The plurality of source electrodes 26, a plurality of gate electrodes 27, and a plurality of drain electrodes 28 are finger-shaped and extend in the X direction. The plurality of source electrodes 26 and a plurality of drain electrodes 28 are arranged alternately in the Y direction. One source electrode 26 and one drain electrode 28 sandwich one gate electrode 27 in the Y direction. A plurality of unit FETs 33 are arranged in the Y direction and have one source electrode 26, one drain electrode 28, and one gate electrode 27.

[0022] Multiple gate electrodes 27 are connected to the input pad 22 at their negative ends in the X direction. Multiple drain electrodes 28 are connected to the output pad 23 at their positive ends in the X direction. Among the source electrodes 26, the source electrode 26 to which the via wiring 25 is connected also serves as the reference potential pad 21. The source wiring 29 crosses the gate electrodes 27 non-contactually, electrically connecting and short-circuiting the reference potential pad 21 and the source electrode 26 to which the via wiring 25 is not connected.

[0023] The source potential (e.g., reference potential) is supplied from the base 10 to the reference potential pad 21 via the junction member 36, electrode 34, and through electrode 13. Furthermore, the source potential is supplied from the reference potential pad 21 to the source electrode 26 via the source wiring 29. The gate potential (e.g., high-frequency signal and gate bias voltage) is supplied from the input pad 22 to the gate electrode 27. The drain potential (e.g., drain bias) is supplied from the output pad 23 to the drain electrode 28. The amplified high-frequency signal is output from the drain electrode 28 to the output pad 23.

[0024] If transistor 32 is a GaN HEMT (Gallium Nitride High Electron Mobility Transistor), the substrate 24 comprises, for example, a silicon carbide substrate or a sapphire substrate, a gallium nitride channel layer, and an aluminum gallium nitride barrier layer. If transistor 32 is an LDMOS (Laterally Diffused Metal Oxide Semiconductor), the substrate is a silicon substrate.

[0025] The source electrode 26 and drain electrode 28 are, for example, a titanium film and an aluminum film from the substrate 24 side. The gate electrode 27 is, for example, a nickel film and a gold film from the substrate 24 side. The reference potential pad 21, input pad 22, output pad 23, via wiring 25 and electrode 34 are metal layers such as a gold layer, copper layer, or aluminum layer. The bonding member 36 is a metal layer formed by sintering a conductive paste such as silver paste.

[0026] As shown in Figures 3 to 6, through electrodes 13A to 13D penetrate the insulating layer 12. Wiring layers 14A to 14D are provided on the insulating layer 12. Through electrode 13A electrically connects and short-circuits wiring layer 14A and the reference potential pad 21. Through electrode 13B electrically connects and short-circuits wiring layer 14A and the base 10. Through electrode 13C electrically connects and short-circuits wiring layer 14B and the input pad 22. Through electrode 13D electrically connects and short-circuits wiring layer 14C and the output pad 23. Wiring layer 14D is provided between wiring layers 14B and 14C and is electrically connected to and short-circuits wiring layer 14A.

[0027] Figure 7 is a circuit diagram showing the equivalent circuit of a semiconductor device according to the first embodiment. In Figure 7, transistor 32 is represented as the true part 40. The true part 40 has a source S, a gate G, and a drain D. Terminal T1 is the input terminal for a high-frequency signal. Terminal T2 is the output terminal for a high-frequency signal. The gate inductance Lg and gate resistance Rg are connected in series between terminal T1 and gate G. The drain inductance Ld and drain resistance Rd are connected in series between terminal T2 and drain D. The inductor L0 and resistor R0 are connected in series between ground and source S.

[0028] The gate-drain capacitance Cgd is connected between nodes N1 and N2. Node N1 is the node between the gate resistor Rg and the gate G. Node N2 is the node between the drain resistor Rd and the drain D. The gate-source capacitance Cgs is connected between nodes N1 and N4. The drain-source capacitance Cds is connected between nodes N2 and N5. Inductors L1, L2, and resistors R1 and R2 are connected in series between nodes N4 and N3, and another inductor L1, L2, and resistors R1 and R2 are connected directly between nodes N5 and N3. Node N3 is the node between ground and inductor L0. Inductor L3 and resistor R3 are connected in series between nodes N4 and N6. Another inductor L3 and resistor R3 are connected in series between nodes N5 and N6. Node N6 is the node between source S and resistor R0, and inductor L4 and resistor R4 are connected in series between nodes N4 and N5.

[0029] As shown in Figures 3 to 6, the gate inductance Lg and gate resistance Rg mainly correspond to the inductance and resistance components in wiring layer 14B, respectively. The drain inductance Ld and drain resistance Rd mainly correspond to the inductance and resistance components in wiring layer 14C, respectively. The inductor L0 and resistance R0 mainly correspond to the inductance and resistance components of via wiring 25, respectively.

[0030] The gate-drain capacitance Cgd mainly corresponds to the capacitance component between wiring layers 14B and 14C. The gate-source capacitance Cgs mainly corresponds to the capacitance component between wiring layers 14B and 14D. The drain-source capacitance Cds mainly corresponds to the capacitance component between wiring layers 14C and 14D. Inductor L1 and resistor R1 mainly correspond to the inductance and resistance components of the through-electrode 13B, respectively. Inductor L2 and resistor R2 mainly correspond to the inductance and resistance components of wiring layer 14A, respectively. Inductor L3 and resistor R3 mainly correspond to the inductance and resistance components of the through-electrode 13A, respectively. Inductor L4 and resistor R4 mainly correspond to the inductance and resistance components of wiring layer 14D, respectively.

[0031] (Comparison Form 1) Figure 8 is a plan view of the semiconductor device according to Comparative Embodiment 1. As shown in Figure 8, the semiconductor device 110 of Comparative Embodiment 1 does not have wiring layers 14A, 14D, or through electrodes 13A and 13B. The other configurations are the same as in the first embodiment and will not be described further.

[0032] In comparative configuration 1, a gate-drain capacitance Cgd is generated between wiring layers 14B and 14C. This gate-drain capacitance Cgd becomes the feedback capacitance of the amplifier 30. When the gate-drain capacitance Cgd increases, the gain and efficiency decrease. In particular, when the center frequency of the operating band increases, the length of the gate electrode 27 in the X direction is shortened to reduce the resistance caused by the gate electrode in order to improve the gain. As a result, the distance between the input pad 22 and the output pad 23 decreases. Consequently, the distance between wiring layers 14B and 14C also decreases. This increases the gate-drain capacitance Cgd.

[0033] (Comparison Form 2) Figure 9 is a plan view of the semiconductor device according to comparative form 2. Figure 10 is a cross-sectional view of AA in Figure 9. In comparative form 2, a wiring layer 14D is provided between wiring layer 14B and wiring layer 14C. The wiring layer 14D is electrically connected to the base 10 via a through electrode 13B. The other configurations are the same as in comparative form 1 and will not be explained. In comparative form 2, a wiring layer 14D electrically connected to the base 10 is placed between wiring layers 14B and 14C. This reduces the gate drain capacitance Cgd.

[0034] Figure 11 is a circuit diagram showing the equivalent circuit of the semiconductor device according to comparative embodiment 2. Compared to Figure 7 of the first embodiment, the inductors L2 and L3 and resistors R2 and R3 are not provided.

[0035] Figure 12 is a schematic diagram showing the maximum gain with respect to frequency in comparison configurations 1 and 2. The frequency on the horizontal axis is displayed logarithmically. As shown in Figure 12, in both comparison configurations 1 and 2, the maximum gain is the maximum stable gain (MSG) in the low-frequency region. In the high-frequency region, the maximum gain is the maximum available power gain (MAG). The transition frequency between MSG and MAG is fk. The rate of decrease in gain with respect to frequency is greater for MAG than for MSG. The transition frequency fk is, for example, a frequency between 1 GHz and 10 GHz.

[0036] In comparison configuration 2, the MSG is improved compared to comparison configuration 1. However, the transition frequency fk becomes lower. As a result, the maximum gain in the high-frequency range is smaller than in comparison configuration 1.

[0037] Figure 13 is a schematic diagram showing the change in the transition frequency fk and the maximum gain at fk for capacitance, resistance, and inductance. In Figure 13, the "-10%" term shows the change in the transition frequency fk and maximum gain @fk when the gate-drain capacitance Cgd, gate-source capacitance Cgs, drain-source capacitance Cds, source resistance Rs, and source inductance Ls are each decreased by 10%. Maximum gain @fk is the maximum gain at fk. The "+10%" term shows the change in the transition frequency fk and maximum gain @fk when the gate-drain capacitance Cgd, gate-source capacitance Cgs, drain-source capacitance Cds, source resistance Rs, and source inductance Ls are each increased by 10%. "+" and "-" indicate an increase and decrease in the transition frequency fk and maximum gain @fk, respectively.

[0038] As shown in Figure 13, when the gate-drain capacitance Cgd decreases, the maximum gain @fk increases but the inversion frequency fk decreases. When the gate-drain capacitance Cgd increases, the inversion frequency fk increases but the maximum gain @fk decreases. Therefore, in Figure 12, it can be considered that in comparison configuration 2, the MSG is larger but the inversion frequency fk is lower compared to comparison configuration 1.

[0039] When the gate-source capacitance Cgs, drain-source capacitance Cds, source resistance Rs, and source inductance Ls decrease, the inversion frequency fk increases and the maximum gain @fk decreases. When the gate-source capacitance Cgs, drain-source capacitance Cds, source resistance Rs, and source inductance Ls increase, the inversion frequency fk decreases and the maximum gain @fk decreases. As in comparative configuration 2, if a wiring layer 14D is provided to reduce the gate-drain capacitance Cgd, the gate-source capacitance Cgs and drain-source capacitance Cds increase, and the inversion frequency fk decreases. It is difficult to reduce the gate-source capacitance Cgs and drain-source capacitance Cds. Therefore, it is conceivable to increase the inversion frequency fk by reducing the source inductance Ls and source resistance Rs. Note that source inductance Ls has a greater impact on high-frequency characteristics than source resistance Rs.

[0040] (Comparative form 3) Figure 14 is a cross-sectional view of the semiconductor device according to comparative form 3. As shown in Figure 14, in the semiconductor device 114 of comparative form 3, multiple via wirings 25 are connected in parallel between one reference potential pad 21 and the base 10. The other configurations are the same as in comparative form 2 and will not be described.

[0041] Figure 15 is a circuit diagram showing the equivalent circuit of the semiconductor device according to comparison configuration 3. Compared to Figure 11 of comparison configuration 2, multiple paths are connected in parallel between source S and node N3. An inductor L0 and a resistor R0 are connected in series to each path.

[0042] In the semiconductor device 114 of comparative configuration 3, by providing multiple via connections 25 in parallel, the inductor L0 and resistor R0 that were connected in series between the source S and ground are connected in parallel. This reduces the source inductance Ls and source resistance Rs. Therefore, the inversion frequency fk can be increased. However, providing multiple via connections 25 in parallel increases the chip size of the semiconductor chip 20, as shown in Figure 14. The semiconductor chip 20 is manufactured using a complex manufacturing process, resulting in a high chip area cost. Therefore, an increase in the chip size of the semiconductor chip 20 increases the cost of the semiconductor device 114.

[0043] (Comparison Form 4) Figure 16 is a cross-sectional view of the semiconductor device according to comparative form 4. As shown in Figure 16, in the semiconductor device 116 of comparative form 4, multiple through electrodes 13B are connected in parallel between the wiring layer 14D and the base 10. The other configurations are the same as in comparative form 2 and will not be described.

[0044] Figure 17 is a circuit diagram showing the equivalent circuit of the semiconductor device according to comparison configuration 4. As shown in Figure 17, compared to Figure 11 of comparison configuration 2, multiple paths are connected in parallel between nodes N4 and N3. An inductor L1 and a resistor R1 are connected in series to each path.

[0045] In the semiconductor device 116 of comparative form 4, unlike the semiconductor device 114 of comparative form 3, multiple via connections 25 are not provided in parallel, so the chip size of the semiconductor chip 20 is the same as in comparative form 2. As shown in Figure 17, multiple paths are provided between nodes N4 and N3, so the inductance and resistance between nodes N4 and N3 are reduced. However, the source inductance Ls and source resistance Rs between source S and ground remain the same as in comparative form 2. Therefore, the inversion frequency fk cannot be increased.

[0046] (Description of the first embodiment) In the first embodiment, as shown in Figures 2 to 6, the reference potential pad 21 is electrically connected to the source electrode 26 of the transistor 32. The source electrode 26 corresponds to the reference potential terminal of the amplifier 30. The through electrode 13A (first through electrode) penetrates the insulating layer 12 and electrically connects the wiring layer 14A (first wiring layer) and the reference potential pad 21. The through electrode 13B (second through electrode) penetrates the insulating layer 12 and electrically connects the wiring layer 14A and the base 10. As a result, as shown in Figure 7, a path 42 is connected in parallel with the inductor L0 and resistor R0 between the source S and ground. The path 42 connects node N6 and node N3. The path 42 has inductors L1, L2, L3 and resistors R1, R2, and R3 connected in series. In other words, in addition to the path from the reference potential pad 21 to the base 10 via the via wiring 25, the reference potential pad 21 is electrically connected to the base 10 via the path from the reference potential pad 21 to the through electrode 13A, the wiring layer 14A, and the through electrode 13B. This allows the source inductance Ls and source resistance Rs to be reduced, thereby increasing the conversion frequency fk. Thus, the maximum gain in the high-frequency range can be improved, and the high-frequency characteristics can be enhanced.

[0047] As shown in Figures 2 to 6, the input pad 22 is electrically connected to the gate electrode 27 of the transistor 32. The output pad 23 is electrically connected to the drain electrode 28 of the transistor 32. The gate electrode 27 corresponds to the input terminal of the amplifier 30. The drain electrode 28 corresponds to the output terminal of the amplifier 30. Wiring layers 14B (second wiring layer) and 14C (third wiring layer) are provided on the insulating layer 12. The through electrode 13C (third through electrode) electrically connects wiring layer 14B and the input pad 22. The through electrode 13D (fourth through electrode) electrically connects wiring layer 14C and the output pad 23. In this way, wiring layer 14A can use wiring layers at the same level as wiring layers 14B and 14C. This simplifies the manufacturing process for forming wiring layer 14A.

[0048] When wiring layers 14B and 14C are provided, a gate-drain capacitance Cgd is generated between wiring layers 14B and 14C. This degrades the high-frequency characteristics. Therefore, wiring layer 14D (the fourth wiring layer) is electrically connected to wiring layer 14A and provided between wiring layers 14C and 14D. This reduces the gate-drain capacitance Cgd, thereby improving high-frequency characteristics such as maximum gain.

[0049] The drain-source capacitance Cds has a greater influence on the inversion frequency fk than the gate-source capacitance Cgs. Here, as shown in Figure 5, when the distance between wiring layers 14D and 14B is Dg and the distance between wiring layers 14D and 14C is Dd, the distance Dg is made shorter than Dd. As a result, although the gate-source capacitance Cgs increases, the drain-source capacitance Cds can be reduced. Therefore, the inversion frequency fk can be increased, and the high-frequency characteristics can be improved. The distance Dg can be less than 1 times the distance Dd, and can be 0.8 times or less. The distances Dg and Dd may also be equal.

[0050] As shown in Figure 3, when the + direction in the X direction is defined as the alignment direction from wiring layer 14B to wiring layer 14C, let D1 be the distance that wiring layer 14A protrudes from wiring layer 14D in the + direction in the X direction, and let D2 be the distance that wiring layer 14A protrudes from wiring layer 14D in the - direction in the X direction. In this case, distance D1 is shorter than distance D2. As a result, although the gate-source capacitance Cgs increases, the drain-source capacitance Cds can be reduced. Therefore, the inversion frequency fk can be increased, and the high-frequency characteristics can be improved. Distance D1 can be 0.8 times or less of distance D2, and can also be 0.6 times or less. Note that when multiple through electrodes 13B are arranged in the Y direction, the distance between wiring layers 14A and 14B increases, so the gate-source capacitance Cgs does not tend to increase. Therefore, distance D1 may be greater than or equal to distance D2.

[0051] If the shortest distance D3 between the centers of the through electrodes 13A and 13B is long, the inductor L2 and resistance R2 of the wiring layer 14A will increase, making it difficult to reduce the source inductance Ls and source resistance Rs. From this perspective, the shortest distance D3 can be made shorter than the minimum width D4 of the semiconductor chip 20. The minimum width D4 corresponds to the length of the shorter side of the rectangle, for example, if the planar shape of the semiconductor chip 20 is rectangular. The shortest distance D3 can be 0.8 times or less the minimum width D4, and can also be 0.6 times or less.

[0052] Multiple reference potential pads 21, wiring layers 14A, and through electrodes 13A and 13B are provided, each flanking the amplifier 30. This allows for a further reduction in source inductance Ls and source resistance Rs, thereby improving high-frequency characteristics.

[0053] An example of amplifier 30 including a transistor 32 having a source, gate, and drain has been described. In this case, the inversion frequency fk can be increased by reducing the source inductance Ls and source resistance Rs between the reference potential pad 21 and the base 10. In addition, the maximum gain can be improved by providing a wiring layer 14D between wiring layers 14B and 14C.

[0054] Even with a typical amplifier 30, high-frequency characteristics deteriorate if the inductance and resistance connected to the reference potential of amplifier 30 are large. Furthermore, high-frequency characteristics deteriorate if the feedback capacitance of amplifier 30 is large. Therefore, amplifier 30 may be replaced with a transistor other than transistor 32.

[0055] The lower surface (-Z plane) of the base 10 is the reference potential plane to which the reference potential is supplied. In this case, in comparative form 2, the source inductance Ls and source resistance Rs become large, mainly due to the inductor L0 and resistance R0 of the via wiring 25. In the first embodiment, as shown in Figure 7, by connecting the path 42 which is connected in parallel to the inductor L0 and resistance R0, the source inductance Ls and source resistance Rs can be reduced and the high-frequency characteristics can be improved.

[0056] (Second Embodiment) Figure 18 is a cross-sectional view of the semiconductor device according to the second embodiment. Figure 19 is a cross-sectional view AA of Figure 18. As shown in Figures 18 and 19, the semiconductor device 102 of the second embodiment does not have a wiring layer 14D. The other configurations are the same as those of the first embodiment and will not be described.

[0057] Figure 20 is a circuit diagram showing the equivalent circuit of the semiconductor device according to the second embodiment. As shown in Figure 20, in the semiconductor device 102 of the second embodiment, the inductor L4 and resistor R4 are not connected between nodes N4 and N5. Even in this case, a path 42 is connected between the source S and ground in parallel with the inductor L0 and resistor R0. This makes it possible to reduce the source inductance Ls and increase the inversion frequency fk. Therefore, high-frequency characteristics can be improved. In the semiconductor device 102 of the second embodiment, the gate-source capacitance Cgs is mainly the capacitance component between wiring layers 14A and 14B. The drain-source capacitance Cds is mainly the capacitance component between wiring layers 14A and 14C.

[0058] Figure 21 is a schematic diagram showing the maximum gain with respect to frequency in the embodiment and the comparative form. As shown in Figure 21, in the semiconductor device 112 of comparative form 2, which has a wiring layer 14D added to the semiconductor device 110 of comparative form 1, the MSG is improved by ΔG. However, the transition frequency fk becomes lower by Δfk'. Therefore, in comparative form 2, although the maximum gain is improved in the low-frequency range compared to comparative form 1, the maximum gain is reduced in the high-frequency range.

[0059] In the semiconductor device 100 of the first embodiment, a through electrode 13A is provided compared to the semiconductor device 112 of comparative embodiment 2. This allows the transition point frequency fk to be increased by Δfk when the MSG is improved. Therefore, the maximum gain in the high-frequency range can be made greater than that of comparative embodiment 2.

[0060] In the semiconductor device 102 of the second embodiment, a through electrode 13A is provided compared to the semiconductor device 110 of comparative embodiment 1. This does not improve the MSG, but it allows the transition point frequency fk to be increased by Δfk. Therefore, the maximum gain in the high-frequency range can be made greater than in comparative embodiment 1. Unlike the semiconductor device 102 of the second embodiment, the wiring layer 14D may not be provided.

[0061] In the first and second embodiments, the frequencies at which the maximum gain is greater than in comparative form 2 and comparative form 1 are, for example, 0.1 GHz to 7 GHz and 0.1 GHz to 6.5 GHz, respectively. Therefore, when the center frequency of the operating band of the amplifier 30 is 0.1 GHz to 7 GHz, the maximum gain can be improved, and when it is 0.1 GHz to 6.5 GHz, the maximum gain can be further improved.

[0062] (Third embodiment) Figure 22 is a cross-sectional view of a semiconductor device according to the third embodiment. As shown in Figure 22, in the semiconductor device 104 of the third embodiment, a metal layer 19 is provided over the entire surface of the insulating layer 16 (second insulating layer). A through electrode 17 (fifth through electrode) penetrates the insulating layer 16 and electrically connects the wiring layer 14A and the metal layer 19. The metal layer 19 is a metal plate such as a copper plate. The through electrode 17 is a metal layer such as a copper layer. The other configurations are the same as in the first embodiment and will not be described.

[0063] (Comparative form 5) Figure 23 is a cross-sectional view of the semiconductor device according to comparative embodiment 5. As shown in Figure 23, the semiconductor device 118 of comparative embodiment 5 does not have a through electrode 13A. The other configurations are the same as in the third embodiment and will not be described.

[0064] In the semiconductor device 118 of comparative form 5, the lower surface (-Z plane) of the base 10 is a heat dissipation surface that releases heat from the semiconductor chip 20, and heat dissipation members such as fins are connected to it. The upper surface (+Z plane) of the metal layer 19 is a reference potential plane, and a reference potential is supplied to it. The path from the reference potential pad 21 to the reference potential plane consists of via wiring 25, the base 10, and through electrodes 13B and 17. Inductors L6 and resistors R6 are provided as the inductance and resistance components of the base 10. Inductors L0, L6, L1 and L5 and resistors R0, R6, R1 and R5 are connected in series in the path from the reference potential pad 21 to the reference potential plane. As a result, the source inductance Ls and source resistance Rs become large, and the high-frequency characteristics deteriorate.

[0065] In the third embodiment, a through electrode 13A is provided. As a result, the path from the reference potential pad 21 to ground includes, in addition to the path in which inductors L0, L6, L1, and L5 and resistors R0, R6, R1, and R5 are connected in series, a path in which inductors L1, L2, and L5 and resistors R1, R2, and R5 are connected in series. Therefore, the source inductance Ls and source resistance Rs can be reduced, and the high-frequency characteristics can be improved.

[0066] In the third embodiment, the upper surface of the metal layer 19 is a reference potential surface to which a reference potential is supplied. In this case as well, by providing the through electrode 13A, the source inductance Ls and source resistance Rs can be reduced, and the high-frequency characteristics can be improved.

[0067] Even if the wiring layer 14A is not provided, as in the second embodiment, the metal layer 19 and the through electrode 17 may still be provided. The upper surface of the metal layer 19 may be used as the reference potential plane.

[0068] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims, not in the sense described above, and all modifications in the sense and scope equivalent to the claims are intended. [Explanation of Symbols]

[0069] 10 base 11A, 11B terminal 12 (First insulating layer), 16 (Second insulating layer) Insulating layer 13, 13A (1st through electrode), 13B (2nd through electrode), 13C (3rd through electrode), 13D (4th through electrode), 17 (5th through electrode) Through electrode 14, 14A (first wiring layer), 14B (second wiring layer), 14C (third wiring layer), 14D (fourth wiring layer) 18 Electronic Components 18A Main Unit 18B, 34 electrodes 19 Metal layer 20, 20A, 20B semiconductor chips 21 Reference Potential Pad 22 Input Pads 23 Output Pads 24 circuit boards 25 via wiring 26 Source electrodes 27 Shuttle gate 28 Drain electrode 29 Source Wiring 30, 30A, 30B Amplifiers 31A, 31B, 31C Passive Circuits 32 transistors 33 Unit FET 36 Joining members 40 Shinbu 42 routes 100, 102, 104, 100, 112, 114, 116, 118 Semiconductor Cds drain source capacity Cgd gate drain capacity Cgs gate source capacity S Sauce G Gate D Drain Ls Source Inductance Rs Source Resistor

Claims

1. A conductive base, A semiconductor chip mounted on a base comprises a substrate, an amplifier provided on the substrate for amplifying high-frequency signals, a reference potential pad provided on the upper surface of the substrate to which the reference potential terminal of the amplifier is electrically connected, and via wiring that penetrates the substrate and electrically connects the reference potential pad to the base. A first insulating layer is provided on the base so as to cover the semiconductor chip, A first wiring layer provided on the first insulating layer, A first through electrode penetrates the first insulating layer and electrically connects the first wiring layer and the reference potential pad, A second through electrode penetrates the first insulating layer and electrically connects the first wiring layer and the base, A semiconductor device equipped with the following features.

2. The semiconductor chip has an input pad electrically connected to the input terminal of the amplifier and provided on the upper surface of the substrate, and an output pad electrically connected to the output terminal of the amplifier and provided on the upper surface of the substrate. The aforementioned semiconductor device is A second wiring layer provided on the first insulating layer, A third wiring layer provided on the first insulating layer, A third through-electrode penetrates the first insulating layer and electrically connects the second wiring layer and the input pad, A fourth through-electrode penetrates the first insulating layer and electrically connects the third wiring layer and the output pad, A semiconductor device according to claim 1, comprising:

3. The semiconductor device according to claim 2, further comprising a fourth wiring layer electrically connected to the first wiring layer and provided on the first insulating layer between the second wiring layer and the third wiring layer.

4. The semiconductor device according to claim 3, wherein the distance between the fourth wiring layer and the second wiring layer is shorter than the distance between the fourth wiring layer and the third wiring layer.

5. The alignment direction is from the second wiring layer to the third wiring layer. The semiconductor device according to claim 3 or 4, wherein the distance the first wiring layer protrudes from the fourth wiring layer in the direction of arrangement is shorter than the distance the first wiring layer protrudes from the fourth wiring layer in the opposite direction of arrangement.

6. The semiconductor device according to any one of claims 2 to 4, wherein a plurality of the reference potential pad, the first wiring layer, the first through electrode, and the second through electrode are provided so as to sandwich the amplifier.

7. The aforementioned amplifier includes a transistor, The aforementioned reference potential terminal is the source of the transistor. The input terminal is the gate of the transistor, The output terminal is the drain of the transistor. The semiconductor device according to any one of claims 2 to 4.

8. The semiconductor device according to any one of claims 1 to 4, wherein the shortest distance between the first through electrode and the second through electrode is smaller than the minimum width of the semiconductor chip.

9. The semiconductor device according to any one of claims 1 to 4, wherein the lower surface of the base is a reference potential surface to which a reference potential is supplied.

10. A second insulating layer is provided on the first insulating layer so as to cover the first wiring layer, A metal layer provided on the second insulating layer, A fifth through-electrode penetrates the second insulating layer and electrically connects the metal layer and the first wiring layer, A semiconductor device according to any one of claims 1 to 4, comprising:

11. The semiconductor device according to claim 10, wherein the upper surface of the metal layer is a reference potential surface to which a reference potential is supplied.

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