Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can further reduce the occupied area. [Solution] A semiconductor device 100A having an upper surface US comprises a first wiring portion WU1 formed on the upper surface US, a first field-effect transistor TR1, and a second field-effect transistor TR2, wherein the first field-effect transistor comprises a first structure ST1 including a source layer SO1, a channel layer CH1, and a drain layer DR1, and the source layer SO1, the channel layer CH1, and the drain layer DR1 are stacked along the vertical direction of the upper surface US, and the second field-effect transistor TR2 comprises a second structure ST2 including a source layer SO2, a channel layer CH2, and a drain layer DR2, and the source layer SO2, the channel layer CH2, and the drain layer DR2 are stacked along the vertical direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Art

[0002] Conventionally, there has been known a nanostructure transistor including: an isolation region; a nanostructure protruding above an upper surface of the isolation region; a gate structure that is surrounded by the nanostructure, has a bottom surface in contact with the isolation region and extending away from the nanostructure by a first distance, and a side wall disposed away from the nanostructure by a second distance that is equal to or greater than the first distance; and a hybrid fin disposed on the side wall of the gate structure (see Patent Document 1). Prior Art Literature Patent Literature

[0003] Patent Document 1 Japanese Unexamined Patent Application Publication No. 2022-27740 Summary of the Invention Problem to be Solved by the Invention

[0004] In recent years, further miniaturization and higher integration have been desired for semiconductor devices. For this reason, further reduction beyond conventional levels is required for the occupied area (also referred to as "footprint") of semiconductor devices.

[0005] The present invention has been made in view of such circumstances, and an object thereof is to provide a semiconductor device capable of further reducing the occupied area and a method for manufacturing the semiconductor device. Means for Solving the Problem

[0006] A semiconductor device according to one aspect of the present invention is a semiconductor device having a first surface, comprising a first wiring portion formed on the first surface, a first field-effect transistor, and a second field-effect transistor, wherein the first field-effect transistor comprises a first structure including a source layer, a channel layer, and a drain layer, the source layer, the channel layer, and the drain layer being stacked along the vertical direction of the first surface, and the second field-effect transistor comprises a second structure including a source layer, a channel layer, and a drain layer, the source layer, the channel layer, and the drain layer being stacked along the vertical direction.

[0007] A method for manufacturing a semiconductor device according to one aspect of the present invention is a method for manufacturing a semiconductor device having a first surface, comprising a first wiring section, a first field-effect transistor, and a second field-effect transistor, and comprising the steps of: forming a first structure of the first field-effect transistor, comprising a source layer, a channel layer, and a drain layer, wherein the source layer, channel layer, and drain layer are stacked along the vertical direction of the first surface; forming a second structure of the second field-effect transistor, comprising a source layer, a channel layer, and a drain layer, wherein the source layer, channel layer, and drain layer are stacked along the vertical direction; and forming the first wiring section on the first surface. [Effects of the Invention]

[0008] According to the present invention, the occupied area can be further reduced. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a perspective view showing an example of the schematic configuration of a semiconductor device in one embodiment. [Figure 2] Figure 2 is a cross-sectional view showing an example of the schematic configuration of a semiconductor device in one embodiment. [Figure 3] Figure 3 is a perspective view showing an example of the schematic configuration of the first structure shown in Figure 2. [Figure 4]Figure 4 is a perspective view showing another example of the schematic configuration of the first structure shown in Figure 2. [Figure 5] Figure 5 is a circuit diagram showing the circuit configuration of the semiconductor device in the first example. [Figure 6] Figure 6 is a plan view showing the schematic configuration of the semiconductor device in the first example. [Figure 7] Figure 7 is a cross-sectional view showing the schematic configuration of the cross-section along the line x-x' shown in Figure 6. [Figure 8] Figure 8 is a diagram illustrating the occupied area of ​​a hypothetical semiconductor device. [Figure 9] Figure 9 is a diagram illustrating the occupied area of ​​the semiconductor device in the first example. [Figure 10] Figure 10 is a circuit diagram showing the circuit configuration of the semiconductor device in the second example. [Figure 11] Figure 11 is a plan view showing the schematic configuration of the semiconductor device in the second example. [Figure 12] Figure 12 is a cross-sectional view showing the schematic configuration of the cross-section along the line x-x' shown in Figure 11. [Figure 13] Figure 13 is a cross-sectional view showing the schematic configuration of the cross-section along the line y1-y1' shown in Figure 11. [Figure 14] Figure 14 is a cross-sectional view showing the schematic configuration of the cross-section along the line y2-y2' shown in Figure 11. [Figure 15] Figure 15 is a circuit diagram showing the circuit configuration of the semiconductor device in the third example. [Figure 16] Figure 16 is a plan view showing the schematic configuration of the semiconductor device in the third example. [Figure 17] Figure 17 is a cross-sectional view showing the schematic configuration of the cross-section along the line x-x' shown in Figure 16. [Figure 18] Figure 18 is a cross-sectional view showing the schematic configuration of the cross-section along the line y1-y1' shown in Figure 16. [Figure 19] Figure 19 is a cross-sectional view showing the schematic configuration of the cross-section along the line y2-y2' shown in Figure 16. [Figure 20]FIG. 20 is a flowchart showing a first example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 21] FIG. 21 is a cross-sectional view for explaining pre-processing steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 22] FIG. 22 is a cross-sectional view for explaining pre-processing steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 23] FIG. 23 is a cross-sectional view for explaining pre-processing steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 24] FIG. 24 is a cross-sectional view for explaining pre-processing steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 25] FIG. 25 is a cross-sectional view for explaining pre-processing steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 26] FIG. 26 is a cross-sectional view for explaining pre-processing steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 27] FIG. 27 is a cross-sectional view for explaining pre-processing steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 28] FIG. 28 is a cross-sectional view for explaining pre-processing steps in a method for manufacturing a semiconductor device according to an embodiment. [Figure 29] FIG. 29 is a cross-sectional view for explaining a step of forming a first structure in a method for manufacturing a semiconductor device according to an embodiment. [Figure 30] FIG. 30 is a cross-sectional view for explaining a step of forming a second structure in a method for manufacturing a semiconductor device according to an embodiment. [Figure 31] FIG. 31 is a cross-sectional view for explaining a step of forming a second structure in a method for manufacturing a semiconductor device according to an embodiment. [Figure 32] FIG. 32 is a cross-sectional view for explaining a step of forming a second structure in a method for manufacturing a semiconductor device according to an embodiment. [Figure 33]Figure 33 is a cross-sectional view illustrating an intermediate process step in a method for manufacturing a semiconductor device in one embodiment. [Figure 34] Figure 34 is a cross-sectional view illustrating an intermediate process step in a method for manufacturing a semiconductor device in one embodiment. [Figure 35] Figure 35 is a cross-sectional view illustrating an intermediate process step in a method for manufacturing a semiconductor device in one embodiment. [Figure 36] Figure 36 is a cross-sectional view illustrating an intermediate process step in a method for manufacturing a semiconductor device in one embodiment. [Figure 37] Figure 37 is a cross-sectional view illustrating an intermediate process step in a method for manufacturing a semiconductor device in one embodiment. [Figure 38] Figure 38 is a cross-sectional view illustrating an intermediate process step in a method for manufacturing a semiconductor device in one embodiment. [Figure 39] Figure 39 is a cross-sectional view illustrating an intermediate process step in a method for manufacturing a semiconductor device in one embodiment. [Figure 40] Figure 40 is a cross-sectional view illustrating an intermediate process step in a method for manufacturing a semiconductor device in one embodiment. [Figure 41] Figure 41 is a cross-sectional view illustrating an intermediate process step in a method for manufacturing a semiconductor device in one embodiment. [Figure 42] Figure 42 is a cross-sectional view illustrating an intermediate process step in a method for manufacturing a semiconductor device in one embodiment. [Figure 43] Figure 43 is a cross-sectional view illustrating an intermediate process step in a method for manufacturing a semiconductor device in one embodiment. [Figure 44] Figure 44 is a cross-sectional view illustrating the process of forming the first wiring section in a method for manufacturing a semiconductor device according to one embodiment. [Figure 45] Figure 45 is a cross-sectional view illustrating the process of forming the first wiring section in a method for manufacturing a semiconductor device according to one embodiment. [Figure 46]Figure 46 is a cross-sectional view illustrating the process of forming a second wiring section in a method for manufacturing a semiconductor device according to one embodiment. [Figure 47] Figure 47 is a cross-sectional view illustrating the process of forming a second wiring section in a method for manufacturing a semiconductor device according to one embodiment. [Figure 48] Figure 48 is a cross-sectional view illustrating the process of forming a second wiring section in a method for manufacturing a semiconductor device according to one embodiment. [Figure 49] Figure 49 is a cross-sectional view illustrating another example of the formation of the first and second wiring sections in a method for manufacturing a semiconductor device according to one embodiment. [Modes for carrying out the invention]

[0010] Embodiments of the present invention are described below. In the following drawings, identical or similar parts are denoted by identical or similar reference numerals. However, the drawings are schematic. Therefore, specific dimensions and other details should be determined by referring to the following description. It should also be noted that there are parts in the drawings where the relationships and ratios of dimensions differ from one another. Furthermore, the technical scope of the present invention should not be interpreted as being limited to these embodiments.

[0011] Each drawing may, for convenience, include a Cartesian coordinate system consisting of the X, Y, and Z axes to clarify the relationships between the drawings and to help understand the positional relationships of each part, layer, and area. The X, Y, and Z axes correspond to each other in each drawing.

[0012] In the following explanation, the direction parallel to the X-axis is referred to as the "X-axis direction," the direction parallel to the Y-axis as the "Y-axis direction," and the direction parallel to the Z-axis as the "Z-axis direction." Furthermore, the direction of the arrowheads for the X, Y, and Z axes is referred to as "positive" or "+ (plus)," and the direction opposite to the arrowhead is referred to as "negative" or "- (minus)." For convenience, the +Z-axis direction will be described as upward and the -Z-axis direction as downward, but the up and down orientation of a semiconductor device is not limited to these directions. Also, the planes specified by the X and Y axes will be referred to as the XY planes, and the same applies to planes specified by the other axes.

[0013] [Semiconductor device] First, the schematic configuration of a semiconductor device according to one embodiment will be described with reference to Figures 1 to 4. Figure 1 is a perspective view showing an example of the schematic configuration of a semiconductor device 100 in one embodiment. Figure 2 is a cross-sectional view showing an example of the schematic configuration of a semiconductor device 100 in one embodiment. Figure 3 is a perspective view showing an example of the schematic configuration of the first structure ST1 shown in Figure 2. Figure 4 is a perspective view showing another example of the schematic configuration of the first structure ST1 shown in Figure 2.

[0014] As shown in Figure 1, the semiconductor device 100 has an upper surface US and a lower surface LS facing the upper surface US. The upper surface US and the lower surface LS are, for example, planes parallel to the XY plane in Figure 1. However, the upper surface US and the lower surface LS are not limited to being planes. At least one of the upper surface US and the lower surface LS may include, for example, a convex portion that protrudes or a concave portion that is recessed. Also, at least one of the upper surface US and the lower surface LS may have a predetermined planar roughness.

[0015] The semiconductor device 100 includes a first wiring section WU1 formed on the upper surface US of the semiconductor device 100, as shown in Figure 2. The first wiring section WU1 is configured to have at least one of the following functions: a power supply function to the semiconductor device 100, a signal input function to the semiconductor device 100, and a signal output function from the semiconductor device 100. More specifically, the first wiring section WU1 is configured to include at least one of the following circuits: a power supply circuit for supplying power from a power source (not shown), an input signal circuit for inputting a signal to the semiconductor device 100, and an input signal circuit for inputting a signal to the semiconductor device 100.

[0016] Furthermore, the semiconductor device 100 includes a first field-effect transistor (FET) TR1 and a second field-effect transistor TR2.

[0017] The first field-effect transistor TR1 and the second field-effect transistor TR2 typically have three terminals: a gate electrode (also simply called the "gate"), a source electrode (also simply called the "source"), and a drain electrode (also simply called the "drain"). The first field-effect transistor TR1 and the second field-effect transistor TR2 are transistors that control the density of electrons or holes by applying or not applying a predetermined voltage to the gate electrode, thereby controlling the current flowing from the source electrode to the drain electrode through the electric field generated in the region between the source electrode and the drain electrode (hereinafter referred to as the "channel" or "channel region"). The first field-effect transistor TR1 and the second field-effect transistor TR2 are classified into n-channel type (also simply called "n-type") and p-channel type (also simply called "p-type") field-effect transistors, depending on the type of channel.

[0018] As shown in Figure 2, the first field-effect transistor TR1 comprises a first structure ST1. The first structure ST1 is made of a material mainly composed of silicon (Si), for example. The first structure ST1 includes a source layer SO1, a channel layer CH1, and a drain layer DR1. The first structure ST1 is configured such that current flows between the source layer SO1 and the drain layer DR1, with the channel layer CH1 serving as the current path. Specifically, the source layer SO1 functions as the source electrode in the first field-effect transistor TR1, and the drain layer DR1 functions as the drain electrode in the first field-effect transistor TR1. The channel layer CH1 plays the role of the channel region in the first field-effect transistor TR1.

[0019] In the first structure ST1, the source layer SO1, the channel layer CH1, and the drain layer DR1 are stacked in a continuous manner along the vertical direction of the upper surface US shown in Figure 1, that is, along the Z-axis direction shown in Figure 2.

[0020] In Figure 2, an example is shown in which the first structure ST1 is stacked in the order of source layer SO1, channel layer CH1, and drain layer DR1, but it is not limited to this. The first structure ST1 may be stacked in the order of drain layer DR1, channel layer CH1, and source layer SO1, for example.

[0021] The semiconductor device 100 further includes a second wiring section WU2 formed on the lower surface LS shown in Figure 1. The source layer SO1 in the first structure ST1 is electrically connected to the second wiring section WU2. In the example shown in Figure 2, current flows in the first structure ST1 in the positive Z-axis direction.

[0022] The second wiring section WU2 is configured to have at least one function, for example, a power supply function to the semiconductor device 100, a signal input function to the semiconductor device 100, and a signal output function from the semiconductor device 100. More specifically, the second wiring section WU2 is configured to include at least one circuit, for example, a power supply circuit for supplying power from a power supply (not shown), an input signal circuit for inputting a signal to the semiconductor device 100, and an input signal circuit for inputting a signal to the semiconductor device 100. Specifically, it is preferable that the second wiring section WU2 includes wiring that electrically connects the power supply and the semiconductor device 100. This makes it possible to realize (configure) a Back Side Power Delivery Network (BSPDN).

[0023] Thus, by further providing a second wiring section WU2 formed on the lower surface LS of the semiconductor device 100, for example, the first wiring section WU1 includes an input signal circuit and an output signal circuit, and the second wiring section WU2 includes a power supply circuit. This makes it possible, for example, to arrange signal lines on the upper surface US and power supply lines on the lower surface LS, thereby separating the signal network from the power supply network. Consequently, the degree of freedom in wiring design can be increased, and the area occupied by wiring can be reduced.

[0024] The first field-effect transistor TR1 further comprises a gate portion GU1. The gate portion GU1 functions as the gate electrode in the first field-effect transistor TR1.

[0025] The second field-effect transistor TR2 comprises a second structure ST2. The second structure ST2 is made of a material mainly composed of silicon (Si), for example. The second structure ST2 includes a drain layer DR2, a channel layer CH2, and a source layer SO2. The second structure ST2 is configured such that current flows between the source layer SO2 and the drain layer DR2, with the channel layer CH2 serving as the current path. Specifically, the drain layer DR2 functions as the drain electrode in the second field-effect transistor TR2, and the source layer SO2 functions as the source electrode in the second field-effect transistor TR2. The channel layer CH2 plays the role of the channel region in the second field-effect transistor TR2.

[0026] In the second structure ST2, the drain layer DR2, the channel layer CH2, and the source layer SO2 are stacked in this order in a continuous manner along the vertical direction of the upper surface US shown in Figure 1, that is, along the Z-axis direction shown in Figure 2.

[0027] In Figure 2, an example is shown in which the second structure ST2 is stacked in the order of drain layer DR2, channel layer CH2, and source layer SO2, but it is not limited to this. The second structure ST2 may also be stacked in the order of source layer SO2, channel layer CH2, and drain layer DR2, for example.

[0028] The source layer SO2 in the second structure ST2 is electrically connected to the first wiring section WU1, which is formed on the upper surface US shown in Figure 1. In the example shown in Figure 2, current flows in the negative Z-axis direction through the first structure ST1.

[0029] The second field-effect transistor TR2 further comprises a gate portion GU2. The gate portion GU2 functions as the gate electrode in the second field-effect transistor TR2.

[0030] The first structure ST1 and the second structure ST2 are stacked in this order along the vertical direction of the upper surface US, that is, along the Z-axis direction. As will be described in detail in the manufacturing method described later, the first structure ST1 and the second structure ST2 are formed integrally.

[0031] Thus, because the first structure ST1 and the second structure ST2 are stacked along the vertical direction of the upper surface US, the occupied area can be reduced compared to the case where two field-effect transistors are arranged along the horizontal direction of the upper surface, which would require the area of ​​two field-effect transistors.

[0032] As shown in Figures 1 and 2, the semiconductor device 100 includes an insulating layer IS in a portion of the space between the first structure ST1 and the second structure ST2 in the Z-axis direction. The insulating layer IS is made of a dielectric material, such as carbon-containing silicon nitride (SiOCN). The presence of the insulating layer IS between the first structure ST1 and the second structure ST2 electrically isolates the first structure ST1 and the second structure ST2.

[0033] As shown in Figure 3, the first structure ST1 has a cylindrical shape extending in the Z-axis direction. The gate portion GU1 of the first field-effect transistor TR1 is configured to have a GAA (Gate All Around) structure that covers the surface of the channel layer CH2 in the first structure ST1. More specifically, the gate portion GU1 is configured to surround the first structure ST1 in a plan view. The gate portion GU1 has a circular shape in a plan view.

[0034] The gate portion GU1 is composed of, for example, an insulating film HK and a metal gate GA1. The insulating film HK is positioned between the first structure ST1 and the metal gate GA1. The insulating film HK is in contact with a portion of the surface of the first structure ST1 and extends in the Z-axis direction. The metal gate GA1 is in contact with the insulating film HK and surrounds the insulating film HK.

[0035] The insulating film HK is composed of a material having a high dielectric constant κ, from the viewpoint of suppressing leakage current. More specifically, the main component of the insulating film HK is a high-κ insulator, preferably a compound with a dielectric constant κ of 4.0 or higher, which is higher than that of silicon oxide (SiO2). Compounds with a dielectric constant κ of 4.0 or higher are less prone to tunneling, and leakage current can be suppressed even when the electrical thickness of the insulating film HK is reduced. Specifically, the main component of the insulating film HK is preferably hafnium oxide (HfO2 or HfZrO2). This makes it easy to realize (construct) an insulating film HK with high dielectric constant and electrical insulation properties.

[0036] The metal gate GA1 is designed to reduce the resistance of the gate portion GU1. The metal gate GA1 is made of a material primarily composed of a conductive metal, such as tungsten (W).

[0037] In the example shown in Figure 3, the first structure ST1 has a cylindrical shape, but it is not limited to this. For example, the first structure ST1 may have an elliptical cylindrical shape. Furthermore, the external shape of the first structure ST1 is not limited to a circle or an ellipse, but may have other shapes.

[0038] As shown in Figure 4, the first structure ST1 may have a plate shape with a main surface parallel to the YZ plane. In this case, the gate portion GU1 has a rectangular shape in plan view.

[0039] Furthermore, the second structure ST2 and gate portion GU2 of the second field-effect transistor TR2 have the same or similar configuration as the first structure ST1 and gate portion GU1 shown in Figures 3 and 4, so their illustration and description are omitted.

[0040] Thus, the gate portion GU1 of the first field-effect transistor TR1 is configured to surround the first structure ST1 in a plan view, and the gate portion GU2 of the second field-effect transistor TR2 is configured to surround the second structure ST2 in a plan view. This increases the contact area with the channel layers CH1 and CH2, prevents short-channel effects, increases the drive current, and suppresses power consumption and leakage current.

[0041] Note that the first field-effect transistor TR1 and the second field-effect transistor TR2 are not limited to the examples shown in Figures 1 to 4. For example, the first field-effect transistor TR1 and the second field-effect transistor TR2 may be MOS (Metal Oxide Semiconductor) type FETs, MIS (Metal-Insulator-Semiconductor) type FETs using an insulating film other than an oxide film, junction type FETs, etc., and their types are not limited.

[0042] Furthermore, as shown in Figure 1, the semiconductor device 100 may further include, for example, a first layer 81, connection parts CO1 and CO2, a spacer SP, and an embedded region 15. These configurations will be described in detail in the first example semiconductor device 100A, which will be described later.

[0043] Next, with reference to Figures 5 to 19, a specific example of a semiconductor device according to one embodiment of the present invention will be described.

[0044] (Example 1) First, a first example of a semiconductor device according to one embodiment of the present invention will be described. Figure 5 is a circuit diagram showing the circuit configuration of the semiconductor device 100A in the first example. Figure 6 is a plan view showing the schematic configuration of the semiconductor device 100A in the first example. Figure 7 is a cross-sectional view showing the schematic configuration of the cross section along the line x-x' shown in Figure 6.

[0045] In the first example, semiconductor device 100A is an inverter. An inverter is a logic circuit that inverts an input signal and outputs it; it is also called a NOT gate.

[0046] In semiconductor device 100A, the first field-effect transistor TR1 is either an n-channel type or a p-channel type, and the second field-effect transistor TR2 is the other of the n-channel type and p-channel type. Specifically, as shown in Figure 5, the first field-effect transistor TR1 is an n-channel type field-effect transistor, and the second field-effect transistor TR2 is a p-channel type field-effect transistor.

[0047] Thus, since the first field-effect transistor TR1 is either an n-channel or p-channel type, and the second field-effect transistor TR2 is the other of the n-channel or p-channel type, the semiconductor device 100A can realize (configure) a complementary MOS (also called "CMOS") by complementaryly combining an n-channel field-effect transistor and a p-channel field-effect transistor.

[0048] A voltage Vin is applied to the gate electrodes of the first field-effect transistor TR1 and the second field-effect transistor TR2. A voltage Vout is also applied to the drain electrodes of both the first and second field-effect transistors TR1 and TR2. Furthermore, a voltage Vgnd is applied to the source electrode of the first field-effect transistor TR1, and a voltage Vdd is applied to the source electrode of the second field-effect transistor TR2.

[0049] As shown in Figure 6, the semiconductor device 100A has, for example, a rectangular outline in plan view. A first wiring section WU1 is formed on the upper surface US of the semiconductor device 100A. The first wiring section WU1 includes contact wiring M1, contact wiring M2, and contact wiring M3. Furthermore, as will be described later with reference to Figure 7, a second wiring section WU2 is formed on the lower surface LS of the semiconductor device 100A. The second wiring section WU2 includes contact wiring M4.

[0050] The semiconductor device 100A further comprises connection parts CO1 and CO2. Connection parts CO1 and CO2 are configured to conduct current to at least one of the first field-effect transistor TR1 and the second field-effect transistor TR2 and the first wiring section WU1. More specifically, connection parts CO1 and CO2 are configured to conduct current to at least one of the first structure ST1 in the first field-effect transistor TR1 and the second structure ST2 in the second field-effect transistor TR2 and the first wiring section WU1.

[0051] Connections CO1 and CO2 are embedded inside the semiconductor device 100A. Connection CO1 is made of a conductive metal, for example, tungsten (W), or a material mainly composed of tungsten (W) and titanium nitride (TiN). Connection CO2 is made of a conductive metal, for example, tungsten (W), tungsten (W) and titanium nitride (TiN), or a material mainly composed of tungsten (W), titanium nitride (TiN), and titanium (Ti).

[0052] Contact wire M1 is configured to supply voltage Vin. Contact wire M1 is electrically connected to connection CO1. Contact wire M3 is configured to supply voltage Vout. Contact wire M3 is electrically connected to connection CO2. Furthermore, contact wire M2 is configured to supply voltage Vdd.

[0053] As shown in Figure 7, the semiconductor device 100A comprises a first wiring section WU1, a transistor layer 10, and a second wiring section WU2.

[0054] The first wiring section WU1 includes a first layer 81 and a second layer 85. The first layer 81 is a film formed by depositing silicon oxide (SiO2) (also called silicon oxide), and its length along the Z-axis (hereinafter also called "thickness") is, for example, 30 nm. The first layer 81 includes a first region 81a, a second region 81b, a third region 81c, and a fourth region 81d, and via electrodes V1, V2, and V3. Via electrodes V1, V2, and V3 are formed, for example, by removing a part of the first layer 81 to form a via (hole) and filling the hole with a conductive material. The conductive material to be filled is, for example, tungsten (W) or copper (Cu). Each of via electrodes V1, V2, and V3 has a length along the X-axis, for example, 20 nm. The second layer 85 is a film formed by depositing silicon oxide (SiO2), and its thickness is, for example, 40 nm. The second layer 85 includes the first region 85a, the second region 85b, and the contact wiring M1, contact wiring M2, and contact wiring M3 described above. The contact wiring M1, contact wiring M2, and contact wiring M3 are formed, for example, by forming wiring grooves in the second layer 85 using the damascene method (also known as "damascene technique" or "damascene process") and embedding a metallic material in the wiring grooves. The embedded metallic material is, for example, tungsten (W) or copper (Cu).

[0055] The second wiring section WU2 includes a first layer 91 and a second layer 95. The first layer 91 is a film formed by depositing silicon oxide (SiO2), and its thickness is, for example, 40 nm. The first layer 91 includes a first region 91a, a second region 91b, and a contact wiring M4. The contact wiring M4 is configured to supply a voltage Vgnd. The contact wiring M4 is formed, for example, by forming a wiring groove in the first layer 91 using the damascene method and embedding a metal material in the wiring groove. The embedded metal material is, for example, tungsten (W) or copper (Cu). The second layer 95 is a film formed by depositing silicon oxide (SiO2), and its thickness is, for example, 20 nm. The second layer 95 includes a first region 95a, a second region 95b, and a via electrode V4. The via electrode V4 is formed, for example, by removing a portion of the second layer 95 to form a via (hole) and filling the hole with a conductive material. The conductive material used for filling is, for example, tungsten (W) or copper (Cu). The via electrode V4 has a length along the X-axis, for example, 20 nm.

[0056] The transistor layer 10 includes a first structure ST1 and gate portion GU1 in the first field-effect transistor TR1, a second structure ST2 and gate portion GU2 in the second field-effect transistor TR2, an insulating layer IS, connection portions CO1 and CO2, and a spacer SP. The transistor layer 10 further includes a diffusion region 11, an embedded region 15, and a separation region 16. The thickness of the transistor layer 10 is, for example, 165 nm. The spacer SP has a thickness of, for example, 45 nm and a length along the X-axis of, for example, 5 nm.

[0057] The diffusion region 11 is an n-type diffusion region. The diffusion region 11 is formed by epitaxially growing SiP from a silicon (Si) substrate, Si pillar, or Si nanosheet (not shown) while doping with impurities such as phosphorus (P). The embedded region 15 is a region in which grooves formed to form the connection CO2 are embedded so that the connection CO2 has a predetermined thickness. The embedded region 15 is formed by depositing silicon oxide (SiO2). The isolation region 16 is a region for separating adjacent semiconductor devices. The isolation region 16 is formed by embedding silicon oxide (SiO2) in grooves formed for the isolation region 16.

[0058] The first structure ST1 and the second structure ST2 are formed by stacking them along the Z-axis direction. Each of the first structure ST1 and the second structure ST2 has a thickness of, for example, 75 nm and a length of, for example, 40 nm along the X-axis direction. The source layer SO1 and the drain layer DR1 in the first structure ST1 each have a thickness of, for example, 30 nm. The channel layer CH1 in the first structure ST1 has a thickness of, for example, 15 nm and a length of, for example, 10 nm along the X-axis direction. In the gate portion GU1, the positive X-axis side and the negative X-axis side, each with the channel layer CH1 in between, have a length of, for example, 15 nm along the X-axis direction. The drain layer DR2 and the source layer SO2 in the second structure ST2 each have a thickness of, for example, 30 nm. The channel layer CH2 in the second structure ST2 has a thickness of, for example, 15 nm and a length of, for example, 10 nm along the X-axis direction. In the gate portion GU2, the positive X-axis side and the negative X-axis side, separated by the channel layer CH2, each have a length along the X-axis direction of, for example, 15 nm. An insulating layer IS and a channel layer CH are formed between the first structure ST1 and the second structure ST2. Each of the insulating layer IS and the channel layer CH has a thickness of, for example, 15 nm. A via electrode V4 of the second wiring portion WU2 is positioned directly beneath the first structure ST1 and the second structure ST2. Also, a via electrode V2 of the first wiring portion WU1 is positioned directly above the first structure ST1 and the second structure ST2. Therefore, the source layer SO1 in the first structure ST1 is in contact with the via electrode V4, and the source layer SO2 in the second structure ST2 is in contact with the via electrode V2. Thus, the source layer SO1 in the first structure ST1 is electrically connected to the contact wiring M4 of the second wiring portion WU2 via the via electrode V4. Furthermore, the source layer SO2 in the second structure ST2 is electrically connected to the contact wiring M2 of the first wiring section WU1 via the via electrode V2.

[0059] Connection portions CO1 and CO2 are formed to extend along the Z-axis. Each of connection portions CO1 and CO2 has a length of, for example, 30 nm along the X-axis. A via electrode V1 of the first wiring portion WU1 is positioned directly above connection portion CO1. Similarly, a via electrode V3 of the first wiring portion WU1 is positioned directly above connection portion CO2. Therefore, connection portion CO1 is in contact with via electrode V1, and connection portion CO2 is in contact with via electrode V3. Thus, connection portion CO1 is electrically connected to the contact wiring M1 of the first wiring portion WU1 via via electrode V1. Similarly, connection portion CO2 is electrically connected to the contact wiring M3 of the first wiring portion WU1 via via electrode V3.

[0060] Here, we will explain the occupied area of ​​the semiconductor device. Figure 8 is a diagram illustrating the occupied area of ​​a hypothetical semiconductor device 100A'. Figure 9 is a diagram illustrating the occupied area of ​​the semiconductor device 100A in the first example. The hypothetical semiconductor device 100A' is a hypothetical semiconductor device for comparison with the semiconductor device 100A in the first example, and components identical or similar to those of semiconductor device 100A are denoted by the same or similar reference numerals, and their explanations are omitted as appropriate.

[0061] As shown in Figure 8(a), the virtual semiconductor device 100A' comprises a first n-channel field-effect transistor TR1' and a second p-channel field-effect transistor TR2'. The first field-effect transistor TR1' includes a nanosheet NS1'. The second field-effect transistor TR2' includes a nanosheet NS2'. Both nanosheets NS1' and NS2' have an elongated sheet shape and extend along the X-axis. A portion of nanosheet NS1' constitutes the channel region of the first field-effect transistor TR1'. Similarly, a portion of nanosheet NS2' constitutes the channel region of the second field-effect transistor TR2'. The gate electrode GA' is formed to cover nanosheets NS1' and NS2'. The first field-effect transistor TR1' is configured such that current flows between the source electrode SO1' and the drain electrode DR1' using nanosheet NS1' as the current path. Furthermore, the second field-effect transistor TR2' is configured such that current flows between the source electrode SO2' and the drain electrode DR2', using the nanosheet NS2' as the current path.

[0062] The virtual semiconductor device 100A' further comprises a connection part CO11' electrically connected to the source electrode SO1', a connection part CO12' electrically connected to the source electrode SO2', a connection part CO21' electrically connected to the drain electrode DR1', and a connection part CO22' electrically connected to the drain electrode DR2'. The virtual semiconductor device 100A' further comprises spacers (not shown) between the source electrodes SO1' and SO2' and the gate electrode GA', and between the gate electrode GA' and the drain electrodes DR1' and DR2'. Furthermore, the virtual semiconductor device 100A' further comprises spacers (not shown) on the negative X-axis side of the source electrodes SO1' and SO2', and on the positive X-axis side of the drain electrodes DR1' and DR2'.

[0063] The hypothetical semiconductor device 100A' has an area occupied in a plan view, for example, as shown in Figure 8(b). For the sake of simplicity, the length of each component along the Y-axis (hereinafter also referred to as "width") is assumed to be the same for all components and is defined as width W1. The length of each spacer not shown in Figure 8(a) along the X-axis is assumed to be the same for all components and is defined as length Lsp.

[0064] In contrast, as shown in Figure 9(a), the second field-effect transistor TR2 in the semiconductor device 100A comprises a second structure ST2 in which a drain layer DR2, a channel layer CH2, and a source layer SO2 are stacked along the Z-axis direction. For the sake of simplicity, the illustration and description of the first field-effect transistor TR1 in the semiconductor device 100A are omitted.

[0065] The semiconductor device 100A has an area occupied in a plan view, for example, as shown in Figure 9(b). For the sake of facilitating comparison with a hypothetical semiconductor device 100A', the width of each component is assumed to be the same as that of the hypothetical semiconductor device 100A', and is therefore assumed to be width W1. Furthermore, the length of each spacer sp along the X-axis is assumed to be the same as the length of the spacers not shown in the hypothetical semiconductor device 100A', and is therefore assumed to be length Lsp. Additionally, the length Lst of the second structure ST2 along the X-axis is assumed to be the same as the length Lga' of the gate electrode GA' of the hypothetical semiconductor device 100A' along the X-axis (Lst = Lga').

[0066] Here, in the semiconductor device 100A, a length Lco of the connecting portion CO1 and the connecting portion CO2 along the X-axis direction is smaller than a length Lco' of a connecting portion CO12' and a connecting portion CO22' in a hypothetical semiconductor device 100A' shown in FIG. 8 (Lco<Lco'). As shown in (a) of FIG. 9, the connecting portion CO2 and the second structure ST2 are electrically connected, as indicated by the thick line, at a surface along the Z-axis direction in the drain layer DR2, that is, at a vertical surface. Therefore, by increasing the length along the Z-axis direction (hereinafter also referred to as "height") of the semiconductor device 100A, the contact area of the vertical surface (also referred to as "contact size") can be increased, so that contact resistance can be reduced.

[0067] On the other hand, as indicated by the thick line in (a) of FIG. 8, in the hypothetical semiconductor device 100A', an electrical connection surface between the connecting portion CO22' and the drain electrode DR2' is a surface parallel to the XY plane, that is, a horizontal plane. Therefore, if an attempt is made to increase the contact area of the surface in order to reduce the contact resistance between the connecting portion CO22' and the drain electrode DR2', the length Lco' of the connecting portion CO22' along the X-axis direction has to be increased. As a result, the occupation area of the hypothetical semiconductor device 100A' increases. In contrast, when the semiconductor device 100A has the same contact resistance as the hypothetical semiconductor device 100A', the lengths of the connecting portion CO1 and the connecting portion CO2 along the X-axis direction are reduced, and the occupation area can be reduced.

[0068] Thus, the semiconductor device 100A comprises a first field-effect transistor TR1, which includes a first structure ST1 comprising a source layer SO1, a channel layer CH1, and a drain layer DR1, wherein the source layer SO1, the channel layer CH1, and the drain layer DR1 are stacked along the vertical direction of the upper surface US, and a second field-effect transistor TR2, which includes a second structure ST2 comprising a source layer SO2, a channel layer CH2, and a drain layer DR2, wherein the source layer SO2, the channel layer CH2, and the drain layer DR2 are stacked along the vertical direction of the upper surface US. As a result, the first structure ST1 and the second structure ST2 can be electrically connected in a vertical plane along the vertical direction, and the contact area in a plan view can be reduced. Therefore, the occupied area of ​​the semiconductor device 100A can be reduced compared to when electrical connections are made in a horizontal plane.

[0069] Returning to the explanation of Figure 7, at least one of the first structure ST1 and the second structure ST2 has a connection surface that electrically connects to at least one of the connection parts CO1 and CO2, and has a connection surface that extends vertically along the upper surface US, that is, along the Z-axis direction. Specifically, the drain layer DR1 of the first structure ST1 does not have an insulating film HK formed on a part of the surface on the positive X-axis side, and this surface is in contact with the connection part CO2 along the Z-axis direction. Therefore, this surface of the drain layer DR1 constitutes the connection surface of the first structure ST1. Similarly, the drain layer DR2 of the second structure ST2 does not have an insulating film HK formed on a part of the surface on the positive X-axis side, and this surface is in contact with the connection part CO2 along the Z-axis direction. Therefore, this surface of the drain layer DR2 constitutes the connection surface of the second structure ST2.

[0070] Thus, at least one of the first structure ST1 and the second structure ST2 has a connecting surface that electrically connects to at least one of the connecting parts CO1 and CO2, and the connecting surface extends along the Z-axis direction, thereby reducing the contact area in a plan view while maintaining the contact area with the connecting parts CO1 and CO2.

[0071] The first structure ST1 and the second structure ST2 are stacked along the Z-axis direction. At least one of the connecting portion CO1 and connecting portion CO2 has a connecting surface that extends along the Z-axis direction to electrically connect the source layer SO1 or drain layer DR1 of the first structure ST1 with the source layer SO2 or drain layer DR2 of the second structure ST2. As described above, the connecting portion CO2 is in contact with the side surface of the drain layer DR1 of the first structure ST1 and the side surface of the drain layer DR2 of the second structure ST2, electrically connecting the drain layer DR1 and the drain layer DR2.

[0072] Thus, by having a connecting surface extending along the Z-axis direction in at least one of the connecting parts CO1 and CO2 to electrically connect the source layer SO1 or drain layer DR1 of the first structure ST1 with the source layer SO2 or drain layer DR2 of the second structure ST2, the occupied area for the connecting parts CO1 and CO2 can be reduced.

[0073] The gate portion GU1 of the first field-effect transistor TR1 is a connection surface that electrically connects to at least one of the connection portions CO1 and CO2, and has a connection surface that extends vertically along the upper surface US, i.e., along the Z-axis direction. Specifically, the gate portion GU1 does not have an insulating film HK formed on its side surface on the negative X-axis side, and this surface is in contact with the connection portion CO1 along the Z-axis direction. Therefore, this surface of the gate portion GU1 constitutes the connection surface. Similarly, the gate portion GU2 of the second field-effect transistor TR2 is a connection surface that electrically connects to at least one of the connection portions CO1 and CO2, and has a connection surface that extends vertically along the upper surface US, i.e., along the Z-axis direction. Specifically, the gate portion GU2 does not have an insulating film HK formed on its side surface on the negative X-axis side, and this surface is in contact with the connection portion CO1 along the Z-axis direction. Therefore, this surface of the gate portion GU2 constitutes the connection surface.

[0074] Thus, the gate portion GU1 of the first field-effect transistor TR1 has a connection surface that electrically connects to at least one of the connection portions CO1 and CO2, and has a connection surface that extends along the Z-axis direction. The gate portion GU2 of the second field-effect transistor TR2 has a connection surface that electrically connects to at least one of the connection portions CO1 and CO2, and has a connection surface that extends along the Z-axis direction. As a result, the area occupied in a plan view can be reduced while maintaining the contact area with the connection portions CO1 and CO2.

[0075] The first field-effect transistor TR1 is configured such that the first structure ST1 and the gate portion GU1 are aligned along the vertical direction of the upper surface US, that is, along the Z-axis direction. In other words, in the X-axis direction, the position of the outer edge of the first structure ST1 and the position of the outer edge of the gate portion GU1 coincide or approximately coincide. Similarly, in the Y-axis direction (not shown in the illustration), the position of the outer edge of the first structure ST1 and the position of the outer edge of the gate portion GU1 coincide or approximately coincide. The second field-effect transistor TR2 is configured such that the second structure ST2 and the gate portion GU2 are aligned along the vertical direction of the upper surface US, that is, along the Z-axis direction. In other words, in the X-axis direction, the position of the outer edge of the second structure ST2 and the position of the outer edge of the gate portion GU2 coincide or approximately coincide. Similarly, in the Y-axis direction (not shown in the illustration), the position of the outer edge of the second structure ST2 and the position of the outer edge of the gate portion GU2 coincide or approximately coincide.

[0076] Thus, the first field-effect transistor TR1 is configured such that the first structure ST1 and the gate portion GU1 are aligned along the Z-axis, and the second field-effect transistor TR2 is configured such that the second structure ST2 and the gate portion GU2 are aligned along the Z-axis, thereby reducing variations in transistor characteristics.

[0077] (Example 2) Next, a second example of a semiconductor device according to one embodiment of the present invention will be described. Figure 10 is a circuit diagram showing the circuit configuration of the semiconductor device 100B in the second example. Figure 11 is a plan view showing the schematic configuration of the semiconductor device 100B in the second example. Figure 12 is a cross-sectional view showing the schematic configuration of the cross section along the x-x' line shown in Figure 11. Figure 13 is a cross-sectional view showing the schematic configuration of the cross section along the y1-y1' line shown in Figure 11. Figure 14 is a cross-sectional view showing the schematic configuration of the cross section along the y2-y2' line shown in Figure 11. In the second example, the semiconductor device 100B is denoted by the same or similar reference numerals as the semiconductor device 100A shown in Figures 5 to 7 for components that are identical or similar, and their descriptions are omitted as appropriate. Furthermore, in the second example, the differences from the first example will be mainly described, and similar effects due to similar configurations will not be mentioned sequentially.

[0078] In the second example, semiconductor device 100B is a NAND (NOT AND) gate. A NAND gate is a logic circuit that outputs the negative logical AND of two input signals.

[0079] As shown in Figure 10, the semiconductor device 100B further comprises a third field-effect transistor TR3 and a fourth field-effect transistor TR4. In the example shown in Figure 10, the first field-effect transistor TR1 and the third field-effect transistor TR3 are each n-channel type field-effect transistors, and the second field-effect transistor TR2 and the fourth field-effect transistor TR4 are each p-channel type field-effect transistors.

[0080] A voltage Vin A is applied to the gate electrodes of the first field-effect transistor TR1 and the fourth field-effect transistor TR4. On the other hand, a voltage Vin B is applied to the gate electrodes of the second field-effect transistor TR2 and the third field-effect transistor TR3. Furthermore, a voltage Vout is applied to the drain electrodes of the first field-effect transistor TR1 and the second field-effect transistor TR2. In addition, a voltage Vgnd is applied to the source electrode of the third field-effect transistor TR3, and a voltage Vdd is applied to the source electrode of the second field-effect transistor TR2. Moreover, the source electrode of the first field-effect transistor TR1 and the drain electrode of the third field-effect transistor TR3 are connected to each other and are at the same potential.

[0081] As shown in Figure 11, the semiconductor device 100B has, for example, a rectangular outline in plan view. A first wiring section WU1 is formed on the upper surface US of the semiconductor device 100B. The first wiring section WU1 includes contact wiring M1, contact wiring M2, contact wiring M3, and contact wiring M4. A second wiring section WU2 is formed on the lower surface LS of the semiconductor device 100B. The second wiring section WU2 includes contact wiring M5, contact wiring M6, and contact wiring M7.

[0082] Contact wires M1 and M2 are configured to supply voltage Vdd, respectively. Contact wire M3 is configured to supply voltage Vout. Contact wire M4 is configured to supply voltage Vin A. Contact wire M5 is configured to supply the field shield voltage Vfs. Contact wire M6 is configured to supply voltage Vin B. Contact wire M7 is configured to supply voltage Vgnd.

[0083] As shown in Figure 12, the semiconductor device 100B comprises a first wiring section WU1, a transistor layer 10, and a second wiring section WU2.

[0084] The first wiring section WU1 further includes via electrodes V1, V2, and V3, in addition to the aforementioned contact wiring M1, M2, and M3.

[0085] The second wiring section WU2 further includes via electrodes V5 and V7 in addition to the aforementioned contact wiring M5 and contact wiring M7.

[0086] The transistor layer 10 includes the first field-effect transistor TR1, the second field-effect transistor TR2, the third field-effect transistor TR3, and the fourth field-effect transistor TR4 as described above, as well as a fifth field-effect transistor TR5 and a sixth field-effect transistor TR6. The third field-effect transistor TR3 has a gate portion GU3, the fourth field-effect transistor TR4 has a gate portion GU4, the fifth field-effect transistor TR5 has a gate portion GU5, and the sixth field-effect transistor TR6 has a gate portion GU6. The transistor layer 10 also includes connectors CO1, CO2, and CO3. Furthermore, the transistor layer 10 includes connectors CO4, CO5, and CO6 as shown in Figure 11.

[0087] The via electrode V7 of the second wiring section WU2 is located directly beneath the third field-effect transistor TR3, and the source electrode of the third field-effect transistor TR3 is in contact with the via electrode V7. Therefore, the source electrode of the third field-effect transistor TR3 is electrically connected to the contact wiring M7 of the second wiring section WU2 via the via electrode V7. Furthermore, the via electrode V2 of the first wiring section WU1 is located directly above the second structure ST2 of the second field-effect transistor TR2, and the source layer SO2 of the second structure ST2 is in contact with the via electrode V2. Therefore, the source layer SO2 of the second structure ST2 is electrically connected to the contact wiring M2 of the first wiring section WU1 via the via electrode V2. In addition, the via electrode V1 of the first wiring section WU1 is located directly above the fourth field-effect transistor TR4, and the source electrode of the fourth field-effect transistor TR4 is in contact with the via electrode V1. Therefore, the source electrode of the fourth field-effect transistor TR4 is electrically connected to the contact wiring M1 of the first wiring section WU1 via the via electrode V1.

[0088] The via electrode V3 of the first wiring section WU1 is located directly above the connection point CO2, and the connection point CO1 is in contact with the via electrode V3. Therefore, the connection point CO2 is electrically connected to the contact wiring M3 of the first wiring section WU1 via the via electrode V3. Furthermore, the via electrode V5 of the second wiring section WU2 is located directly below the connection point CO3, and the connection point CO3 is in contact with the via electrode V5. Therefore, the connection point CO3 is electrically connected to the contact wiring M5 of the second wiring section WU2 via the via electrode V5.

[0089] In the first structure ST1, the drain layer DR1 lacks an insulating film HK on a portion of its surface facing the positive X-axis, and this surface is in contact with the connection part CO2 along the Z-axis. Similarly, the drain layer DR1 of the first structure ST1 lacks an insulating film HK on a portion of its surface facing the negative X-axis, and this surface is in contact with the connection part CO1 along the Z-axis. Therefore, these two surfaces of the drain layer DR1 constitute the connection surface of the first structure ST1. Furthermore, in the second structure ST2, the drain layer DR2 lacks an insulating film HK on a portion of its surface facing the positive X-axis, and this surface is in contact with the connection part CO2 along the Z-axis. Similarly, the drain layer DR2 of the second structure ST2 lacks an insulating film HK on a portion of its surface facing the negative X-axis, and this surface is in contact with the connection part CO1 along the Z-axis. Therefore, these two surfaces of the drain layer DR2 constitute the connection surface of the second structure ST2.

[0090] The gate portion GU4 of the fourth field-effect transistor TR4 includes a metal gate GA4. The drain electrode of the first fourth field-effect transistor TR4 does not have an insulating film HK formed on a portion of the surface on the positive X-axis side, and this surface is in contact with the connection portion CO1 along the Z-axis direction. Therefore, this surface of the drain electrode constitutes the connection surface.

[0091] As mentioned above, the connection part CO2 is in contact with the surface of the drain layer DR1 of the first structure ST1 and the surface of the drain layer DR2 of the second structure ST2, electrically connecting the drain layer DR1 and the drain layer DR2. Similarly, the connection part CO1 is in contact with the surface of the drain layer DR1 of the first structure ST1 and the surface of the drain layer DR2 of the second structure ST2, electrically connecting the drain layer DR1 and the drain layer DR2. / / Therefore, the three drain electrodes of the first, second, and fourth field-effect transistors are electrically connected.

[0092] The gate portion GU5 of the fifth field-effect transistor TR5 does not have an insulating film HK formed on the negative X-axis side, and this side is in contact with the connection portion CO3 along the Z-axis direction. Therefore, this side of the gate portion GU5 constitutes the connection surface. Similarly, the gate portion GU6 of the sixth field-effect transistor TR6 does not have an insulating film HK formed on the negative X-axis side, and this side is in contact with the connection portion CO3 along the Z-axis direction. Therefore, this side of the gate portion GU6 constitutes the connection surface.

[0093] The channel portions of the fifth field-effect transistor TR5 and the sixth field-effect transistor TR6 are configured to be electrically cut off. More specifically, the gate portions GU5 and GU6 are configured to have a field shield voltage Vfs applied to them. Specifically, the field shield voltage Vfs is supplied to the gate portions GU5 and GU6 from the contact wiring M5 of the second wiring portion WU2 via the via electrode V5. Therefore, both the fifth field-effect transistor TR5 and the sixth field-effect transistor TR6 are cut off. In the example shown in Figure 12, the fifth field-effect transistor TR5 and the sixth field-effect transistor TR6, rather than the fourth field-effect transistor TR4, correspond to an example of the "fourth field-effect transistor" of the present invention.

[0094] Thus, the source and drain portions of the fifth field-effect transistor TR5 and the source and drain portions of the sixth field-effect transistor TR6 are configured to be electrically isolated. This allows the fifth field-effect transistor TR5 and the sixth field-effect transistor TR6 to be easily isolated and cut off from other elements such as the fourth field-effect transistor TR4.

[0095] As shown in Figure 13, the first wiring section WU1 further includes via electrodes V4 in addition to the contact wiring M4 described above.

[0096] The transistor layer 10 further contains CO4 at the connection point.

[0097] The via electrode V4 of the first wiring section WU1 is positioned directly above the connection point CO4, and the connection point CO4 is in contact with the via electrode V4. Therefore, the connection point CO4 is electrically connected to the contact wiring M4 of the first wiring section WU1 via the via electrode V4.

[0098] The gate portion GU5 of the fifth field-effect transistor TR5 includes a metal gate GA5. The gate portion GU6 of the sixth field-effect transistor TR6 includes a metal gate GA6. The gate portion GU4 of the fourth field-effect transistor TR4 does not have an insulating film HK formed on the negative Y-axis side, and this surface is in contact with the connection portion CO4 along the Z-axis direction. Therefore, this surface of the gate portion GU4 constitutes the connection surface.

[0099] As shown in Figure 14, the transistor layer 10 further includes connection points CO5 and CO6.

[0100] The via electrode V4 of the first wiring section WU1 is located directly above the connection point CO5, and the connection point CO5 is in contact with the via electrode V4. Therefore, the connection point CO5 is electrically connected to the contact wiring M4 of the first wiring section WU1 via the via electrode V4. Also, the via electrode V6 of the second wiring section WU2 is located directly below the connection point CO6, and the connection point CO6 is in contact with the via electrode V6. Therefore, the connection point CO6 is electrically connected to the contact wiring M6 of the second wiring section WU2 via the via electrode V6.

[0101] The gate portion GU1 of the first field-effect transistor TR1 does not have an insulating film HK formed on the Y-axis negative side, and this side is in contact with the connection portion CO5 along the Z-axis direction. Therefore, this side of the gate portion GU1 constitutes the connection surface. Similarly, the gate portion GU2 of the second field-effect transistor TR2 does not have an insulating film HK formed on the Y-axis positive side, and this side is in contact with the connection portion CO6 along the Z-axis direction. Therefore, this side of the gate portion GU2 constitutes the connection surface. Furthermore, the gate portion GU3 of the third field-effect transistor TR3 includes a metal gate GA3. The gate portion GU3 does not have an insulating film HK formed on the Y-axis positive side, and this side is in contact with the connection portion CO6 along the Z-axis direction. Therefore, this side of the gate portion GU3 constitutes the connection surface.

[0102] The first field-effect transistor TR1, the second field-effect transistor TR2, and the third field-effect transistor TR3 are arranged vertically along the top surface US, i.e., along the Z-axis. This reduces the occupied area compared to when the three field-effect transistors are arranged horizontally along the top surface, which would require the area of ​​three field-effect transistors.

[0103] (Example 3) Next, a third example of a semiconductor device according to one embodiment of the present invention will be described. Figure 15 is a circuit diagram showing the circuit configuration of the semiconductor device 100C in the third example. Figure 16 is a plan view showing the schematic configuration of the semiconductor device 100C in the third example. Figure 17 is a cross-sectional view showing the schematic configuration of the cross section along the x-x' line shown in Figure 16. Figure 18 is a cross-sectional view showing the schematic configuration of the cross section along the y1-y1' line shown in Figure 16. Figure 19 is a cross-sectional view showing the schematic configuration of the cross section along the y2-y2' line shown in Figure 16. In the third example, the semiconductor device 100C has the same or similar reference numerals as the semiconductor device 100A shown in Figures 5 to 7 for components that are the same or similar, and their descriptions are omitted as appropriate. Furthermore, in the third example, the differences from the first example will be mainly described, and similar effects and benefits due to similar configurations will not be mentioned sequentially.

[0104] In the third example, semiconductor device 100C is a NOR (NOT OR) gate. A NOR gate is a logic circuit that outputs the negative OR of two input signals.

[0105] As shown in Figure 15, the semiconductor device 100C further comprises a third field-effect transistor TR3 and a fourth field-effect transistor TR4. In the example shown in Figure 15, the first field-effect transistor TR1 and the fourth field-effect transistor TR4 are each n-channel type field-effect transistors, and the second field-effect transistor TR2 and the third field-effect transistor TR3 are each p-channel type field-effect transistors.

[0106] A voltage Vin B is applied to the gate electrodes of the first field-effect transistor TR1 and the second field-effect transistor TR2. On the other hand, a voltage Vin A is applied to the gate electrodes of the third field-effect transistor TR3 and the fourth field-effect transistor TR4. Furthermore, a voltage Vout is applied to the drain electrodes of the first field-effect transistor TR1 and the second field-effect transistor TR2. In addition, a voltage Vgnd is applied to the source electrode of the first field-effect transistor TR1 and the source electrode of the fourth field-effect transistor TR4, and a voltage Vdd is applied to the source electrode of the third field-effect transistor TR3. Moreover, the source electrode of the second field-effect transistor TR2 and the drain electrode of the third field-effect transistor TR3 are connected to each other and are at the same potential.

[0107] As shown in Figure 16, the semiconductor device 100C has, for example, a rectangular outline in plan view. A first wiring section WU1 is formed on the upper surface US of the semiconductor device 100C. The first wiring section WU1 includes contact wiring M1, contact wiring M2, contact wiring M3, and contact wiring M4. A second wiring section WU2 is formed on the lower surface LS of the semiconductor device 100B. The second wiring section WU2 includes contact wiring M5, contact wiring M6, and contact wiring M7.

[0108] Contact wire M1 is configured to supply the field shield voltage Vfs. Contact wire M2 is configured to supply the voltage Vdd. Contact wire M3 is configured to supply the voltage Vout. Contact wire M4 is configured to supply the voltage Vin A. Contact wire M5 is configured to supply the voltage Vgnd. Contact wire M6 is configured to supply the voltage Vgnd. Contact wire M7 is configured to supply the voltage Vin B.

[0109] As shown in Figure 17, the semiconductor device 100C comprises a first wiring section WU1, a transistor layer 10, and a second wiring section WU2.

[0110] The first wiring section WU1 further includes via electrodes V1, V2, and V3, in addition to the aforementioned contact wiring M1, M2, and M3.

[0111] The second wiring section WU2 further includes via electrodes V5, V6, and V7, in addition to the aforementioned contact wiring M5, M6, and M7.

[0112] The transistor layer 10 includes the first field-effect transistor TR1, the second field-effect transistor TR2, the third field-effect transistor TR3, and the fourth field-effect transistor TR4 as described above, as well as a fifth field-effect transistor TR5 and a sixth field-effect transistor TR6. The third field-effect transistor TR3 has a gate portion GU3, the fourth field-effect transistor TR4 has a gate portion GU4, the fifth field-effect transistor TR5 has a gate portion GU5, and the sixth field-effect transistor TR6 has a gate portion GU6. The transistor layer 10 also includes connectors CO1, CO2, and CO3. Furthermore, the transistor layer 10 includes connectors CO4, CO5, and CO6 as shown in Figure 16.

[0113] In the first field-effect transistor TR1, a via electrode V6 of the second wiring section WU2 is located directly beneath the first structure ST1, and the source layer SO1 of the first structure ST1 is in contact with the via electrode V6. Therefore, the source layer SO1 of the first structure ST1 is electrically connected to the contact wiring M6 of the second wiring section WU2 via the via electrode V6. Furthermore, in the third field-effect transistor TR3, a via electrode V2 of the first wiring section WU1 is located directly above the third structure ST3, and the source electrode of the third structure ST3 is in contact with the via electrode V2. Therefore, the source electrode of the third structure ST3 is electrically connected to the contact wiring M2 of the first wiring section WU1 via the via electrode V2. In addition, a via electrode V5 of the second wiring section WU2 is located directly beneath the fourth field-effect transistor TR4, and the source electrode of the fourth field-effect transistor TR4 is in contact with the via electrode V5. Therefore, the source electrode of the fourth field-effect transistor TR4 is electrically connected to the contact wiring M5 of the second wiring section WU2 via the via electrode V5.

[0114] The via electrode V3 of the first wiring section WU1 is positioned directly above the connection point CO2, and the connection point CO1 is in contact with the via electrode V3. Therefore, the connection point CO2 is electrically connected to the contact wiring M3 of the first wiring section WU1 via the via electrode V3. Also, the via electrode V1 of the first wiring section WU1 is positioned directly above the connection point CO3, and the connection point CO3 is in contact with the via electrode V1. Therefore, the connection point CO3 is electrically connected to the contact wiring M1 of the first wiring section WU1 via the via electrode V1.

[0115] In the first structure ST1, the drain layer DR1 lacks an insulating film HK on a portion of its surface facing the positive X-axis, and this surface is in contact with the connection part CO2 along the Z-axis. Similarly, the drain layer DR1 of the first structure ST1 lacks an insulating film HK on a portion of its surface facing the negative X-axis, and this surface is in contact with the connection part CO1 along the Z-axis. Therefore, these two surfaces of the drain layer DR1 constitute the connection surface of the first structure ST1. Furthermore, in the second structure ST2, the drain layer DR2 lacks an insulating film HK on a portion of its surface facing the positive X-axis, and this surface is in contact with the connection part CO2 along the Z-axis. Similarly, the drain layer DR2 of the second structure ST2 lacks an insulating film HK on a portion of its surface facing the negative X-axis, and this surface is in contact with the connection part CO1 along the Z-axis. Therefore, these two surfaces of the drain layer DR2 constitute the connection surface of the second structure ST2.

[0116] The drain electrode of the fourth field-effect transistor TR4 lacks an insulating film HK on a portion of its surface facing the positive X-axis, and this surface is in contact with the connection point CO1 along the Z-axis. Therefore, this surface of the drain electrode constitutes the connection surface.

[0117] As described above, the connecting part CO2 is in contact with the surface of the drain layer DR1 of the first structure ST1 and the surface of the drain layer DR2 of the second structure ST2, electrically connecting the drain layer DR1 and the drain layer DR2. Similarly, the connecting part CO1 is in contact with the surface of the drain layer DR1 of the first structure ST1 and the surface of the drain layer DR2 of the second structure ST2, electrically connecting the drain layer DR1 and the drain layer DR2.

[0118] The gate portion GU5 of the fifth field-effect transistor TR5 does not have an insulating film HK formed on the negative X-axis side, and this side is in contact with the connection portion CO3 along the Z-axis direction. Therefore, this side of the gate portion GU5 constitutes the connection surface. Similarly, the gate portion GU6 of the sixth field-effect transistor TR6 does not have an insulating film HK formed on the negative X-axis side, and this side is in contact with the connection portion CO3 along the Z-axis direction. Therefore, this side of the gate portion GU6 constitutes the connection surface.

[0119] The channel portions of the fifth field-effect transistor TR5 and the sixth field-effect transistor TR6 are configured to be electrically cut off. More specifically, the gate portions GU5 and GU6 are configured to have a field shield voltage Vfs applied to them. Specifically, the field shield voltage Vfs is supplied to the gate portions GU5 and GU6 from the contact wiring M1 of the first wiring portion WU1 via the via electrode V1. Therefore, both the fifth field-effect transistor TR5 and the sixth field-effect transistor TR6 are cut off. In the example shown in Figure 17, the fifth field-effect transistor TR5 and the sixth field-effect transistor TR6, rather than the fourth field-effect transistor TR4, correspond to an example of the "fourth field-effect transistor" of the present invention.

[0120] As shown in Figure 18, the first wiring section WU1 further includes via electrodes V4 in addition to the contact wiring M4 described above.

[0121] The transistor layer 10 further contains CO4 at the connection point.

[0122] The via electrode V4 of the first wiring section WU1 is positioned directly above the connection point CO4, and the connection point CO4 is in contact with the via electrode V4. Therefore, the connection point CO4 is electrically connected to the contact wiring M4 of the first wiring section WU1 via the via electrode V4.

[0123] The gate portion GU5 of the fifth field-effect transistor TR5 includes a metal gate GA5. The gate portion GU6 of the sixth field-effect transistor TR6 includes a metal gate GA6. The gate portion GU4 of the fourth field-effect transistor TR4 includes a metal gate GA4. The gate portion GU4 does not have an insulating film HK formed on the negative Y-axis side, and this side is in contact with the connection portion CO4 along the Z-axis direction. Therefore, this side of the gate portion GU4 constitutes the connection surface.

[0124] As shown in Figure 19, the second wiring section WU2 further includes via electrodes V6 and V7 in addition to the contact wiring M6 and M7 described above.

[0125] The transistor layer 10 further includes connection points CO5 and CO6.

[0126] The via electrode V4 of the first wiring section WU1 is located directly above the connection point CO5, and the connection point CO5 is in contact with the via electrode V4. Therefore, the connection point CO5 is electrically connected to the contact wiring M4 of the first wiring section WU1 via the via electrode V4. Also, the via electrode V7 of the second wiring section WU2 is located directly below the connection point CO6, and the connection point CO6 is in contact with the via electrode V7. Therefore, the connection point CO6 is electrically connected to the contact wiring M7 of the second wiring section WU2 via the via electrode V7.

[0127] The gate portion GU1 of the first field-effect transistor TR1 does not have an insulating film HK formed on the Y-axis positive side, and this side is in contact with the connection portion CO6 along the Z-axis direction. Therefore, this side of the gate portion GU1 constitutes the connection surface. Similarly, the gate portion GU2 of the second field-effect transistor TR2 does not have an insulating film HK formed on the Y-axis positive side, and this side is in contact with the connection portion CO6 along the Z-axis direction. Therefore, this side of the gate portion GU2 constitutes the connection surface. Furthermore, the gate portion GU3 of the third field-effect transistor TR3 includes a metal gate GA3. The gate portion GU3 does not have an insulating film HK formed on the Y-axis negative side, and this side is in contact with the connection portion CO5 along the Z-axis direction. Therefore, this side of the gate portion GU3 constitutes the connection surface.

[0128] The first field-effect transistor TR1, the second field-effect transistor TR2, and the third field-effect transistor TR3 are arranged vertically along the top surface US, i.e., along the Z-axis. This reduces the occupied area compared to when the three field-effect transistors are arranged horizontally along the top surface, which would require the area of ​​three field-effect transistors.

[0129] [Manufacturing method for semiconductor devices] Next, a method for manufacturing a semiconductor device according to one embodiment will be described with reference to Figures 20 to 49. Figure 20 is a flowchart showing a first example of a method for manufacturing a semiconductor device 100 in one embodiment. Figures 21 to 28 are cross-sectional views illustrating the pre-process step S210 of the method for manufacturing a semiconductor device 100 in one embodiment. Figure 29 is a cross-sectional view illustrating the step S221 for forming the first structure ST1 of the method for manufacturing a semiconductor device 100 in one embodiment. Figures 30 to 32 are cross-sectional views illustrating the step S222 for forming the second structure ST2 of the method for manufacturing a semiconductor device 100 in one embodiment. Figures 33 to 43 are cross-sectional views illustrating the intermediate process step S230 of the method for manufacturing a semiconductor device 100 in one embodiment. Figures 44 and 45 are cross-sectional views illustrating the step S241 for forming the first wiring section WU1 of the method for manufacturing a semiconductor device 100 in one embodiment. Figures 46 to 48 are cross-sectional views illustrating the step S242 for forming the second wiring section WU2 of the method for manufacturing a semiconductor device 100 in one embodiment. Figure 49 is a cross-sectional view illustrating another example of the formation of the first wiring section WU1 and the second wiring section WU2 in the manufacturing method of the semiconductor device 100 in one embodiment. Figures 21 to 49 show a portion of the semiconductor device 100 manufactured by the manufacturing method for the sake of simplicity. Furthermore, unless otherwise specified, the manufacturing method of the semiconductor device 100 will be described below using the semiconductor device 100A in the first example described above.

[0130] As shown in Figure 20, the manufacturing method S200 first performs a pre-processing step (S210). This step S210 (hereinafter also referred to as the "pre-processing step S210") includes steps performed in advance to form the first structure ST1 in the first field-effect transistor TR1 and the second structure ST2 in the second field-effect transistor TR2.

[0131] The pre-processing step S210 includes, for example, the following steps: As shown in Figure 21, a silicon oxide (SiO2) film f1 and a silicon nitride (SiN) film f2 are alternately deposited on a silicon (Si) substrate SU using low-pressure chemical vapor deposition (LP-CVD). The thickness of the silicon oxide (SiO2) film f1 is, for example, 30 nm, and the thickness of the silicon nitride (SiN) film f2 is, for example, 15 nm.

[0132] Next, as shown in Figure 22, grooves are formed in the silicon oxide (SiO2) film f1 and the silicon nitride (SiN) film f2 by lithography and etching. The outer diameter of the grooves is, for example, 10 nm. Then, undoped silicon (Si) channels INT are formed within the formed grooves by epitaxial growth. Overgrown portions are removed by chemical mechanical polishing (CMP). In addition, to form an element isolation region, the silicon oxide (SiO2) film f1 and silicon nitride (SiN) film f2 on the outer periphery of the device are etched back by lithography and etching.

[0133] Next, as shown in Figure 23, a silicon oxide (SiO2) film g1 is embedded in the grooves formed by etch-back using flowable CVD, and then planarized by CMP. Then, a silicon nitride (SiN) film f3 of about 50 nm is deposited over the entire surface of the planarized surface. Furthermore, a silicon oxide (SiO2) film f4 of about 100 nm is deposited over the entire surface of the silicon nitride (SiN) film f3.

[0134] Next, as shown in Figure 24, the silicon oxide (SiO2) film f4, silicon nitride (SiN) film f3, silicon oxide (SiO2) film f1, and silicon nitride (SiN) film f2 are etched back by reactive etching (RIE). Then, the silicon (Si) substrate SU is etched back to a depth of approximately 40 nm by RIE to form trenches.

[0135] Next, as shown in Figure 25, a silicon nitride (SiN) film of approximately 100 nm is deposited over the entire surface, and then etched back using RIE, leaving the silicon nitride (SiN) film g2 in the trenches formed in the silicon (Si) substrate SU. At this time, the process conditions are set so that the silicon oxide (SiO2) film f4 deposited on the surface is completely removed.

[0136] Next, as shown in Figure 26, a silicon oxide (SiO2) film g3 is embedded in the groove and planarized by CMP.

[0137] Next, as shown in Figure 27, the silicon oxide (SiO2) film g3 is etched by RIE to the position shown in the figure. Then, a silicon nitride (SiN) film is deposited and the entire surface is etched back to form a silicon nitride (SiN) wall SW of about 7 nm on the side wall of the groove.

[0138] Next, as shown in Figure 28, the silicon oxide (SiO2) film g3 at the bottom of the groove is removed by combining silicon oxide (SiO2) RIE and DHF (Dolute Hydrogen Fluoride) (also called DHF cleaning). At this point, a portion of the side surface of the silicon (Si) channel INT is exposed.

[0139] The above describes the general steps included in the preliminary process step S210.

[0140] Returning to the explanation of Figure 20, next, the first structure ST1 in the first field-effect transistor TR1 is formed (S221). As previously mentioned, the first structure ST1 includes a source layer SO1, a channel layer CH1, and a drain layer DR1, and the source layer SO1, channel layer CH1, and drain layer DR1 are stacked along the vertical direction of the upper surface US.

[0141] Specifically, as shown in Figure 29, phosphorus-doped silicon (Si) source and drain layers (labeled "N+" and "N" in Figure 29) are formed in a silicon (Si) channel INT by epitaxial growth. The growth conditions are, for example, a temperature of 700 degrees Celsius and a phosphorus concentration of 5 e20 cm⁻¹. 3 That concludes the process. This completes the formation of the first structure ST1.

[0142] Returning to the explanation of Figure 20, next, the second structure ST2 in the second field-effect transistor TR2 is formed (S222). As previously mentioned, the second structure ST2 includes a source layer SO2, a channel layer CH2, and a drain layer DR2, and the source layer SO2, channel layer CH2, and drain layer DR2 are stacked along the vertical direction of the upper surface US.

[0143] First, as shown in Figure 30, the silicon nitride (SiN) wall SW is removed using high-temperature phosphoric acid (also called hot phosphoric acid). Then, a silicon oxide (SiO2) film g4 is embedded in the groove and planarized by CMP.

[0144] Next, as shown in Figure 31, the silicon oxide (SiO2) film g4 is etched by RIE to the position shown in the figure. Then, the silicon oxide (SiO2) present at the top of the groove is removed by DHF. At this point, a portion of the side surface of the silicon (Si) channel INT is exposed.

[0145] Next, as shown in Figure 32, boron-doped silicon germanium (SiGe) source and drain layers (labeled "P+" and "P" in Figure 32) are formed in a silicon (Si) channel INT by epitaxial growth. The growth conditions are, for example, a temperature of 670 degrees Celsius and a boron concentration of 1 e20 cm⁻¹. 3 In summary, the germanium (Ge) concentration is between 30% and 60%. This condition allows for a reduction in the Schottky barrier height (SBH) of the metal contact to be fabricated later. This then forms the second structure ST2.

[0146] Returning to the explanation of Figure 20, the next step is to perform an intermediate process (S230). This step S230 (hereinafter also referred to as the "intermediate process step S230") includes steps that are performed in advance to form the first wiring section WU1 and the second wiring section WU2.

[0147] Intermediate process step S230 includes, for example, the following steps: As shown in Figure 33, the silicon oxide (SiO2) film g4 is etched and removed by RIE. Then, all silicon nitride (SiN) films f2 and f3 are removed by hot phosphoric acid. Next, the entire device surface is washed with DHF or ozone (O3) water, and then an insulating film HK mainly composed of hafnium oxide (HfO2), etc., is deposited to a thickness of approximately 2 nm by atomic layer deposition (ALD).

[0148] Next, as shown in Figure 34, a conductive film f5 containing approximately 3 nm of titanium nitride (TiN) and approximately 50 nm of tungsten (W) is formed by ALD. To adjust the threshold, a ternary metal carbide (TiAlC) may be formed on the titanium nitride (TiN). Alternatively, titan oxynitride (TiON) may be formed instead of titanium nitride (TiN). Furthermore, La oxide may be deposited on the titanium nitride (TiN) and annealed to form a dipole for threshold adjustment. Finally, the conductive film f5 and the insulating film HK are polished by CMP.

[0149] Next, as shown in Figure 35, the conductive film f5 is removed by RIE and etching is stopped with the insulating film HK. At this time, the conductive film f5 remains between the source layer and the drain layer (indicated as "N+" and "N" in Figure 35) of the first structure ST1. Similarly, the conductive film f5 remains between the drain layer and the source layer (indicated as "P+" and "P" in Figure 35) of the second structure ST2. As a result, gate portions GU1 and GU2 are formed.

[0150] Next, as shown in Figure 36, the grooves are filled with a silicon oxide (SiO2) film g5 and planarized by CMP. Then, using the mask MA shown in the figure, a portion of the silicon oxide (SiO2) film g5 is removed by lithography and etching to form the grooves.

[0151] Next, as shown in Figure 37, a silicon nitride (SiN) wall sw1 of about 7 nm is formed on the side wall of the groove. Then, the silicon oxide (SiO2) film g5 at the bottom of the groove is etched using DHF, exposing the side surface of the conductive film f5 remaining at the bottom.

[0152] Next, as shown in Figure 38, a conductive film g6 containing approximately 3 nm of titanium nitride (TiN) and approximately 50 nm of tungsten (W) is formed by ALD, and then planarized by CMP. Then, the conductive film g6 is etched to the position shown in the figure by RIE or the like.

[0153] Next, as shown in Figure 39, a portion of the silicon nitride (SiN) wall sw1 is removed using hot phosphoric acid or hydrogen fluoride (HF). Then, a conductive film g7 containing approximately 3 nm of titanium nitride (TiN) and approximately 50 nm of tungsten (W) is formed over the entire surface by ALD, and planarized by CMP. Here, the conductive film g7 is connected to the side surface of the gate portion GU1 of the first field-effect transistor TR1 and to the side surface of the gate portion GU2 of the second field-effect transistor TR2.

[0154] Next, as shown in Figure 40, a portion of the silicon oxide (SiO2) film g5 is removed by lithography and etching using the mask MA shown in the figure to form grooves.

[0155] Next, as shown in Figure 41, a silicon nitride (SiN) wall sw2 of approximately 7 nm is formed on the side wall of the groove. Then, the silicon oxide (SiO2) film g5 at the bottom of the groove is etched by DHF, exposing the side surface of the conductive film f5 remaining between the first structure ST1 and the second structure ST2. Furthermore, the remaining conductive film f5 is removed by SPM (Sulfuric acid-hydrogen peroxide mixture) cleaning. At this time, an air gap AG is formed in the removed region.

[0156] Next, as shown in Figure 42, a carbon-containing silicon nitride (SiOCN) film f6 is deposited by ALD.

[0157] Next, as shown in Figure 43, a carbon-containing silicon nitride (SiOCN) film f6 is left between the first structure ST1 and the second structure ST2 by isotropic etch-back across the entire surface. Then, the insulating film HK between the upper half of the side surface of the drain layer of the first structure ST1 and the lower half of the side surface of the drain layer of the second structure ST2 is removed by dry etching. Furthermore, a conductive film g8 containing approximately 3 nm of titanium (Ti), approximately 3 nm of titanium nitride (TiN), and approximately 50 nm of tungsten (W) is formed on the entire surface by CVD or ALD. Here, the surface of the drain layer of the first structure ST1 and the surface of the drain layer of the second structure ST2 are electrically connected by the conductive film g8.

[0158] The above describes the general steps included in the intermediate process step S230.

[0159] Returning to the explanation of Figure 20, next, the first wiring section WU1 is formed (S241). As mentioned above, the first wiring section WU1 is formed on the upper surface US of the semiconductor device 100.

[0160] Specifically, as shown in Figure 44, a silicon oxide (SiO2) film f7 is deposited in the same manner as a normal LSI process to form vias va1, va2, and va3. The materials for vias va1, va2, and va3 are tungsten (W) or cobalt (Co), respectively.

[0161] Next, as shown in Figure 45, a silicon oxide (SiO2) film f8 is deposited, and metal wirings me1, me2, and me3 are formed by the damascene method. The materials for the metal wirings me1, me2, and me3 are tungsten (W) or copper (Cu), respectively. This forms the first wiring section WU1.

[0162] Thus, the manufacturing method S200 for the semiconductor device 100 includes the steps of: forming a first structure ST1 for a first field-effect transistor TR1, comprising a source layer SO1, a channel layer CH1, and a drain layer DR1, wherein the source layer, channel layer, and drain layer are stacked along the vertical direction of the upper surface US; forming a second structure ST2 for a second field-effect transistor TR2, comprising a source layer SO2, a channel layer CH2, and a drain layer DR2, wherein the source layer SO2, channel layer CH2, and drain layer DR2 are stacked along the vertical direction of the upper surface US; and forming a first wiring portion WU1 on the upper surface US. As a result, the first structure ST1 and the second structure ST2 can be electrically connected on a vertical plane along the vertical direction, thereby reducing the contact area in a plan view. Therefore, the occupied area of ​​the semiconductor device 100 can be reduced compared to the case where electrical connection is made on a horizontal plane. Furthermore, by reducing the area occupied by each semiconductor device 100, the number of semiconductor devices 100 that can be manufactured on a single wafer (aluminium substrate) can be increased, thereby lowering the manufacturing cost per semiconductor device 100.

[0163] Returning to the explanation of Figure 20, next, the second wiring section WU2 is formed (S242). As mentioned above, the second wiring section WU2 is formed on the lower surface LS of the semiconductor device 100.

[0164] Specifically, as shown in Figure 46, a support substrate is attached to the surface, the wafer is flipped over, and the bottom surface (back side) shown in the figure is polished. Polishing is then stopped when the conductive film g7 and the source layer of the first structure ST1 (indicated as "N+" and "N" in the figure) are exposed.

[0165] Next, as shown in Figure 47, a silicon oxide (SiO2) film f9 is deposited on the bottom surface (back surface) shown in the figure to form vias va4. The material for vias va4 is tungsten (W) or cobalt (Co).

[0166] Next, as shown in Figure 48, a silicon oxide (SiO2) film f10 is deposited on the bottom surface (back surface) shown in the figure, and metal wiring me4 is formed by the damascene method. The material of the metal wiring me4 is tungsten (W) or copper (Cu). This forms the second wiring section WU2.

[0167] Note that the arrangement of vias and metal wiring is not limited to the example shown in Figure 48. For example, as shown in Figure 49, via va1 may be formed on the silicon oxide (SiO2) film f9 on the bottom (back) surface, and metal wiring me1 may be formed on the silicon oxide (SiO2) film f10 on the bottom (back) surface. In this way, the degree of freedom in circuit design can be increased by freely forming vias and metal wiring on the front and back surfaces.

[0168] After step S242, manufacturing method S200 is completed.

[0169] In this embodiment, the manufacturing method S200 described may be performed in any order, as long as no inconsistencies occur in the process.

[0170] The exemplary embodiments of the present invention have been described above. According to semiconductor devices 100, 100A, 100B, and 100C according to one embodiment of the present invention, the first field-effect transistor TR1 comprises a first structure ST1 including a source layer SO1, a channel layer CH1, and a drain layer DR1, wherein the source layer SO1, the channel layer CH1, and the drain layer DR1 are stacked along the vertical direction of the upper surface US. The second field-effect transistor TR2 comprises a second structure ST2 including a source layer SO2, a channel layer CH2, and a drain layer DR2, wherein the source layer SO2, the channel layer CH2, and the drain layer DR2 are stacked along the vertical direction of the upper surface US. As a result, the first structure ST1 and the second structure ST2 can be electrically connected in a vertical plane along the vertical direction, and the contact area in a plan view can be reduced. Therefore, the occupied area of ​​the semiconductor devices 100, 100A, 100B, and 100C can be reduced compared to the case where electrical connection is made in a horizontal plane.

[0171] Furthermore, according to a method for manufacturing semiconductor devices 100, 100A, 100B, and 100C according to one embodiment of the present invention, the method includes: a step S221 for forming a first structure ST1 of a first field-effect transistor TR1, which includes a source layer SO1, a channel layer CH1, and a drain layer DR1, with the source layer, channel layer, and drain layer stacked along the vertical direction of the upper surface US; a step S222 for forming a second structure ST2 of a second field-effect transistor TR2, which includes a source layer SO2, a channel layer CH2, and a drain layer DR2, with the source layer SO2, channel layer CH2, and drain layer DR2 stacked along the vertical direction of the upper surface US; and a step S241 for forming a first wiring portion WU1 on the upper surface US. As a result, the first structure ST1 and the second structure ST2 can be electrically connected in a vertical plane along the vertical direction, and the contact area in a plan view can be reduced. Therefore, compared to the case where electrical connections are made on a horizontal plane, the occupied area of ​​semiconductor devices 100, 100A, 100B, and 100C can be reduced. Furthermore, by reducing the occupied area per semiconductor device 100, the number of semiconductor devices 100, 100A, 100B, and 100C that can be manufactured on a single wafer (aluminium substrate) can be increased, and the manufacturing cost per semiconductor device 100, 100A, 100B, and 100C can be reduced.

[0172] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit its interpretation. The present invention can be modified or improved without departing from its spirit, and equivalents thereof are also included. That is, embodiments to which those skilled in the art have made appropriate design changes are also included in the scope of the present invention, as long as they retain the features of the present invention. For example, the elements and their arrangement, materials, conditions, shapes, sizes, etc., of the embodiments are not limited to those exemplified and can be modified as appropriate. Furthermore, the embodiments are illustrative, and it goes without saying that partial substitution or combination of configurations shown in different embodiments is possible, and these are also included in the scope of the present invention as long as they retain the features of the present invention. [Explanation of Symbols]

[0173] 10...transistor layer, 100, 100A, 100B, 100C...semiconductor equipment, CH1, CH2...channel layer, CO1, CO2, CO3, CO4, CO5, CO6...connection part, DR1, DR2...drain layer, GU1, GU2, GU3, GU4, GU5, GU6...gate part, LS...bottom surface, SO1, SO2...source layer, ST1...first structure, ST2...second structure, S200...manufacturing method, TR1...first field-effect transistor, TR2...second field-effect transistor, TR3...third field-effect transistor, TR4...fourth field-effect transistor, TR5...fifth field-effect transistor, TR6...sixth field-effect transistor, US...top surface, WU1...first wiring part, WU2...second wiring part.

Claims

1. A semiconductor device having a first surface, The first wiring portion formed on the first surface, The first field-effect transistor and A second field-effect transistor is included, The first field-effect transistor comprises a first structure including a source layer, a channel layer, and a drain layer, wherein the source layer, the channel layer, and the drain layer are stacked along a direction perpendicular to the first surface, The second field-effect transistor comprises a second structure including a source layer, a channel layer, and a drain layer, wherein the source layer, the channel layer, and the drain layer are stacked along the vertical direction. Semiconductor equipment.

2. The device further comprises a connection portion configured to allow current to pass through at least one of the first field-effect transistor and the second field-effect transistor to the first wiring portion, At least one of the first structure and the second structure has a connecting surface that is electrically connected to the connecting portion, and the connecting surface extends along the vertical direction. The semiconductor device according to claim 1.

3. The first structure and the second structure are stacked along the vertical direction. The semiconductor device according to claim 1.

4. The device further comprises a connection portion configured to allow current to pass through at least one of the first field-effect transistor and the second field-effect transistor to the first wiring portion, The connecting portion has a connecting surface that extends along the vertical direction so as to electrically connect the source layer or drain layer of the first structure and the source layer or drain layer of the second structure. The semiconductor device according to claim 3.

5. The device further comprises a connection portion configured to allow current to pass through at least one of the first field-effect transistor and the second field-effect transistor to the first wiring portion, The first field-effect transistor further comprises a gate section, The second field-effect transistor further comprises a gate section, The gate portion of the first field-effect transistor has a connection surface that is electrically connected to the connection portion, and has a connection surface that extends along the vertical direction. The gate portion of the second field-effect transistor has a connection surface that electrically connects with the connection portion, and has a connection surface that extends along the vertical direction. The semiconductor device according to claim 1.

6. The first field-effect transistor is configured such that the first structure and the gate portion are aligned along the vertical direction. The second field-effect transistor is configured such that the second structure and the gate portion are aligned along the vertical direction. The semiconductor device according to claim 5.

7. The gate portion of the first field-effect transistor is configured to surround the first structure in a plan view. The gate portion of the second field-effect transistor is configured to surround the second structure in a plan view. The semiconductor device according to claim 5.

8. It further includes a third field-effect transistor, The first field-effect transistor, the second field-effect transistor, and the third field-effect transistor are arranged along the vertical direction. The semiconductor device according to claim 1.

9. Further comprising a fourth field-effect transistor, The fourth field-effect transistor further comprises a gate portion configured to be electrically isolated. The semiconductor device according to claim 1.

10. The present invention further comprises a second wiring portion formed on a second surface facing the first surface, The semiconductor device according to claim 1.

11. The first field-effect transistor is either an n-channel type or a p-channel type. The second field-effect transistor is the other of the n-channel and p-channel types. The semiconductor device according to any one of claims 1 to 10.

12. A method for manufacturing a semiconductor device comprising a first wiring section, a first field-effect transistor, and a second field-effect transistor, and having a first surface, A step of forming a first structure of the first field-effect transistor, comprising a source layer, a channel layer, and a drain layer, wherein the source layer, the channel layer, and the drain layer are stacked along a direction perpendicular to the first surface, A step of forming a second structure of the second field-effect transistor, comprising a source layer, a channel layer, and a drain layer, wherein the source layer, the channel layer, and the drain layer are stacked along the vertical direction, The process includes the step of forming the first wiring portion on the first surface, A method for manufacturing a semiconductor device.

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