memory devices

Abstract

To improve the yield of memory devices. [Solution] A memory device according to one embodiment includes a semiconductor layer 21, a first wiring layer 22 that is spaced apart in a first direction from the semiconductor layer without any other wiring layers in between, a plurality of second wiring layers 23 that are located on the opposite side of the semiconductor layer from the first wiring layer and are spaced apart in the first direction, a plurality of memory pillars MP that each extend in the first direction and are in contact with the semiconductor layer, and the portion that intersects each of the plurality of second wiring layers functions as a memory cell, and a member SLT that extends within a first plane including the first direction and a second direction intersecting the first direction, and divides the first wiring layer and the plurality of second wiring layers in a third direction intersecting each of the first direction and the second direction. The member includes a fill material LI that extends within the first plane on the side of the plurality of second wiring layers from the semiconductor layer side of the first wiring layer, and an insulating material SP that is provided between the fill material and each of the semiconductor layer, the first wiring layer, and the plurality of second wiring layers, and has a lower thermal conductivity than the fill material.

Description

Technical Field

[0001] Embodiments relate to a memory device. Background Art

[0002] NAND flash memory is known as a memory device capable of non-volatile storage of data. In memory devices such as NAND flash memory, a three-dimensional memory structure is employed for higher integration and larger capacity. Prior Art Literature Patent Literature

[0003] Patent Literature 1 United States Patent Application Publication No. 2014 / 0264542 Specification Patent Literature 2 United States Patent Application Publication No. 2016 / 0133640 Specification Patent Literature 3 United States Patent Application Publication No. 2020 / 0303408 Specification Summary of Invention Problem to be Solved by Invention

[0004] Improve the yield of memory devices. Means for Solving the Problem

[0005] The memory device of the embodiment includes a semiconductor layer, a first wiring layer that is spaced apart in a first direction from the semiconductor layer without any other wiring layers in between, a plurality of second wiring layers that are located on the opposite side of the semiconductor layer from the first wiring layer and are spaced apart in the first direction, a plurality of memory pillars that each extend in the first direction and are in contact with the semiconductor layer, and the portions that intersect each of the plurality of second wiring layers function as memory cells, and a member that extends within a first plane including the first direction and a second direction intersecting the first direction, and divides the first wiring layer and the plurality of second wiring layers in a third direction intersecting each of the first direction and the second direction. The member includes a fill material that extends within the first plane on the side of the plurality of second wiring layers from the semiconductor layer side of the first wiring layer, and an insulating material that is provided between the fill material and each of the semiconductor layer, the first wiring layer, and the plurality of second wiring layers, and has a lower thermal conductivity than the fill material. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of a memory system including a memory device according to the first embodiment. [Figure 2] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a memory device according to the first embodiment. [Figure 3] A plan view showing an example of a planar layout of a memory cell array included in a memory device according to the first embodiment. [Figure 4] A plan view showing an example of a planar layout in region IV of Figure 3, of the memory cell array provided in the memory device according to the first embodiment. [Figure 5] A cross-sectional view along the VV line in Figure 4, showing an example of the cross-sectional structure of a memory cell array provided in the memory device according to the first embodiment. [Figure 6] A cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory pillar in a memory cell array according to the first embodiment. [Figure 7] A perspective view showing an overview of the bonding structure of a memory device according to the first embodiment. [Figure 8]A cross-sectional view showing an example of the cross-sectional structure of a bonding pad provided in a memory device according to the first embodiment. [Figure 9] A cross-sectional view showing an example of the cross-sectional structure of a memory device according to the first embodiment. [Figure 10] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 11] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 12] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 13] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 14] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 15] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 16] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 17] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 18] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 19] A cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in a memory device according to a modified example of the first embodiment. [Figure 20] A cross-sectional view showing an example of the cross-sectional structure of a memory cell array provided in a memory device according to the second embodiment. [Figure 21] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the second embodiment. [Figure 22] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the second embodiment. [Figure 23] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the second embodiment. [Figure 24] Cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory device according to the second embodiment. [Figure 25] Cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the first modification of the second embodiment. [Figure 26] Cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the second modification of the second embodiment. [Figure 27] Cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the third embodiment. [Figure 28] Cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory device according to the third embodiment. [Figure 29] Cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory device according to the third embodiment. [Figure 30] Cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory device according to the third embodiment. [Figure 31] Cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory device according to the third embodiment. [Figure 32] Cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory device according to the third embodiment. [Figure 33] Cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the first modification of the third embodiment. [Figure 34] Cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the second modification of the third embodiment. [Figure 35] Cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the third modification of the third embodiment. [Figure 36] Cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the fourth modification of the third embodiment. [Figure 37] Cross-sectional view illustrating an example of a cross-sectional structure of a memory cell array included in the memory device according to the fourth embodiment. [Figure 38]A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 39] A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 40] A cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in a memory device according to a modified example of the fourth embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. The dimensions and proportions in the drawings are not necessarily the same as those in reality.

[0008] In the following explanation, components having substantially the same function and structure will be assigned the same reference numeral. When elements with similar structures need to be specifically distinguished, different letters or numbers may be added to the end of the same reference numeral.

[0009] 1. First Embodiment 1.1 Configuration 1.1.1 Memory System Configuration Figure 1 is a block diagram showing an example of the configuration of a memory system including a memory device according to the first embodiment. Memory system 1 is a storage device configured to be connected to an external host (not shown). Memory system 1 is, for example, an SD TM These include memory cards, UFS (universal flash storage), and SSDs (solid state drives). Memory system 1 includes a memory controller 2 and a memory device 3.

[0010] The memory controller 2 is composed of an integrated circuit, such as a system-on-a-chip (SoC). The memory controller 2 controls the memory device 3 based on requests from the host. Specifically, for example, the memory controller 2 writes data to the memory device 3 when requested to write by the host. The memory controller 2 also reads data from the memory device 3 when requested to read by the host and sends it to the host.

[0011] Memory device 3 is a non-volatile memory. Memory device 3 is, for example, a NAND flash memory. Memory device 3 stores data in a non-volatile manner.

[0012] Communication between the memory controller 2 and the memory device 3 conforms to, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0013] 1.1.2 Memory Device Configuration Next, with reference to the block diagram shown in Figure 1, the internal configuration of the memory device according to the first embodiment will be described. The memory device 3 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0014] The memory cell array 10 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). The number of blocks BLK included in the memory cell array 10 may be one or less. A block BLK is a collection of multiple memory cells. A block BLK is used, for example, as a data erasure unit. The memory cell array 10 is also provided with multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0015] The command register 11 stores the command CMD received by the memory device 3 from the memory controller 2. The command CMD includes instructions that cause the sequencer 13 to perform read operations, write operations, erase operations, etc.

[0016] The address register 12 stores the address information ADD received by the memory device 3 from the memory controller 2. The address information ADD includes, for example, the block address BAd, the page address PAAd, and the column address CAD. For example, the block address BAd, the page address PAAd, and the column address CAD are used for selecting the block BLK, word line, and bit line, respectively.

[0017] The sequencer 13 controls the operation of the entire memory device 3. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16, etc., based on the command CMD stored in the command register 11, to perform read operations, write operations, erase operations, etc.

[0018] The driver module 14 generates voltages used in read, write, and erase operations. Then, based on the page address PAd stored in the address register 12, for example, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line.

[0019] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address Bad stored in the address register 12. Then, the row decoder module 15 transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0020] During a write operation, the sense amplifier module 16 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 2. During a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line and transfers the determination result to the memory controller 2 as read data DAT.

[0021] 1.1.3 Memory cell array Next, the configuration of the memory cell array provided in the memory device according to the first embodiment will be described.

[0022] 1.1.3.1 Circuit Configuration Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array provided in the memory device according to the first embodiment. In Figure 2, one of the multiple block BLKs included in the memory cell array 10 is shown. As shown in Figure 2, the block BLK includes, for example, four string units SU0 to SU3.

[0023] Each string unit SU includes multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). The number of bit lines BL may be one or less. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, and stores data nonvolatilically. Each of the selection transistors ST1 and ST2 is used to select the string unit SU during various operations.

[0024] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. The drain of selection transistor ST1 is connected to the associated bit line BL. The source of selection transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. The drain of selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of selection transistor ST2 is connected to the source line SL.

[0025] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of selection transistors ST1 in string units SU0 to SU3 are connected to selection gate lines SGD0 to SGD3, respectively. The gates of multiple selection transistors ST2 are connected to the selection gate line SGS.

[0026] Bit lines BL0 to BLm are each assigned a different column address. Each bit line BL is shared among multiple block BLKs by a NAND string NS that is assigned the same column address. Word lines WL0 to WL7 are provided for each block BLK. Source lines SL are shared, for example, among multiple block BLKs.

[0027] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0028] The circuit configuration of the memory cell array 10 provided in the memory device 3 according to the first embodiment is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to any number.

[0029] 1.1.3.2 Planar Layout Figure 3 is a plan view showing an example of a planar layout of a memory cell array in a memory device according to the first embodiment. In Figure 3, four blocks BLK0 to BLK3 are shown as examples of the multiple blocks BLK in the memory cell array 10.

[0030] The memory cell array 10 includes a stacked wiring structure. The stacked wiring structure is a structure in which wiring layers (word lines WL0 to WL7, and selected gate lines SGD and SGS) are stacked.

[0031] In the following, the plane approximately parallel to the stacking plane of the wiring layers will be referred to as the XY plane. The directions that are orthogonal to each other in the XY plane will be the X direction and the Y direction. The direction approximately perpendicular to the XY plane and moving from the selected gate line SGS to the selected gate line SGD will be referred to as the Z1 direction. The direction approximately perpendicular to the XY plane and moving from the selected gate line SGD to the selected gate line SGS will be referred to as the Z direction. If neither the Z1 direction nor the Z2 direction is specified, it will be referred to as the Z direction.

[0032] As shown in Figure 3, the stacked wiring structure has memory regions MRa and MRb aligned in the X direction, and a lead region HR. Memory regions MRa and MRb are regions where memory cell transistors MT are provided. The lead region HR is a region where contacts are provided to electrically connect each wiring layer and the low decoder module 15. The lead region HR is located, for example, between memory region MRa and memory region MRb.

[0033] Each of the multiple block BLKs includes a portion of the stacked wiring structure that extends in the X direction across the memory area MRa, the lead area HR, and the memory area MRb. The multiple block BLKs are aligned in the Y direction. The memory cell array 10 includes, for example, multiple members SLT and multiple members SHE.

[0034] Each SLT component, for example, although not shown in Figure 3, has a structure in which a plate-shaped fill material LI is embedded in a plate-shaped insulating material SP. Each SLT component extends in the X direction so as to traverse the memory area MRa, the lead area HR, and the memory area MRb. Multiple SLT components are arranged in the Y direction. Each SLT component separates adjacent wiring layers through it. In the memory cell array 10, each region separated by an SLT component corresponds to one block BLK.

[0035] Each component SHE is, for example, a plate-shaped insulator. The group of components SHE includes a group of components SHE aligned in the Y direction in the memory region MRa, and a group of components SHE aligned in the Y direction in the memory region MRb. Each component SHE located in the memory region MRa extends in the X direction so as to traverse the memory region MRa. Each component SHE located in the memory region MRb extends in the X direction so as to traverse the memory region MRb.

[0036] In the example shown in Figure 3, in each of the memory regions MRa and MRb, three members SHE are arranged between two adjacent members SLT in the Y direction. Each member SHE has, for example, a structure in which an insulator is embedded. Each member SHE separates the selected gate line SGD of the adjacent wiring layer through the member SHE. In the memory cell array 10, each region separated by a pair of adjacent members SLT and SHE, or a pair of two adjacent members SHE, corresponds to one string unit SU.

[0037] The planar layout of the memory cell array 10 may be any other layout. For example, the number of member SHEs placed between two adjacent member SLTs can be designed to be any number. The number of string units SUs provided in each block BLK can be changed based on the number of member SHEs placed between two adjacent member SLTs.

[0038] Figure 4 is a plan view showing an example of the planar layout in region IV of Figure 3 of the memory cell array provided by the memory device according to the first embodiment. In Figure 4, a portion of the memory region MRb of block BLK0 is shown. Although not shown in Figure 4, the memory region MRa has the same configuration as the memory region MRb.

[0039] As shown in Figure 4, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL in the memory region MR.

[0040] Each memory pillar MP functions as a single NAND string NS. Multiple memory pillar MPs are arranged in a staggered pattern, for example, 19 rows, in the region between two adjacent members SLT. For example, counting from the top of the paper, one member SHE is placed overlapping the 5th, 10th, and 15th memory pillar MPs.

[0041] Multiple bit lines BL each extend in the Y direction and are aligned in the X direction. Each bit line BL is positioned to overlap with at least one memory pillar MP for each string unit SU. In the example in Figure 4, two bit lines BL overlap one memory pillar MP. The memory pillar MP is electrically connected to one of the multiple overlapping bit lines BL via contact CV. On the other hand, contact CV between a memory pillar MP that overlaps with member SHE (i.e., in contact with two different selection gate lines SGD) and a bit line BL may be omitted.

[0042] Furthermore, the planar layout in the memory area MR may be any other layout. For example, the number and arrangement of memory pillars MP and members SHE placed between two adjacent members SLT can be changed as appropriate. The number of bit lines BL overlapping each memory pillar MP can be designed to be any number.

[0043] 1.1.3.3 Cross-sectional structure Figure 5 is a cross-sectional view along the VV line in Figure 4, showing an example of the cross-sectional structure of a memory cell array in the memory device according to the first embodiment. In Figure 5, the YZ cross-sectional structure of the memory region MR is shown.

[0044] As shown in Figure 5, the memory cell array 10 includes, for example, wiring layers 21, 22, 23, and 24, a conductive layer 25, and insulating layers 31, 32, 33, 34, 35, and 36. The insulating layers 31, 32, 33, 34, 35, and 36 include, for example, silicon oxide. In Figure 5, the Z1 direction corresponds to the top of the paper.

[0045] A wiring layer 21 is provided on the insulating layer 31. The wiring layer 21 is formed, for example, in a plate shape extending in the XY plane. The wiring layer 21 is used as a source wire SL. The wiring layer 21 includes conductive layers 21a and 21b, and semiconductor layers 21c and 21d. The Z2-direction side surfaces of the conductive layers 21a and 21b, and the semiconductor layer 21c are formed to have irregularities in the region that overlaps with the memory pillar MP and member SLT when viewed in the Z direction.

[0046] The conductive layer 21a is provided on the Z1-direction side surface of the insulating layer 31. The conductive layer 21a has a shape that is recessed in the Z2 direction in the region that includes the portion overlapping with the memory pillar MP and member SLT when viewed in the Z direction. The conductive layer 21a contains, for example, tungsten and has the function of lowering the resistance value of the source wire SL.

[0047] The conductive layer 21b is provided on the Z1-direction side surface of the conductive layer 21a. The conductive layer 21b has a shape that is recessed in the Z2 direction in the region that includes the portion overlapping with the memory pillar MP and member SLT when viewed in the Z direction. The conductive layer 21b contains, for example, titanium nitride and is used as a barrier metal.

[0048] The semiconductor layer 21c is provided on the Z1-direction side surface of the conductive layer 21b. The semiconductor layer 21c has a shape that is recessed in the Z2 direction in the region that includes the portion overlapping with the memory pillar MP and the member SLT when viewed in the Z direction. The semiconductor layer 21c covers the Z2-direction side end of the semiconductor film 42 of the memory pillar MP (described later) and the Z2-direction side end of the insulating film 52 of the member SLT (described later). The semiconductor layer 21c contains, for example, polysilicon.

[0049] The semiconductor layer 21d is provided on the Z1-direction side surface of the semiconductor layer 21c. The semiconductor layer 21d is formed, for example, as a plate extending in the XY plane. The semiconductor layer 21d contains, for example, polysilicon.

[0050] An insulating layer 32 is provided on the Z1-direction side surface of the semiconductor layer 21d. A wiring layer 22 is provided on the Z1-direction side surface of the insulating layer 32. The wiring layer 22 is formed, for example, in the shape of a plate extending in the XY plane. The wiring layer 22 contains, for example, tungsten or molybdenum and is used as a selectable gate wire (SGS).

[0051] Multiple insulating layers 33 and wiring layers 23 are alternately arranged on the Z1-direction side of the wiring layer 22. The multiple wiring layers 23 are formed, for example, in a plate shape extending in the XY plane. The multiple wiring layers 23 contain, for example, tungsten or molybdenum and are used as word lines WL0 to WL7 in order from the wiring layer 21 side.

[0052] An insulating layer 34 is provided on the Z1-direction side of the uppermost wiring layer 23. A wiring layer 24 is provided on the Z1-direction side of the insulating layer 35. The wiring layer 24 is formed, for example, in a plate shape extending in the XY plane. The wiring layer 24 contains, for example, tungsten or molybdenum and is used as a selectable gate wire SGD. An insulating layer 35 is provided on the Z1-direction side of the wiring layer 24.

[0053] Each of the multiple memory pillars MP extends in the Z direction and penetrates the wiring layers 22-24 and the insulating layers 32-34. Each of the multiple memory pillars MP includes, for example, a core film 41, a semiconductor film 42, and a multilayer film 43. The core film 41 is an insulator extending in the Z direction. The semiconductor film 42 covers the core film 41. The Z2-direction end of the semiconductor film 42 is in contact with the semiconductor layer 21c. The multilayer film 43 covers the side surface of the semiconductor film 42, excluding the Z2-direction end. The Z2-direction end face of the multilayer film 43 is aligned with, for example, the Z2-direction face of the semiconductor layer 21d.

[0054] Figure 6 is a cross-sectional view along line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory pillar in a memory device according to the first embodiment. In Figure 6, a cross-section is shown that includes the memory pillar MP and the wiring layer 23 and is parallel to the XY plane. As shown in Figure 6, the laminated film 43 includes, for example, a tunnel insulating film 44, a charge storage film 45, and a block insulating film 46.

[0055] The core film 41 is provided, for example, in the central portion of the memory pillar MP. The semiconductor film 42 surrounds the core film 41 when viewed in the Z direction. The tunnel insulating film 44 surrounds the semiconductor film 42 when viewed in the Z direction. The charge storage film 45 surrounds the tunnel insulating film 44 when viewed in the Z direction. The block insulating film 46 surrounds the charge storage film 45 when viewed in the Z direction. The wiring layer 23 surrounds the block insulating film 46 when viewed in the Z direction. The semiconductor film 42 is used as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The tunnel insulating film 44 and the block insulating film 46 each contain, for example, silicon oxide. The charge storage film 45 contains, for example, silicon nitride.

[0056] With the above configuration, each memory pillar MP functions as a single NAND string NS. That is, the portion where the memory pillar MP intersects with the wiring layer 22 functions as a selection transistor ST2. The portion where the memory pillar MP intersects with the wiring layer 23 functions as a memory cell transistor MT. The portion where the memory pillar MP intersects with the wiring layer 24 functions as a selection transistor ST1.

[0057] A contact CV is provided on the Z1-direction side surface of the semiconductor film 42 of the memory pillar MP. A conductive layer 25 is provided on the Z1-direction side surface of the contact CV. The conductive layer 25 is formed, for example, in the shape of a line extending in the Y direction. The conductive layer 25 contains, for example, copper and is used as a bit line BL. An insulating layer 36 is provided on the Z1-direction side surface of the conductive layer 25. The layer on which the conductive layer 25 is provided is also called layer M0.

[0058] The fill material LI is a plate-shaped member that extends in the XZ plane. The fill material LI has a higher thermal conductivity and Young's modulus than the insulating material SP. The fill material LI contains, for example, tungsten or polysilicon. The fill material LI intersects with the wiring layers 23 and 24, as well as the insulating layers 33-35. The end face of the fill material LI on the Z2 direction side is located on the Z1 direction side of the Z2 direction side of the wiring layer 22.

[0059] The insulating material SP includes insulating films 51 and 52. Insulating film 51 is an insulator that covers the side surface and the end face on the Z2 direction side of the fill material LI. Insulating film 51 has a portion (bottom) that extends in the Z direction on the Z2 direction side of the fill material LI. The bottom of insulating film 51 reaches, for example, the semiconductor layer 21c. Insulating film 52 is provided so as to cover the bottom of insulating film 51 in the Z2 direction. Insulating films 51 and 52 include, for example, silicon oxide. When the fill material LI is conductive, insulating films 51 and 52 electrically insulate the fill material LI from each of the wiring layers 22 to 24.

[0060] In the member SLT composed of the fill material LI and insulating material SP as described above, the width b of the member SLT in the Y direction is greater than twice the film thickness a of the portion of the insulating film 51 that covers the side surface of the fill material LI. The distance c from the Z2-direction end face of the insulating material SP to the Z2-direction end face of the fill material LI is greater than the film thickness a of the insulating film 51.

[0061] 1.1.4 Structure of memory devices Next, the structure of the memory device according to the first embodiment will be described.

[0062] 1.1.4.1 Laminated structure Figure 7 is a perspective view showing an overview of the bonded structure of a memory device according to the first embodiment. As shown in Figure 7, the memory device 3 comprises a memory chip 100 and a circuit chip 200. The memory chip 100 includes a structure corresponding to a memory cell array 10. The circuit chip 200 includes structures corresponding to, for example, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0063] Furthermore, each of the memory chip 100 and the circuit chip 200 includes a plurality of bonding pads BP. The memory device 3 is formed by bonding the memory chip 100 and the circuit chip 200 together via a plurality of bonding pads BP.

[0064] 1.1.4.2 Adhesive Pads Figure 8 is a cross-sectional view showing an example of the cross-sectional structure of a bonding pad provided in a memory device according to the first embodiment. In the example in Figure 8, the bonding pads BP of the memory chip 100 and the circuit chip 200 on the bonding surface, as well as the contacts connected to each bonding pad BP, are shown.

[0065] As shown in Figure 8, during the bonding process, the bonding pad BP of the memory chip 100 is connected to the bonding pad BP of the circuit chip 200. In the example in Figure 8, the area of ​​the bonding pad BP of the memory chip 100 and the circuit chip 200 on the bonding surface is approximately equal. In such a case, if copper is used for the bonding pad BP, the copper of the bonding pad BP of the memory chip 100 and the copper of the bonding pad BP of the circuit chip 200 may become integrated, making it difficult to confirm the boundary between the copper. However, bonding can be confirmed by the distortion of shape due to the misalignment of the bonding pads BP and the misalignment of the copper barrier metal (occurrence of discontinuities on the side).

[0066] Furthermore, when the bonded pads BP are formed by the damascene method, each side has a tapered shape. As a result, the side walls of the portion where the bonded bonded pads BP meet are not straight in the cross-sectional shape along the Z direction, and the shape of the cross-section is not rectangular.

[0067] Furthermore, when bonded pads BP are bonded together, the bottom, sides, and top surfaces of the copper forming them are covered with barrier metal. In contrast, in a typical wiring layer using copper, an insulating layer (such as silicon nitride or silicon carbonitride) that prevents copper oxidation is provided on the top surface of the copper, and no barrier metal is provided. Therefore, even if there is no misalignment during bonding, it is possible to distinguish it from a typical wiring layer.

[0068] 1.1.4.3 Cross-sectional structure Figure 9 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to the first embodiment. In Figure 9, the Z2 direction corresponds to the top of the paper.

[0069] As shown in Figure 9, the memory device 3 further includes conductive layers 26 and 27, a protective layer 30, and contacts V0 and V1 in the memory chip 100. The memory device 3 also includes a substrate 60, an insulating layer 61, conductive layers 62, 63, 64, and 65, a transistor TR, and contacts CS, C1, C2, C3, and C4 in the circuit chip 200.

[0070] First, let me explain the memory chip 100.

[0071] The protective layer 30 is provided on the Z2-direction side surface of the insulating layer 31. The protective layer 30 is a layer corresponding to the surface of the memory device 3 and includes, for example, a resin material such as polyimide. In areas not shown, a portion of the protective layer 30 is removed. A power pad, which is responsible for electrical connection to the outside, is provided in the portion where the protective layer 30 has been removed.

[0072] A contact V0 is provided on the Z1-direction side surface of the conductive layer 25. A conductive layer 26 is provided on the Z1-direction side surface of the contact V0.

[0073] A contact V1 is provided on the Z1-direction side surface of the conductive layer 26. A conductive layer 27 is provided on the Z1-direction side surface of contact V1. The conductive layer 27 functions as a bonding pad BP on the bonding surface of the memory chip 100 with the circuit chip 200. The conductive layers 26 and 27, as well as contacts V0 and V1, are covered by an insulating layer 36. The layers on which the conductive layers 26 and 27 are provided are also called layer M1 and bonding layer B1, respectively.

[0074] Next, we will describe the circuit chip 200.

[0075] The substrate 60 is a silicon substrate. An insulating layer 61 is provided on the surface of the substrate 60 in the Z2 direction. Transistors TR are provided on the substrate 60 and the insulating layer 61.

[0076] The transistor TR is a structure that constitutes various circuits provided on the circuit chip 200. In the example in Figure 9, the transistor TR corresponds to a circuit connected to the bit line BL (for example, a transistor in the sense amplifier module 16).

[0077] A contact C1 is provided on the Z2-direction side surface of the gate electrode of transistor TR. A contact CS is provided on the Z2-direction side surface of the region of the substrate 50 that functions as the source or drain of transistor TR. A conductive layer 62 is provided on the Z2-direction side surfaces of each of contacts CS and C1. Contacts CS and C1, and the conductive layer 62, contain, for example, tungsten.

[0078] A contact C2 is provided on the Z2-direction side surface of the conductive layer 62. A conductive layer 63 is provided on the Z2-direction side surface of contact C2. A contact C3 is provided on the Z2-direction side surface of conductive layer 63. A conductive layer 64 is provided on the Z2-direction side surface of contact C3. A contact C4 is provided on the Z2-direction side surface of conductive layer 64. A conductive layer 65 is provided on the Z2-direction side surface of contact C4. Conductive layer 65 is in contact with the corresponding conductive layer 27 and functions as an adhesive pad BP on the bonding surface of the circuit chip 200 with the memory chip 100. Conductive layers 62, 63, 64, and 65, as well as contacts CS, C1, C2, C3, and C4, are covered by an insulating layer 61. The layers on which the conductive layers 62, 63, 64, and 65 are provided are also called layers D0, D1, D2, and the bonding layer B2, respectively.

[0079] 1.2 Manufacturing method Figures 10 to 18 show examples of the structure of a memory device during manufacturing according to the first embodiment. Of these, Figures 10 to 15 are cross-sectional views of the memory cell array 10 in the memory chip 100 before bonding, and correspond to Figure 5. Figures 16 to 18 are cross-sectional views of the memory chip 100 and circuit chip 200 after bonding, and correspond to Figure 9.

[0080] The memory chip 100 and the circuit chip 200 are manufactured separately. The following focuses on the manufacturing method of the memory chip 100.

[0081] First, as shown in Figure 10, an insulating layer 71 is provided on the Z1-direction side surface of the substrate 70. The substrate 70 is the substrate for the memory chip 100 and includes, for example, silicon. The insulating layer 71 includes, for example, silicon oxide.

[0082] A semiconductor layer 72 is provided on the Z1-direction side surface of the insulating layer 71. An insulating layer 73 is provided on the Z1-direction side surface of the semiconductor layer 72. A semiconductor layer 21d is provided on the Z1-direction side surface of the insulating layer 73. The semiconductor layer 72 includes, for example, polysilicon. The insulating layer 73 includes, for example, silicon oxide.

[0083] Then, a laminated structure corresponding to the laminated wiring structure is provided on the Z1 direction side of the semiconductor layer 21d. Specifically, an insulating layer 32 and a sacrificial layer 74 are provided in this order on the Z1 direction side surface of the semiconductor layer 21d. Insulating layers 33 and sacrificial layers 75 are alternately laminated on the Z1 direction side surface of the sacrificial layer 74. Insulating layers 34 and sacrificial layers 76 are provided in this order on the Z1 direction side surface of the uppermost sacrificial layer 75. An insulating layer 35 is provided on the Z1 direction side surface of the sacrificial layer 76. Sacrificial layers 74 to 76 include, for example, silicon nitride.

[0084] Next, as shown in Figure 11, multiple holes (not shown) are provided in the region of the stacked structure where the memory pillar MP is to be installed. The bottom surfaces of the multiple holes reach, for example, the semiconductor layer 72. Then, the stacked film 43, the semiconductor film 42, and the core film 41 are deposited in this order within each hole, and each hole is filled. This forms the structure corresponding to the memory pillar MP. In the structure corresponding to the memory pillar MP, the stacked film 43 covers the Z2 direction edge of the semiconductor film 42.

[0085] Next, as shown in Figure 12, a groove SH1 is formed in the region where the member SLT is to be installed. The bottom surface of the groove SH1 reaches, for example, the semiconductor layer 72. Then, the layered structure replacement process is performed through the groove SH1.

[0086] In the replacement process of the laminated structure, sacrificial layers 74, 75, and 76 are selectively removed via grooves SH1 by wet etching with thermal phosphoric acid or the like. Then, the conductor is embedded in the space where the sacrificial layers 74, 75, and 76 were removed via grooves SH1. Subsequently, the conductor formed inside grooves SH1 is removed by an etch-back process. This separates the conductor formed inside grooves SH1 into multiple conductor layers. This forms a wiring layer 22 that functions as a selective gate line SGS, multiple wiring layers 23 each that functions as a word line WL, and a wiring layer 24 that functions as a selective gate line SGD. The wiring layers 22, 23, and 24 formed in this process may contain a barrier metal. In this case, in the formation of the conductor after the removal of sacrificial layers 74, 75, and 76, for example, titanium nitride is deposited as a barrier metal, followed by tungsten.

[0087] Next, as shown in Figure 13, an insulating film 52 and a sacrificial film 77 are deposited in the groove SH1 in that order, thereby filling the groove SH1. The sacrificial film 77 contains, for example, SOC (spin-on carbon).

[0088] Next, as shown in Figure 14, a groove SH2 is formed in the region where the member SLT is to be installed. Specifically, first, a portion of the sacrificial film 77 is etched back, leaving a portion corresponding to the bottom of the insulating film 51. Then, the insulating film 52 is removed to approximately the same height as the Z1-direction side of the sacrificial film 77 remaining after the etch-back process. Subsequently, the groove SH2 is formed by removing the sacrificial film 77 remaining after the etch-back process.

[0089] Within groove SH2, at least a portion of wiring layer 24 and wiring layer 23 is exposed. Wiring layer 22 may be partially exposed, but it is preferable that it is not completely exposed. That is, the Z1-side surface of the insulating film 52 remaining on the Z2-side of groove SH2 is preferably located on the Z1-side side of the wiring layer 22 than the Z2-side surface.

[0090] Next, as shown in Figure 15, an insulating film 51 and a filler material LI are deposited in the groove SH2 in that order, and the groove SH2 is filled. The width of the groove SH2 at the height where the insulating film 52 remains is smaller than twice the thickness a of the insulating film 51. Therefore, the portion of the groove SH2 at the height where the insulating film 52 remains is closed by the insulating film 51. In contrast, the width b of the portion of the groove SH2 on the Z1 side of the insulating film 52 is larger than twice the thickness a of the insulating film 51. Therefore, the portion of the groove SH2 on the Z1 side of the insulating film 52 is not closed by the insulating film 51. The portion of the groove SH2 that is not closed by the insulating film 51 is then filled by the filler material LI. Thus, the member SLT is formed.

[0091] Subsequently, the structure on the Z1 direction side is formed from the component SHE and the stacked wiring structure, and the manufacturing of the memory chip 100 is completed.

[0092] Next, as shown in Figure 16, the memory chip 100 and the circuit chip 200 are bonded together.

[0093] Next, as shown in Figure 17, the substrate 70, the insulating layer 71, and the semiconductor layer 72 are removed. Then, the insulating layer 73 and the portion of the laminated film 43 on the Z2 direction side of the semiconductor layer 21d are removed. As a result, the portion of the semiconductor film 42 on the Z2 direction side of the semiconductor layer 21d is exposed. In addition, when removing the insulating layer 73 and the laminated film 43, the portion of the insulating film 52 on the Z2 direction side of the semiconductor layer 21d is also partially removed.

[0094] Next, as shown in Figure 18, a semiconductor is provided so as to cover the semiconductor layer 21d, the semiconductor film 42, and the insulating film 52. The semiconductor includes, for example, amorphous silicon. After film formation, impurities such as arsenic are implanted into the semiconductor. The semiconductor is then heated and crystallized, for example by laser annealing. This forms a conductive semiconductor layer 21c.

[0095] Conductive layers 21b and 21a are stacked in this order on the Z2-direction side of the semiconductor layer 21c. This forms a wiring layer 21 that functions as a source line SL.

[0096] Subsequently, an insulating layer 31 and a protective layer 30 are formed on the Z2 side from the wiring layer 21. Thus, the memory device 3 is formed.

[0097] 1.3 Effects of the First Embodiment According to the first embodiment, the yield of the memory device 3 can be improved. This effect will be explained below.

[0098] The fill material LI extends in the XZ plane from the semiconductor layer 21d side of the wiring layer 22 towards the multiple wiring layers 23. The insulating material SP is provided between the fill material LI and each of the semiconductor layer 21d, wiring layer 22, multiple wiring layers 23, and wiring layer 24, and has a lower thermal conductivity than the fill material LI. This allows for the interposition of an insulating material SP of sufficient thickness between the fill material LI and the semiconductor layer 21c. Therefore, when the semiconductor layer 21c is heated by laser annealing, heat is absorbed by the fill material LI, which has a relatively high thermal conductivity, and this prevents the semiconductor layer 21c from not crystallizing sufficiently near the component SLT. Consequently, the degradation of the characteristics of the wiring layer 21 near the component SLT can be suppressed.

[0099] Furthermore, the length b of the component SLT in the Y direction is longer than twice the length a of the portion of the insulating material SP (insulating film 51) between the fill material LI and each of the multiple wiring layers 23. The length c of the portion of the insulating material SP on the semiconductor layer 21d side of the fill material LI in the Z direction is longer than length a. Thus, the film thickness of the insulating material SP on the semiconductor layer 21d side of the fill material LI is significantly greater than the film thickness of the insulating material SP on the side of the fill material LI. This reduces the amount of heat generated during the laser annealing process that is transferred to the fill material LI. Therefore, crystallization of the semiconductor layer 21d near the component SLT can be promoted.

[0100] Furthermore, the fill material LI has a higher Young's modulus than the insulating material SP. This allows for a higher bending strength of the memory cell array 10 compared to when the component SLT is composed solely of the insulating material SP.

[0101] 1.4 Modifications of the First Embodiment Various modifications can be applied to the first embodiment described above.

[0102] In the first embodiment described above, the case in which the insulating material SP is formed by two types of insulating films 51 and 52 was described, but the invention is not limited thereto. The insulating material SP may be formed by one type of insulating film.

[0103] Figure 19 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in a memory device according to a modified example of the first embodiment. Figure 19 corresponds to Figure 5 in the first embodiment.

[0104] As shown in Figure 19, in a modified example of the first embodiment, the insulating material SP includes an insulating film 53 instead of insulating films 51 and 52.

[0105] The insulating film 53 is an insulator that covers the side surface and the end surface on the Z2 direction side of the fill material LI. The insulating film 53 has a portion (bottom) that extends in the Z direction on the Z2 direction side of the fill material LI. The bottom of the insulating film 53 is thicker than the film thickness a of the portion covering the side surface of the fill material LI and reaches the semiconductor layer 21c. The insulating film 53 contains, for example, silicon oxide. The insulating film 53 electrically insulates the fill material LI from each of the wiring layers 22 to 24 when the fill material LI is conductive.

[0106] In the member SLT composed of the fill material LI and insulating material SP described above, the width b of member SLT in the Y direction is greater than twice the film thickness a of the portion of the insulating film 53 that covers the side surface of the fill material LI. The distance c from the Z2-direction end face of insulating material SP to the Z2-direction end face of fill material LI is greater than the film thickness a of the portion of the insulating film 53 that is Z1-direction from the bottom.

[0107] Such an insulating film 53 can be realized by using a film deposition process (bottom-up fill process) in which the thickness of the film formed on the bottom surface of the groove SH1 is greater than the thickness of the film formed on the sides.

[0108] Even with the above configuration, similar to the first embodiment, the thickness of the insulating material SP on the semiconductor layer 21d side of the fill material LI can be made significantly larger than the thickness of the insulating material SP on the side of the fill material LI. This reduces the amount of heat generated during the laser annealing process that is transferred to the fill material LI. As a result, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0109] 2. Second Embodiment Next, a memory device according to the second embodiment will be described. The second embodiment differs from the first embodiment in that the Z2-direction end of the member SLT does not reach the wiring layer 21. The following description will mainly focus on the configuration and manufacturing method that differ from the first embodiment. The description of the configuration and manufacturing method equivalent to that of the first embodiment will be omitted as appropriate.

[0110] 2.1 Configuration Figure 20 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in the memory device according to the second embodiment. Figure 20 corresponds to Figure 5 in the first embodiment.

[0111] As shown in Figure 20, in the second embodiment, the memory cell array 10 further includes a stop film 37.

[0112] The Z2-direction end of the component SLT does not reach the wiring layer 21. Therefore, the regions of the conductive layers 21a and 21b and the semiconductor layer 21c that overlap with the component SLT in the Z direction have a flat shape. On the other hand, within the region that overlaps with the memory pillar MP in the Z direction, the Z2-direction-side surfaces of the conductive layers 21a and 21b and the semiconductor layer 21c are formed to have irregularities, similar to the first embodiment.

[0113] A stop film 37 is provided on the entire surface of the semiconductor layer 21d on the Z1 direction side. The stop film 37 has the function of preventing the progress of etching when forming grooves corresponding to the member SLT. The stop film 37 is an insulator comprising at least one material selected from, for example, aluminum oxide (Al2O3), silicon carbide (SiC), and carbon (C). The stop film 37 has a different film type from the insulating layer 32.

[0114] An insulating layer 32 is provided on the Z1-direction side of the stop film 37. The structure on the Z1-direction side of the insulating layer 32 is the same as that of the first embodiment.

[0115] The fill material LI intersects with the wiring layers 23 and 24, and the insulator layers 33 to 35. The fill material LI may or may not intersect with the wiring layer 22.

[0116] The insulating material SP covers the side surface and the end surface in the Z2 direction of the fill material LI. The end of the insulating material SP in the Z2 direction is located within the stop film 37.

[0117] 2.2 Manufacturing method Figures 21, 22, 23, and 24 show examples of the structure of a memory device during manufacturing according to the second embodiment. Figures 21, 22, 23, and 24 are planar layouts of the memory cell array 10 in the memory chip 100 during manufacturing, and correspond to Figure 20.

[0118] First, as shown in Figure 21, an insulating layer 71, a semiconductor layer 72, an insulating layer 73, a semiconductor layer 21d, and a stop film 37 are provided in this order on the Z1-direction surface of the substrate 70.

[0119] Then, a laminated structure corresponding to the laminated wiring structure is provided on the Z1 direction side of the stop film 37. Specifically, an insulating layer 32 and a sacrificial layer 74 are provided in this order on the Z1 direction side surface of the stop film 37. An insulating layer 33 and a sacrificial layer 75 are alternately laminated on the Z1 direction side surface of the sacrificial layer 74. An insulating layer 34 and a sacrificial layer 76 are provided in this order on the Z1 direction side surface of the uppermost sacrificial layer 75. An insulating layer 35 is provided on the Z1 direction side surface of the sacrificial layer 76.

[0120] Next, as shown in Figure 22, multiple holes (not shown) are provided in the region of the stacked structure where the memory pillar MP is to be installed. The bottom surfaces of the multiple holes reach, for example, the stop film 37. Subsequently, the bottom of each hole is further etched. As a result, the bottom surfaces of the multiple holes reach the semiconductor layer 72.

[0121] Subsequently, the laminated film 43, semiconductor film 42, and core film 41 are deposited in each hole in this order, and each hole is filled. This forms a structure corresponding to the memory pillar MP. In the structure corresponding to the memory pillar MP, the laminated film 43 covers the Z2-direction edge of the semiconductor film 42.

[0122] Next, as shown in Figure 23, a groove SH3 is formed in the region where the member SLT is to be installed. The bottom surface of the groove SH3 reaches, for example, the stop film 37. Then, the laminated structure replacement process is performed through the groove SH3. This forms the wiring layers 22, 23, and 24.

[0123] Next, as shown in Figure 24, insulating material SP and filler material LI are deposited in groove SH3 in that order, and groove SH3 is filled. This forms member SLT.

[0124] Subsequently, the structure on the Z1 direction side is formed from the component SHE and the stacked wiring structure, and the manufacturing of the memory chip 100 is completed. The subsequent steps are the same as in the first embodiment.

[0125] 2.3 Effects according to the second embodiment According to the second embodiment, the stop film 37 is provided between the insulating material SP and the semiconductor layer 21d, and extends in the XY plane so as to enclose the insulating material SP when viewed in the Z direction. The stop film 37 contains at least one material selected from aluminum oxide (Al2O3), silicon carbide (SiC), and carbon ((C)). This allows etching of the laminated structure to be stopped by the stop film 37 during the formation of the component SLT. Therefore, when the semiconductor film 42 of the memory pillar MP is exposed, the exposure of the fill material LI can be suppressed. Consequently, when the semiconductor layer 21c is heated by laser annealing, heat is absorbed by the fill material LI, which has a relatively high thermal conductivity, and this can suppress the semiconductor layer 21c near the component SLT from not crystallizing sufficiently. Furthermore, the crystallization of the semiconductor layer 21d near the component SLT can be promoted.

[0126] 2.4 Modified Examples of the Second Embodiment Various modifications can be applied to the second embodiment described above.

[0127] 2.4.1 First Modification of the Second Embodiment In the second embodiment described above, the case in which the stop film 37 is provided between the semiconductor layer 21d and the insulating layer 32 was explained, but the invention is not limited to this. The stop film 37 may also be provided between the insulating layer 32 and the wiring layer 22.

[0128] Figure 25 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in a memory device according to the first modified example of the second embodiment. Figure 25 corresponds to Figure 20 in the second embodiment.

[0129] As shown in Figure 25, an insulating layer 32 is provided on the Z1-direction side surface of the semiconductor layer 21d. A stop film 37 is provided over the entire Z1-direction side surface of the insulating layer 32. A wiring layer 22 is provided on the Z1-direction side surface of the stop film 37. The structure on the Z1-direction side of the wiring layer 22 is the same as in the second embodiment.

[0130] In the configuration described above, the Z2-direction end of the insulating material SP is located within the stop film 37. This allows an insulator, including the insulating layer 32, the insulating material SP, and the stop film 37, to be interposed between the fill material LI and the wiring layer 21. Therefore, similar to the second embodiment, the amount of heat generated during the laser annealing process that is transferred to the fill material LI can be reduced. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0131] 2.4.2 Second Modification of the Second Embodiment In the second embodiment and the first modification of the second embodiment described above, a case in which a stop film 37 and an insulating layer 32 are laminated between the semiconductor layer 21d and the wiring layer 22 was described, but the invention is not limited to this. It is sufficient that a stop film 37 is provided between the semiconductor layer 21d and the wiring layer 22, and the insulating layer 32 is not required.

[0132] Figure 26 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in a memory device according to a second modified example of the second embodiment. Figure 26 corresponds to Figure 20 in the second embodiment.

[0133] As shown in Figure 26, a stop film 37 is provided on the entire surface of the semiconductor layer 21d on the Z1 direction side. A wiring layer 22 is provided on the Z1 direction side surface of the stop film 37. The structure on the Z1 direction side of the wiring layer 22 is the same as in the second embodiment.

[0134] In the configuration described above, the Z2-direction end of the insulating material SP is located within the stop film 37. This allows an insulator, including the insulating material SP and the stop film 37, to be interposed between the fill material LI and the wiring layer 21. Therefore, similar to the second embodiment, the amount of heat generated during the laser annealing process that is transferred to the fill material LI can be reduced. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0135] 3. Third Embodiment Next, a memory device according to the third embodiment will be described. The third embodiment differs from the second embodiment in that the stop film is provided in the same layer as the insulating layer 32. The following description will mainly focus on the configuration and manufacturing method that differ from the second embodiment. The configuration and manufacturing method equivalent to that of the second embodiment will be omitted as appropriate.

[0136] 3.1 Configuration Figure 27 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in the memory device according to the third embodiment. Figure 27 corresponds to Figure 20 in the second embodiment.

[0137] As shown in Figure 27, in the third embodiment, the memory cell array 10 includes a stop film 38 instead of a stop film 37.

[0138] Similar to the second embodiment, the Z2-direction end of the member SLT does not reach the wiring layer 21. Therefore, the regions of the conductive layers 21a and 21b and the semiconductor layer 21c that overlap with the member SLT when viewed in the Z direction have a flat shape.

[0139] A stop film 38 is provided on the Z1-direction side surface of the semiconductor layer 21d, in a region that overlaps with the member SLT when viewed in the Z direction. The stop film 38 has the function of hindering the progress of etching when forming grooves corresponding to the member SLT. The stop film 38 is an insulator containing at least one material selected from, for example, aluminum oxide (Al2O3), silicon carbide (SiC), and carbon (C). The stop film 38 has a different film type from the insulator layer 32.

[0140] An insulating layer 32 is provided in the region of the semiconductor layer 21d on the Z1-direction side where the stop film 38 is not provided. The Z1-direction side of the insulating layer 32 and the Z1-direction side of the stop film 38 are aligned. That is, the film thicknesses of the insulating layer 32 and the stop film 38 are approximately equal.

[0141] A wiring layer 22 is provided on the Z1-direction side of each of the insulating layer 32 and the stop film 38. The structure on the Z1-direction side of the wiring layer 22 is the same as that of the second embodiment.

[0142] The fill material LI intersects with the wiring layers 23 and 24, and the insulator layers 33 to 35. The fill material LI may or may not intersect with the wiring layer 22.

[0143] The insulating material SP covers the side surface and the end surface in the Z2 direction of the fill material LI. The end of the insulating material SP in the Z2 direction is located within the stop film 38.

[0144] 3.2 Manufacturing method Figures 28, 29, 30, 31, and 32 show examples of the structure of a memory device in the manufacturing process according to the third embodiment. Figures 28, 29, 30, 31, and 32 are planar layouts of the memory cell array 10 in the memory chip 100 in the manufacturing process, and correspond to Figure 27.

[0145] First, as shown in Figure 28, an insulating layer 71, a semiconductor layer 72, an insulating layer 73, a semiconductor layer 21d, and an insulating layer 32 are provided in this order on the Z1-direction surface of the substrate 70.

[0146] Then, the region of the insulating layer 32 where the stop film 38 is to be placed is removed, for example, by anisotropic etching. This forms a groove SH4. The semiconductor layer 21d is exposed at the bottom of the groove SH4.

[0147] Next, as shown in Figure 29, the groove SH4 is filled with the stop film 38. The portion of the stop film 38 that is located outside the groove SH4 is etched back. This makes the film thickness of the insulating layer 32 and the stop film 38 the same.

[0148] Then, a laminated structure corresponding to the laminated wiring structure is provided on the Z1 direction side of the insulator layer 32 and the stop film 38. Specifically, a sacrificial layer 74 is provided on the Z1 direction side of the insulator layer 32 and the stop film 38. Insulator layers 33 and sacrificial layers 75 are alternately laminated on the Z1 direction side of the sacrificial layer 74. Insulator layers 34 and sacrificial layers 76 are provided in this order on the Z1 direction side of the uppermost sacrificial layer 75. An insulator layer 35 is provided on the Z1 direction side of the sacrificial layer 76.

[0149] Next, as shown in Figure 30, multiple holes (not shown) are provided in the region of the stacked structure where the memory pillar MP is to be installed. The bottom surfaces of the multiple holes reach the semiconductor layer 72. Subsequently, the stacked film 43, the semiconductor film 42, and the core film 41 are deposited in this order within each hole, and each hole is filled. This forms the structure corresponding to the memory pillar MP. In the structure corresponding to the memory pillar MP, the stacked film 43 covers the Z2-direction edge of the semiconductor film 42.

[0150] Next, as shown in Figure 31, a groove SH5 is formed in the region where the member SLT is to be installed. The bottom surface of the groove SH5 reaches, for example, the stop film 38. Then, the laminated structure replacement process is performed through the groove SH5. This forms the wiring layers 22, 23, and 24.

[0151] Next, as shown in Figure 32, insulating material SP and filler material LI are deposited in the groove SH5 in that order, and the groove SH5 is filled. This forms the member SLT.

[0152] Subsequently, the structure on the Z1 direction side is formed from the component SHE and the stacked wiring structure, and the manufacturing of the memory chip 100 is completed. The subsequent steps are the same as in the second embodiment.

[0153] 3.3 Effects of the Third Embodiment According to the third embodiment, the stop film 38 has a portion that is provided at the same position in the Z direction as the insulating layer 32. The stop film 38 comprises at least one material selected from aluminum oxide (Al2O3), silicon carbide (SiC), and carbon (C). The stop film 38 extends in the XY plane such that it encloses at least the portion of the insulating material SP on the Z2 direction side of the fill material LI (the bottom of the groove corresponding to the member SLT) when viewed in the Z direction. This allows etching of the laminated structure to be stopped by the stop film 38 during the formation of the member SLT. Therefore, when the semiconductor film 42 of the memory pillar MP is exposed, the exposure of the fill material LI can be suppressed. Consequently, when the semiconductor layer 21c is heated by laser annealing, heat is absorbed by the fill material LI, which has a relatively high thermal conductivity, and this can suppress the semiconductor layer 21c near the member SLT from not crystallizing sufficiently. Furthermore, the crystallization of the semiconductor layer 21d near the member SLT can be promoted.

[0154] 3.4 Modified Examples of the Third Embodiment Various modifications can be applied to the third embodiment described above.

[0155] 3.4.1 First Modification of the Third Embodiment In the third embodiment described above, the case in which the thickness of the stop film 38 is approximately equal to that of the insulating layer 32 was explained, but the invention is not limited to this. The thickness of the stop film 38 may be thinner than that of the insulating layer 32.

[0156] Figure 33 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in a memory device according to the first modified example of the third embodiment. Figure 33 corresponds to Figure 27 in the third embodiment.

[0157] As shown in Figure 33, an insulating layer 32 is provided on the Z1-direction side surface of the semiconductor layer 21d. The insulating layer 32 has a shape that is recessed in the Z2 direction in the region that includes the part that overlaps with the member SLT when viewed in the Z direction.

[0158] A stop film 38 is provided on the Z1-side surface of the insulator layer 32 in a region that overlaps with the member SLT when viewed in the Z direction (a region that is recessed in the Z2 direction). The Z1-side surface of the insulator layer 32 and the Z1-side surface of the stop film 38 are aligned. That is, the stop film 38 has a thinner film thickness than the insulator layer 32. Such a structure can be obtained by removing a portion of the insulator layer 32 by anisotropic etching when forming the groove SH4.

[0159] A wiring layer 22 is provided on the Z1-direction side of the insulating layer 32 and the stop film 38. The structure on the Z1-direction side of the wiring layer 22 is the same as that of the third embodiment.

[0160] In the configuration described above, the Z2-direction end of the insulating material SP is located within the stop film 38. This allows an insulator, including the insulating layer 32, the insulating material SP, and the stop film 38, to be interposed between the fill material LI and the wiring layer 21. Therefore, similar to the third embodiment, the amount of heat generated during the laser annealing process that is transferred to the fill material LI can be reduced. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0161] 3.4.2 Second Modified Example of the Third Embodiment Furthermore, the thickness of the stop film 38 may be thicker than that of the insulating layer 32.

[0162] Figure 34 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in a memory device according to a second modified example of the third embodiment. Figure 34 corresponds to Figure 27 in the third embodiment.

[0163] As shown in Figure 34, a stop film 38 is provided on the Z1-direction side surface of the semiconductor layer 21c, in a region that overlaps with the member SLT when viewed in the Z direction.

[0164] In the region of the semiconductor layer 21c on the Z1-direction side where the stop film 38 is not provided, the semiconductor layer 21d and the insulating layer 32 are stacked in this order. The Z1-direction side of the insulating layer 32 and the Z1-direction side of the stop film 38 are aligned. That is, the thickness of the stop film 38 is thicker than the thickness of the insulating layer 32 and is approximately equal to the combined thickness of the semiconductor layer 21d and the insulating layer 32. Such a structure can be obtained by removing the insulating layer 32 and the semiconductor layer 21d by anisotropic etching when forming the groove SH4.

[0165] A wiring layer 22 is provided on the Z1-direction side of the insulating layer 32 and the stop film 38. The structure on the Z1-direction side of the wiring layer 22 is the same as that of the third embodiment.

[0166] In the configuration described above, the Z2-direction end of the insulating material SP is located within the stop film 38. This allows an insulator, including the insulating material SP and the stop film 38, to be interposed between the fill material LI and the wiring layer 21. Therefore, similar to the third embodiment, the amount of heat generated during the laser annealing process that is transferred to the fill material LI can be reduced. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0167] 3.4.3 Third Modified Example of the Third Embodiment Furthermore, the stop film 38 may extend into the semiconductor layer 21c.

[0168] Figure 35 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in a memory device according to a third modified example of the third embodiment. Figure 35 corresponds to Figure 27 in the third embodiment.

[0169] As shown in Figure 35, each of the conductive layers 21a and 21b, and the semiconductor layer 21c, has a shape that is recessed in the Z2 direction in the region that includes the portion that overlaps with the memory pillar MP and the member SLT when viewed in the Z direction.

[0170] A stop film 38 is provided in the region on the Z1-direction side surface of the semiconductor layer 21c that is recessed in the Z2 direction corresponding to the member SLT. In the region on the Z1-direction side surface of the semiconductor layer 21c where the stop film 38 is not provided, the semiconductor layer 21d and the insulating layer 32 are stacked in this order. The Z1-direction side surface of the insulating layer 32 and the Z1-direction side surface of the stop film 38 are aligned. This structure can be obtained by removing the insulating layer 32, semiconductor layer 21d, and insulating layer 73 by anisotropic etching during the formation of the groove SH4, and further removing a portion of the semiconductor layer 72.

[0171] In the configuration described above, the Z2-direction end of the insulating material SP is located within the stop film 38. This allows an insulator, including the insulating material SP and the stop film 38, to be interposed between the fill material LI and the wiring layer 21. Therefore, similar to the third embodiment, the amount of heat generated during the laser annealing process that is transferred to the fill material LI can be reduced. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0172] 3.4.4 Fourth Modification of the Third Embodiment Furthermore, the stop film 38 may have a thinner film thickness than the insulating layer 32 and may be provided so as to cover the insulating layer 32.

[0173] Figure 36 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in a memory device according to a fourth modified example of the third embodiment. Figure 36 corresponds to Figure 27 in the third embodiment.

[0174] As shown in Figure 36, a stop film 38 is provided on the Z1-direction side surface of the semiconductor layer 21d, in a region that overlaps with the member SLT when viewed in the Z direction. Then, an insulating layer 32 is provided so as to cover the stop film 38 and the region on the Z1-direction side surface of the semiconductor layer 21d where the stop film 38 is not provided. Such a structure can be obtained by further forming the insulating layer 32 on the Z1-direction side surface of the structure after the stop film 38 has been embedded in the groove SH4.

[0175] A wiring layer 22 is provided on the Z1-direction side of the insulating layer 32. The structure on the Z1-direction side of the wiring layer 22 is the same as that of the third embodiment.

[0176] In the configuration described above, the Z2-direction end of the insulating material SP is located within the stop film 38. This allows an insulator, including the insulating material SP and the stop film 38, to be interposed between the fill material LI and the wiring layer 21. Therefore, similar to the third embodiment, the amount of heat generated during the laser annealing process that is transferred to the fill material LI can be reduced. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0177] 4. Fourth Embodiment Next, a memory device according to the fourth embodiment will be described. The fourth embodiment differs from the third embodiment in that a stop film is provided on the Z2 direction side of the insulating layer 32. The following description will mainly focus on the configuration and manufacturing method that differ from the third embodiment. The configuration and manufacturing method equivalent to that of the third embodiment will be omitted as appropriate.

[0178] 4.1 Configuration Figure 37 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in the memory device according to the fourth embodiment. Figure 37 corresponds to Figure 27 in the third embodiment.

[0179] As shown in Figure 37, in the fourth embodiment, the memory cell array 10 includes a stop film 39 instead of a stop film 38.

[0180] Similar to the third embodiment, the Z2-direction end of the member SLT does not reach the wiring layer 21. Therefore, the regions of the conductive layers 21a and 21b and the semiconductor layer 21c that overlap with the member SLT when viewed in the Z direction have a flat shape.

[0181] A stop film 39 is provided on the Z1-direction side surface of the semiconductor layer 21c, in a region that overlaps with the member SLT when viewed in the Z direction. The stop film 39 has the function of hindering the progress of etching when forming grooves corresponding to the member SLT. The stop film 39 is an insulator containing at least one material selected from, for example, aluminum oxide (Al2O3), silicon carbide (SiC), and carbon (C). The stop film 39 has a different film type from the insulator layer 32.

[0182] A semiconductor layer 21d is provided on the Z1-direction side surface of the semiconductor layer 21c in a region where the stop film 39 is not provided. The Z1-direction side surface of the semiconductor layer 21d and the Z1-direction side surface of the stop film 39 are aligned.

[0183] An insulating layer 32 is provided on the Z1-direction side of each of the semiconductor layer 21d and the stop film 39. The structure on the Z1-direction side of the insulating layer 32 is the same as that of the third embodiment.

[0184] The fill material LI intersects with the wiring layers 23 and 24, and the insulator layers 33 to 35. The fill material LI may or may not intersect with the wiring layer 22.

[0185] The insulating material SP covers the side surface and the end surface in the Z2 direction of the fill material LI. The end of the insulating material SP in the Z2 direction is located within the stop film 39.

[0186] 4.2 Manufacturing method Figures 38 and 39 show an example of the structure of a memory device in the manufacturing process according to the fourth embodiment. Figures 38 and 39 are planar layouts of the memory cell array 10 in the memory chip 100 in the manufacturing process, and correspond to Figure 37.

[0187] First, as shown in Figure 38, an insulating layer 71, a semiconductor layer 72, an insulating layer 73, and a semiconductor layer 21d are provided in this order on the Z1-direction surface of the substrate 70.

[0188] Then, the region of the semiconductor layer 21d where the stop film 39 is to be placed is removed, for example, by anisotropic etching. This forms a groove SH6. The insulating layer 73 is exposed at the bottom of the groove SH6.

[0189] Next, as shown in Figure 39, the groove SH6 is filled with the stop film 39. The portion of the stop film 39 that is located outside the groove SH6 is etched back. This makes the film thickness of the semiconductor layer 21d and the stop film 39 the same.

[0190] Then, a laminated structure corresponding to the laminated wiring structure is provided on the Z1 direction side of the semiconductor layer 21d and the stop film 39. Specifically, an insulating layer 32 and a sacrificial layer 74 are laminated in this order on the Z1 direction side surfaces of the semiconductor layer 21d and the stop film 39. An insulating layer 33 and a sacrificial layer 75 are alternately laminated on the Z1 direction side surface of the sacrificial layer 74. An insulating layer 34 and a sacrificial layer 76 are provided in this order on the Z1 direction side surface of the uppermost sacrificial layer 75. An insulating layer 35 is provided on the Z1 direction side surface of the sacrificial layer 76.

[0191] The subsequent steps are equivalent to those in the third embodiment.

[0192] 4.3 Effects of the Fourth Embodiment According to the fourth embodiment, the side of the stop film 39 facing the wiring layer 22 aligns with the side of the insulator layer 32 facing the semiconductor layer 21d. The stop film 39 comprises at least one material selected from aluminum oxide (Al2O3), silicon carbide (SiC), and carbon (C). The stop film 39 extends in the XY plane such that it encloses at least the portion of the insulator SP (the bottom of the groove corresponding to the member SLT) on the Z2 side of the fill material LI when viewed in the Z direction. This allows etching of the laminated structure to be stopped by the stop film 39 during the formation of the member SLT. Therefore, when the semiconductor film 42 of the memory pillar MP is exposed, exposure of the fill material LI can be suppressed. Consequently, when the semiconductor layer 21c is heated by laser annealing, heat is absorbed by the fill material LI, which has a relatively high thermal conductivity, and this can suppress the semiconductor layer 21c near the member SLT from not crystallizing sufficiently. Furthermore, crystallization of the semiconductor layer 21d near the member SLT can be promoted.

[0193] 4.4 Modified Version of the Fourth Embodiment Various modifications can be applied to the fourth embodiment described above.

[0194] For example, the stop film 39 may extend into the semiconductor layer 21c.

[0195] Figure 40 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in a memory device according to a modified example of the fourth embodiment. Figure 40 corresponds to Figure 37 in the fourth embodiment.

[0196] As shown in Figure 40, each of the conductive layers 21a and 21b, and the semiconductor layer 21c, has a shape that is recessed in the Z2 direction in the region that includes the portion that overlaps with the memory pillar MP and the member SLT when viewed in the Z direction.

[0197] A stop film 39 is provided on the Z1-direction surface of the semiconductor layer 21c in a region that is recessed in the Z2 direction corresponding to the member SLT. A semiconductor layer 21d is provided on the Z1-direction surface of the semiconductor layer 21c in a region where the stop film 39 is not provided. The Z1-direction surface of the semiconductor layer 21d and the Z1-direction surface of the stop film 39 are aligned. This structure can be obtained by removing the semiconductor layer 21d and the insulating layer 73 by anisotropic etching during the formation of the groove SH6, and further removing a portion of the semiconductor layer 72.

[0198] In the configuration described above, the Z2-direction end of the insulating material SP is located within the stop film 39. This allows an insulator, including the insulating material SP and the stop film 39, to be interposed between the fill material LI and the wiring layer 21. Therefore, similar to the fourth embodiment, the amount of heat generated during the laser annealing process that is transferred to the fill material LI can be reduced. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0199] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0200] 1…Memory system 2…Memory controller 3…Memory devices 10…Memory cell array 11... Command Register 12… Address Register 13… Sequencer 14…Driver module 15… Raw Decoder Module 16…Sense Amp Module 21,22,23,24…wiring layer 21a, 21b, 25, 26, 27, 62, 63, 64, 65...conductor layer 30...Protective layer 31, 32, 33, 34, 35, 36, 61, 71, 73… Insulating layer 37, 38, 39… Stop membrane 41… Core film 42… Semiconductor film 43…Multilayer film 44...Tunnel insulating film 45...Charge storage film 46…Block Insulating Film 51, 52, 53… Insulating film 60, 70… circuit board 74, 75, 76… Victims 77…Sacrificial membrane 100...memory chips 200... Circuit chips

Claims

1. Semiconductor layer, The semiconductor layer and the first wiring layer are arranged separately in the first direction without any other wiring layers in between, A plurality of second wiring layers are located on the opposite side of the semiconductor layer from the first wiring layer, and each is spaced apart in the first direction, A plurality of memory pillars, each extending in the first direction and in contact with the semiconductor layer, and the portion that intersects with each of the plurality of second wiring layers functions as a memory cell, A member that extends within a first plane including the first direction and a second direction intersecting the first direction, and divides the first wiring layer and the plurality of second wiring layers in a third direction intersecting each of the first and second directions, Equipped with, The aforementioned member is A fill material extending within the first plane from the semiconductor layer side of the first wiring layer toward the plurality of second wiring layers, An insulating material having a lower thermal conductivity than the fill material is provided between the fill material and each of the semiconductor layer, the first wiring layer, and the plurality of second wiring layers. including, Memory device.

2. The length of the portion of the insulating material that is on the semiconductor layer side of the fill material in the first direction is longer than the length of the portion of the insulating material that is between the fill material and each of the plurality of second wiring layers. The memory device according to claim 1.

3. Of the insulating material, the portion on the semiconductor layer side of the fill material is, A first insulating film is provided which is continuous with the portion of the insulating material between each of the plurality of second wiring layers, A second insulating film is provided between the first insulating film and the semiconductor layer, including, The memory device according to claim 1.

4. Semiconductor layer, The semiconductor layer and a first wiring layer that is arranged separately in the first direction without any other wiring layers in between, A plurality of second wiring layers are located on the opposite side of the semiconductor layer from the first wiring layer, and each is spaced apart in the first direction, A plurality of memory pillars, each extending in the first direction and in contact with the semiconductor layer, and the portion that intersects with each of the plurality of second wiring layers functions as a memory cell, A member extending within a first plane including the first direction and a second direction intersecting the first direction, dividing the first wiring layer and the plurality of second wiring layers in a third direction intersecting each of the first and second directions, wherein the member includes a fill material and an insulating material provided between the fill material and each of the semiconductor layer, the first wiring layer, and the plurality of second wiring layers, and having a lower thermal conductivity than the fill material. An insulating film is provided between the insulating material and the semiconductor layer, and encloses the portion of the insulating material that is on the semiconductor layer side of the fill material when viewed in the first direction, A memory device equipped with the following features.

5. The insulating film comprises at least one material selected from aluminum oxide (Al₂O₃), silicon carbide (SiC), and carbon ((C)). The memory device according to claim 4.

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