Voltage monitoring circuit and power supply circuit

Abstract

Reduce the circuit area of ​​the voltage monitoring circuit. [Solution] The voltage monitoring circuit (1) includes a first field-effect transistor (Q2) configured to have a first reference voltage (VREF1) applied to its gate, a second field-effect transistor (M1) configured to have a second reference voltage (VREF2) greater than the first reference voltage applied to its gate, a third field-effect transistor (Q1) configured to have a voltage to be monitored (VIN) applied to its gate and whose source is connected to the source of the first field-effect transistor and the source of the second field-effect transistor, a fourth field-effect transistor (M3) configured to switch on / off in accordance with the drain current of the second field-effect transistor, and a fifth field-effect transistor (Q5) configured to switch on / off in accordance with the drain current of the first field-effect transistor.

Description

[Technical Field]

[0001] The present disclosure relates to a voltage monitoring circuit and a power supply circuit. [Background Art]

[0002] A window comparator is a voltage monitoring circuit configured to monitor whether a voltage to be monitored falls within a predetermined range (a range greater than a first reference voltage and less than a second reference voltage).

[0003] A conventional window comparator is constituted by two comparators and one OR circuit (see, for example, Patent Document 1). [Prior Art Literature] [Patent Literature]

[0004] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2016-75252 (paragraphs 0067 and 0068)

[0005] [Summary] A conventional window comparator includes two comparators and one OR circuit, and thus has a problem of an increased circuit area.

[0006] The voltage monitoring circuit disclosed in the present specification comprises: a first field effect transistor configured such that a first reference voltage is applied to a gate thereof; a second field effect transistor configured such that a second reference voltage higher than the first reference voltage is applied to a gate thereof; a third field effect transistor configured such that the voltage to be monitored is applied to a gate thereof, and a source thereof is connected to a source of the first field effect transistor and a source of the second field effect transistor; a fourth field effect transistor configured to be switched on / off in accordance with a drain current of the second field effect transistor; and a fifth field effect transistor configured to be switched on / off in accordance with a drain current of the first field effect transistor.

[0007] The power supply circuit disclosed herein comprises a voltage monitoring circuit having the above configuration. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows the configuration of the power supply monitoring circuit according to the first embodiment. [Figure 2] Figure 2 shows the input voltage and output voltage waveforms in the power supply monitoring circuit according to the first embodiment. [Figure 3] Figure 3 shows the configuration of the power supply monitoring circuit according to the second embodiment. [Figure 4] Figure 4 shows the input voltage and output voltage waveforms in the power supply monitoring circuit according to the second embodiment. [Figure 5] Figure 5 shows the configuration of the power supply monitoring circuit according to the third embodiment. [Figure 6] Figure 6 shows the input voltage and output voltage waveforms in the power supply monitoring circuit according to the third embodiment. [Figure 7] Figure 7 shows the configuration of the power supply monitoring circuit according to the fourth embodiment. [Figure 8] Figure 8 shows the input voltage and output voltage waveforms in the power supply monitoring circuit according to the fourth embodiment. [Figure 9] Figure 9 shows the configuration of the power supply monitoring circuit according to the fifth embodiment. [Figure 10] Figure 10 shows the input voltage and output voltage waveforms in the power supply monitoring circuit according to the fifth embodiment. [Figure 11] Figure 11 shows the configuration of the power supply monitoring circuit according to the sixth embodiment. [Figure 12] Figure 12 shows the input voltage and output voltage waveforms in the power supply monitoring circuit according to the sixth embodiment. [Figure 13] Figure 13 shows the configuration of the power supply monitoring circuit according to the seventh embodiment. [Figure 14]Figure 14 shows the input voltage and output voltage waveforms in the power supply monitoring circuit according to the seventh embodiment. [Figure 15] Figure 15 shows the configuration of the power supply monitoring circuit according to the eighth embodiment. [Figure 16] Figure 16 shows the input voltage and output voltage waveforms in the power supply monitoring circuit according to the eighth embodiment. [Figure 17] Figure 17 shows a schematic configuration of the power supply unit.

[0009] [Detailed explanation] In this specification, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) refers to a field-effect transistor whose gate structure consists of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with low resistance, an insulating layer, and a P-type, N-type, or intrinsic semiconductor layer. In other words, the gate structure of a MOSFET is not limited to a three-layer structure of metal, oxide, and semiconductor. Hereinafter, a P-channel MOSFET will be referred to as a PMOS transistor, and an N-channel MOSFET will be referred to as an NMOS transistor.

[0010] <First Embodiment> Figure 1 shows the configuration of the power supply monitoring circuit 1 according to the first embodiment. The power supply monitoring circuit 1 comprises a comparator, a PMOS transistor M1, an NMOS transistor M2, and a PMOS transistor M3.

[0011] The comparator provided in the power supply monitoring circuit 1 comprises an input differential pair including PMOS transistors Q1 and Q2, a first current mirror circuit including PMOS transistors Q3 to Q5, a current source CS1, and a second current mirror circuit including NMOS transistors Q6 and Q7.

[0012] The power supply voltage is applied to the sources of PMOS transistors Q3 to Q5, and the back gates of PMOS transistors Q1 to Q5, M1, and M3. The gates of PMOS transistors Q3 to Q5 and the drain of PMOS transistor Q3 are connected to the first terminal of current source CS1.

[0013] The drain of PMOS transistor Q4 is connected to the sources of PMOS transistors Q1, Q2, and M1.

[0014] The input voltage VIN is applied to the gate of PMOS transistor Q1. The first reference voltage VREF1 is applied to the gate of PMOS transistor Q2. The second reference voltage VREF2 is applied to the gate of PMOS transistor M1.

[0015] The drain of PMOS transistor Q1 is connected to the drain of NMOS transistor Q6 and the gates of NMOS transistors Q6, Q7, and M2. The drain of PMOS transistor Q2 is connected to the drain of NMOS transistor Q7 and the gate of NMOS transistor Q8. The drain of PMOS transistor M1 is connected to the drain of NMOS transistor M2 and the gate of PMOS transistor M3.

[0016] The drain of PMOS transistor Q5 is connected to the source of PMOS transistor M3. The output voltage VOUT is output from connection node N1 between the drain of PMOS transistor Q5 and the source of PMOS transistor M3.

[0017] The drain of PMOS transistor M3 is connected to the drain of NMOS transistor Q8.

[0018] The ground voltage is applied to the second terminal of current source CS1, and the sources and back gates of NMOS transistors Q6 to Q8 and M2.

[0019] The power supply monitoring circuit 1 configured as described above operates as follows.

[0020] When the input voltage VIN is less than the first reference voltage VREF1, the drain currents of PMOS transistor Q2 and PMOS transistor M1 are both less than the drain current of PMOS transistor Q1. As a result, the gate voltage of NMOS transistor Q8 goes LOW, turning NMOS transistor Q8 off, and the gate voltage of PMOS transistor M3 goes LOW, turning PMOS transistor M3 on. Consequently, the output voltage VOUT becomes HIGH.

[0021] When the input voltage VIN is greater than the first reference voltage VREF1 and less than the second reference voltage VREF2, the drain currents of PMOS transistor Q1 and PMOS transistor Q2 are both greater than the drain current of PMOS transistor M1. As a result, the gate voltage of NMOS transistor Q8 becomes HIGH, turning NMOS transistor Q8 on, and the gate voltage of PMOS transistor M3 becomes LOW, turning PMOS transistor M3 on. Consequently, the output voltage VOUT becomes LOW.

[0022] When the input voltage VIN is greater than the second reference voltage VREF2, the drain current of PMOS transistor Q2 and the drain current of PMOS transistor M1 become greater than the drain current of PMOS transistor Q1. As a result, the gate voltage of NMOS transistor Q8 becomes HIGH, turning NMOS transistor Q8 ON, and the gate voltage of PMOS transistor M3 becomes HIGH, turning PMOS transistor M3 OFF. Consequently, the output voltage VOUT becomes HIGH.

[0023] In other words, the power supply monitoring circuit 1 is configured to monitor whether the input voltage VIN, which is the voltage to be monitored, is within a predetermined range (a range greater than the first reference voltage VREF1 and less than the second reference voltage VREF2). As shown in Figure 2, the power supply monitoring circuit 1 is configured to output a LOW level output voltage VOUT when the input voltage VIN is within the predetermined range, and to output a HIGH level output voltage VOUT when the input voltage VIN is outside the predetermined range.

[0024] Since the power supply monitoring circuit 1 does not require two comparators, the circuit size can be reduced. If you want to invert the logic of the output voltage VOUT, you can add an inverter to the power supply monitoring circuit 1, with its input terminal connected to connection node N1, and use the voltage output from the output terminal of that inverter as the output voltage VOUT.

[0025] <Second Embodiment> Figure 3 shows the configuration of the power supply monitoring circuit 2 according to the second embodiment. The power supply monitoring circuit 2 comprises a comparator, an NMOS transistor M11, a PMOS transistor M12, and an NMOS transistor M13.

[0026] The comparator provided in the power supply monitoring circuit 2 comprises an input differential pair including NMOS transistors Q11 and Q12, a first current mirror circuit including NMOS transistors Q13 to Q15, a current source CS11, and a second current mirror circuit including PMOS transistors Q16 and Q17.

[0027] The ground voltage is applied to the sources of NMOS transistors Q13 to Q15 and the back gates of NMOS transistors Q11 to Q15, M11, and Q18. The gates of NMOS transistors Q13 to Q15 and the drain of NMOS transistor Q13 are connected to the first terminal of current source CS11.

[0028] The drain of NMOS transistor Q14 is connected to the sources of NMOS transistors Q11, Q12, and M11.

[0029] The input voltage VIN is applied to the gate of NMOS transistor Q11. The first reference voltage VREF1 is applied to the gate of NMOS transistor Q12. The second reference voltage VREF2 is applied to the gate of NMOS transistor M11.

[0030] The drain of NMOS transistor Q11 is connected to the drain of PMOS transistor Q16 and to the gates of PMOS transistors Q16, Q17, and M12. The drain of NMOS transistor Q12 is connected to the drain of PMOS transistor Q17 and to the gate of NMOS transistor Q18. The drain of NMOS transistor M11 is connected to the drain of PMOS transistor M12 and to the gate of PMOS transistor M13.

[0031] The drain of NMOS transistor Q15 is connected to the source of NMOS transistor Q18. The output voltage VOUT is output from node N11, which connects the drain of NMOS transistor Q15 to the source of NMOS transistor Q18.

[0032] The drain of NMOS transistor Q18 is connected to the drain of PMOS transistor M13.

[0033] The power supply voltage is applied to the second terminal of the current source CS11 and to the sources and back gates of the PMOS transistors Q16, Q17, M12, and M13.

[0034] The power supply monitoring circuit 2, configured as described above, performs the following operations.

[0035] When the input voltage VIN is less than the first reference voltage VREF1, the drain current of NMOS transistor Q12 and the drain current of NMOS transistor M11 become greater than the drain current of NMOS transistor Q11. As a result, the gate voltage of NMOS transistor Q18 goes LOW, turning NMOS transistor Q18 off, and the gate voltage of PMOS transistor M13 goes LOW, turning PMOS transistor M13 on. Consequently, the output voltage VOUT becomes LOW.

[0036] When the input voltage VIN is greater than the first reference voltage VREF1 and less than the second reference voltage VREF2, the drain currents of NMOS transistor Q11 and NMOS transistor Q12 are both less than the drain current of NMOS transistor M11. As a result, the gate voltage of NMOS transistor Q18 becomes HIGH, turning NMOS transistor Q18 on, and the gate voltage of PMOS transistor M13 becomes LOW, turning PMOS transistor M13 on. Consequently, the output voltage VOUT becomes HIGH.

[0037] When the input voltage VIN is greater than the second reference voltage VREF2, the drain current of NMOS transistor Q12 and the drain current of NMOS transistor M11 become smaller than the drain current of NMOS transistor Q11. As a result, the gate voltage of NMOS transistor Q18 becomes HIGH, turning NMOS transistor Q18 ON, and the gate voltage of PMOS transistor M13 becomes HIGH, turning PMOS transistor M13 OFF. Consequently, the output voltage VOUT becomes LOW.

[0038] In other words, the power supply monitoring circuit 2 is configured to monitor whether the input voltage VIN, which is the voltage to be monitored, is within a predetermined range (a range greater than the first reference voltage VREF1 and less than the second reference voltage VREF2). As shown in Figure 4, the power supply monitoring circuit 2 is configured to output a HIGH level output voltage VOUT when the input voltage VIN is within the predetermined range, and to output a LOW level output voltage VOUT when the input voltage VIN is outside the predetermined range.

[0039] Since the power supply monitoring circuit 2 does not require two comparators, the circuit size can be reduced. If you want to invert the logic of the output voltage VOUT, you can add an inverter to the power supply monitoring circuit 2, with its input terminal connected to connection node N11, and use the voltage output from the output terminal of that inverter as the output voltage VOUT.

[0040] <Third Embodiment> Figure 5 shows the configuration of the power supply monitoring circuit 3 according to the third embodiment. The power supply monitoring circuit 3 is configured by removing the PMOS transistor M3 from the power supply monitoring circuit 1 and adding NMOS transistors M4, M5, and M6.

[0041] The source and back gate of NMOS transistor M4 are connected to the drain of NMOS transistor Q8. The drain of NMOS transistor M4 is connected to the drain of PMOS transistor Q5. The output voltage VOUT is output from node N1, which connects the drain of PMOS transistor Q5 to the drain of NMOS transistor M4.

[0042] The gate of NMOS transistor M4 is connected to the drain of PMOS transistor M5 and the drain of NMOS transistor M6.

[0043] The gate of PMOS transistor M5 is connected to the gates of PMOS transistors Q3 to Q5, the drain of PMOS transistor Q3, and the first terminal of current source CS1. The power supply voltage is applied to the source and back gate of PMOS transistor M5.

[0044] The gate of NMOS transistor M6 is connected to the drain of PMOS transistor M1 and the drain of NMOS transistor M2. Ground voltage is applied to the source and back gate of NMOS transistor M6.

[0045] The power supply monitoring circuit 3, like the power supply monitoring circuit 1, is configured to monitor whether the input voltage VIN, which is the voltage to be monitored, is within a predetermined range (a range greater than the first reference voltage VREF1 and less than the second reference voltage VREF2). As shown in Figure 6, the power supply monitoring circuit 3 is configured to output a LOW level output voltage VOUT when the input voltage VIN is within the predetermined range, and to output a HIGH level output voltage VOUT when the input voltage VIN is outside the predetermined range.

[0046] In Figure 6, the output voltage VOUT of power supply monitoring circuit 1 is shown by a dashed line, and the output voltage VOUT of power supply monitoring circuit 3 is shown by a solid line. The LOW level of the output voltage VOUT of power supply monitoring circuit 1 is higher than the ground voltage by the threshold voltage of the PMOS transistor M3, whereas in power supply monitoring circuit 3, the LOW level of the output voltage VOUT can be brought closer to the ground voltage GND.

[0047] Since the power supply monitoring circuit 3 does not require two comparators, the circuit size can be reduced. If you want to invert the logic of the output voltage VOUT, you can add an inverter to the power supply monitoring circuit 3 with its input terminal connected to connection node N1, and use the voltage output from the output terminal of that inverter as the output voltage VOUT.

[0048] <Fourth Embodiment> Figure 7 shows the configuration of the power supply monitoring circuit 4 according to the fourth embodiment. The power supply monitoring circuit 4 is configured by removing the NMOS transistor Q18 from the power supply monitoring circuit 2 and adding PMOS transistors M14, M15, and M16.

[0049] The source and back gate of PMOS transistor M14 are connected to the drain of PMOS transistor M13. The drain of PMOS transistor M14 is connected to the drain of NMOS transistor Q15. The output voltage VOUT is output from node N1, which connects the drain of NMOS transistor Q15 and the drain of PMOS transistor M14.

[0050] The gate of PMOS transistor M14 is connected to the drain of NMOS transistor M15 and the drain of PMOS transistor M16.

[0051] The gate of NMOS transistor M15 is connected to the gates of NMOS transistors Q13 to Q15, the drain of NMOS transistor Q13, and the first terminal of current source CS11. Ground voltage is applied to the source and back gate of NMOS transistor M15.

[0052] The gate of PMOS transistor M16 is connected to the drain of NMOS transistor Q12 and the drain of PMOS transistor Q17. The power supply voltage is applied to the source and back gate of PMOS transistor M16.

[0053] The power supply monitoring circuit 4, like the power supply monitoring circuit 2, is configured to monitor whether the input voltage VIN, which is the voltage to be monitored, is within a predetermined range (a range greater than the first reference voltage VREF1 and less than the second reference voltage VREF2). As shown in Figure 8, the power supply monitoring circuit 4 is configured to output a LOW level output voltage VOUT when the input voltage VIN is within the predetermined range, and to output a HIGH level output voltage VOUT when the input voltage VIN is outside the predetermined range.

[0054] In Figure 8, the output voltage VOUT of power supply monitoring circuit 2 is shown by a dashed line, and the output voltage VOUT of power supply monitoring circuit 4 is shown by a solid line. The HIGH level of the output voltage VOUT of power supply monitoring circuit 2 is lower than the power supply voltage by the threshold voltage of the NMOS transistor Q18, whereas in power supply monitoring circuit 4, the HIGH level of the output voltage VOUT can be brought closer to the power supply voltage.

[0055] Since the power supply monitoring circuit 4 does not require two comparators, the circuit size can be reduced. If you want to invert the logic of the output voltage VOUT, you can add an inverter to the power supply monitoring circuit 4, with its input terminal connected to connection node N11, and use the voltage output from the output terminal of that inverter as the output voltage VOUT.

[0056] <Fifth Embodiment> Figure 9 shows the configuration of the power supply monitoring circuit 5 according to the fifth embodiment. The power supply monitoring circuit 5 is configured by removing the PMOS transistor M3 from the power supply monitoring circuit 1 and adding an NMOS transistor M7.

[0057] The drain of NMOS transistor Q8 is connected to the drain of PMOS transistor Q5. The output voltage VOUT is output from node N1, which connects the drain of NMOS transistor Q8 to the drain of PMOS transistor Q5.

[0058] The drain of NMOS transistor M7 is connected to the gate of NMOS transistor Q8, the drain of PMOS transistor Q2, and the drain of NMOS transistor Q7.

[0059] The gate of NMOS transistor M7 is connected to the drain of PMOS transistor M1 and the drain of NMOS transistor M2.

[0060] Ground voltage is applied to the source and back gate of the NMOS transistor M7.

[0061] When the input voltage VIN is less than the first reference voltage VREF1, the drain current of PMOS transistor Q2 and the drain current of PMOS transistor M1 are both less than the drain current of PMOS transistor Q1. As a result, the gate voltage of NMOS transistor Q8 goes LOW, turning NMOS transistor Q8 off, and the gate voltage of NMOS transistor M7 goes LOW, turning NMOS transistor M7 on. Consequently, the output voltage VOUT becomes HIGH.

[0062] When the input voltage VIN is greater than the first reference voltage VREF1 and less than the second reference voltage VREF2, the drain currents of PMOS transistor Q1 and PMOS transistor Q2 are both greater than the drain current of PMOS transistor M1. As a result, the gate voltage of NMOS transistor Q8 becomes HIGH, turning NMOS transistor Q8 ON, and the gate voltage of NMOS transistor M7 becomes LOW, turning NMOS transistor M7 OFF. Consequently, the output voltage VOUT becomes LOW.

[0063] When the input voltage VIN is greater than the second reference voltage VREF2, the drain current of PMOS transistor M1 becomes greater than the drain current of PMOS transistor Q1. This causes the gate voltage of NMOS transistor M7 to become HIGH, turning NMOS transistor M7 on. When NMOS transistor M7 is on, the gate voltage of NMOS transistor Q8 becomes LOW, turning NMOS transistor Q8 off. As a result, the output voltage VOUT becomes HIGH.

[0064] As described above, the NMOS transistor Q8 is configured to switch on and off in response to the drain currents of the PMOS transistor M1 and the PMOS transistor Q2.

[0065] The power supply monitoring circuit 5, like the power supply monitoring circuit 1, is configured to monitor whether the input voltage VIN, which is the voltage to be monitored, is within a predetermined range (a range greater than the first reference voltage VREF1 and less than the second reference voltage VREF2). As shown in Figure 10, the power supply monitoring circuit 5 is configured to output a LOW level output voltage VOUT when the input voltage VIN is within the predetermined range, and to output a HIGH level output voltage VOUT when the input voltage VIN is outside the predetermined range.

[0066] In Figure 10, the output voltage VOUT of power supply monitoring circuit 1 is shown by a dashed line, and the output voltage VOUT of power supply monitoring circuit 5 is shown by a solid line. The LOW level of the output voltage VOUT of power supply monitoring circuit 1 is higher than the ground voltage by the threshold voltage of the PMOS transistor M3, whereas power supply monitoring circuit 5 has the disadvantages of a tendency for the offset to be large and the inability to make a large difference between the first reference voltage VREF1 and the second reference voltage VREF2, but it can bring the LOW level of the output voltage VOUT closer to the ground voltage GND.

[0067] Since the power supply monitoring circuit 5 does not require two comparators, the circuit size can be reduced. If it is desired to invert the logic of the output voltage VOUT, an inverter with its input terminal connected to connection node N1 can be added to the power supply monitoring circuit 5, and the voltage output from the output terminal of that inverter can be used as the output voltage VOUT.

[0068] <Sixth Embodiment> Figure 11 shows the configuration of the power supply monitoring circuit 6 according to the sixth embodiment. The power supply monitoring circuit 6 is configured by removing the NMOS transistor Q18 from the power supply monitoring circuit 2 and adding an NMOS transistor M17.

[0069] The drain of PMOS transistor M13 is connected to the drain of NMOS transistor Q15. The output voltage VOUT is output from node N11, which connects the drain of PMOS transistor M13 to the drain of NMOS transistor Q15.

[0070] The drain of PMOS transistor M17 is connected to the gate of PMOS transistor M13, the drain of PMOS transistor M12, and the drain of NMOS transistor M11.

[0071] The gate of PMOS transistor M17 is connected to the drain of PMOS transistor Q17 and the drain of NMOS transistor Q12.

[0072] The power supply voltage is applied to the source and back gate of the PMOS transistor M17.

[0073] When the input voltage VIN is less than the first reference voltage VREF1, the drain current of NMOS transistor Q12 becomes greater than the drain current of NMOS transistor Q11. This causes the gate voltage of PMOS transistor M17 to go LOW, turning PMOS transistor M17 ON. When PMOS transistor M17 is ON, the gate voltage of PMOS transistor M13 goes HIGH, turning PMOS transistor M13 OFF. As a result, the output voltage VOUT becomes LOW.

[0074] When the input voltage VIN is greater than the first reference voltage VREF1 and less than the second reference voltage VREF2, the drain currents of NMOS transistor Q11 and NMOS transistor Q12 are both less than the drain current of NMOS transistor M11. As a result, the gate voltage of PMOS transistor M17 becomes HIGH, turning it off, and the gate voltage of PMOS transistor M13 becomes LOW, turning it on. Consequently, the output voltage VOUT becomes HIGH.

[0075] When the input voltage VIN is greater than the second reference voltage VREF2, the drain current of NMOS transistor Q12 and the drain current of NMOS transistor M11 become smaller than the drain current of NMOS transistor Q11. As a result, the gate voltage of PMOS transistor M17 becomes HIGH, turning it off, and the gate voltage of PMOS transistor M13 becomes HIGH, turning it off. Consequently, the output voltage VOUT becomes LOW.

[0076] As described above, the PMOS transistor M13 is configured to switch on and off in response to the drain current of the NMOS transistor M11 and the drain current of the NMOS transistor Q12.

[0077] The power supply monitoring circuit 6, like the power supply monitoring circuit 2, is configured to monitor whether the input voltage VIN, which is the voltage to be monitored, is within a predetermined range (a range greater than the first reference voltage VREF1 and less than the second reference voltage VREF2). As shown in Figure 12, the power supply monitoring circuit 6 is configured to output a HIGH level output voltage VOUT when the input voltage VIN is within the predetermined range, and to output a LOW level output voltage VOUT when the input voltage VIN is outside the predetermined range.

[0078] In Figure 12, the output voltage VOUT of power supply monitoring circuit 2 is shown by a dashed line, and the output voltage VOUT of power supply monitoring circuit 6 is shown by a solid line. The HIGH level of the output voltage VOUT of power supply monitoring circuit 2 is lower than the power supply voltage by the threshold voltage of the NMOS transistor Q18, whereas power supply monitoring circuit 6 has the disadvantages of a tendency for the offset to be large and the inability to make a large difference between the first reference voltage VREF1 and the second reference voltage VREF2, but it can bring the HIGH level of the output voltage VOUT closer to the power supply voltage.

[0079] The power supply monitoring circuit 6 does not require two comparators, thus reducing the circuit size. Furthermore, if the logic of the output voltage VOUT needs to be inverted, an inverter with its input terminal connected to connection node N11 can be added to the power supply monitoring circuit 6, and the voltage output from the output terminal of that inverter can be used as the output voltage VOUT.

[0080] <Seventh Embodiment> Figure 13 shows the configuration of the power supply monitoring circuit 7 according to the seventh embodiment. The power supply monitoring circuit 7 is configured by adding an NMOS transistor M8, a PMOS transistor M9, and an inverter INV1 to the power supply monitoring circuit 5, and connecting the drain of the NMOS transistor M7 to the drain of the PMOS transistor M9 and the input terminal of the inverter INV1 instead of the gate of the NMOS transistor Q8, the drain of the PMOS transistor Q2, and the drain of the NMOS transistor Q7.

[0081] The drain of NMOS transistor M8 is connected to the gate of NMOS transistor Q8, the drain of PMOS transistor Q2, and the drain of NMOS transistor Q7. The gate of NMOS transistor M8 is connected to the output terminal of inverter INV1. Ground voltage is applied to the source and back gate of NMOS transistor M8.

[0082] The gate of PMOS transistor M9 is connected to the gates of PMOS transistors Q3 to Q5, the drain of PMOS transistor Q3, and the first terminal of current source CS1. The power supply voltage is applied to the source and back gate of PMOS transistor M9.

[0083] When the input voltage VIN is less than the first reference voltage VREF1, the drain current of PMOS transistor M1 becomes less than the drain current of PMOS transistor Q1. As a result, the gate voltage of NMOS transistor M7 becomes LOW, turning NMOS transistor M7 off. With NMOS transistor M7 off, its drain voltage becomes HIGH, and due to logic inversion by inverter INV1, the gate voltage of NMOS transistor M8 becomes LOW, turning NMOS transistor M8 off. Also, the drain current of PMOS transistor Q2 becomes less than the drain current of PMOS transistor Q1. As a result, the gate voltage of NMOS transistor Q8 becomes LOW, turning NMOS transistor Q8 off. Consequently, the output voltage VOUT becomes HIGH.

[0084] When the input voltage VIN is greater than the first reference voltage VREF1 and less than the second reference voltage VREF2, the drain currents of PMOS transistor Q1 and PMOS transistor Q2 are both greater than the drain current of PMOS transistor M1. As a result, the gate voltage of NMOS transistor M7 becomes LOW, turning NMOS transistor M7 off. With NMOS transistor M7 off, its drain voltage becomes HIGH, and due to logic inversion by inverter INV1, the gate voltage of NMOS transistor M8 becomes LOW, turning NMOS transistor M8 off. The gate voltage of NMOS transistor Q8 becomes HIGH, turning NMOS transistor Q8 on. As a result, the output voltage VOUT becomes LOW.

[0085] When the input voltage VIN is greater than the second reference voltage VREF2, the drain current of PMOS transistor M1 becomes greater than the drain current of PMOS transistor Q1. As a result, the gate voltage of NMOS transistor M7 becomes HIGH, turning NMOS transistor M7 ON. With NMOS transistor M7 ON, its drain voltage becomes LOW, and due to logic inversion by inverter INV1, the gate voltage of NMOS transistor M8 becomes HIGH, turning NMOS transistor M8 ON. With NMOS transistor M8 ON, the gate voltage of NMOS transistor Q8 becomes LOW, turning NMOS transistor Q8 OFF. As a result, the output voltage VOUT becomes HIGH.

[0086] As described above, the NMOS transistor Q8 is configured to switch on and off in response to the drain currents of the PMOS transistor M1 and the PMOS transistor Q2.

[0087] The power supply monitoring circuit 7, like the power supply monitoring circuit 1, is configured to monitor whether the input voltage VIN, which is the voltage to be monitored, is within a predetermined range (a range greater than the first reference voltage VREF1 and less than the second reference voltage VREF2). As shown in Figure 14, the power supply monitoring circuit 7 is configured to output a LOW level output voltage VOUT when the input voltage VIN is within the predetermined range, and to output a HIGH level output voltage VOUT when the input voltage VIN is outside the predetermined range.

[0088] In Figure 14, the output voltage VOUT of power supply monitoring circuit 1 is shown by a dashed line, and the output voltage VOUT of power supply monitoring circuit 7 is shown by a solid line. The LOW level of the output voltage VOUT of power supply monitoring circuit 1 is higher than the ground voltage by the threshold voltage of the PMOS transistor M3, whereas power supply monitoring circuit 7 has the disadvantages of a tendency for the offset to be large and the inability to make a large difference between the first reference voltage VREF1 and the second reference voltage VREF2, but it can bring the LOW level of the output voltage VOUT closer to the ground voltage GND.

[0089] The power supply monitoring circuit 7 does not require two comparators, thus reducing the circuit size. Furthermore, if the logic of the output voltage VOUT needs to be inverted, an inverter with its input terminal connected to connection node N1 can be added to the power supply monitoring circuit 7, and the voltage output from the output terminal of that inverter can be used as the output voltage VOUT.

[0090] <Eighth Embodiment> Figure 15 shows the configuration of the power supply monitoring circuit 8 according to the eighth embodiment. The power supply monitoring circuit 8 is configured by adding a PMOS transistor M18, an NMOS transistor M19, and an inverter INV11 to the power supply monitoring circuit 6, and connecting the drain of PMOS transistor M17 to the drain of NMOS transistor M19 and the input terminal of inverter INV11 instead of the gate of PMOS transistor M13, the drain of PMOS transistor M12, and the drain of NMOS transistor M11.

[0091] The drain of PMOS transistor M18 is connected to the gate of PMOS transistor M13, the drain of NMOS transistor M11, and the drain of PMOS transistor M12. The gate of PMOS transistor M18 is connected to the output terminal of inverter INV11. The power supply voltage is applied to the source and back gate of PMOS transistor M18.

[0092] The gate of NMOS transistor M19 is connected to the gates of NMOS transistors Q13 to Q15, the drain of NMOS transistor Q13, and the first terminal of current source CS11. Ground voltage is applied to the source and back gate of NMOS transistor M19.

[0093] When the input voltage VIN is less than the first reference voltage VREF1, the drain current of NMOS transistor Q12 becomes greater than the drain current of NMOS transistor Q11. As a result, the gate voltage of PMOS transistor M17 becomes LOW, turning PMOS transistor M17 ON. With PMOS transistor M17 ON, its drain voltage becomes HIGH, and logic inversion by inverter INV11 causes the gate voltage of PMOS transistor M18 to become LOW, turning PMOS transistor M18 ON. With PMOS transistor M18 ON, the gate voltage of PMOS transistor M13 becomes HIGH, turning PMOS transistor M13 OFF. As a result, the output voltage VOUT becomes LOW.

[0094] When the input voltage VIN is greater than the first reference voltage VREF1 and less than the second reference voltage VREF2, the drain currents of NMOS transistor Q11 and NMOS transistor Q12 are both less than the drain current of NMOS transistor M11. As a result, the gate voltage of PMOS transistor M17 becomes HIGH, turning PMOS transistor M17 off. With PMOS transistor M17 off, its drain voltage becomes LOW, and due to logic inversion by inverter INV11, the gate voltage of PMOS transistor M18 becomes HIGH, turning PMOS transistor M18 off. The gate voltage of PMOS transistor M13 becomes LOW, turning PMOS transistor M13 on. As a result, the output voltage VOUT becomes HIGH.

[0095] When the input voltage VIN is greater than the second reference voltage VREF2, the drain current of NMOS transistor Q12 becomes smaller than the drain current of NMOS transistor Q11. As a result, the gate voltage of PMOS transistor M17 becomes HIGH, turning PMOS transistor M17 off. With PMOS transistor M17 off, its drain voltage becomes LOW, and due to logic inversion by inverter INV11, the gate voltage of PMOS transistor M18 becomes HIGH, turning PMOS transistor M18 off. Also, the drain current of NMOS transistor M11 becomes smaller than the drain current of NMOS transistor Q11. As a result, the gate voltage of PMOS transistor M13 becomes HIGH, turning PMOS transistor M13 off. Consequently, the output voltage VOUT becomes LOW.

[0096] As described above, the PMOS transistor M13 is configured to switch on and off in response to the drain current of the NMOS transistor M11 and the drain current of the NMOS transistor Q12.

[0097] The power supply monitoring circuit 8, like the power supply monitoring circuit 2, is configured to monitor whether the input voltage VIN, which is the voltage to be monitored, is within a predetermined range (a range greater than the first reference voltage VREF1 and less than the second reference voltage VREF2). As shown in Figure 16, the power supply monitoring circuit 8 is configured to output a HIGH level output voltage VOUT when the input voltage VIN is within the predetermined range, and to output a LOW level output voltage VOUT when the input voltage VIN is outside the predetermined range.

[0098] In Figure 16, the output voltage VOUT of power supply monitoring circuit 2 is shown by a dashed line, and the output voltage VOUT of power supply monitoring circuit 8 is shown by a solid line. The HIGH level of the output voltage VOUT of power supply monitoring circuit 2 is lower than the power supply voltage by the threshold voltage of the NMOS transistor Q18, whereas power supply monitoring circuit 8 has the disadvantages of a tendency for the offset to be large and the difference between the first reference voltage VREF1 and the second reference voltage VREF2 not being large, but it can bring the HIGH level of the output voltage VOUT closer to the power supply voltage.

[0099] Since the power supply monitoring circuit 8 does not require two comparators, the circuit size can be reduced. If it is desired to invert the logic of the output voltage VOUT, an inverter with its input terminal connected to connection node N11 can be added to the power supply monitoring circuit 8, and the voltage output from the output terminal of that inverter can be used as the output voltage VOUT.

[0100] <Examples of application> The power supply monitoring circuits 1 to 8 described above are mounted, for example, in the power supply circuit 10 shown in Figure 17. The power supply circuit 10 includes a DC / DC converter 11 and an output voltage monitoring circuit 12. The DC / DC converter 11 converts the input voltage Vi into an output voltage Vo. The DC / DC converter 11 may be a switching regulator or a linear regulator. The output voltage monitoring circuit 12 is configured to monitor whether the output voltage Vo, which is the voltage to be monitored, is within a predetermined range (a range greater than the first reference voltage VREF1 and less than the second reference voltage VREF2). Any of the power supply monitoring circuits 1 to 8 described above is used as the output voltage monitoring circuit 12. The usage of the output voltage VOUT output from the output voltage monitoring circuit 12 is not particularly limited, but for example, the DC / DC converter 11 may be configured to stop operating in accordance with the output voltage VOUT when the output voltage Vo is outside the predetermined range. In the power supply circuit 10, any of the power supply monitoring circuits 1 to 8 described above will monitor the output voltage Vo, but any of the power supply monitoring circuits 1 to 8 described above may monitor a voltage other than the output voltage Vo.

[0101] <Other> The embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of this disclosure is indicated by the claims rather than by the description of the embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0102] <Note> A note is added to this disclosure, which provides specific configuration examples in the embodiments described above.

[0103] The voltage monitoring circuits (1-8) of this disclosure have a configuration (first configuration) comprising: first field-effect transistors (Q2, Q12) configured to have a first reference voltage (VREF1) applied to their gates; second field-effect transistors (M1, M11) configured to have a second reference voltage (VREF2) greater than the first reference voltage applied to their gates; third field-effect transistors (Q1, Q11) configured to have a voltage to be monitored (VIN) applied to their gates and whose sources are connected to the sources of the first field-effect transistors and the second field-effect transistors; fourth field-effect transistors (M3, M13, M6, M7, M13) configured to switch on / off in accordance with the drain current of the second field-effect transistors; and fifth field-effect transistors (Q8, Q18, M16, M17) configured to switch on / off in accordance with the drain current of the first field-effect transistors.

[0104] The voltage monitoring circuit in the first configuration described above does not require two comparators, thus reducing the circuit size.

[0105] In the voltage monitoring circuit of the first configuration described above, the fourth field-effect transistor and the fifth field-effect transistor may be configured to be connected in series (second configuration).

[0106] In the voltage monitoring circuit of the second configuration described above, the fourth field-effect transistor (M3, M13) may be a P-channel type field-effect transistor, and the fifth field-effect transistor (Q8, Q18) may be an N-channel type field-effect transistor (third configuration).

[0107] In the voltage monitoring circuit of the first configuration described above, the circuit may further include a sixth field-effect transistor (M4) whose gate is connected to the drain of the fourth field-effect transistor (M6) and which is connected in series with the fifth field-effect transistor (Q8), wherein the first to third field-effect transistors are P-channel type field-effect transistors and the fourth to sixth field-effect transistors are N-channel type field-effect transistors (fourth configuration).

[0108] In the voltage monitoring circuit of the first configuration described above, the circuit may further include a sixth field-effect transistor (M14) whose gate is connected to the drain of the fifth field-effect transistor (M16) and which is connected in series with the fourth field-effect transistor (M13), wherein the first to third field-effect transistors are N-channel type field-effect transistors and the fourth to sixth field-effect transistors are P-channel type field-effect transistors (fifth configuration).

[0109] In the voltage monitoring circuit of the first configuration described above, the first to third field-effect transistors are P-channel type field-effect transistors, the fourth to fifth field-effect transistors are N-channel type field-effect transistors, the gate of the fifth field-effect transistor (Q8) is connected to the drain of the fourth field-effect transistor (M7), and the fifth field-effect transistor may be configured to switch on / off in accordance with the drain current of the first field-effect transistor and the drain current of the second field-effect transistor (sixth configuration).

[0110] In the voltage monitoring circuit of the first configuration described above, the first to third field-effect transistors are N-channel type field-effect transistors, the fourth to fifth field-effect transistors are P-channel type field-effect transistors, the gate of the fourth field-effect transistor (M13) is connected to the drain of the fifth field-effect transistor (M17), and the fourth field-effect transistor may be configured to switch on / off in accordance with the drain current of the first field-effect transistor and the drain current of the second field-effect transistor (seventh configuration).

[0111] The voltage monitoring circuit of the first configuration described above may further include a sixth field-effect transistor (M8) configured such that the inverting logic of the drain voltage of the fourth field-effect transistor (M7) is applied to its gate, and its drain is connected to the gate of the fifth field-effect transistor (Q8), wherein the first to third field-effect transistors are P-channel type field-effect transistors, the fourth to sixth field-effect transistors are N-channel type field-effect transistors, and the fifth field-effect transistor is configured to switch on / off in accordance with the drain current of the first field-effect transistor and the drain current of the second field-effect transistor (eighth configuration).

[0112] The voltage monitoring circuit of the first configuration described above may further include a sixth field-effect transistor (M18) configured such that the inverting logic of the drain voltage of the fifth field-effect transistor (M17) is applied to its gate, and its drain is connected to the gate of the fourth field-effect transistor (M13), wherein the first to third field-effect transistors are N-channel type field-effect transistors, the fourth to sixth field-effect transistors are P-channel type field-effect transistors, and the fourth field-effect transistor is configured to switch on / off in accordance with the drain current of the first field-effect transistor and the drain current of the second field-effect transistor (the ninth configuration).

[0113] The power supply circuit (10) of the present disclosure has a configuration that includes a voltage monitoring circuit in any of the first to ninth configurations described above (the tenth configuration). [Explanation of Symbols]

[0114] 1-8 Voltage monitoring circuit 10 Power circuit 11 DC / DC Converters 12 Output Voltage Monitoring Circuit CS1, CS11 current source INV1, INV11 Inverter M1, M3, M5, M9, M12-M14, M16-M18, Q1-Q5, Q16, Q17 PMOS transistors M2, M4, M6, M7, M8, M11, M15, M19, Q6~Q8, Q11~Q15, Q18 NMOS transistors N1, N11 connected nodes

Claims

1. A first field-effect transistor configured such that a first reference voltage is applied to its gate, A second field-effect transistor configured such that a second reference voltage greater than the first reference voltage is applied to its gate, A third field-effect transistor is configured such that a monitored voltage is applied to its gate and its source is connected to the source of the first field-effect transistor and the source of the second field-effect transistor, A fourth field-effect transistor configured to switch on / off in accordance with the drain current of the second field-effect transistor, A fifth field-effect transistor configured to switch on / off in accordance with the drain current of the first field-effect transistor, A voltage monitoring circuit equipped with the following features.

2. The voltage monitoring circuit according to claim 1, wherein the fourth field-effect transistor and the fifth field-effect transistor are configured to be connected in series.

3. The voltage monitoring circuit according to claim 2, wherein the fourth field-effect transistor is a P-channel type field-effect transistor and the fifth field-effect transistor is an N-channel type field-effect transistor.

4. The system further comprises a sixth field-effect transistor, the gate of which is connected to the drain of the fourth field-effect transistor and the sixth field-effect transistor, configured to be connected in series with the fifth field-effect transistor. The first to third field-effect transistors are P-channel type field-effect transistors. The voltage monitoring circuit according to claim 1, wherein the fourth to sixth field-effect transistors are N-channel type field-effect transistors.

5. The system further comprises a sixth field-effect transistor, the gate of which is connected to the drain of the fifth field-effect transistor and the sixth field-effect transistor, configured to be connected in series with the fourth field-effect transistor. The first to third field-effect transistors are N-channel type field-effect transistors. The voltage monitoring circuit according to claim 1, wherein the fourth to sixth field-effect transistors are P-channel type field-effect transistors.

6. The first to third field-effect transistors are P-channel type field-effect transistors. The fourth and fifth field-effect transistors are N-channel type field-effect transistors. The gate of the fifth field-effect transistor is configured to be connected to the drain of the fourth field-effect transistor. The voltage monitoring circuit according to claim 1, wherein the fifth field-effect transistor is configured to switch on and off in accordance with the drain current of the first field-effect transistor and the drain current of the second field-effect transistor.

7. The first to third field-effect transistors are N-channel type field-effect transistors. The fourth and fifth field-effect transistors are P-channel type field-effect transistors. The gate of the fourth field-effect transistor is configured to be connected to the drain of the fifth field-effect transistor. The voltage monitoring circuit according to claim 1, wherein the fourth field-effect transistor is configured to switch on and off in accordance with the drain current of the first field-effect transistor and the drain current of the second field-effect transistor.

8. The system further comprises a sixth field-effect transistor, configured such that the inverting logic of the drain voltage of the fourth field-effect transistor is applied to its gate, and its drain is connected to the gate of the fifth field-effect transistor. The first to third field-effect transistors are P-channel type field-effect transistors. The fourth to sixth field-effect transistors are N-channel type field-effect transistors. The voltage monitoring circuit according to claim 1, wherein the fifth field-effect transistor is configured to switch on and off in accordance with the drain current of the first field-effect transistor and the drain current of the second field-effect transistor.

9. The system further comprises a sixth field-effect transistor, configured such that the inverting logic of the drain voltage of the fifth field-effect transistor is applied to its gate, and its drain is connected to the gate of the fourth field-effect transistor. The first to third field-effect transistors are N-channel type field-effect transistors. The fourth to sixth field-effect transistors are P-channel type field-effect transistors. The voltage monitoring circuit according to claim 1, wherein the fourth field-effect transistor is configured to switch on and off in accordance with the drain current of the first field-effect transistor and the drain current of the second field-effect transistor.

10. A power supply circuit comprising a voltage monitoring circuit according to any one of claims 1 to 9.

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