Semiconductor equipment

Abstract

To provide a semiconductor device that can suppress snapback behavior in IGBT mode. [Solution] The semiconductor portion has an eighth semiconductor layer of the second conductivity type located within a second semiconductor layer of the first conductivity type on a third semiconductor layer of the second conductivity type located between the first electrode and the second semiconductor layer in the transistor region, and also located at the boundary between the transistor region and the diode region. A part of the second semiconductor layer is located between the eighth semiconductor layer and the first semiconductor layer. The interface between the first semiconductor layer and the second semiconductor layer does not have a step on the eighth semiconductor layer.

Description

[Technical Field]

[0001] Embodiments relate to a semiconductor device. [Background Art]

[0002] Insulated Gate Bipolar Transistors (IGBTs) are widely used as semiconductor devices for power control. Many applications that use IGBTs have a mode in which a freewheeling current flows from the emitter side to the collector side, and a Free-Wheel Diode (FWD) is connected in parallel to the IGBT to allow this freewheeling current to flow. Reverse Conducting IGBT (RC-IGBT) is a semiconductor device in which the FWD and the IGBT are integrated into a single chip. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2015 / 0249084 [Patent Document 2] US Patent No. 9620499 [Patent Document 3] US Patent No. 8080853 [Patent Document 4] Japanese Patent Laid-Open No. 2023-172272 [Patent Document 5] Japanese Patent Laid-Open No. 2015-154000 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] An embodiment provides a semiconductor device capable of suppressing snapback operation in an IGBT mode. [Means for Solving the Problem]

[0005] According to the embodiment, the semiconductor device comprises a first electrode, a second electrode, a semiconductor portion located between the first electrode and the second electrode in a first direction, having a transistor region and a diode region adjacent to the transistor region in a direction intersecting the first direction, and a third electrode located at least within the semiconductor portion of the transistor region, wherein the semiconductor portion comprises a first semiconductor layer of a first conductivity type located in the transistor region and the diode region, a second semiconductor layer of a first conductivity type located between the first electrode and the first semiconductor layer in the transistor region and the diode region, having a higher concentration of first conductivity type impurities than the first semiconductor layer, a third semiconductor layer of a second conductivity type located between the first electrode and the second semiconductor layer in the transistor region and electrically connected to the first electrode, and a fourth semiconductor layer of a second conductivity type located between the first semiconductor layer and the second electrode in the transistor region. The transistor region includes a fifth semiconductor layer of a first conductivity type located between the fourth semiconductor layer and the second electrode and electrically connected to the second electrode; a sixth semiconductor layer of a first conductivity type located between the first electrode and the second semiconductor layer in the diode region, having a higher concentration of first conductivity type impurities than the first semiconductor layer, adjacent to the third semiconductor layer in the direction intersecting the first direction, and electrically connected to the first electrode; a seventh semiconductor layer of a second conductivity type located between the first semiconductor layer and the second electrode in the diode region and electrically connected to the second electrode; and an eighth semiconductor layer of a second conductivity type located on the third semiconductor layer within the second semiconductor layer and at the boundary between the transistor region and the diode region, wherein a part of the second semiconductor layer is located between the eighth semiconductor layer and the first semiconductor layer, and the interface between the first semiconductor layer and the second semiconductor layer does not have a step on the eighth semiconductor layer.

[0006] According to the embodiment, the semiconductor device comprises a first electrode, a second electrode, a semiconductor portion located between the first electrode and the second electrode in a first direction, having a transistor region and a diode region adjacent to the transistor region in a direction intersecting the first direction, and a third electrode located at least within the semiconductor portion of the transistor region, wherein the semiconductor portion comprises a first semiconductor layer of a first conductivity type located in the transistor region and the diode region, a second semiconductor layer of a first conductivity type located between the first electrode and the first semiconductor layer in the transistor region and the diode region, having a higher concentration of first conductivity type impurities than the first semiconductor layer, a third semiconductor layer of a second conductivity type located between the first electrode and the second semiconductor layer in the transistor region and electrically connected to the first electrode, a fourth semiconductor layer of a second conductivity type located between the first semiconductor layer and the second electrode in the transistor region, and the fourth semiconductor layer in the transistor region The diode region includes: a fifth semiconductor layer of a first conductivity type located between the first electrode and the second electrode and electrically connected to the second electrode; a sixth semiconductor layer of a first conductivity type located between the first electrode and the second semiconductor layer in the diode region, with a higher concentration of first conductivity type impurities than the first semiconductor layer, adjacent to the third semiconductor layer in the direction intersecting the first direction, and electrically connected to the first electrode; a seventh semiconductor layer of a second conductivity type located between the first semiconductor layer and the second electrode in the diode region and electrically connected to the second electrode; and an eighth semiconductor layer of a second conductivity type located on the third semiconductor layer within the second semiconductor layer, and located between the boundary between the transistor region and the diode region and the boundary between the third semiconductor layer and the sixth semiconductor layer in the direction intersecting the first direction, wherein a part of the second semiconductor layer is located between the eighth semiconductor layer and the first semiconductor layer, and the interface between the first semiconductor layer and the second semiconductor layer does not have a step on the eighth semiconductor layer. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic cross-sectional view of a semiconductor device according to the first embodiment. [Figure 2] This is a schematic plan view of the semiconductor portion in a semiconductor device according to the first embodiment. [Figure 3] This is a schematic cross-sectional view of a semiconductor device according to the second embodiment. [Figure 4] This is a schematic cross-sectional view of a semiconductor device according to the third embodiment. [Figure 5] This is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment. [Figure 6] This is a schematic cross-sectional view of a semiconductor device according to the fifth embodiment. [Figure 7] (a) and (b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 8] (a) and (b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Modes for carrying out the invention]

[0008] The embodiments will be described below with reference to the drawings. In each drawing, the same components are denoted by the same reference numerals. In each drawing, the direction along the Z axis is referred to as the first direction Z, the direction along the X axis as the second direction X, and the direction along the Y axis as the third direction Y. The second direction X and the third direction Y intersect the first direction Z. In this embodiment, for example, the first direction Z, the second direction X, and the third direction Y are orthogonal to each other. In this specification, for example, the direction of the Z-axis arrow may be described as relatively upward, and the direction opposite to the Z-axis arrow may be described as relatively downward.

[0009] In this specification, the thickness of each element represents the maximum thickness in the first direction Z. Also, in this specification, the distance between each element in a particular direction represents the shortest distance in that particular direction.

[0010] As shown in Figure 1, the semiconductor device 1 comprises a first electrode 21, a second electrode 22, a third electrode 23, a semiconductor portion 10, and an insulating film 40.

[0011] The semiconductor portion 10 is located between the first electrode 21 and the second electrode 22 in the first direction Z. The semiconductor portion 10 has a first surface 10A and a second surface 10B located on the opposite side of the first surface 10A in the first direction Z. The first electrode 21 is provided on the first surface 10A. The second electrode 22 is provided on the second surface 10B.

[0012] For example, silicon can be used as the material of the semiconductor portion 10. Alternatively, for example, silicon carbide, gallium nitride or the like may be used as the material of the semiconductor portion 10. In the present embodiment, the first conductivity type is described as n-type and the second conductivity type as p-type in the semiconductor portion 10, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0013] FIG. 2 is a schematic plan view of the semiconductor portion 10 as viewed from the second surface 10B. The cross-section of the semiconductor portion 10 shown in FIG. 1 corresponds to the A-A cross-section in FIG. 2.

[0014] The semiconductor portion 10 has an element region 100 and a termination region 200. The termination region 200 is located between the element region 100 and the outer edge of the semiconductor portion 10 in the second direction X and the third direction Y. In a plan view, the termination region 200 surrounds the element region 100.

[0015] As shown in FIG. 1, the semiconductor portion 10 has a transistor region 110 and a diode region 120. In the present embodiment, the diode region 120 is adjacent to the transistor region 110 in the second direction X. The transistor region 110 and the diode region 120 are included in the element region 100. In the element region 100, the transistor regions 110 and the diode regions 120 are alternately arranged, for example, in the second direction X.

[0016] The semiconductor portion 10 includes an n-type first semiconductor layer 11, an n-type second semiconductor layer 12, a p-type third semiconductor layer 13, a p-type fourth semiconductor layer 14, an n-type fifth semiconductor layer 15, an n-type sixth semiconductor layer 16, a p-type seventh semiconductor layer 17, and a p-type eighth semiconductor layer 18.

[0017] The transistor region 110 includes an IGBT. In the IGBT of the transistor region 110, the first electrode 21 functions as a collector electrode, the second electrode 22 functions as an emitter electrode, the first semiconductor layer 11 functions as an n-type base layer (or a drift layer), the second semiconductor layer 12 functions as an n-type buffer layer, the third semiconductor layer 13 functions as a p-type collector layer, the fourth semiconductor layer 14 functions as a p-type base layer, and the fifth semiconductor layer 15 functions as an n-type emitter layer, respectively.

[0018] The first semiconductor layer 11 (n-type base layer) is continuously located across the transistor region 110 and the diode region 120.

[0019] The second semiconductor layer 12 (n-type buffer layer) is located between the first electrode 21 and the first semiconductor layer 11 in both the transistor region 110 and the diode region 120. The second semiconductor layer 12 is continuously located across the transistor region 110 and the diode region 120. The n-type impurity concentration of the second semiconductor layer 12 is higher than the n-type impurity concentration of the first semiconductor layer 11.

[0020] The third semiconductor layer 13 (p-type collector layer) is located between the first electrode 21 and the second semiconductor layer 12 in the transistor region 110. The third semiconductor layer 13 is in contact with the first electrode 21 and is electrically connected to the first electrode 21.

[0021] The fourth semiconductor layer 14 (p-type base layer) is located between the first semiconductor layer 11 and the second electrode 22 in the transistor region 110. A part of the fourth semiconductor layer 14 is in contact with the second electrode 22. In the first direction Z, the fourth semiconductor layer 14 is in contact with the first semiconductor layer 11 and forms a pn junction with the first semiconductor layer 11.

[0022] The fifth semiconductor layer 15 (n-type emitter layer) is located between the fourth semiconductor layer 14 and the second electrode 22 in the transistor region 110. The n-type impurity concentration of the fifth semiconductor layer 15 is higher than that of the first semiconductor layer 11. The fifth semiconductor layer 15 is electrically connected to the second electrode 22. The second electrode 22 is, for example, in contact with the upper surface of the fifth semiconductor layer 15. The second electrode 22 may also have a trench contact structure in contact with the side surface of the fifth semiconductor layer 15.

[0023] The diode region 120 has a diode connected in parallel to the IGBT of the transistor region 110. In the diode of the diode region 120, the first electrode 21 functions as the cathode electrode, the second electrode 22 as the anode electrode, the sixth semiconductor layer 16 as the n-type cathode layer, and the seventh semiconductor layer 17 as the p-type anode layer.

[0024] The sixth semiconductor layer 16 (n-type cathode layer) is located between the first electrode 21 and the second semiconductor layer 12 in the diode region 120. The n-type impurity concentration of the sixth semiconductor layer 16 is higher than that of the first semiconductor layer 11. The sixth semiconductor layer 16 is in contact with the first electrode 21 and is electrically connected to the first electrode 21. The sixth semiconductor layer 16 (n-type cathode layer) is adjacent to the third semiconductor layer 13 (p-type collector layer) in the second direction X, for example.

[0025] The seventh semiconductor layer 17 (p-type anode layer) is located between the first semiconductor layer 11 and the second electrode 22 in the diode region 120 and is electrically connected to the second electrode 22. In the first direction Z, the seventh semiconductor layer 17 is in contact with the first semiconductor layer 11 and forms a pn junction with the first semiconductor layer 11.

[0026] The fifth semiconductor layer 15 (n-type emitter layer) is not provided in the diode region 120.

[0027] The third electrode 23 extends downward from the second surface 10B side of the semiconductor portion 10 in the transistor region 110 and is located within the semiconductor portion 10. In the transistor region 110, the lower end of the third electrode 23 is located below the pn junction between the fourth semiconductor layer 14 (p-type base layer) and the first semiconductor layer 11 (n-type base layer). For example, conductive polycrystalline silicon can be used as the material for the third electrode 23.

[0028] The insulating film 40 is provided between the third electrode 23 and the semiconductor portion 10. In the transistor region 110, the side surface of the third electrode 23 faces the fourth semiconductor layer 14 (p-type base layer) via the insulating film 40. The insulating film 40 is also provided between the third electrode 23 and the second electrode 22.

[0029] In this embodiment, the third electrode 23 is also located in the diode region 120. The third electrode 23 extends downward from the second surface 10B side of the semiconductor portion 10 in the diode region 120 and is located within the semiconductor portion 10. In the diode region 120, the lower end of the third electrode 23 is located below the pn junction between the seventh semiconductor layer 17 (p-type anode layer) and the first semiconductor layer 11 (n-type base layer). Note that the third electrode 23 does not necessarily have to be located in the diode region 120.

[0030] In this embodiment, a plurality of third electrodes 23 are arranged in the transistor region 110 and the diode region 120, spaced apart from each other in the second direction X. Each third electrode 23 extends in the third direction Y.

[0031] The plurality of third electrodes 23 arranged in the transistor region 110 include a third electrode 23A located closest to the diode region 120. The insulating film 40A covering the side of this third electrode 23A that is on the diode region 120 side in the second direction X is adjacent to the seventh semiconductor layer 17 (p-type anode layer). In this embodiment, the boundary between the insulating film 40A and the seventh semiconductor layer 17 (p-type anode layer) is defined as the boundary B1 between the transistor region 110 and the diode region 120. In the cross-sectional view of Figure 1 including boundary B1, a dashed line is shown as a virtual line passing through boundary B1 and extending in the first direction Z.

[0032] The boundary B2 between the third semiconductor layer 13 (p-type collector layer) and the sixth semiconductor layer 16 (n-type cathode layer) may or may not coincide with the boundary B1 between the transistor region 110 and the diode region 120. The boundary B2 between the third semiconductor layer 13 (p-type collector layer) and the sixth semiconductor layer 16 (n-type cathode layer) may be located closer to the transistor region 110 or closer to the diode region 120 than the boundary B1 between the transistor region 110 and the diode region 120. In the example shown in Figure 1, the boundary B2 between the third semiconductor layer 13 and the sixth semiconductor layer 16 is located closer to the diode region 120.

[0033] The third electrode 23, located in the transistor region 110, functions as the gate electrode (trench gate) in the IGBT and is connected to gate wiring (not shown). For example, the end of the third electrode 23 (gate electrode) extending in the third direction Y from the transistor region 110 to the termination region 200 is connected to the gate wiring in the termination region 200. The third electrode 23 (gate electrode) may also be connected to the gate wiring in the element region 100.

[0034] The third electrode 23 located in the diode region 120 is not connected to the gate wiring, but is connected to, for example, the second electrode 22. For example, the end of the third electrode 23 extending in the third direction Y from the diode region 120 to the termination region 200 is connected to the second electrode 22 in the termination region 200. The third electrode 23 may also be connected to the second electrode 22 in the element region 100. The third electrode 23 located in the diode region 120 does not function as a gate electrode in the transistor. By forming a dummy trench electrode in the diode region 120, variations in the shape and dimensions of the trench and the third electrode 23 (gate electrode) formed in the transistor region 110 can be reduced, and variations in withstand voltage between the transistor region 110 and the diode region 120 can also be reduced.

[0035] In IGBT operation in transistor region 110, a positive potential is applied to the first electrode 21 (collector electrode), and a ground potential is applied to the second electrode 22 (emitter electrode). When a potential exceeding a predetermined threshold (a potential higher than the potential of the second electrode 22 (emitter potential)) is applied to the third electrode 23 (gate electrode) of transistor region 110, an inversion layer (n-type channel) is formed in the region of the fourth semiconductor layer 14 (p-type base layer) facing the third electrode 23, and electrons are injected from the second electrode 22 into the first semiconductor layer 11 (n-type base layer) via the fifth semiconductor layer 15 (n-type emitter layer) and the n-type channel. As a result, the third semiconductor layer 13 (p-type collector layer) is positively biased with respect to the first semiconductor layer 11, holes are injected from the third semiconductor layer 13 into the first semiconductor layer 11, and the IGBT in transistor region 110 turns on.

[0036] When a potential lower than the threshold is applied to the third electrode 23 (gate electrode) of the transistor region 110, the n-type channel disappears and the IGBT is turned off. In the off state of the IGBT, a depletion layer extends from the pn junction between the fourth semiconductor layer 14 and the first semiconductor layer 11, and from the boundary between the insulating film 40 and the first semiconductor layer 11, within the first semiconductor layer 11, maintaining the breakdown voltage. The second semiconductor layer 12 (n-type buffer layer), which has a higher n-type impurity concentration than the first semiconductor layer 11 (n-type base layer), suppresses punch-through where the depletion layer reaches the third semiconductor layer 13 (p-type collector layer).

[0037] In the diode operation in the diode region 120, when a forward voltage is applied between the second electrode 22 and the first electrode 21 such that the potential of the second electrode 22 (anode potential) is higher than the potential of the first electrode 21 (cathode potential), holes are injected from the seventh semiconductor layer 17 (p-type anode layer) into the first semiconductor layer 11, and electrons are injected from the sixth semiconductor layer 16 (n-type cathode layer) into the first semiconductor layer 11, causing a forward current to flow through the diode in the diode region 120.

[0038] In the IGBT mode of semiconductor device 1, the IGBT is on and the diode is off. In the diode mode of semiconductor device 1, the IGBT is off and the diode is on. The IGBT mode and diode mode alternate repeatedly.

[0039] In IGBT mode, a portion of the electron current supplied from the fifth semiconductor layer 15 (n-type emitter layer) can flow across the second semiconductor layer 12 (n-type buffer layer) to the sixth semiconductor layer 16 (n-type cathode layer) of the diode region 120, due to the potential barrier between the second semiconductor layer 12 (n-type buffer layer) and the third semiconductor layer 13 (p-type collector layer). This is called MOS operation. MOS operation causes a snapback in the IV characteristics (represented by a graph where the horizontal axis is voltage and the vertical axis is current), which switches to the negative resistance region, making it difficult to control the IGBT operation as desired.

[0040] According to this embodiment, snapback can be suppressed by a p-type eighth semiconductor layer 18 located within the second semiconductor layer 12 (n-type buffer layer) on the third semiconductor layer 13 (p-type collector layer), and located at the boundary B1 between the transistor region 110 and the diode region 120. The fact that the eighth semiconductor layer 18 is located at the boundary B1 between the transistor region 110 and the diode region 120 means that the eighth semiconductor layer 18 is in contact with the imaginary line (dashed line) passing through the boundary B1 in the cross-sectional view described above. In this embodiment, the side surface of the eighth semiconductor layer 18 on the transistor region 110 side is in contact with the imaginary line passing through the boundary B1.

[0041] The eighth semiconductor layer 18 is located on the third semiconductor layer 13 (p-type collector layer) in the first direction Z, but not on the sixth semiconductor layer 16 (n-type cathode layer). In this embodiment, the eighth semiconductor layer 18 is in contact with the third semiconductor layer 13. The eighth semiconductor layer 18 does not penetrate the second semiconductor layer 12 in the first direction Z. In the first direction Z, a part 12A of the second semiconductor layer 12 is located between the eighth semiconductor layer 18 and the first semiconductor layer 11.

[0042] In the second semiconductor layer 12, the thickness in the first direction Z of a portion 12A adjacent to the boundary B1 between the transistor region 110 and the diode region 120 is narrowed. The thickness in the first direction Z of a portion 12A located on the eighth semiconductor layer 18 in the second semiconductor layer 12 is smaller than the thickness in the first direction Z of the portion of the transistor region 110 located on the third semiconductor layer 13 in the second semiconductor layer 12, and the thickness in the first direction Z of the portion of the diode region 120 located on the sixth semiconductor layer 16 in the second semiconductor layer 12. As a result, the electron current crossing the second semiconductor layer 12 (n-type buffer layer) in IGBT mode is less likely to flow towards the sixth semiconductor layer 16 side of the diode region 120, thereby suppressing snapback. The eighth semiconductor layer 18 acts as a resistance when the electron current crossing the second semiconductor layer 12 flows towards the diode region 120 side. When the ratio of the thickness of the eighth semiconductor layer 18 to the thickness of the second semiconductor layer 12 becomes 1 / 2, the above resistance becomes approximately twice as large.

[0043] For example, in a semiconductor device 1 with a voltage withstand design of 1200V, the n-type impurity concentration of the second semiconductor layer 12 (n-type buffer layer) is set to 1 × 10⁻¹⁶ 16 cm -3 This can be done. In this case, in order to suppress punch-through, it is preferable that the thickness of a portion 12A of the second semiconductor layer 12 on the eighth semiconductor layer 18 be 0.2 μm or more.

[0044] If the eighth semiconductor layer 18 is located on the transistor region 110 side of the boundary B1 between the transistor region 110 and the diode region 120, the eighth semiconductor layer 18 is less likely to resist the electron current flowing downward from directly above the eighth semiconductor layer 18 in the transistor region 110. For this reason, it is preferable that the eighth semiconductor layer 18 is located on the diode region 120 side of the boundary B1 between the transistor region 110 and the diode region 120 in the second direction X.

[0045] The interface between the first semiconductor layer 11 and the second semiconductor layer 12 does not have a step on the eighth semiconductor layer 18. The interface between the first semiconductor layer 11 and the second semiconductor layer 12 is not curved in a convex shape on the eighth semiconductor layer 18. A part 12A of the second semiconductor layer 12 located on the eighth semiconductor layer 18 is not convex toward the first semiconductor layer 11. Below the eighth semiconductor layer 18, the first electrode 21 is not convex toward the semiconductor portion 10. Below the eighth semiconductor layer 18, the interface between the first electrode 21 and the semiconductor portion 10 is parallel to the second direction X and the third direction Y, and is flat. In the semiconductor portion 10, the thickness in the first direction Z of the portion where the eighth semiconductor layer 18 is located (the distance in the first direction Z between the first electrode 21 and the second electrode 22) is the same as the thickness in the first direction Z of the portion where the eighth semiconductor layer 18 is not located (the distance in the first direction Z between the first electrode 21 and the second electrode 22). In other words, the thickness of the first semiconductor layer 11 in the first direction Z is not partially thinner above the eighth semiconductor layer 18. The distance in the first direction Z between the eighth semiconductor layer 18 and the seventh semiconductor layer 17 is smaller than the distance in the first direction Z between the sixth semiconductor layer 16 and the seventh semiconductor layer 17, and the distance in the first direction Z between the third semiconductor layer 13 and the fourth semiconductor layer 14. According to the semiconductor device 1 of this embodiment, the decrease in breakdown voltage near the boundary B1 between the transistor region 110 and the diode region 120 can be reduced.

[0046] The following describes other embodiments, focusing mainly on their configurations that differ from the first embodiment described above.

[0047] [Second Embodiment] Figure 3 is a schematic cross-sectional view of the semiconductor device 2 according to the second embodiment.

[0048] The eighth semiconductor layer 18 does not have to be located in contact with the line passing through the boundary B1 between the transistor region 110 and the diode region 120. In the semiconductor device 2 according to the second embodiment, the eighth semiconductor layer 18 is located within the second semiconductor layer 12 on the third semiconductor layer 13, and in the second direction X, it is located between the boundary B1 between the transistor region 110 and the diode region 120 and the boundary B2 between the third semiconductor layer 13 and the sixth semiconductor layer 16. In this case as well, the eighth semiconductor layer 18 acts as a resistance when the electron current crossing the second semiconductor layer 12 flows towards the diode region 120, thereby suppressing snapback.

[0049] [Third Embodiment] Figure 4 is a schematic cross-sectional view of the semiconductor device 3 according to the third embodiment.

[0050] In the semiconductor device 3 according to the third embodiment, the boundary B2 between the third semiconductor layer 13 and the sixth semiconductor layer 16 is located on the diode region 120 side of the eighth semiconductor layer 18 in the second direction X. Even in this case, the eighth semiconductor layer 18 acts as a resistance when the electron current crossing the second semiconductor layer 12 flows towards the diode region 120 side, thereby suppressing snapback.

[0051] [Fourth Embodiment] Figure 5 is a schematic cross-sectional view of the semiconductor device 4 according to the fourth embodiment.

[0052] In the semiconductor device 4 according to the fourth embodiment, the eighth semiconductor layer 18 is located away from the third semiconductor layer 13 in the first direction Z. Even in this case, the eighth semiconductor layer 18 acts as a resistance when the electron current crossing the second semiconductor layer 12 flows towards the diode region 120, thereby suppressing snapback.

[0053] Furthermore, in the first direction Z, a portion 12A of the second semiconductor layer 12 is located between the eighth semiconductor layer 18 and the first semiconductor layer 11, thus suppressing punch-through.

[0054] [Fifth Embodiment] As shown in Figure 6, in the semiconductor device 5 according to the fifth embodiment, a portion 13A of the third semiconductor layer 13 may protrude convexly toward the second semiconductor layer 12 in the transistor region 110, away from the boundary B1 between the transistor region 110 and the diode region 120. In other words, the convex portion 13A in the third semiconductor layer 13 may be periodically provided, not limited to the boundary B1.

[0055] Figures 7(a) to 8(b) show an example of a method for manufacturing a semiconductor device according to the embodiment.

[0056] As shown in Figure 7(a), impurities such as phosphorus (P) are implanted into the first semiconductor layer 11 from the first surface 10A side by ion implantation, thereby forming a second semiconductor layer 12 over the entire surface on the first surface 10A side.

[0057] After forming the second semiconductor layer 12, impurities such as phosphorus (P) are implanted into the second semiconductor layer 12 from the first surface 10A side by ion implantation, thereby forming a sixth semiconductor layer 16 over the entire surface on the first surface 10A side, as shown in Figure 7(b).

[0058] After forming the sixth semiconductor layer 16, as shown in Figure 8(a), a portion of the sixth semiconductor layer 16 on the first surface 10A side is covered with resist 301. Then, impurities such as boron (B) are implanted from the first surface 10A exposed at the opening 301A of the resist 301 by ion implantation to form the third semiconductor layer 13 adjacent to the sixth semiconductor layer 16.

[0059] After forming the third semiconductor layer 13, the sixth semiconductor layer 16 and the third semiconductor layer 13 are covered with resist 302 on the first surface 10A side. A portion of the third semiconductor layer 13 is exposed at an opening 302A in the resist 302. Then, through the opening 302A, an impurity such as boron (B) is implanted from the first surface 10A into a portion of the second semiconductor layer 12 by ion implantation to form the eighth semiconductor layer 18.

[0060] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0061] 1-5... Semiconductor device, 10... Semiconductor part, 10A... First surface, 10B... Second surface, 11... First semiconductor layer, 12... Second semiconductor layer, 13... Third semiconductor layer, 14... Fourth semiconductor layer, 15... Fifth semiconductor layer, 16... Sixth semiconductor layer, 17... Seventh semiconductor layer, 18... Eighth semiconductor layer, 21... First electrode, 22... Second electrode, 23... Third electrode, 40... Insulating film, 100... Element region, 110... Transistor region, 120... Diode region, 200... Termination region

Claims

1. First electrode and The second electrode and A semiconductor portion located between the first electrode and the second electrode in a first direction, the semiconductor portion having a transistor region and a diode region adjacent to the transistor region in a direction intersecting the first direction, A third electrode located at least within the semiconductor portion of the transistor region, Equipped with, The aforementioned semiconductor section is A first semiconductor layer of a first conductivity type located in the transistor region and the diode region, A second semiconductor layer of a first conductivity type is located between the first electrode and the first semiconductor layer in the transistor region and the diode region, and has a higher concentration of first conductivity type impurities than the first semiconductor layer. A third semiconductor layer of second conductivity type is located between the first electrode and the second semiconductor layer in the transistor region and is electrically connected to the first electrode, A fourth semiconductor layer of second conductivity type located between the first semiconductor layer and the second electrode in the transistor region, A fifth semiconductor layer of first conductivity type is located between the fourth semiconductor layer and the second electrode in the transistor region and is electrically connected to the second electrode, A sixth semiconductor layer of a first conductivity type is located between the first electrode and the second semiconductor layer in the diode region, has a higher concentration of first conductivity type impurities than the first semiconductor layer, is adjacent to the third semiconductor layer in the direction intersecting the first direction, and is electrically connected to the first electrode. A seventh semiconductor layer of second conductivity type is located between the first semiconductor layer and the second electrode in the diode region and is electrically connected to the second electrode, An eighth semiconductor layer of second conductivity type is located on the third semiconductor layer, within the second semiconductor layer, and at the boundary between the transistor region and the diode region, It has, A portion of the second semiconductor layer is located between the eighth semiconductor layer and the first semiconductor layer. A semiconductor device wherein the interface between the first semiconductor layer and the second semiconductor layer does not have a step on the eighth semiconductor layer.

2. The semiconductor device according to claim 1, wherein the eighth semiconductor layer is located on the diode side of the boundary between the transistor region and the diode region in the direction intersecting the first direction.

3. First electrode and The second electrode and A semiconductor portion located between the first electrode and the second electrode in a first direction, the semiconductor portion having a transistor region and a diode region adjacent to the transistor region in a direction intersecting the first direction, A third electrode located at least within the semiconductor portion of the transistor region, Equipped with, The aforementioned semiconductor section is A first semiconductor layer of a first conductivity type located in the transistor region and the diode region, A second semiconductor layer of a first conductivity type is located between the first electrode and the first semiconductor layer in the transistor region and the diode region, and has a higher concentration of first conductivity type impurities than the first semiconductor layer. A third semiconductor layer of second conductivity type is located between the first electrode and the second semiconductor layer in the transistor region and is electrically connected to the first electrode, A fourth semiconductor layer of second conductivity type located between the first semiconductor layer and the second electrode in the transistor region, A fifth semiconductor layer of first conductivity type is located between the fourth semiconductor layer and the second electrode in the transistor region and is electrically connected to the second electrode, A sixth semiconductor layer of a first conductivity type is located between the first electrode and the second semiconductor layer in the diode region, has a higher concentration of first conductivity type impurities than the first semiconductor layer, is adjacent to the third semiconductor layer in the direction intersecting the first direction, and is electrically connected to the first electrode. A seventh semiconductor layer of second conductivity type is located between the first semiconductor layer and the second electrode in the diode region and is electrically connected to the second electrode, An eighth semiconductor layer of second conductivity type is located on the third semiconductor layer and within the second semiconductor layer, and is located between the boundary between the transistor region and the diode region and the boundary between the third semiconductor layer and the sixth semiconductor layer in the direction intersecting the first direction, It has, A portion of the second semiconductor layer is located between the eighth semiconductor layer and the first semiconductor layer. A semiconductor device wherein the interface between the first semiconductor layer and the second semiconductor layer does not have a step on the eighth semiconductor layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein the eighth semiconductor layer is in contact with the third semiconductor layer.

5. The semiconductor device according to any one of claims 1 to 3, wherein the eighth semiconductor layer is located away from the third semiconductor layer in the first direction.

6. The semiconductor device according to any one of claims 1 to 3, wherein the portion of the second semiconductor layer located on the eighth semiconductor layer does not protrude toward the first semiconductor layer.

7. The semiconductor device according to any one of claims 1 to 3, wherein the distance in the first direction between the eighth semiconductor layer and the seventh semiconductor layer is smaller than the distance in the first direction between the sixth semiconductor layer and the seventh semiconductor layer, and the distance in the first direction between the third semiconductor layer and the fourth semiconductor layer.

8. The semiconductor device according to any one of claims 1 to 3, wherein the thickness in the first direction of the portion of the semiconductor part in which the eighth semiconductor layer is located is the same as the thickness in the first direction of the portion of the semiconductor part in which the eighth semiconductor layer is not located.

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