Sampling clock generation circuit

Abstract

To obtain a sampling clock generation circuit capable of generating a sampling clock with good SFDR performance. [Solution] The sampling clock generation circuit 10 includes an amplifier 7 that amplifies the signal level of the input reference clock, a directional coupler 6 that splits the reference clock input from the amplifier 7 to a clock IC 3 and an attenuator 5 for output, an attenuator 5 that reduces the signal level of the reference clock branched from the directional coupler 6 for input, and a bandbus filter 4 that reduces noise and spurious components contained in the signal output from the attenuator 5 and outputs the reduced signal as a sampling clock to the AD converter 1.

Description

[[Technical Field]]

[0001] The present disclosure relates to a sampling clock generation circuit that generates a sampling clock for use in a data converter adopting JESD204. [[Background Art]]

[0002] JESD204 is an interface standard established by JEDEC (Solid State Technology Association), which is an interface standard for connecting data converters such as AD (Analog-to-Digital) converters and DA (Digital-to-Analog) converters to digital circuits such as FPGA (Field-Programmable Gate Array).

[0003] The following Patent Document 1 discloses an apparatus and a method for clock synchronization and frequency conversion that provide improvements such as reduction of system clock errors caused by environmental factors by using a digital compensation signal. Patent Document 1 also mentions JESD204, and describes that "the frequency conversion IC provides support for data conversion clocking such as AD conversion and DA conversion for the support for JESD204B". [[Prior Art Literature]] [[Patent Literature]]

[0004] [[Patent Document 1]] Japanese Unexamined Patent Publication No. 2019-9781 [[Summary of Invention]] [[Problem to be Solved by Invention]]

[0005] However, the method described in Patent Document 1 does not mention the analog aspect of sampling technology using a low-noise clock, and therefore does not address this point. In the JESD standard, a control signal described as "SYSREF" or "SYNC~" (the inverted signal of SYNC) is used. In this paper, these "SYSREF" and "SYNC~" signals are collectively referred to as the "SYSREF signal." The SYSREF signal is a trigger signal used as a timing trigger or control trigger for sampling in a data converter.

[0006] Since the SYSREF signal and the sampling clock to the data converter (also called the "device clock") need to be synchronized, a typical design employs a configuration in which a reference clock, which is the reference signal for a single oscillator, is issued to the data converter and the digital circuit respectively by a clock IC and a distributor.

[0007] On the other hand, in the above configuration, spurious signals generated by the clock IC are added to the sampling clock supplied to the data converter, resulting in unwanted image signals in the output spectrum of the data converter. These unwanted image signals lead to a decrease in the SFDR (Spurious Free Dynamic Range) performance of the entire system using the data converter. Therefore, the technology described in Patent Document 1, which does not consider the analog aspect of sampling technology using a low-noise clock, makes it difficult to generate a sampling clock with good SFDR performance.

[0008] This disclosure has been made in view of the above, and aims to provide a sampling clock generation circuit capable of generating a sampling clock with good SFDR performance. [Means for solving the problem]

[0009] To solve the above-mentioned problems and achieve the objective, this disclosure provides a sampling clock generation circuit used in a control system that controls a data converter and has a reference clock generation circuit that generates a reference clock, and which generates a sampling clock to be output to the data converter. The sampling clock generation circuit comprises a first circuit section that amplifies the signal level of an input reference clock, a second circuit section that branches the reference clock input from the first circuit section to the reference clock generation circuit and another circuit section located downstream and outputs them, a third circuit section that attenuates the signal level of the reference clock branched from the second circuit section and input, and a fourth circuit section that reduces noise and spurious components contained in the signal output from the third circuit section and outputs the reduced signal as a sampling clock to the data converter. [Effects of the Invention]

[0010] The sampling clock generation circuit described herein has the effect of generating a sampling clock with good SFDR performance. [Brief explanation of the drawing]

[0011] [Figure 1] Block diagram showing an example configuration of a control system including a sampling clock generation circuit according to the embodiment. [Modes for carrying out the invention]

[0012] The sampling clock generation circuit according to the embodiment of this disclosure will be described in detail below with reference to the attached drawings.

[0013] Embodiment. Figure 1 shows an example configuration of a control system 50 including a sampling clock generation circuit 10 according to an embodiment. As shown in Figure 1, the control system 50 according to the embodiment comprises an AD converter (ADC) 1 to be controlled, a digital circuit 2 for controlling the AD converter 1, a clock IC 3, and a sampling clock generation circuit 10. The clock IC 3 operates as a reference clock generation circuit that generates the SYSREF signal, which is the reference clock of the control system 50. The sampling clock generation circuit 10 is a circuit that generates a sampling clock to be output to the AD converter 1.

[0014] The sampling clock generation circuit 10 according to this embodiment comprises an amplifier (AMP) 7 as a first circuit section, a directional coupler 6 as a second circuit section, an attenuator (ATT) 5 as a third circuit section, and a bandbus filter (BPF) 4 as a fourth circuit section. The AD converter 1 is an example of a data converter, and the sampling clock generation circuit 10 according to this embodiment can also be applied to other examples of data converters, such as a DA converter.

[0015] Amplifier 7 amplifies the signal level of the reference clock (ref. clock) input from outside the control system 50. The amplified reference clock signal is input to directional coupler 6. Directional coupler 6 splits the input reference clock into two outputs: one to clock IC 3 and the other to attenuator 5 located downstream.

[0016] The reference clock input to clock IC3 is attenuated by directional coupler 6, but its signal level is adjusted by amplifier 7 to a signal level suitable for input to clock IC3. That is, amplifier 7 cancels out the decrease in signal strength when the input reference clock passes through directional coupler 6, and adjusts the signal level of the reference clock output to clock IC3 by directional coupler 6 so that the signal level of the reference clock output to clock IC3 is suitable for input to clock IC3. When directional coupler 6 splits the reference clock into two directions, to clock IC3 and to attenuator 5, it is configured to reduce noise and spurious components contained in the reflected signal from clock IC3.

[0017] Clock IC 3 generates a SYSREF signal synchronized with the reference clock and outputs the generated SYSREF signal to the digital circuit 2 and the AD converter 1. Clock IC 3 also outputs the reference clock received from the directional coupler 6 to the digital circuit 2.

[0018] Due to the action of the directional coupler 6, the reflected signal from the clock IC 3, that is, the reflected signal of the reference clock directed from the clock IC 3 towards the directional coupler 6, is greatly attenuated. Therefore, the attenuator 5 receives a reference clock that contains almost no spurious signals or noise from the clock IC 3.

[0019] The attenuator 5 attenuates the signal level of a reference clock that is branched from the directional coupler 6 and input thereto. The reference clock that has passed through the attenuator 5 is input to the band-pass filter 4. The band-pass filter 4 reduces noise and spurious components other than a desired frequency, which are contained in the input reference clock, and outputs the reduced signal to an AD data converter as a sampling clock. Although a band-pass filter is illustrated as an example of the filter circuit characteristics in FIG. 1, any filter circuit other than a band-pass filter may be used as long as it has characteristics capable of reducing noise and spurious components other than the desired frequency.

[0020] The signal level input to the AD converter 1 is adjusted by the attenuator 5 so as to be a signal level appropriate for the input of the AD converter 1. That is, the attenuator 5 attenuates the signal level of the reference clock whose signal intensity is increased by the amplifier 7 and the signal level of the reflected signal from the clock IC 3, and adjusts the signal level of the reference clock output from the attenuator 5 to the band-pass filter 4 such that the signal level of the sampling clock output from the band-pass filter 4 to the AD converter 1 becomes a signal level suitable for input to the AD converter 1.

[0021] The digital circuit 2 controls the AD converter 1 in accordance with the JESD204 standard using SYSREF output from the clock IC 3 and the reference clock.

[0022] According to the sampling clock generation circuit 10 according to the embodiment, providing a directional coupler 6 in the preceding stage of the clock IC 3 has the effect of suppressing spurious emissions and noise from the clock IC 3 from sneaking into the sampling clock generation circuit 10. Further, according to the sampling clock generation circuit 10 according to the embodiment, by providing an attenuator 5 and a band-pass filter 4 between the directional coupler 6 and the AD converter 1, unnecessary spurious emissions and noise superimposed on the reference clock are attenuated, making it possible to supply a clean sampling clock to the AD converter 1. This makes it possible to implement the sampling clock generation circuit 10 having analog characteristics with high SFDR performance that does not generate image signals.

[0023] It should be noted that the configuration shown in the above embodiment is merely an example, and can be combined with other known techniques, and a part of the configuration can be omitted or modified within a range that does not depart from the gist of the present disclosure.

[0024] Finally, various aspects of the present disclosure are collectively described as supplementary notes.

[0025] (Supplementary Note 1) A sampling clock generation circuit that is used in a control system that includes a reference clock generation circuit generating a reference clock and controls a data converter, and generates a sampling clock to be output to the data converter, wherein: a first circuit section that amplifies a signal level of an input reference clock; a second circuit section that branches and outputs the reference clock input from the first circuit section to the reference clock generation circuit and another circuit section located at a subsequent stage; a third circuit section that attenuates a signal level of the reference clock branched and input from the second circuit section; a fourth circuit section that reduces noise and spurious components contained in a signal output from the third circuit section, and outputs the reduced signal as the sampling clock to the data converter; A sampling clock generation circuit characterized by comprising the following features. (Note 2) The first circuit section is an amplifier, The amplifier cancels out the decrease in signal strength when the input reference clock passes through the second circuit section, and adjusts the signal level of the reference clock output by the second circuit section to the reference clock generation circuit so that the signal level of the reference clock output by the second circuit section to the reference clock generation circuit is suitable for input to the reference clock generation circuit. A sampling clock generation circuit as described in Appendix 1, characterized by the above. (Note 3) The second circuit section is a directional coupler, The directional coupler outputs the input reference clock in two directions, to the reference clock generation circuit and the third circuit section, and reduces noise and spurious components contained in the reflected signal from the reference clock generation circuit. A sampling clock generation circuit as described in Appendix 1 or 2, characterized by the above. (Note 4) The third circuit section is an attenuator, The attenuator reduces the signal level of the reference clock whose signal strength has been increased by the first circuit and the signal level of the reflected signal from the reference clock generation circuit, and adjusts the signal level of the reference clock output to the fourth circuit so that the signal level of the sampling clock output by the fourth circuit to the data converter is suitable for input to the data converter. A sampling clock generation circuit as described in any one of the appendices 1 to 3, characterized by the above. (Note 5) The fourth circuit section is a filter circuit, The filter circuit reduces noise and spurious components other than the desired frequency included in the input sampling clock. A sampling clock generation circuit as described in any one of the appendices 1 to 4, characterized by the above. [Explanation of Symbols]

[0026] 1 AD converter (ADC), 2 Digital circuitry, 3 Clock IC, 4 Bandbus filter (BPF), 5 Attenuator (ATT), 6 Directional coupler, 7 Amplifier (AMP), 10 Sampling clock generation circuit, 50 Control system.

Claims

1. A sampling clock generation circuit used in a control system that controls a data converter and has a reference clock generation circuit for generating a reference clock, wherein the sampling clock generation circuit generates a sampling clock to be output to the data converter, A first circuit section that amplifies the signal level of the input reference clock, A second circuit unit that branches the reference clock input from the first circuit unit and outputs it to the reference clock generation circuit and another circuit unit located downstream, A third circuit section that attenuates the signal level of the reference clock branched from the second circuit section and input, A fourth circuit unit reduces noise and spurious components contained in the signal output from the third circuit unit and outputs the reduced signal as the sampling clock to the data converter. A sampling clock generation circuit characterized by comprising the following features.

2. The first circuit section is an amplifier, The amplifier cancels out the decrease in signal strength when the input reference clock passes through the second circuit section, and adjusts the signal level of the reference clock output by the second circuit section to the reference clock generation circuit so that the signal level of the reference clock output by the second circuit section to the reference clock generation circuit is suitable for input to the reference clock generation circuit. The sampling clock generation circuit according to feature 1.

3. The second circuit section is a directional coupler, The directional coupler outputs the input reference clock in two directions, to the reference clock generation circuit and the third circuit section, and reduces noise and spurious components contained in the reflected signal from the reference clock generation circuit. A sampling clock generation circuit according to claim 1 or 2.

4. The third circuit section is an attenuator, The attenuator reduces the signal level of the reference clock whose signal strength has been increased by the first circuit and the signal level of the reflected signal from the reference clock generation circuit, and adjusts the signal level of the reference clock output by the fourth circuit to the fourth circuit so that the signal level of the sampling clock output by the fourth circuit to the data converter is at a signal level suitable for input to the data converter. A sampling clock generation circuit according to claim 1 or 2.

5. The fourth circuit section is a filter circuit, The filter circuit reduces noise and spurious components other than the desired frequency included in the input sampling clock. A sampling clock generation circuit according to claim 1 or 2.

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