Semiconductor and display devices

Abstract

This suppresses changes in transistor characteristics and increases the W / L ratio of the transistor. The present invention provides a semiconductor device that can rapidly change the output signal without any additional processing. [Solution] Two transistors are connected in parallel between the wiring supplied with a low potential and the output terminal. Continue. And when outputting a low potential from the output terminal, both transistors are turned on. After doing this, one of the transistors is turned off. This suppresses the change in the transistor's characteristics. This is possible, and it also allows for rapid output signal generation without increasing the W / L ratio of the transistor. It can be changed sharply.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device and a display device having the semiconductor device. In particular, This invention relates to a sequential circuit and a semiconductor device such as a shift register having said sequential circuit. [Background technology]

[0002] In recent years, the development of sequential circuits composed of transistors with the same polarity has been actively pursued. Furthermore, Patent Document 1 discloses a sequential circuit that can suppress changes in the characteristics of a transistor. It is being done.

[0003] Figure 17(A) shows the configuration of a conventional sequential circuit. The conventional sequential circuit uses transistor T13 It has transistors T14 and T15 connected in parallel. In a sequential circuit, transistor T13 turns on, and transistors T14 and transistors When T15 is turned off, the first clock signal C1 is output. If 1 is at a high level, the first scan signal Vg1 will also be at a high level (see Figure 17(B)). (Illuminate). And in odd-numbered frames, transistor T13 is turned off, and transistor T1 When 4 is turned on, transistor T15 is turned off, outputting the first supply voltage VSS. (See Figure 17(C)). Also, in even frames, transistor T13 is turned off. As a result, transistor T14 turns off and transistor T15 turns on, the first supply The feed voltage VSS is output (see Figure 17(D)). Thus, in odd-numbered frames, By turning off transistor T15 and transistor T14 on even frames, Changes in the characteristics of transistors T14 and T15 are suppressed. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2007-004167 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, in conventional sequential circuits, one of the two transistors connected in parallel is turned off. To drive only the other transistor, two transistors connected in parallel... Each of these requires sufficient driving capability. Therefore, the W of the transistor (W is the channel width) There was a problem where ) / L (where L is the channel length) became large. Also, the W of the transistor If / L is not large enough, the change in the output signal will be gradual, and there will be a delay or lag in the output signal. There were problems such as the occurrence of [unclear / unclear].

[0006] Therefore, one aspect of the present invention suppresses changes in the characteristics of a transistor, and A semiconductor device that can rapidly change the output signal without increasing the W / L ratio. One of the objectives is to provide such a product. Furthermore, one aspect of the present invention relates to a semiconductor including a novel circuit configuration. One of the objectives is to provide an apparatus. Note that the description of these objectives does not imply the existence of other objectives. This does not preclude it. Furthermore, one aspect of the present invention does not need to solve all of these problems. It shall be considered that... Furthermore, any other issues shall be determined from the description in the specification, drawings, claims, etc. This becomes clear, and from the descriptions in the specification, drawings, claims, etc., other issues are not addressed. It is possible to extract it. [Means for solving the problem]

[0007] One aspect of the present invention provides a first transisto r, in which a first potential is input to one of a source and a drain, and the other of the source and the drain is a second transisto electrically connected to the other of the source and the drain of the first transistor r, wherein one of a source and a drain is electrically connected to one of a source and a drain of the second transistor electrically connected thereto, and the other of the source and the drain is the source or the drai of the first transistor n, a third transistor electrically connected to the other of said source and drain, and means for controlling turning on or off of the first transistor, the second transisto r and the third transistor, which is a method for driving a semiconductor device. The semiconductor device supplies the first signal through the first transistor and outputting the signal, the method comprising a first step of outputting the first signal through the first transistor, and supplying the first potential to the second transistor and the third transistor outputting the first potential through the second transistor and the third transistor, a second step of outputting the first potential through the second transistor and the third transistor , and a third step of outputting the first potential through the second transistor; and a first period comprising the above steps, wherein the first signal is output through the first transistor outputting the first potential through the second transistor and the third transistor, a fourth step of outputting the first signal through the first transistor , outputting the first potential through the second transistor and the third transistor, a fifth step of outputting the first potential through the second transistor and the third transistor , and a sixth step of outputting the first potential through the third transistor, and a second period comprising the above steps are sequentially repeated .

[0008] In one aspect of the present invention described above, in the first period, the first step, the second step, and the third step is performed two or more times each, and in the second period, the fourth step, the fifth ste p and the sixth step may each be performed two or more times. In addition, in one aspect of the present invention describe d above, a channel width of the second transistor is 90% or more of a channel width of the third transistor The above may be 110% or less. Also, in one embodiment of the present invention, the first transient The channel width of the first transistor is greater than the channel width of the second transistor, and the channel width of the third transistor It can be larger than the channel width of the ZISTA.

[0009] One aspect of the present invention is that either the source or the drain is electrically connected to the first wiring, and the source Alternatively, the other end of the drain of the first transistor is electrically connected to the second wiring, and the source or One side of the drain is electrically connected to the first wiring, and the other side of the source or drain is connected to the second A second transistor is electrically connected to the wiring, and the first terminal is connected to the first transistor's terminal. A first switch is electrically connected to the gate of a second transistor, and the first terminal is connected to the gate of a second transistor. The second terminal is electrically connected to the second terminal of the first switch. Switch 2 and the first terminal are electrically connected to the third wiring, and the second terminal is connected to the first switch A third switch is electrically connected to the gate of the inverter, and the first terminal is electrically connected to the third wiring. A fourth terminal is electrically connected to the gate of the second transistor, and the second terminal is electrically connected to the gate of the second transistor. This semiconductor device is characterized by having a switch.

[0010] One aspect of the present invention described above is that either the source or the drain is connected to a fourth wiring, and the source or The other end of the drain is connected to the second terminal of the first switch, and the gate is connected to the fourth wiring. A third transistor is connected to the second wiring, with either the source or the drain connected to the source. Alternatively, a fourth transistor whose other drain is connected to the second terminal of the first switch, It may also have a first switch and a fourth switch. A first period in which the first switch is on and the second and third switches are off, and the first Switch and the fourth switch are off, and the second and third switches are on. It may have a second period. [Effects of the Invention]

[0011] One aspect of the present invention can suppress changes in the characteristics of a transistor, and A semiconductor device that can make the output signal change steeper without increasing the W / L of the sta. It is possible to provide a suitable location. Furthermore, one aspect of the present invention relates to a semiconductor device including a novel circuit configuration. We can provide this. [Brief explanation of the drawing]

[0012] [Figure 1] A diagram showing the configuration of a sequential circuit. [Figure 2] Timing chart for a sequential circuit. [Figure 3] Timing chart for a sequential circuit. [Figure 4] A diagram illustrating the operation of a sequential circuit. [Figure 5] A diagram illustrating the operation of a sequential circuit. [Figure 6] A diagram illustrating the operation of a sequential circuit. [Figure 7] A diagram illustrating the operation of a sequential circuit. [Figure 8] A diagram showing the configuration of a sequential circuit. [Figure 9] A diagram showing the configuration of a sequential circuit. [Figure 10] A diagram showing the configuration of a sequential circuit. [Figure 11] A diagram showing the configuration of a shift register. [Figure 12] A diagram showing the panel configuration. [Figure 13] A diagram showing the cross-sectional structure of a transistor. [Figure 14] Top view and cross-sectional view of a liquid crystal display device. [Figure 15]A diagram showing electronic equipment. [Figure 16] A diagram showing the configuration of a sequential circuit. [Figure 17] A diagram illustrating the configuration and operation of a conventional sequential circuit. [Modes for carrying out the invention]

[0013] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the present invention may have forms and characteristics that do not depart from the spirit and scope of the invention. Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents of the embodiments described below.

[0014] Furthermore, this invention relates to all semiconductors using transistors, such as integrated circuits, RF tags, and display devices. Conducting devices are included in this category. Integrated circuits include microprocessors and image processing circuits. , DSP (Digital Signal Processor), Microcontroller LSI (Large Scale Integrated Circuit) including R, FPGA (Field Programmable Gate Array) and CPLD Programmable logic circuits (PLDs) such as Complex PLDs This category includes (a Logic Device). Furthermore, the display device includes, A light-emitting device that has light-emitting elements in each pixel, such as liquid crystal displays and organic light-emitting elements (OLEDs). Electronic paper, DMD (Digital Micromirror Device) , PDP (Plasma Display Panel), FED (Field Emi This category includes things like computer displays.

[0015] In this specification, a display device refers to a display element such as a liquid crystal element or a light-emitting element that has a shape in each pixel. A completed panel and a module with an IC including a controller mounted on the panel. This includes "ru" and "to" within that category.

[0016] In this specification, "connection" means an electrical connection, and current, voltage, or potential is... This corresponds to a state where it can be supplied or transmitted. Therefore, a connected state is a state where it is directly connected. It does not necessarily refer to a state in which current, voltage, or potential is available or To enable transmission, circuit elements such as wiring, resistors, diodes, and transistors are used. This category also includes situations where components are indirectly connected. Furthermore, components that appear independent on the circuit diagram are also included. Even when elements are connected to each other, in reality, for example, a part of the wiring acts as an electrode. In some cases, such as when it is possible, a single conductive film may possess the functions of multiple components. In the specification, connection means that one conductive film combines the functions of multiple components. Cases where this is the case are also included in that category.

[0017] The source of a transistor is the source region, which is a part of the semiconductor film that functions as the active layer. This refers to the region, or the source electrode connected to the semiconductor film mentioned above. Similarly, the transistor's Rain refers to a drain region which is part of the semiconductor film, or a region connected to the semiconductor film. It refers to the drain electrode. Similarly, "gate" refers to the gate electrode.

[0018] Furthermore, the source and drain of a transistor are determined by the polarity of the transistor and the input to each terminal. The name changes depending on the level of the potential being generated. Generally, n-channel type transients In a stator, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the dot. It is called rain. Also, in p-channel transistors, the terminal to which a low potential is applied is The terminal to which a high potential is applied is called the source, and is called the drain. Above, assuming the source and drain are fixed, we will explain the connection relationship of the transistor. Although it may be clarified in some cases, in practice the names of source and drain are assigned according to the potential relationship described above. It will change.

[0019] (Embodiment 1) This embodiment describes a sequential circuit (also referred to as a semiconductor device) according to one aspect of the present invention. do.

[0020] Figure 1(A) shows the sequential circuit of this embodiment. The sequential circuit in Figure 1(A) is a transistor M1, Transistor M2a, Transistor M2b, Switch S3a, Switch S3b, S It has a switch S4a, a switch S4b, and a circuit 10.

[0021] Transistor M1 has a first terminal (also called the source or drain) that is in contact with the wiring 11. The second terminal (also known as the source or drain) is connected to the wiring 12, The transistor M2a is connected to node N1. The first terminal of transistor M2a is connected to wiring 13. The second terminal is connected to wiring 12, and the gate is connected to node N2a. M2b has a first terminal connected to wiring 13 and a second terminal connected to wiring 12, and a gate It is connected to node N2b. Switch S3a has its first terminal connected to node N3, The second terminal is connected to node N2a. Switch S3b has its first terminal connected to node N3. The connection is established, and the second terminal is connected to node N2b. Switch S4a has the first terminal connected It is connected to line 14, and the second terminal is connected to node N2a. Switch S4b is the first The terminal is connected to wiring 14, and the second terminal is connected to node N2b. Circuit 10 is first The first terminal is connected to wiring 15, the second terminal is connected to wiring 14, and the third terminal is connected to node N It is connected to terminal 1, and the fourth terminal is connected to node N3.

[0022] Circuit 10 supplies a potential to node N1 to control the on or off state of transistor M1. It has the function of turning on transistor M1 at node N1. It has the function of supplying a potential and then putting node N1 into a floating state. In addition, circuit 10 has the function of It has the function of supplying a potential to turn off transistor M1 to circuit N1. Furthermore, circuit 1 0 controls the on / off state of transistor M2a or transistor M2b at node N3. It has the function of supplying a potential for transitioning to node N3. Specifically, circuit 10 has the function of supplying a potential to transition to node N3. It has the function of supplying the potential that turns on either transistor M2a or transistor M2b. The path 10 provides a potential at node N3 that turns off either transistor M2a or transistor M2b. It has the function of supplying. The potential supplied by circuit 10 to node N3 is supplied by switch S3a If it is on, it is supplied to node N2a, and if switch S3b is on, it is supplied to node N2b. It is supplied. Also, the connection relationship of circuit 10 can be changed as appropriate depending on the configuration of circuit 10. Cut.

[0023] Furthermore, transistors in a sequential circuit are assumed to have the same polarity. The polarity of the transistors is as follows: There are N-channel and P-channel types. In this embodiment, for convenience, transistor M1, Transistors M2a and M2b are N-channel type.

[0024] Furthermore, the transistor determines whether there is continuity or non-continuity between the connection point of the first terminal and the connection point of the second terminal. It has a control function. For example, transistor M1 controls the conduction between wiring 11 and wiring 12 or It has a function to control non-conductivity. Transistor M2a controls the conductivity between wiring 13 and wiring 12. It has the function of controlling non-conductivity. Transistor M2b controls the conduction between wiring 13 and wiring 12. Alternatively, it has a function to control non-conductivity.

[0025] Furthermore, the transistor has an electrical current between the gate's connection point and the first or second terminal's connection point. It has the function of maintaining the position difference between wiring 12 and node N1. It has the function of maintaining the potential difference between them.

[0026] Alternatively, the transistor can be replaced with a switch. The first terminal of the transistor is the switch. The first terminal of the switch corresponds to the first terminal of the transistor, and the second terminal of the transistor corresponds to the second terminal of the switch. For example, transistor M2a has its first terminal connected to wire 13 and its second terminal connected to wire 1 It may be replaced with a switch connected to 2. Transistor M2b is connected to the first terminal of wire 1. It may be replaced with a switch connected to 3, with the second terminal connected to wiring 12.

[0027] Furthermore, signals or electrical potentials are input to the wiring, and the wiring transmits the input signals or electrical potentials. It has a function. For example, the signal or potential of wiring 11 has the function of raising the potential of wiring 12. It is preferable that the signal or potential of wiring 13 has the function of lowering the potential of wiring 12. It is preferable to have it. Wiring 14 controls the on or off of transistor M2a. Functions include controlling the on / off state of transistor M2b, or controlling circuit 10. It is preferable that it has a function. The signal or potential of the wiring 15 has a function to control the circuit 10. It is preferable to do so.

[0028] In this embodiment, for convenience, the signal CK1 (also called the clock signal) is input to wiring 11. Then, a signal OUT (also called an output signal) is output from wiring 12, and the potential V1 is output to wiring 13. (Also called the first potential) is supplied, and the signal RE (also called the reset signal) is connected to wiring 14. It is assumed that the signal SP (also called the start signal) is input to wiring 15. For convenience, signals CK1, SP, and RE have high and low levels. Let's assume that the low-level potential is potential V1 and the high-level potential is potential V2. Let this be called the second potential (also known as the potential V1). Potential V2 is a higher potential than potential V1.

[0029] Next, we will explain the operation of the sequential circuit shown in Figure 1(A).

[0030] Figures 2 and 3 are timing charts used to explain the operation of the sequential circuit in Figure 1(A). Let's look at an example. The timing charts in Figures 2 and 3 have periods Ta and Tb. Figure 2 shows a timing chart of period Ta having periods T1a to T4a. Figure 3 shows the timing chart for period Tb, which has periods T1b to T4b. Figures 2 and 3 show the on / off relationship of switches S3a and S4b, and switches The relationship between S3b and switch S4a (on or off), signal CK1, signal SP, signal RE, Potential VN1 at node N1, potential VN2a at node N2a, potential VN2b at node N2b, parallel This indicates a signal OUT.

[0031] Figures 4 to 7 show the operation of the sequential circuit in Figure 1(A) during each period (also called each step). A schematic diagram is shown. Figure 4(A) is period T1a, Figure 4(B) is period T2a, and Figure 5(A) is period T 3a, Figure 5(B) is for period T4a, Figure 6(A) is for period T1b, Figure 6(B) is for period T2b, Figure Figure 7(A) shows the operation of the sequential circuit in Figure 1(A) during period T3b, and Figure 7(B) shows the operation of the sequential circuit in Figure 1(A) during period T4b. A schematic diagram is shown.

[0032] First, let's explain the operation during period Ta. During period Ta, switch S3a and switch Switch S4b is ON, and switches S3b and S4a are OFF.

[0033] During period T1a, signal CK1 becomes low level, signal SP becomes high level, and signal R E becomes low level. At node N1, the potential at which transistor M1 turns on is at circuit 10. Because it is supplied from there, transistor M1 turns on. Then, circuit 10 to node N1 Because the supply of potential to these nodes is cut off, node N1 becomes floating. The potential of node N1 is Because the potential is maintained at which zista M1 turns on, transistor M1 remains on. Furthermore, at node N2a, the potential that turns off transistor M2a is supplied from circuit 10 to switch S It is supplied via 3a. Therefore, transistor M2a is turned off. Also, node N2 Signal RE is supplied to b via switch S4b. Since signal RE is at a low level, , transistor M2b turns off. Also, the signal CK1 is connected to transistor M1 in wiring 12. It is supplied via [this]. Since signal CK1 is low level, the potential of wiring 12 is [potential V1]. Yes, that means the signal OUT becomes low level.

[0034] During period T2a, signal CK1 becomes high level, signal SP becomes low level, and signal R E remains at a low level. The potential supply from circuit 10 to node N1 remains cut off. Therefore, node N1 remains in a floating state, and transistor M1 remains on. Furthermore, at node N2a, the potential that turns off transistor M2a is from circuit 10 to switch S3. Because power is still being supplied via a, transistor M2a remains off. Signal RE continues to be supplied to node N2b via switch S4b. Signal RE is Because it remains at a low level, transistor M2b remains off. Also, wiring 12 The signal CK1 remains supplied via transistor M1. The signal CK1 is high-frequency. Because it is a bell, the potential of wiring 12 becomes potential V2. In other words, signal OUT becomes high level. Yes.

[0035] Furthermore, node N1 is in a floating state, and transistor M1 is connected to wiring 12 and node N1. Because the potential difference between them is maintained, the potential of node N1 rises as the potential of wiring 12 rises. This is the so-called bootstrap operation. This causes the potential of node N1 to transition The potential of the first terminal of transistor M1 (e.g., potential V2) and the threshold voltage of transistor M1 Since it can be set to a value exceeding the sum, the potential of wiring 12 can be raised to potential V2. can.

[0036] During period T3a, signal CK1 is at a low level, and signal SP remains at a low level. The signal RE becomes high level. Node N1 has a potential that turns off transistor M1 in the circuit. Since it is supplied from 10, transistor M1 turns off. Also, node N2a has a transistor Because the potential that turns on the inverter M2a is supplied from the circuit 10 via the switch S3a. Transistor M2a turns on. Also, the signal RE is switched to node N2b. It remains supplied via [the same method]. Since the signal RE is at a high level, transistor M2b It turns on. That is, both transistor M2a and transistor M2b turn on. Furthermore, the potential V1 in wiring 12 is present in both transistors M2a and M2b. It is supplied via. Therefore, the potential of wiring 12 becomes potential V1. In other words, signal OUT is It becomes a U-level.

[0037] Furthermore, the potential V1 in wiring 12 is transmitted through both transistor M2a and transistor M2b. Because it is supplied in this way, the W / L ratio of transistors M2a and M2b is increased. This allows for a shorter falling edge time for the signal OUT.

[0038] During period T4a, signal CK1 repeatedly switches between high and low levels, and signal SP is low. The bell remains, and the signal RE becomes low level. Transistor M1 is connected to node N1. Since the potential that causes the transistor to turn off is still supplied from circuit 10, transistor M1 remains off. Furthermore, at node N2a, the potential at which transistor M2a turns on is from circuit 10. Because it remains supplied via switch S3a, transistor M2a remains on. Furthermore, the signal RE remains supplied to node N2b via switch S4b. Since the signal RE is low level, transistor M2b turns off. Also, wiring 12 The potential V1 is supplied via transistor M2a. Therefore, the potential of wiring 12 is potential V It remains at 1. In other words, the signal OUT remains at a low level.

[0039] Furthermore, period T4a is longer than periods T1a through T3a and accounts for the majority of the operating period. And transistor M2b is off during period T4a. Therefore, the transistor This shortens the time that transistor M2b is ON, suppressing changes in the characteristics of transistor M2b. It is possible.

[0040] Next, we will explain the operation during period Tb. During period Tb, switch S3a and switch Switch S4b is off, and switches S3b and S4a are on.

[0041] During period T1b, signal CK1 becomes low level, signal SP becomes high level, and signal R E becomes low level. At node N1, the potential at which transistor M1 turns on is at circuit 10. Because it is supplied from there, transistor M1 turns on. Then, circuit 10 to node N1 Because the supply of potential to these nodes is cut off, node N1 becomes floating. The potential of node N1 is Because the potential is maintained at which zista M1 turns on, transistor M1 remains on. Furthermore, at node N2b, the potential that turns off transistor M2b is supplied from circuit 10 to switch S It is supplied via 3b. Therefore, transistor M2b is turned off. Also, node N2 Signal RE is supplied to a via switch S4a. Since signal RE is at a low level, , transistor M2a turns off. Also, the signal CK1 is connected to transistor M1 in wiring 12. It is supplied via [this]. Since signal CK1 is low level, the potential of wiring 12 is [potential V1]. Yes, that means the signal OUT becomes low level.

[0042] During period T2b, signal CK1 becomes high level, signal SP becomes low level, and signal R E remains at a low level. The potential supply from circuit 10 to node N1 remains cut off. Therefore, node N1 remains in a floating state, and transistor M1 remains on. Furthermore, at node N2b, the potential that turns off transistor M2b is supplied from circuit 10 to switch S3. Because power is still being supplied via b, transistor M2b remains off. Signal RE continues to be supplied to node N2a via switch S4a. Signal RE is Because it remains at a low level, transistor M2a remains off. Also, wiring 12 The signal CK1 remains supplied via transistor M1. The signal CK1 is high-frequency. Because it is a bell, the potential of wiring 12 becomes potential V2. In other words, signal OUT becomes high level. Yes.

[0043] Furthermore, node N1 is in a floating state, and transistor M1 is connected to wiring 12 and node N1. Because the potential difference between them is maintained, the potential of node N1 also rises as the potential of wiring 12 rises. This is the so-called bootstrap operation. This causes the potential of node N1 to transition The potential of the first terminal of transistor M1 (e.g., potential V2) and the threshold voltage of transistor M1 Since it can be set to a value exceeding the sum, the potential of wiring 12 can be raised to potential V2. can.

[0044] During period T3b, signal CK1 is at a low level, and signal SP remains at a low level. The signal RE becomes high level. Node N1 has a potential that turns off transistor M1 in the circuit. Since it is supplied from 10, transistor M1 turns off. Also, node N2b has a transistor Because the potential that turns on the inverter M2b is supplied from the circuit 10 via the switch S3b. Transistor M2b turns on. Also, signal RE is connected to switch S4a at node N2a. It remains supplied through. Since the signal RE is at a high level, transistor M2a It turns on. That is, both transistor M2a and transistor M2b turn on. Furthermore, the potential V1 in wiring 12 is present in both transistors M2a and M2b. It is supplied via. Therefore, the potential of wiring 12 becomes potential V1. In other words, signal OUT is It becomes a U-level.

[0045] Furthermore, the potential V1 in wiring 12 is transmitted through both transistor M2a and transistor M2b. Because it is supplied in this way, the W / L ratio of transistors M2a and M2b is increased. This allows for a shorter falling edge time for the signal OUT.

[0046] During period T4b, signal CK1 repeatedly switches between high and low levels, and signal SP is low. The bell remains, and the signal RE becomes low level. Transistor M1 is connected to node N1. Since the potential that causes the transistor to turn off is still supplied from circuit 10, transistor M1 remains off. Furthermore, at node N2b, the potential at which transistor M2b turns on is from circuit 10. Because it remains supplied via switch S3b, transistor M2b remains on. Furthermore, the signal RE continues to be supplied to node N2a via switch S4a. Since the signal RE is low level, transistor M2a turns off. Also, wiring 12 The potential V1 is supplied via transistor M2b. Therefore, the potential of wiring 12 is potential V It remains at 1. In other words, the signal OUT remains at a low level.

[0047] Furthermore, period T4b is longer than periods T1b through T3b and accounts for the majority of the operating period. And transistor M2a is off during period T4b. Therefore, the transistor This shortens the time that transistor M2a is ON, suppressing changes in the characteristics of transistor M2a. It is possible.

[0048] As described above, the sequential circuit in Figure 1(A) can suppress changes in the characteristics of the transistor. Furthermore, it shortens the fall time of the output signal without increasing the W / L of the transistor. It can be done.

[0049] Note that the potential at which transistor M1 turns on is the first terminal or the second terminal of transistor M1. A value exceeding the sum of the terminal potential (e.g., potential V1) and the threshold voltage of transistor M1. Yes. Also, the potential at which transistor M1 turns off is the first terminal of transistor M1 or The value is less than the sum of the potential of the second terminal (e.g., potential V1) and the threshold voltage of transistor M1. It is a value. For example, the potential at which transistor M1 turns off is potential V1. The potential at which transistor M2a or transistor M2b turns on is the potential at which transistor M2 a or the potential of the first terminal of transistor M2b (e.g., potential V1) and transistor M2a Or it is a value that exceeds the sum of the threshold voltage of transistor M2b. For example, transistor The potential at which transistor M2a or transistor M2b turns on is potential V2. The potential at which transistor M2a or transistor M2b turns off is the potential at which transistor M2a or The potential of the first terminal of transistor M2b (e.g., potential V1) and transistor M2a or It is a value less than the sum of the threshold voltage of transistor M2b. For example, transistor M2a or The potential at which transistor M2b turns off is potential V1. The potential at which M1 turns off is the potential at which either transistor M2a or transistor M2b turns off. It may be equal to or different from this. Also, the potential at which transistor M2a turns on. This voltage may be equal to or different from the potential at which transistor M2b turns on. Furthermore, the potential at which transistor M2a turns off is equal to the potential at which transistor M2b turns off. They can be similar, or they can be different.

[0050] The above description of operation is merely an example and is not limited thereto. For example, circuit 10 is, During interval T1a, a potential is supplied to node N2a that turns on transistor M2a, and during period T At 1b, a potential that turns on transistor M2b may be supplied to node N2b. In this case, during period T1a, transistor M2a turns on, and potential V1 becomes the transistor It is supplied to wiring 12 via transistor M2a. Also, during period T1b, transistor M2 When b is turned on, potential V1 is supplied to wiring 12 via transistor M2b.

[0051] Furthermore, circuit 10 stops supplying potential to node N1 during periods T4a and T4b. This is also possible. In this case, node N1 will be in a floating state during periods T4a and T4b. The potential at node N1 is the potential during period T3a or period T3b (transistor M1 is off). Because it is maintained at a potential of (this potential), transistor M1 remains off.

[0052] Furthermore, circuit 10 stops supplying potential to node N3 during periods T4a and T4b. This is also possible. In this case, during period T4a, nodes N3 and N2a will be in a floating state. The potential of node N2a is maintained at the potential that turns on transistor M2a, therefore the The generator M2a remains on. Also, during period T4b, node N3 and node N2b becomes floating. The potential of node N2b is at the potential that turns on transistor M2b. Because it is maintained, transistor M2b remains on.

[0053] Note that the W (W is the channel width) / L (L is the channel length) of transistor M1 is shown in Figure 1(A). The largest transistor in the sequential circuit is preferable. For example, The W / L of transistor M1 is greater than the W / L of transistors M2a and M2b. This is preferable. Also, if circuit 10 has a transistor, the W / L of transistor M1 It is preferable that this is greater than the W / L of the transistor in circuit 10.

[0054] Furthermore, the W / L ratio of transistor M2a is approximately equal to that of transistor M2b. This is preferable. For example, the W / L of transistor M2a is ±1 of the W / L of transistor M2b. It is preferable that the value be within 0%, and more preferably within ±5%.

[0055] In this specification, W / L may be replaced with W. This is because the transistor This is because the channel lengths are often equal or approximately equal.

[0056] Note that the transition between period Ta and period Tb occurs during either period T4a or period T4b. This is preferable. Specifically, during period T4a, switch S3a and switch S4b When it goes from on to off, switches S3b and S4a go from off to on. Preferred. Also, during period T4b, switches S3b and S4a switch from off to on. It is preferable that switches S3a and S4b switch from on to off. This prevents malfunctions caused by the switching between periods Ta and Tb.

[0057] Also, after switches S3a and S4b are turned from on to off, switch S3b And switch S4a may change from off to on. Similarly, switch S3b and switch After switch S4a changes from on to off, switches S3a and S4b change from off to on It may be a switch. That is, switch S3a, switch S3b, switch S4a and switch The switch S4b may have a period of time when it is off. In this case, the fourth terminal of circuit 10 This prevents electrical conductivity between the wire 14 and the other wire.

[0058] Furthermore, periods T1a to T4a can be repeated multiple times (for example, 100 times or more, more preferably 200 times) After repeating the process at least once, more preferably 300 times or more, the period is cut from period Ta to period Tb. It is preferable to change. Also, it is preferable to repeat periods T1b to T4b multiple times (100 times or more). (Preferably 200 times or more, more preferably 300 times or more) After this is repeated, the period Tb or It is preferable to switch to period Ta. That is, period Ta is period T1a to period T Multiple of any of 4a (for example, 100 or more, more preferably 200 or more, even more preferably It is preferable to have 300 or more. Also, period Tb is period T1b to period Multiple T4b (100 or more, more preferably 200 or more) It is preferable to have 300 or more of these. This way, the switching between period Ta and period Tb This can suppress the increase in power consumption associated with the process. However, if the number of repetitions is too large... This may cause variations in the characteristics of transistors M2a and M2b. Therefore, the number of times periods T1a to T4a are repeated, or periods T1b to T4b are repeated The number of repetitions is less than 1000 times, more preferably less than 700 times, and even more preferably 500 times. It is preferable that the number be less than 100.

[0059] A transistor can be used as the switch. Figure 1(B) is shown in Figure 1(A). ) in which switches S3a, S3b, S4a and S4b are used transistors M3a, M3b, M4a and M4 The sequential circuits with b applied to each are shown. Transistor M3a, Transistor M3b, Transistor Transistors M4a and M4b have the same polarity as transistor M1. Zistar M3a has its first terminal connected to node N3 and its second terminal connected to node N2a. The gate is then connected to wiring 16a. Transistor M3b has its first terminal at node N It is connected to 3, the second terminal is connected to node N2b, and the gate is connected to wiring 16b. Transistor M4a has its first terminal connected to wire 14 and its second terminal connected to node N2a It is connected to and the gate is connected to wiring 16b. Transistor M4b has the first terminal connected It is connected to wire 14, the second terminal is connected to node N2b, and the gate is connected to wire 16a. The signal or potential of wiring 16a controls whether transistor M3a is turned on or off. It is preferable that it has a function, or a function to control the on or off state of transistor M4b. Furthermore, the signal or potential of wiring 16b controls whether transistor M3b is on or off. It is preferable to have a function to do so, or a function to control the on or off state of transistor M4a. In this embodiment, for convenience, the signal SELa is input to wiring 16a, and wiring 16 The signal SELb is assumed to be input to b.

[0060] During period Ta, signal SELa is at a high level, and signal SELb is at a low level. That is, transistors M3a and M4b are on, and transistor M3b and Transistor M4a is off. During period Tb, the signal SELa is at a low level. The signal SELb is at a high level. Therefore, transistors M3a and M4b The switch is off, and transistors M3b and M4a are on. That is, Transistor M3a, transistor M3b, transistor M4a and transistor M4b are Switches S3a, S3b, S4a, and S4b are similar in each case. The on or off state is controlled at the timing. Therefore, the sequential circuit in Figure 1(B) is equivalent to Figure 1(A). Since it can perform the same operation as the sequential circuit shown in Figure 1(A), it has the same effect as the sequential circuit shown in Figure 1(A). It plays.

[0061] Furthermore, the potential V1 may be the low-level potential of signals SELa and SELb. Furthermore, not limited to this, the low-level potentials of signals SELa and SELb are set to potential V1. It can also be set to the full value. This way, the potential difference between the gate and source of the transistor can be set to 0[ Since it can be reduced to less than [V], changes in the transistor's characteristics can be suppressed.

[0062] Alternatively, the high-level potentials of signals SELa and SELb may be taken as potential V2. Furthermore, not limited to this, the high-level potentials of signals SELa and SELb are measured from potential V2. It may also be set to a higher value. This will raise the potentials of nodes N2a and N2b. It is possible.

[0063] Furthermore, after signal SELa changes from high level to low level, signal SELb changes to low level. It is also acceptable for the signal SELb to change from a high level to a low level. After that, the signal SELa may change from a low level to a high level. That is, the signal S There may be periods during which ELa and the signal SELb are at low levels. This way the circuit This prevents electrical conductivity between the fourth terminal of 10 and the wiring 14.

[0064] Furthermore, the W / L ratio of transistor M3a is approximately equal to that of transistor M3b. Preferred. For example, the W / L of transistor M3a is ±1 of the W / L of transistor M3b. It is preferable that it be within 0%. More preferably, it is within ±5%. It is preferable that the W / L of transistor M4a is approximately equal to the W / L of transistor M4b. For example, the W / L of transistor M4a is within ±10% of the W / L of transistor M4b. It is preferable that it be within the range. More preferably, it is within ±5%. Also, transistor M W / L of 1 is transistor M3a, transistor M3b, transistor M4a and transistor It is preferable that the W / L of transistor M4b is greater than that of transistor M2a and The W / L of transistor M2b is, transistor M3a, transistor M3b, transistor It is preferable that the W / L of M4a and transistor M4b is greater. The W / L of transistors M4a and M4b is the same as that of transistors M3a and M3 It is preferable that b is greater than W / L.

[0065] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, etc. Cut.

[0066] (Embodiment 2) In this embodiment, the circuit can be applied to the sequential circuit 10 of Embodiment 1. I will explain.

[0067] The circuit 10 in Figure 8(A) includes transistor M5, transistor M6, and circuit 20. Transistors M5 and M6 have the same polarity as transistor M1. The Zistar M5 has its first terminal connected to wiring 15 and its second terminal connected to node N1. The gate is connected to wire 15. Transistor M6 has its first terminal connected to wire 13. The second terminal is connected to node N1, and the gate is connected to wiring 14. Circuit 20 is the Terminal 1 is connected to node N1, and terminal 2 is connected to node N3.

[0068] Circuit 20, depending on the potential of node N1, outputs transistor M2a or transistor to node N3. It has the function of supplying a potential to control whether the M2b is on or off. Specifically, Circuit 20 operates when the potential at node N1 is low (for example, during periods T3a, T3b, and T4a) Or, during period T4b, etc., transistor M2a or transistor M2b It has the function of supplying a potential that turns on. Also, circuit 20 has a high potential at node N1. At times (for example, during period T1a, period T1b, period T2a, or period T2b, etc.), N3 has the function of supplying a potential that turns off either transistor M2a or transistor M2b. Furthermore, the input terminal of circuit 20 is connected to node N1, and the output terminal is connected to node N3. It may be replaced with the inverter circuit described above.

[0069] During periods T1a and T1b, transistor M5 turns on, and transistor M6 It turns off. Signal SP is supplied to node N1 via transistor M5. Signal S Since P is at a high level, the potential at node N1 rises. The potential at node N1 transitions Subtract the threshold voltage of transistor M5 from the gate potential of transistor M5 (for example, potential V2). When the value reaches a certain point, transistor M5 turns off. Therefore, node N1 becomes floating. Furthermore, circuit 20 has a potential that turns off either transistor M2a or transistor M2b. It will be supplied to N3.

[0070] During periods T2a and T2b, transistor M5 remains off, and the transistor Transistor M6 remains off. Also, circuit 20 is either transistor M2a or transistor M The potential that turns off 2b remains supplied to node N3.

[0071] During periods T3a and T3b, transistor M5 remains off, and the transistor Transistor M6 turns on. Potential V1 is supplied to node N1 via transistor M6. Therefore, the potential of node N1 becomes potential V1. Also, circuit 20 has transistor M2a or The potential that turns on transistor M2b is supplied to node N3.

[0072] During periods T4a and T4b, transistor M5 remains off, and the transistor Transistor M6 turns off. Also, in circuit 20, either transistor M2a or transistor M2b turns off. The potential that results in a certain value remains supplied to node N3.

[0073] Circuit 10 in Figure 8(B) is different from that in Figure 8(A) in that transistor M7a and transistor It differs in that it has M7b. Transistors M7a and M7b are transistors It has the same polarity as transistor M1. Transistor M7a has its first terminal connected to wiring 13. The second terminal is connected to node N1, and the gate is connected to node N2a. Transis Terminal M7b has its first terminal connected to wiring 13, and its second terminal connected to node N1. The node is connected to node N2b.

[0074] During periods T1a, T2a, T1b, and T2b, transistor M7a and Transistor M7b is off. Also, during periods T3a and T3b, the transistor st.M7a and transistor M7b are ON. Also, during period T4a, Transistor M7a is ON, and transistor M7b is OFF. Also, during period T4b... Transistor M7a is off, and transistor M7b is on. Figure 8(B) In path 10, during periods T3a, T4a, T3b, and T4b, the potential V1 is It is supplied to node N1. Therefore, it becomes easier to maintain the potential of node N1 at potential V1.

[0075] In circuit 10 of Figure 9(A), compared to Figure 8(A), the gate of transistor M5 is connected to wiring 17 The connection point is different. The signal or potential of wiring 17 is the ON or ON of transistor M5. It is preferable to have a function to control the OFF state. In this embodiment, for convenience, the wiring 17 is Assume that signal CK2 is input. Signal CK2 is the inverted signal of signal CK1. There are signals with a different phase from signal CK1. For example, signal CK2 has phases T1a and T It is high in period 1b, low in periods T2a and T2b, and in period T3 Periods a and T3b are high or low levels, and periods T4a and T4b are It alternates between high and low levels.

[0076] During periods T1a and T1b, transistor M5 is turned on. Therefore, the signal SP This is supplied to node N1 via transistor M5. Since signal SP is at a high level The potential of node N1 rises. However, the potential of node N1 is equal to the gate of transistor M5. When the threshold voltage of transistor M5 is subtracted from the potential (for example, potential V2), The transistor M5 turns off. Also, during periods T2a and T2b, the transistor M5 is off. Also, during periods T3a and T3b, signal CK2 is at a high level. Therefore, transistor M5 is on. Thus, the signal SP passes through transistor M5. And it is supplied to node N1. On the other hand, if the signal CK2 is at a low level, transistor M5 It is off. Also, during periods T4a and T4b, transistor M5 is on and off. The process repeats. If transistor M5 is on, signal SP passes through transistor M5. It is supplied to node N1. In circuit 10 of Figure 9(A), during periods T4a and T4b, Then, signal SP is supplied to node N1. Since signal SP is low level, node N This makes it easier to maintain the potential at 1 at potential V1.

[0077] In circuit 10 of Figure 9(B), compared to Figure 8(A), the first terminal of transistor M5 is wired... The connection point is different from that of 18. The signal or potential of wiring 18 turns on transistor M1. It has the function of making it so. In this embodiment, for convenience, the potential V2 is supplied to the wiring 18. Let's assume that.

[0078] During periods T1a and T1b, transistor M5 is ON. Therefore, the potential V2 Because this is supplied to node N1 via transistor M5, the potential of node N1 rises. However, the potential of node N1 is less than the potential of the gate of transistor M5 (e.g., potential V2). When the threshold voltage of transistor M5 is subtracted from the threshold voltage of transistor M5, transistor M5 turns off. Furthermore, in periods T2a to T4a and T2b to T4b, the transition The M5 is off. In circuit 10 of Figure 9(B), during periods T1a and T1b, The potential V2 is supplied to node N1. Therefore, the current flowing through wiring 15 can be reduced. can.

[0079] Note that in Figure 8(B), the gate of transistor M5 is connected to wiring 17, similar to Figure 9(A). Alternatively, you can connect it, or, as in Figure 9(B), connect the first terminal of transistor M5 to wire 18. This is also possible. In particular, in Figure 8(B), the gate of transistor M5 is connected to wiring 17. Then, in periods T4a and T4b, at node N1, transistor M7a or transistor The potential V1 supplied via transistor M7b is supplied to wiring 15 via transistor M5. Therefore, it becomes easier to maintain the potential of wiring 15 at potential V1.

[0080] Note that in Figures 8(A), 8(B), and 9(B), the first terminal of transistor M5 It may also be connected to wiring 17. In this way, for example, a portion of period T1a, period T4a, period During T1b, or part of period T4b, the potential of the first terminal of transistor M5 is low. Therefore, it is possible to suppress changes in the characteristics of transistor M5.

[0081] Note that in Figures 8(A), 8(B), and 9(B), the first terminal is connected to the wiring 15. The second terminal is connected to node N1, and the gate is connected to wiring 17, and the transistor is... It may be newly added. Doing so will produce the same effect as circuit 10 in Figure 9(A). Cut.

[0082] Note that in Figures 8(A), 8(B), and 9(A), the first terminal is connected to wiring 18 or wiring It is connected to 17, the second terminal is connected to node N1, and the gate is connected to wiring 15. A transistor may be added. This would produce the same effect as circuit 10 in Figure 9(B). It is possible.

[0083] Furthermore, as shown in Figure 9(A), the first terminal of circuit 10 is connected to the wiring 15, and the second terminal is connected to the If there is a transistor connected to wire N1 and whose gate is connected to wire 17, You can omit "Zista M6".

[0084] Furthermore, in the circuit 10 described above, the first terminal of transistor M6 is connected to the wiring 11. That's good too.

[0085] In addition, in the circuit 10 described above, the first terminal of circuit 20 may be connected to wiring 12.

[0086] In the circuit 10 described above, the first terminal of transistor M6 is connected to wire 18 or wire 1 Alternatively, you may connect it to 7 and connect the second terminal of transistor M6 to node N3. Terminal 1 is connected to wire 18 or wire 17, and terminal 2 is connected to node N3, A transistor may be newly provided to which the first terminal is connected to wiring 14. Alternatively, the first terminal may be connected It is connected to wire 18 or wiring 17, the second terminal is connected to node N2a, and the gate is wiring 1 A transistor connected to 4, and the first terminal connected to wire 18 or wire 17, and the second A transistor whose terminal is connected to node N2b and whose gate is connected to wiring 14, and a new It may be provided in [location].

[0087] Next, we will describe a circuit that can be applied to circuit 20.

[0088] The circuit 20 in Figure 10(A) has transistors M8 and M9. Transistors M8 and M9 have the same polarity as transistor M1. 8 has its first terminal connected to wiring 18 and its second terminal connected to the second terminal of circuit 20. The gate is connected to wire 18. Transistor M9 has its first terminal connected to wire 13. The second terminal is connected to the second terminal of circuit 20, and the gate is connected to the first terminal of circuit 20. It continues. In periods T1a, T2a, T1b, and T2b, the transistor M8 is ON, and transistor M9 is ON. Also, period T3a, period T4a, period During interval T3b and period T4b, transistor M8 turns on and then off, The M9 is off.

[0089] The first terminal of transistor M8 may also be connected to wire 11 or wire 17. The gate of transistor M8 may be connected to wire 11 or wire 17. Both the first terminal and the gate of the M8 may be connected to the wiring 11 or the wiring 17.

[0090] The circuit 20 in Figure 10(B) has transistors M10 to M13. Transistors M10 through M13 have the same polarity as transistor M1. The Zista M10 has its first terminal connected to wiring 18, and its second terminal connected to the second terminal of circuit 20. It is connected to the first terminal of transistor M11, which is connected to the wiring 13, and the second terminal is The second terminal of circuit 20 is connected, and the gate is connected to the first terminal of circuit 20. The first terminal of transistor M12 is connected to wire 18, and the second terminal is connected to transistor M10. The gate is connected, and the gate is connected to wiring 18. Transistor M13 is connected to the first terminal The wire is connected to wiring 13, and the second terminal is connected to the gate of transistor M10, and the gate is It is connected to the first terminal of circuit 20. Periods T1a, T2a, T1b and T2 In b, transistor M10 is off and transistor M11 is on, Transistor M12 is ON, and transistor M13 is ON. Period T3a, Period T4 a. During periods T3b and T4b, transistor M10 is ON, and Transistor M11 is off, transistor M12 turns on and then off, and transistor M1 3 is off.

[0091] Note that the first terminal of transistor M10, the first terminal of transistor M12, and The gate of ZISTA M12 may be connected to wiring 11 or wiring 17. This will allow period T4 During periods a and T4b, the circuit 20 outputs a signal that alternates between high and low levels. Therefore, the characteristic changes of transistors M2a and M2b can be controlled. It can be suppressed.

[0092] The circuit 20 in Figure 10(C) consists of transistors M14 to M18 and capacitive elements. It has C. Transistors M14 to M18 have the same pole as transistor M1. It is a type of transistor. Transistor M14 has its first terminal connected to wiring 18 and its second terminal connected to the circuit It is connected to the second terminal of 20. Transistor M15 has its first terminal connected to wiring 13. The second terminal is connected to the second terminal of circuit 20, and the gate is connected to the first terminal of circuit 20. The process continues. Transistor M16 has its first terminal connected to wiring 18, and its gate is... It is connected to the gate of transistor M14. Transistor M17 has its first terminal connected to wiring 13. The second terminal is connected to the second terminal of transistor M16, and the gate is the first terminal of circuit 20. It is connected to terminal 1. Transistor M18 has its first terminal connected to wiring 13, and the second terminal The terminal is connected to the gate of transistor M14, and the gate is connected to the first terminal of circuit 20. The capacitive element C has its first electrode connected to the first terminal of the circuit 20, and its second electrode connected to It is connected to the second terminal of the transistor M16. Periods T1a, T2a, T1b and During period T2b, transistor M14 is off and transistor M15 is on. Transistor M16 is off, transistor M17 is on, transistor M18 is ON. During periods T3a, T4a, T3b, and T4b, Transistor M14 is ON, transistor M15 is OFF, and transistor M16 Transistor M17 is ON, transistor M18 is OFF, and transistor M18 is OFF. (See diagram) Circuit 20 of 10(C) performs capacitive coupling of capacitive element C during periods T3a and T3b. To turn on transistors M14 and M16, the second part of circuit 20 The rise time of the terminal potential can be shortened. Therefore, transistor M2a or Because the timing at which transistor M2b turns on can be made earlier, the signal OUT The fall-off time can be shortened.

[0093] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, etc. Cut.

[0094] (Embodiment 3) In this embodiment, a shift register circuit to which a sequential circuit according to one aspect of the present invention is applied is provided. I will explain.

[0095] Figure 11 shows the shift register circuit of this embodiment. The shift register circuit in Figure 11 is There are N (where N is a natural number greater than or equal to 3) sequential circuits 30. However, Figure 11 shows sequential circuits 3 Only 0[1] or sequential circuits 30[3] are shown.

[0096] In the shift register circuit of Figure 11, the sequential circuit of Figure 1(B) is applied as the sequential circuit 30. In sequential circuit 30[i] (where i is between 2 and N-1), the signal SOUT[ i-1] is input, signal SELa is input to wiring 16a, and signal SE is input to wiring 16b. Lb is input, the signal SOUT[i+1] is input to wire 14, and the potential V is input to wire 13. A value of 1 is input, and the signal SOUT[i] is output from wiring 12. Also, the sequence of odd-numbered stages In path 30, signal SCK1 is input to wiring 11, and in even-numbered sequential circuits 30 The signal SCK2 is input to wiring 11. Also, sequential circuit 30[1] is sequential circuit 30 Compared to [i], the difference is that the signal SSP is input to wiring 11. Also, sequential circuit 30[N], compared to the sequential circuit 30[i], sends a reset signal or signal SSP to wiring 14. The input location is different.

[0097] Signal SCK1 is the same as signal CK1, and signal SCK2 is the same as signal CK2. Furthermore, signal SSP is the start pulse of the shift register circuit, and is the same as signal SP. This is the signal for [username]. Also, signal SOUT is the same as signal OUT.

[0098] Furthermore, when applying a configuration where circuit 10 is connected to wiring 17 as shown in Figure 9(A), In the odd-numbered sequential circuit 30, the signal SCK2 is input to wiring 17, and the even-numbered sequential circuit 3 In case 0, simply input the signal SCK1 to wiring 17.

[0099] Furthermore, when applying a configuration in which wiring 18 is connected as shown in Figure 9(B) as circuit 10, In each stage of the sequential circuit 30, it is sufficient to supply potential V2 to the wiring 18.

[0100] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, etc. Cut.

[0101] (Embodiment 4) In this embodiment, a panel configuration using liquid crystal elements as display elements is shown as an example.

[0102] The panel 60 shown in Figure 12(A) comprises a pixel section 61, a scan line drive circuit 63, and a signal line drive circuit. a path 64. The pixel unit 61 includes a plurality of pixels 62 and selects the pixels 62 row by row a plurality of scanning lines G for this purpose, and a plurality of signals for supplying image signals to the selected pixels 62 lines S. Each pixel 62 is connected to at least one of the scanning lines G and at least one of the signal lines S respectively. The scanning line driving circuit 63 outputs signals to the scanning lines G The signal line driving circuit 64 outputs image signals to the signal lines S.

[0103] The scanning line driving circuit 63 includes a shift register circuit. Output signals of the shift register circuit are sequentially input to the scanning lines G. The shift register circuit of this scanning line driving circuit 63 is incorporated in the present invention a sequential circuit according to one aspect of the present invention can be applied.

[0104] Note that the type and number of wirings provided in the pixel unit 61 depend on the configuration, number and arrangement of the pixels 62 can be determined as follows. Specifically, in the case of the pixel unit 61 shown in FIG. 12(A), x columns × y rows of pixels 62 are arranged in a matrix, including signal lines S1 to Sx and scanning lines G1 to scanning lines Gy are arranged in the pixel unit 61, which is illustrated as an example.

[0105] FIG. 12(B) shows an example of the configuration of the pixel 62. The pixel 62 includes a liquid crystal element 65 and a transi stor 66 and a capacitive element 67. The liquid crystal element 65 has a first electrode (also referred to as a pixel electrode ) a second electrode (also referred to as a counter electrode), and a liquid crystal to which a voltage is applied between the first electrode and the second electrode a liquid crystal layer containing a crystal material. One of a source and a drain of the transistor 66 is connected to a signa any one of the signal lines S1 to Sx, and the other of the source and the drain is connected to a liquid crystal ele connected to the first electrode of the element 65, and a gate is connected to any one of the scanning lines G1 to Gy Transistor 66 controls the conduction or non-conductivity between the signal line S and the first electrode of the liquid crystal element 65. It has a control function. The capacitive element 67 has a first electrode connected to the first electrode of the liquid crystal element 65. The second electrode is connected to a capacitance line (not shown). The capacitance element 67 is connected to the first of the liquid crystal element 65. It has the function of maintaining the potential difference between the electrode and the capacitance line.

[0106] Furthermore, the second electrode of the liquid crystal element 65 may be common to each pixel 62. In element 62, the second electrode of the capacitive element 67 may be connected to the same capacitive wiring. The capacitance line may be supplied with the same common potential as the second electrode of the liquid crystal element 65.

[0107] Pixel 62 is a transistor, diode, resistor, capacitive element, inductor, etc. It may also have other elements.

[0108] In one aspect of the present invention, in pixel 62, liquid crystal element 65 and capacitive element 67 are stored A transistor with a small off-current is used as a switch to hold the stored charge. This is desirable. Specifically, in the case of pixel 62 shown in Figure 12(B), the off-power of transistor 66 If the current is small, it is possible to prevent charge leakage through transistor 66. This ensures that the liquid crystal element 65 and the capacitive element 67 maintain a potential corresponding to the image signal applied to them more reliably. Therefore, within one frame period, the transparency of the liquid crystal element 65 due to charge leakage... This prevents changes in the overflow rate, thereby improving the quality of the displayed image. Also, if the off-current of transistor 66 is small, charge will leak through transistor 66. This prevents that from happening, so the area of ​​the capacitive element 67 can be kept small. to increase the transmittance of the panel 60, thereby reducing the loss of light supplied from a light supply unit such as a backlight or a frontlight inside the panel 60, and reducing the power consumption of the liquid crystal display device.

[0109] In the present embodiment, a panel using a liquid crystal element as the display element has been described; however, a light-emitting element may be used as the display element. The light-emitting element includes LED (Light Emitt ing Diode) and OLED (Organic Light Emitting D iode), and the scope thereof includes elements whose luminance is controlled by current or voltage . For example, an OLED includes at least an EL layer, an anode, and a cathode. The EL layer is composed of a single layer or a plurality of layers provided between the anode and the cathode, and among these layers, at least a light-emitting layer containing a light-emitting substance is included. The EL layer is supplied with current when the potential difference between the cathode and the anode becomes equal to or higher than the threshold voltage Vth of the light-emitting element, and when the potential difference between the cathode and the anode becomes equal to or higher than the threshold voltage Vth of the light-emitting element, the supplied current enables electroluminescence to be obtained. Electroluminescence includes light emission (fluorescence) when returning from a singlet excited state to the ground state, and light emission (phosphorescence) when returning from a triplet excited state to the ground state .

[0110] By applying the sequential circuit according to one aspect of the present invention to the scanning line driving circuit 63, the fall time of the signal of the scanning line G can be shortened. Therefore, it is possible to prevent image signals corresponding to another row from being input to the pixel 62, so that more accurate image signals can be held and display quality can be improved.

[0111] Furthermore, when a sequential circuit according to one aspect of the present invention is applied to the scanning line driving circuit 63, the pixel 62 It is preferable that the transistor 66 has the same polarity as transistor M1. The transistors provided on the same board as the probe drive circuit 63 have the same polarity as transistor M1. It is preferable to have one.

[0112] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, etc. Cut.

[0113] (Embodiment 5) A semiconductor device according to one aspect of the present invention is amorphous, microcrystalline, polycrystalline, or single crystal, A transistor having a channel-forming region in a semiconductor film such as condensate or germanium is used. It's fine if it's like that, and it has a wider band gap than silicon, and the intrinsic carrier density is like silicon. A transistor with a channel formation region in a semiconductor film with a lower density may also be used.

[0114] The silicon was fabricated using vapor phase growth methods such as plasma CVD or sputtering. Amorphous silicon, and amorphous silicon, are crystallized by processes such as laser annealing. Polycrystalline silicon and single-crystal silicon wafers are subjected to hydrogen ions and other substances to exfoliate the surface layer. Crystalline silicon and other materials can be used.

[0115] Impurities such as water or hydrogen, which act as electron donors, are reduced, and oxygen is deficient. By reducing the amount of the oxide semiconductor (purified OS), the purified oxide semiconductor becomes i It is an intrinsic semiconductor (Type I) or very close to Type I. Therefore, when a highly purified oxide semiconductor film is used... Transistors with a channel formation region have significantly low off-current and high reliability.

[0116] Specifically, a transistor having a channel formation region in a highly purified oxide semiconductor film The small current can be proven through various experiments. For example, if the channel width is 1 × 1 0 6 Even with a μm element and a channel length of 10 μm, the voltage between the source electrode and the drain electrode When the drain voltage is in the range of 1V to 10V, the off-current is measured by the semiconductor parameter analyzer. Below the measurement limit of the riser, i.e., 1 × 10⁻⁶ -13 It is possible to obtain the characteristic of being A or less. In this case, the off-current normalized by the transistor's channel width is 100 Hz / It can be seen that it is less than μm. Also, by connecting the capacitive element and the transistor, the capacitive element A circuit is used to control the charge flowing in or out of a capacitive element using the transistor, to turn off Current measurements were performed. In these measurements, a highly purified oxide semiconductor film was attached to the transistor. By using this as the channel formation region, the transition is determined from the change in the amount of charge per unit time of the capacitive element. The off-current of the transistor was measured. As a result, the current between the source and drain electrodes of the transistor was measured. It was found that an even smaller off-current of several tens of yA / μm can be obtained when the voltage is 3V. Therefore, transistors using highly purified oxide semiconductor films in the channel formation region. The off-current is significantly smaller compared to transistors using crystalline silicon.

[0117] Unless otherwise specified, in this specification, off-current refers to the off-current of an n-channel transistor. In this case, with the drain at a higher potential than the source and gate, the potential of the source is based When the gate potential is 0 or less, the current flowing between the source and drain is... This means that. Alternatively, in this specification, off-current refers to a p-channel transistor. In this case, with the drain at a lower potential than the source and gate, the potential of the source is based When the gate potential is greater than or equal to zero, the current flowing between the source and drain It means that.

[0118] Next, an example of a transistor having a channel formation region in an oxide semiconductor film is shown in the diagram. See the explanation below.

[0119] Figure 13(A) shows a transistor 201 provided in the pixel and a transistor provided in the drive circuit. The cross-sectional structure of ZISTA 202 is shown as an example.

[0120] The transistor 201 shown in Figure 13(A) is provided on an insulating surface and functions as a gate. A conductive film 204, an insulating film 205 on the conductive film 204, and a conductive film on the insulating film 205. A semiconductor film 206 is provided in a position overlapping with 204, and on the semiconductor film 206, the source It also has conductive films 207 and 208 that function as drains. Also, Figure 13 In (A), an insulating film 209 and an insulating film are placed on the semiconductor film 206, conductive film 207 and conductive film 208. The edge films 210 are arranged in a sequential stacking manner. The transistor 201 is insulated from the insulating film 20 9 and insulating film 210 may be included as components. Also, insulating film 209 and insulating film An insulating film 211 is provided on 210. And insulating film 209, insulating film 210, The insulating film 211 is provided with an opening, and on the insulating film 211, A conductive film 203 is provided, connected to the conductive film 207.

[0121] Furthermore, the conductive film 203 functions as the first electrode of the display element. For example, the liquid crystal element is the first electrode It has a first electrode and a second electrode, and a liquid crystal layer to which an electric field is applied by the first electrode and the second electrode. When forming a liquid crystal element on transistor 201, in addition to the conductive film 203, a second electrode is also formed. A conductive film that functions as such and a liquid crystal layer can be provided on the insulating film 211. If it is an OLED, the conductive film 203 which functions as either the anode or cathode is added The conductive film, which functions as the other side of the anode or cathode, and the EL layer are separated by an insulating film 211. It should be placed on top.

[0122] Furthermore, by using resin for the insulating film 211, irregularities will occur on the surface of the conductive film 203. This can prevent this. In other words, it can improve the flatness of the surface on which the conductive film 203 is formed. Specifically, as the insulating film 211, acrylic resin, epoxy resin, benzocyclobutyrate Organic materials such as polyamides, polyimides, and other organic materials can be used. In addition to the material, silicone resin and the like can be used. By stacking multiple edge films, a more flat insulating film 211 can be formed.

[0123] Furthermore, the conductive film 203 is made of indium oxide, indium oxide-tin oxide (ITO:In Indium oxide containing silicon or silicon oxide Tin oxide, indium zinc oxide, tan oxide Indium oxide containing gusten and zinc oxide, and Al-Zn oxide containing nitrogen. Conductors, nitrogen-containing Zn-based oxide semiconductors, nitrogen-containing Sn-Zn-based oxide semiconductors, Gold (Au), Platinum (Pt), Nickel (Ni), Tungsten (W), Chromium (Cr), Molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu), palladium (Pd) In addition to titanium (Ti), elements belonging to Group 1 or Group 2 of the periodic table, namely lithium Alkali metals such as lithium (Li) and cesium (Cs), as well as magnesium (Mg) and calcium Alkaline earth metals such as um (Ca), strontium (Sr), and alloys containing these metals. Rare earth golds such as (MgAg, AlLi), europium (Eu), and ytterbium (Yb). Metals and alloys containing them can be used. Note that the conductive film 203 may be, for example, S After forming a conductive film using the above materials by methods such as puttering or vapor deposition, photolithography The conductive film is formed by etching it using the Fi method to create the desired shape. It is possible.

[0124] The transistor 202 shown in Figure 13(A) is provided on an insulating surface and functions as a gate. A conductive film 212, an insulating film 205 on the conductive film 212, and a conductive film on the insulating film 205. A semiconductor film 213 is provided in a position overlapping with 212, and a source is provided on the semiconductor film 213. It also has conductive films 214 and 215 that function as drains. Also, Figure 13 In (A), an insulating film 209 and an insulating film 215 are placed on the semiconductor film 213, conductive film 214 and conductive film 215. The edge films 210 are arranged to be stacked in order. Also, insulating film 209 and insulating film 210 An insulating film 211 made of resin is provided on top.

[0125] In Figure 13(A), the back gate of transistor 202 in the drive circuit is... The conductive film capable of this function is used together with the conductive film 203 which functions as an electrode for the liquid crystal element in the pixel, and is insulating It may also be formed on film 211. With the above configuration, a conductive film can be formed by etching or the like to achieve a desired result. By processing the shape, the conductive film 203 and the conductive film that functions as a back gate are formed. This can be achieved. Therefore, without increasing the manufacturing process of semiconductor devices, the back gate and A conductive film that functions in this way can be provided. The back gate was in a floating state. It is also acceptable for the potential to be supplied from another source. In the latter case, a normal gate ( The front gate and the back gate may be given the same potential, or the back gate may be given the same potential. A fixed potential, such as ground potential, may be applied only to the gate. By controlling the potential, the threshold voltage of transistor 202 can be controlled. Also, By adding a back gate, the channel formation area is increased, resulting in an increase in drain current. This is possible. Furthermore, by providing a back gate, a depletion layer is more likely to form in the semiconductor film. Therefore, it is possible to improve the S value.

[0126] In Figure 13(A), an insulating film is placed between the semiconductor film 206 and the semiconductor film 213 and the insulating film 211. The example shows the case where the edge film 209 and insulating film 210 are provided, but the semiconductor film 206 and The insulating film provided between the semiconductor film 213 and the insulating film 211 may be a single layer, or 3 Multiple layers as described above are also acceptable.

[0127] Furthermore, the insulating film 210 contains oxygen in a quantity greater than the stoichiometric composition, and when heated, the above oxygen It is desirable that the insulating film has the function of supplying a portion of it to the semiconductor film 206. The border film 210 preferably has few defects, and typically, by ESR measurement, silicon The spin density of the signal appearing at g=2.001, which originates from the dangling bond, is 1 × 10⁻⁶. 1 8 spins / cm 3 The following is preferable. However, the insulating film 210 is a semiconductor film 20 If 6 and the semiconductor film 213 are directly attached, damage will occur to the semiconductor film 206 during the formation of the insulating film 210. When given a size, as shown in Figure 13(A), the insulating film 209 is made of semiconductor film 206 and It is preferable to place it between the semiconductor film 213 and the insulating film 210. The insulating film 209 is formed when the semiconductor The damage inflicted on the body membrane 206 is less than that caused by the insulating film 210, and it also allows oxygen to permeate. It is desirable that the insulating film has the function of [doing something]. However, semiconductor film 206 and semiconductor film 2 While minimizing the damage inflicted on 13, directly on semiconductor film 206 and semiconductor film 213 If a contact insulating film 210 can be formed, then an insulating film 209 does not necessarily need to be provided. That's good too.

[0128] Furthermore, it is preferable that the insulating film 209 has few defects, and typically, ESR measurement is used to determine this. The spin density of the signal appearing at g=2.001, which originates from silicon dangling bonds, is 3 ×10 17 spins / cm 3 The following is preferable. This is included in the insulating film 209. If the defect density is high, oxygen will bond to the defect, and the oxygen in the insulating film 209 This is because the amount of light transmitted decreases.

[0129] Furthermore, it is important that there are few defects at the interface between the insulating film 209 and the semiconductor film 206 and the semiconductor film 213. Preferably, and typically, by ESR measurement with the magnetic field applied parallel to the film surface, half g = , which originates from oxygen vacancies in the oxide semiconductor used in the conductive film 206 and the semiconductor film 213. Preferably, the spin density of the signal appearing at 1.93 is 1×10 17 spins / cm 3 or less, more preferably detection is below the lower limit.

[0130] Specifically, as the insulating film 209 or the insulating film 210, a silicon oxide film or silicon oxynitride film can be used.

[0131] Next, FIG. 13B exemplarily shows a cross-sectional structure of a transistor 201, a conductive film 203 connected to the transistor 201, and a transistor 202 in a case where an insulating film 217 is provided between the insulating film 210 and the insulating film 211 in the cross-sectional structure shown in FIG. 13A. It is desirable that the insulating film 217 has a blocking effect that prevents diffusion of oxygen, hydrogen, and water. Alternatively, it is desirable that the insulating film 217 has a blocking effect that prevents diffusion of hydrogen and water.

[0132] The higher the density and denseness of an insulating film, and the fewer dangling bonds it has and the more chemically stable it is, the higher blocking effect it exhibits. Examples of insulating films exhibiting a blocking effect against oxygen, hydrogen, and water include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and the like, which can be used to form the insulating film. Examples of insulating films exhibiting a blocking effect against hydrogen and water include silicon nitride, silicon nitride oxide, and the like, which can be used.

[0133] When the insulating film 217 has a blocking effect against water, hydrogen and the like, impurities such as water and hydrogen existing in the insulating film 211 formed using resin and outside the panel can be prevented from reaching the semiconductor film 206 or the semiconductor film ​It can prevent the oxide from penetrating 213. When semiconductors are used, some of the water or hydrogen that enters the oxide semiconductor becomes an electron donor. Therefore, by using the insulating film 217 having the above blocking effect, the transient This prevents the threshold voltages of transistors 201 and 202 from shifting due to donor generation. It is possible.

[0134] When an oxide semiconductor is used for the semiconductor film 206 or semiconductor film 213, the insulating film 217 is oxygen This blocking effect prevents oxygen from diffusing from the oxide semiconductor to the outside. Therefore, the number of oxygen vacancies that act as donors in oxide semiconductors is reduced. Then, the threshold voltages of transistors 201 and 202 shift due to the generation of donors. This can prevent it from happening.

[0135] The adhesion between insulating film 217 and insulating film 211 is higher than the adhesion between insulating film 210 and insulating film 211. In this case, the peeling of the insulating film 211 can be prevented by using the insulating film 217.

[0136] Furthermore, when oxide semiconductor films are used as semiconductor films 206 and 213, The conductor preferably contains at least indium (In) or zinc (Zn). Furthermore, to reduce variations in the electrical characteristics of transistors using the oxide semiconductor. It is preferable to have gallium (Ga) in addition to those as a stabilizer. It is preferable to have tin (Sn) as a stabilizer. It is preferable to have hafnium (Hf). Also, aluminum is used as a stabilizer. It is preferable to have aluminum (Al). Also, zirconium (Zr) is preferred as a stabilizer. It is preferable that it includes ).

[0137] Among oxide semiconductors, In-Ga-Zn oxides and In-Sn-Zn oxides are carbon Unlike silicon dioxide, gallium nitride, or gallium oxide, sputtering and wet processes This makes it possible to fabricate transistors with excellent electrical characteristics, and offers superior mass-producibility. These are some of the advantages. Also, unlike silicon carbide, gallium nitride, or gallium oxide The above In-Ga-Zn oxide is used to form transistors with excellent electrical properties on a glass substrate. It is possible to manufacture these. Furthermore, it can accommodate larger substrate sizes.

[0138] Also, other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lu It may contain one or more types of tecium (Lu).

[0139] For example, as oxide semiconductors, indium oxide, gallium oxide, tin oxide, zinc oxide, I n-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, S n-Mg oxides, In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides Materials (also written as IGZO), In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides, I n-Hf-Zn oxides, In-La-Zn oxides, In-Pr-Zn oxides, In -Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In- Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-H o-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb -Zn oxides, In-Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, In- Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn In-Sn-Hf-Zn oxides and In-Hf-Al-Zn oxides are used. It is possible.

[0140] For example, an In-Ga-Zn oxide is an oxide containing In, Ga, and Zn. This is about taste, and the ratio of In, Ga, and Zn is not important. Also, metal elements other than In, Ga, and Zn are not considered. It may contain. In-Ga-Zn oxides have sufficiently high resistance in the absence of an electric field and are off-electric. It is possible to significantly reduce the flow rate, and it also has high mobility.

[0141] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxidation with atomic ratio a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Oxides with a similar composition to the substance can be used. Alternatively, In:Sn:Zn=1: 1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is advisable to use In-Sn-Zn oxides with a specific ratio or oxides with a similar composition.

[0142] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, Furthermore, even with In-Ga-Zn oxides, mobility can be increased by reducing the bulk defect density. It is possible to do so.

[0143] In one aspect of the present invention, single crystals, polycrystalline (also called polycrystals), or amorphous materials are used. Oxide semiconductor films having states such as these can be used in transistors. Preferably Oxide semiconductor films are CAAC-OS (C Axis Aligned Crystal This film is made of line oxide semiconductor material.

[0144] CAAC-OS films are neither perfectly single crystals nor perfectly amorphous. The crystalline portion contained within the OS film must be small enough to fit within a cube with sides less than 100 nm. There are many. Also, transmission electron microscopes (TEM) In the image observed using a microscope, the amorphous region contained in the CAAC-OS film and The boundary with the crystalline portion is not clear. Also, TEM revealed grain boundaries in the CAAC-OS film. Also called inboundary. ) cannot be confirmed. Therefore, the CAAC-OS film has grain boundaries. The resulting decrease in electron mobility is suppressed.

[0145] The crystalline portion contained in the CAAC-OS film has a c-axis that is the normal vector to the surface on which the CAAC-OS film is formed. Aligned in a direction parallel to the normal vector of the plane or surface, and triangular when viewed from a direction perpendicular to the ab plane. Having a shape or hexagonal atomic arrangement, the metal atoms are layered or when viewed from a direction perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. Furthermore, between different crystalline regions, the a-axis is... The orientation of the b-axis may be different. In this specification, when simply referred to as vertical, 8 The range of 5° to 95° is also included. Furthermore, when simply describing something as parallel, -5 This will include the range of 5° to 5°.

[0146] Furthermore, the distribution of crystalline regions in the CAAC-OS film does not need to be uniform. For example, CAA In the formation process of a C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the shape The proportion of crystalline material may be higher near the surface compared to near the surface of the material. Also, CA By adding impurities to the AC-OS film, the crystalline region in the impurity-added area becomes amorphous. It can also become qualitative.

[0147] The c-axis of the crystalline portion contained in the CAAC-OS film is the normal vector to the surface on which the CAAC-OS film is formed. Because it aligns in a direction parallel to the normal vector of the surface or the material, the shape of the CAAC-OS film (formed Depending on the cross-sectional shape of the surface or face, they may face in different directions. Oh, the direction of the c-axis of the crystalline portion is the normal vector to the surface on which the CAAC-OS film was formed. The direction is parallel to the normal vector of the crystalline or surface. The crystalline portion is formed by deposition, and It is formed by performing crystallization treatments such as heat treatment after film formation.

[0148] Transistors using CAAC-OS film exhibit changes in electrical characteristics due to irradiation with visible light or ultraviolet light. Dynamics can be reduced. Therefore, this transistor is highly reliable.

[0149] CAAC-OS films are used, for example, for polycrystalline oxide semiconductor sputtering targets. The film is deposited using a sputtering method. Ions are directed onto the sputtering target. Upon collision, the crystalline region contained in the sputtering target cleaves from the ab plane, and a -The sputtering particles are exfoliated as flat or pellet-shaped sputtering particles having a surface parallel to the -b surface. In this case, the flat sputtering particles maintain their crystalline state and form a base By reaching the plate, the CAAC-OS film can be deposited.

[0150] Furthermore, it is preferable to apply the following conditions for forming the CAAC-OS film.

[0151] By reducing the inclusion of impurities during film formation, it is possible to suppress the disruption of the crystalline state due to impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, and nitrogen, etc.) present in the deposition chamber. It would be good to reduce it. Also, it would be good to reduce the impurity concentration in the film formation gas. Specifically, the dew point is A film-forming gas with a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0152] Furthermore, by increasing the substrate heating temperature during film deposition, the sputtering particles can be prevented from migrating after reaching the substrate. A reaction occurs. Specifically, the substrate heating temperature is preferably between 100°C and 740°C. The film is deposited at a temperature between 200°C and 500°C. By increasing the substrate heating temperature during film deposition, the flat When plate-shaped sputtering particles reach the substrate, migration occurs on the substrate. The flat surface of the sputtered particles adheres to the substrate.

[0153] Furthermore, by increasing the oxygen content in the deposition gas and optimizing the power, plasma damage during film deposition can be reduced. It is preferable to reduce this. The oxygen content in the film-forming gas is 30% by volume or more, preferably 100% by volume. Let the product be %.

[0154] As an example of a target for sputtering, an In-Ga-Zn oxide target is used. The following is shown.

[0155] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a predetermined molar ratio and then subjected to pressure treatment. Furthermore, by heat treatment at a temperature between 1000°C and 1500°C, polycrystalline In-G is produced. The target is an α-Zn oxide. X, Y, and Z are arbitrary positive numbers. The given molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z The powder is 2 The ratios are 2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. The type of powder and the molar ratio in which they are mixed will be determined by the sputtering target being prepared. You can adjust it as needed depending on the situation.

[0156] Furthermore, semiconductor films 206 and 213 are metal oxides with different atomic ratios of metals. Multiple oxide semiconductor films formed using the target have a stacked structure. This is also good. For example, the atomic ratio of the target is In:Ga:Zn for the first layer of oxide semiconductor film. =1:1:1, the second oxide semiconductor film has an In:Ga:Zn ratio of 3:1:2, It may be formed. Also, the atomic ratio of the target is In:Ga for the first layer oxide semiconductor film. :Zn=1:3:2, the second oxide semiconductor film is In:Ga:Zn=3:1:2, the third layer The oxide semiconductor film may be formed such that In:Ga:Zn = 1:1:1.

[0157] Alternatively, semiconductor films 206 and 213 are target metal oxides containing different metals. Multiple oxide semiconductor films formed using the material may have a stacked structure.

[0158] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, etc. Cut.

[0159] (Embodiment 6) Using a liquid crystal display device as an example, Figure 14 shows the appearance of a semiconductor device according to one aspect of the present invention. Let's use this to explain. Figure 14(A) shows substrate 4001 and substrate 4006 sealed with sealing material 4005. This is a top view of the liquid crystal display device that has been bonded together. Also, Figure 14(B) is a broken version of Figure 14(A). This corresponds to a cross-sectional view along line A1-A2, and Figure 14(C) is the same as the dashed line B1-B2 in Figure 14(A). This corresponds to a cross-sectional view in [location]. Note that in Figure 14, FFS (Fringe Field S) is shown. This example shows a liquid crystal display in witching mode.

[0160] The pixel section 4002 and the pair of scan line driving circuits 4004 are surrounded on the substrate 4001. A sealing material 4005 is provided as shown. Also, a pixel section 4002 and a scanning line driving circuit 40 A substrate 4006 is provided on top of 04. Therefore, the pixel section 4002 and the scanning line driving circuit 4004 is sealed by substrate 4001, sealing material 4005, and substrate 4006. Furthermore, in a region different from the region surrounded by the sealing material 4005 on the substrate 4001, The signal line drive circuit 4003 is implemented.

[0161] Furthermore, a sequential circuit according to one aspect of the present invention can be applied to the scanning line drive circuit 4004. This allows the W / L ratio of the transistor to be reduced, thus enabling a smaller bezel. ru.

[0162] The pixel section 4002 and the scanning line driving circuit 4004, which are provided on the substrate 4001, are transistors It has multiple of these. In Figure 14(B), the transistor 4010 included in the pixel section 4002 This illustrates the transistor 4022 included in the scan line drive circuit 4004. Figure 14(C) illustrates the transistor 4010 included in the pixel section 4002.

[0163] In the pixel section 4002 and the scan line driving circuit 4004, transistor 4010 and An insulating film 4020 made of resin is provided on the ZISTA 4022. On 4020, the first electrode 4021 of the liquid crystal element 4023 and the conductive film 4024 are provided. The conductive film 4024 functions as a discharge path for the charge accumulated in the insulating film 4020. Alternatively, the conductive film 4024 and insulating film 4020 can be connected to the transistor 4022. The conductive film 4024 can also be used as a back gate component.

[0164] An insulating film 4025 is provided on the insulating film 4020, the first electrode 4021, and the conductive film 4024. It is desirable that the insulating film 4025 has a high blocking effect against water, hydrogen, etc. As the insulating film 4025, silicon nitride film, silicon nitride oxide film, etc., can be used. ru.

[0165] As shown in Figures 14(B) and 14(C), in one aspect of the present invention, the insulating film 4020 is It is removed at the edges of the panel. And the insulating film 4025 on insulating film 4020 is Between the sealing material 4005 and the substrate 4001, transistor 4010 and transistor 4 It is in contact with insulating film 4026, which functions as a gate insulating film for 022.

[0166] If the insulating film 4025 and insulating film 4026 have a high blocking effect against water, hydrogen, etc., At the edge of the panel, the insulating film 4025 and the insulating film 4026 come into contact, so that the outside of the panel From the encapsulating material 4005, water, hydrogen, etc., enter the transistor 4010 and the transistor. This prevents 4022 from penetrating the semiconductor film each of them possesses.

[0167] The second electrode 4027 of the liquid crystal element 4023 is provided on the insulating film 4025. Between the second electrode 4027 and the insulating film 4025 and the substrate 4006, there is a liquid crystal layer 4028. It is provided. The liquid crystal element 4023 consists of a first electrode 4021, a second electrode 4027, and liquid crystal. It has layer 4028.

[0168] In the liquid crystal element 4023, the value of the voltage applied between the first electrode 4021 and the second electrode 4027 Accordingly, the orientation of the liquid crystal molecules contained in the liquid crystal layer 4028 changes, and the transmittance changes. Then, the liquid crystal element 4023 is affected by the potential of the image signal applied to the first electrode 4021. By controlling the transmittance, it is possible to display gradations.

[0169] In one aspect of the present invention, the liquid crystal layer of the liquid crystal display device is, for example, a thermotropic liquid crystal. Alternatively, a liquid crystal material classified as a lyotropic liquid crystal can be used. Examples include nematic liquid crystals, smectic liquid crystals, cholesteric liquid crystals, or discs. Liquid crystal materials classified as corticocrystalline liquid crystals can be used. Alternatively, the liquid crystal layer can be, for example, Alternatively, liquid crystal materials classified as ferroelectric liquid crystals or antiferroelectric liquid crystals can be used. For example, the liquid crystal layer may contain main-chain polymer liquid crystals, side-chain polymer liquid crystals, or composite polymer liquid crystals. Liquid crystal materials classified as polymer liquid crystals, such as microcrystalline liquid crystals, or low-molecular-weight liquid crystals can be used. Alternatively, the liquid crystal layer may contain, for example, a liquid crystal material classified as polymer-dispersed liquid crystal (PDLC). It can be used.

[0170] Furthermore, a liquid crystal exhibiting a blue phase without an alignment layer may be used as the liquid crystal layer. The blue phase is the liquid crystal phase. One such example is when a cholesteric liquid crystal is heated, and it transitions from the cholesteric phase to the isotropic phase. This phase appears just before transfer. The blue phase only appears within a narrow temperature range, so Kaira The temperature range is improved by adding a curing agent or UV-curing resin. The liquid crystal exhibits a blue phase and a chiral agent. A liquid crystal composition containing these elements has a short response time of 1 msec or less and is optically isotropic, therefore orientation It is preferable because it requires no processing and has low dependence on the viewing angle.

[0171] In one aspect of the present invention, a color filter is used in a liquid crystal display device to produce color You could display an image, or sequentially light up multiple light sources that emit light of different hues. And you can display a color image.

[0172] Furthermore, the image signal from the signal line drive circuit 4003 and various control signals from the FPC 4018 and The power supply potential is transmitted through the wiring 4030 and 4031 to the scan line drive circuit 4004. or is provided to the pixel unit 4002.

[0173] In this embodiment, the liquid crystal driving method is FFS (Fringe Field Stabilization). The example given was using the (witching) mode, but the LCD driving method is TN( Twisted Nematic) mode, STN (Super Twisted Nematic) matic) mode, VA (Vertical Alignment) mode, MVA ( Multi-domain Vertical Alignment) mode, IPS ( In-Plane Switching mode, OCB (Optically Com Pensated Birefringence mode, Blue phase mode, TBA (T (Transverse Bend Alignment) mode, VA-IPS mode, E CB(Electrically Controlled Birefringence) ) Mode, FLC (Ferroelectric Liquid Crystal) Mode AFLC (AntiFerroelectric Liquid Crystal) Mode, PDLC (Polymer Dispersed Liquid Crystal) l) Mode, PNLC (Polymer Network Liquid Crystal) l) Mode, Guest Host Mode, ASV (Advanced Super View) It is also possible to apply modes and other settings.

[0174] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, etc. Cut.

[0175] (Embodiment 7) A semiconductor device according to one aspect of the present invention comprises a display device, a personal computer, and a recording medium. Image playback devices (typically DVDs: Digital Versatile Discs) To be used in a device that has a display capable of playing back recording media such as the above and displaying the images thereof. This is possible. In addition, electronic devices that can use a semiconductor device according to one aspect of the present invention And mobile phones, game consoles including portable devices, personal digital assistants, e-books, video cameras, digital cameras Still camera, goggle-type display (head-mounted display), navigation Sound systems, audio playback devices (car audio, digital audio players, etc.), Photocopiers, fax machines, printers, multifunction printers, automated teller machines (AT) Examples include vending machines. Specific examples of these electronic devices are shown in Figure 15.

[0176] Figure 15(A) shows a portable game console, comprising a casing 5001, casing 5002, display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, stand It has illustration 5008, etc. Display unit 5003 or display unit 5004, or other A semiconductor device according to one aspect of the present invention can be used in the circuit. The portable game console has two display units 5003 and 5004, but The number of display units in a game console is not limited to this.

[0177] Figure 15(B) shows a display device, which includes a housing 5201, a display unit 5202, a support base 5203, etc. The semiconductor device according to one aspect of the present invention is used in the display unit 5202 or in other circuits. It is possible to do so. Furthermore, the display devices include those for personal computers and those for receiving TV broadcasts. This includes all information display devices, such as those used for advertising.

[0178] Figure 15(C) shows a notebook personal computer, consisting of a casing 5401 and a display unit 5402. It has a keyboard 5403, a pointing device 5404, etc. Display unit 5402 Alternatively, a semiconductor device according to one aspect of the present invention can be used in other circuits.

[0179] Figure 15(D) shows a portable information terminal, consisting of a first housing 5601, a second housing 5602, and a first display unit. It includes 5603, a second display unit 5604, a connection unit 5605, an operation key 5606, etc. Table 1 The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 56 It is located at 02. And the first housing 5601 and the second housing 5602 are connected at the connection part 56 They are connected by 05, and the angle between the first housing 5601 and the second housing 5602 is the connection part It is made movable by 5605. The video switching in the first display unit 5603 is connected Switching according to the angle between the first housing 5601 and the second housing 5602 in section 5605 It is also acceptable to have a configuration that allows for this. In the first display unit 5603 or the second display unit 5604, or otherwise A semiconductor device according to one aspect of the present invention can be used in the circuit. At least one of 603 and the second display unit 5604 is provided with a function as a position input device. A semiconductor device may be used. Note that the function as a position input device is provided by the semiconductor. This can be added by installing a touch panel on the device. Alternatively, it can be used as a position input device. The function is achieved by placing a photoelectric conversion element, also called a photosensor, in the pixel portion of a semiconductor device. It can also be added.

[0180] Figure 15(E) shows a video camera, consisting of a first housing 5801, a second housing 5802, and a display unit 58 03, it has an operation key 5804, a lens 5805, a connector 5806, etc. Operation key 580 4 and lens 5805 are provided in the first housing 5801, and the display unit 5803 is in the second housing It is located in 5802. And the first housing 5801 and the second housing 5802 are connected by a connection part. They are connected by 5806, and the angle between the first housing 5801 and the second housing 5802 is, It is made movable by the connecting part 5806. The video switching in the display unit 5803 is connected Configuration performed according to the angle between the first housing 5801 and the second housing 5802 in section 5806. It is also possible to use a semiconductor according to one aspect of the present invention in the display unit 5803 or in other circuits. The device can be used.

[0181] Herein, one aspect of the present invention includes the semiconductor device described below.

[0182] One aspect of the present invention is a transistor M2a, a transistor M2b, a switch S3a, a switch This is a semiconductor device having transistor S3b, switch S4a and switch S4b. M2a has its first terminal connected to wire 13 and its second terminal connected to wire 12. The M2b has a first terminal connected to wiring 13 and a second terminal connected to wiring 12. Switch S3a has its second terminal connected to the gate of transistor M2a. Switch S3b has a first terminal connected to the first terminal of switch S3a, and a second terminal connected to a transistor. It is connected to the gate of the Zistor M2b. Switch S4a has its first terminal connected to wiring 14. The second terminal is connected to the gate of transistor M2a. Switch S4b is the first The terminal is connected to wiring 14, and the second terminal is connected to the gate of transistor M2b (Figure) 16(A)).

[0183] Note that in the above semiconductor device, switches S3a and S4b are ON, and switch S During the period Ta when switch 3b and switch S4a are off, and when switch S3a and switch S4b are off It has a period Tb during which it is off and switches S3b and S4a are on. This is also fine. Also, switches S3a, S3b, S4a and S4b are It may have periods of time off.

[0184] In the semiconductor device described above, the period Ta is when the potential of the first terminal of switch S3a is trough This is the value at which transistor M2a turns on, and the potential of wiring 14 is such that transistor M2b turns on. The period T3a is a value such that the potential of the first terminal of switch S3a is equal to the potential of transistor M2a. This is the value at which the potential of wiring 14 is the value at which transistor M2b turns off during period T4. a and may have. Also, during the period Tb, the potential of the first terminal of switch S3b is This is the value at which transistor M2b turns on, and the potential of wiring 14 turns transistor M2a on. The period T3b is such that the potential of the first terminal of switch S3b is such that transistor M2b The value at which the transistor M2a turns on is the value at which the potential of wiring 14 turns off during period T. It may have 4b and .

[0185] The semiconductor device described above may also have transistors M8 and M9. Transistor M8 has its first terminal connected to wiring 18 and its second terminal connected to switch S3a. The first terminal is connected and the gate is connected to wiring 18. Transistor M9 is the first The terminal is connected to wiring 13, and the second terminal is connected to the first terminal of switch S3a (Figure) 16(B)).

[0186] Furthermore, one aspect of the present invention relates to transistor M1, transistor M2a and transistor M2 This is a semiconductor device having b. Transistor M1 has a first terminal connected to wiring 11, The second terminal is connected to wiring 12. Transistor M2a has its first terminal connected to wiring 13. The second terminal is connected to wiring 12. Transistor M2b has the first terminal connected to wiring It is connected to 13, and the second terminal is connected to wiring 12 (see Figure 16(C)). Then, above In the semiconductor device described above, transistor M1 is ON, and transistors M2a and transistor The period during which M2b is off (period T1a, period T2a, period T1b, or period T2b), and Transistor M1 is off, and transistors M2a and M2b are on. A period (for example, period T3a or period T3b) and transistors M1 and M2b The period when is off and transistor M2a is on (e.g., period T4a), and the transition During the period when transistors M1 and M2a are off and transistor M2b is on ( For example, it has a period T4b) and

[0187] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, etc. Cut. [Explanation of Symbols]

[0188] C1 Clock signal C Capacitive element CK1 signal CK2 signal G scan line G1 scan line Gy scan lines M1 Transistor M2a Transistor M2b Transistor M3a Transistor M3b Transistor M4a transistor M4b Transistor M5 Transistor M6 Transistor M7a transistor M7b Transistor M8 Transistor M9 Transistor M10 Transistor M11 Transistor M12 Transistor M13 Transistor M14 Transistor M15 Transistor M16 Transistor M17 Transistor M18 Transistor N1 node N2a node N2b node N3 node S signal line Sx signal line S1 signal line S3a switch S3b Switch S4a Switch S4b Switch SCK1 signal SCK2 signal Ta period Tb period T1a period T1b period T2a period T2b period T3a period T3b period T4a period T4b period T13 Transistor T14 Transistor T15 Transistor V1 Potential V2 potential Vg1 scan signal VN1 potential VN2a potential VN2b potential SP signal RE signal OUT signal SELa signal SELb signal SSP signal SOUT signal 10 circuits 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16a Wiring 16b Wiring 17 Wiring 18 Wiring 20 circuits 30 sequential circuits 60 panels 61 pixel section 62 pixels 63 Scan line drive circuit 64 Signal Line Drive Circuit 65 liquid crystal buttons 66 transistors 67 Capacitive elements 201 Transistors 202 transistors 203 Conductive film 204 Conductive film 205 Insulating film 206 Semiconductor film 207 Conductive film 208 Conductive film 209 Insulating film 210 insulating film 211 Insulating film 212 Conductive film 213 Semiconductor film 214 Conductive film 215 Conductive film 217 Insulating film 4001 circuit board 4002 pixel section 4003 Signal Line Drive Circuit 4004 Scan Line Drive Circuit 4005 Sealing material 4006 circuit board 4010 Transistor 4018 FPC 4020 Insulating film 4021 Electrode 4022 Transistor 4023 Liquid crystal element 4024 Conductive film 4025 Insulating film 4026 Insulating film 4027 Electrode 4028 Liquid Crystal Layer 4030 Wiring 5001 enclosure 5002 enclosure 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation Keys 5008 Stylus 5201 enclosure 5202 Display section 5203 Support stand 5401 enclosure 5402 Display section 5403 Keyboard 5404 Pointing device 5601 enclosure 5602 enclosure 5603 Display section 5604 Display section 5605 Connection part 5606 Operation Keys 5801 enclosure 5802 enclosure 5803 Display section 5804 Operation Keys 5805 Lens 5806 Connection part

Claims

1. It has first to fifth transistors, The source and drain of the first transistor are always in electrical contact with the source and drain of the third transistor. The source and drain of the first transistor are always in electrical contact with one of the source and drain of the second transistor. The gate of the first transistor is always in contact with the first signal line. The source and drain of the second transistor are always in electrical contact with the first wiring. The gate of the second transistor is always in contact with the second signal line. The source and drain of the third transistor are always in electrical contact with one of the source and drain of the fourth transistor. The gate of the third transistor is always in conductivity with the second signal line. The source and drain of the fourth transistor are always in electrical contact with the first wiring. The gate of the fourth transistor is always in contact with the first signal line. The source and drain of the fifth transistor are always in electrical contact with the second wiring. The gate of the fifth transistor is always in electrical contact with the second wiring. A semiconductor device in which the fifth transistor is turned on when the second wiring is conductive to at least one of the source and drain of the first transistor via the channel forming region of the fifth transistor.

2. It has first to fifth transistors, The source and drain of the first transistor are always in electrical contact with the source and drain of the third transistor. The source and drain of the first transistor are always in electrical contact with one of the source and drain of the second transistor. The gate of the first transistor is always in contact with the first signal line. The source and drain of the second transistor are always in electrical contact with the first wiring. The gate of the second transistor is always in contact with the second signal line. The source and drain of the third transistor are always in electrical contact with one of the source and drain of the fourth transistor. The gate of the third transistor is always in conductivity with the second signal line. The source and drain of the fourth transistor are always in electrical contact with the first wiring. The gate of the fourth transistor is always in contact with the first signal line. The source and drain of the fifth transistor are always in electrical contact with the source and drain of the first transistor. The gate of the fifth transistor is always in electrical contact with the second wiring. A semiconductor device in which the fifth transistor is turned on when the second wiring is conductive to at least one of the source and drain of the first transistor via the channel forming region of the fifth transistor.

3. It has a gate driver and a pixel, The gate driver has first to fifth transistors, The source and drain of the first transistor are always in electrical contact with the source and drain of the third transistor. The source and drain of the first transistor are always in electrical contact with one of the source and drain of the second transistor. The gate of the first transistor is always in contact with the first signal line. The source and drain of the second transistor are always in electrical contact with the first wiring. The gate of the second transistor is always in contact with the second signal line. The source and drain of the third transistor are always in electrical contact with one of the source and drain of the fourth transistor. The gate of the third transistor is always in conductivity with the second signal line. The source and drain of the fourth transistor are always in electrical contact with the first wiring. The gate of the fourth transistor is always in contact with the first signal line. The source and drain of the fifth transistor are always in electrical contact with the second wiring. The gate of the fifth transistor is always in electrical contact with the second wiring. When the second wiring is in a conductive state with at least one of the source and drain of the first transistor via the channel forming region of the fifth transistor, the fifth transistor is on. The device comprises an insulating layer located above at least one of the first to fifth transistors, and a conductive layer having a region located above the insulating layer. A display device in which the insulating layer is made of resin, and the conductive layer is in contact with the upper surface of the insulating layer.

4. It has a gate driver and a pixel, The gate driver has first to fifth transistors, The source and drain of the first transistor are always in electrical contact with the source and drain of the third transistor. The source and drain of the first transistor are always in electrical contact with one of the source and drain of the second transistor. The gate of the first transistor is always in contact with the first signal line. The source and drain of the second transistor are always in electrical contact with the first wiring. The gate of the second transistor is always in contact with the second signal line. The source and drain of the third transistor are always in electrical contact with one of the source and drain of the fourth transistor. The gate of the third transistor is always in conductivity with the second signal line. The source and drain of the fourth transistor are always in electrical contact with the first wiring. The gate of the fourth transistor is always in contact with the first signal line. The source and drain of the fifth transistor are always in electrical contact with the source and drain of the first transistor. The gate of the fifth transistor is always in electrical contact with the second wiring. When the second wiring is in a conductive state with at least one of the source and drain of the first transistor via the channel forming region of the fifth transistor, the fifth transistor is on. The device comprises an insulating layer located above at least one of the first to fifth transistors, and a conductive layer having a region located above the insulating layer. A display device in which the insulating layer is made of resin, and the conductive layer is in contact with the upper surface of the insulating layer.

5. It has first to fifth transistors, The source and drain of the first transistor are always in electrical contact with the source and drain of the third transistor. The source and drain of the first transistor are always in electrical contact with one of the source and drain of the second transistor. The gate of the first transistor is always in contact with the first signal line. The source and drain of the second transistor are always in electrical contact with the first wiring. The gate of the second transistor is always in contact with the second signal line. The source and drain of the third transistor are always in electrical contact with one of the source and drain of the fourth transistor. The gate of the third transistor is always in conductivity with the second signal line. The source and drain of the fourth transistor are always in electrical contact with the first wiring. The gate of the fourth transistor is always in contact with the first signal line. The source and drain of the fifth transistor are always in electrical contact with the second wiring. The gate of the fifth transistor is always in electrical contact with the second wiring. When the second wiring is in a conductive state with at least one of the source and drain of the first transistor via the channel forming region of the fifth transistor, the fifth transistor is on. At least one of the first to fifth transistors is a semiconductor device having an oxide semiconductor in its channel formation region.

6. It has first to fifth transistors, The source and drain of the first transistor are always in electrical contact with the source and drain of the third transistor. The source and drain of the first transistor are always in electrical contact with one of the source and drain of the second transistor. The gate of the first transistor is always in contact with the first signal line. The source and drain of the second transistor are always in electrical contact with the first wiring. The gate of the second transistor is always in contact with the second signal line. The source and drain of the third transistor are always in electrical contact with one of the source and drain of the fourth transistor. The gate of the third transistor is always in conductivity with the second signal line. The source and drain of the fourth transistor are always in electrical contact with the first wiring. The gate of the fourth transistor is always in contact with the first signal line. The source and drain of the fifth transistor are always in electrical contact with the source and drain of the first transistor. The gate of the fifth transistor is always in electrical contact with the second wiring. When the second wiring is in a conductive state with at least one of the source and drain of the first transistor via the channel forming region of the fifth transistor, the fifth transistor is on. At least one of the first to fifth transistors is a semiconductor device having an oxide semiconductor in its channel formation region.

7. It has a gate driver and a pixel, The gate driver has first to fifth transistors, The source and drain of the first transistor are always in electrical contact with the source and drain of the third transistor. The source and drain of the first transistor are always in electrical contact with one of the source and drain of the second transistor. The gate of the first transistor is always in contact with the first signal line. The source and drain of the second transistor are always in electrical contact with the first wiring. The gate of the second transistor is always in contact with the second signal line. The source and drain of the third transistor are always in electrical contact with one of the source and drain of the fourth transistor. The gate of the third transistor is always in conductivity with the second signal line. The source and drain of the fourth transistor are always in electrical contact with the first wiring. The gate of the fourth transistor is always in contact with the first signal line. The source and drain of the fifth transistor are always in electrical contact with the second wiring. The gate of the fifth transistor is always in electrical contact with the second wiring. When the second wiring is in a conductive state with at least one of the source and drain of the first transistor via the channel forming region of the fifth transistor, the fifth transistor is on. At least one of the first to fifth transistors has an oxide semiconductor in its channel formation region. The device comprises an insulating layer located above at least one of the first to fifth transistors, and a conductive layer having a region located above the insulating layer. A display device in which the insulating layer is made of resin, and the conductive layer is in contact with the upper surface of the insulating layer.

8. It has a gate driver and a pixel, The gate driver has first to fifth transistors, The source and drain of the first transistor are always in electrical contact with the source and drain of the third transistor. The source and drain of the first transistor are always in electrical contact with one of the source and drain of the second transistor. The gate of the first transistor is always in contact with the first signal line. The source and drain of the second transistor are always in electrical contact with the first wiring. The gate of the second transistor is always in contact with the second signal line. The source and drain of the third transistor are always in electrical contact with one of the source and drain of the fourth transistor. The gate of the third transistor is always in conductivity with the second signal line. The source and drain of the fourth transistor are always in electrical contact with the first wiring. The gate of the fourth transistor is always in contact with the first signal line. The source and drain of the fifth transistor are always in electrical contact with the source and drain of the first transistor. The gate of the fifth transistor is always in electrical contact with the second wiring. When the second wiring is in a conductive state with at least one of the source and drain of the first transistor via the channel forming region of the fifth transistor, the fifth transistor is on. At least one of the first to fifth transistors has an oxide semiconductor in its channel formation region. The device comprises an insulating layer located above at least one of the first to fifth transistors, and a conductive layer having a region located above the insulating layer. A display device in which the insulating layer is made of resin, and the conductive layer is in contact with the upper surface of the insulating layer.

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