Semiconductor equipment
Patent Information
- Application Number
- JP2022154412
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-06-15
- Filing Date
- 2022-09-28
- Publication Date
- 2026-09-30
AI Technical Summary
【0008】 本開示の半導体装置によれば、回路基板への実装面積を削減することが可能となる。
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Figure 2026153013000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device.
Background Art
[0002] Conventionally, there has been known a semiconductor device in which a semiconductor element such as a diode or a transistor is covered with a resin package (for example, Patent Document 1). The semiconductor device described in Patent Document 1 includes a semiconductor element, a lead frame, and a resin package. The lead frame includes a plurality of leads, and one of the plurality of leads includes a die bonding pad. The semiconductor element is mounted on the die bonding pad. The resin package covers the semiconductor element and partially covers each of the plurality of leads. A portion of each lead exposed from the resin package serves as a terminal of the semiconductor device.
[0003] Such a semiconductor device is mounted on a circuit board of, for example, an electronic device, and used in a power supply circuit. The power supply circuit includes DC-DC converters such as a half-bridge circuit and a chopper circuit. When the semiconductor device described in Patent Document 1 is used for, for example, a half-bridge circuit, two semiconductor devices are mounted on the circuit board.
Prior Art Literature
Patent Literature
[0004]
Patent Document 1
Summary of Invention
Problem to be Solved by the Invention
[0005] In recent years, along with the miniaturization of electronic devices, miniaturization of circuit boards mounted on electronic devices has been demanded. However, as described above, in a configuration where two semiconductor devices are mounted on a circuit board, the mounting area on the circuit board increases, so it is not easy to achieve miniaturization of the circuit board.
[0006] This disclosure was conceived in view of the above circumstances, and its purpose is to provide a semiconductor device that can reduce the mounting area on a circuit board. [Means for solving the problem]
[0007] The semiconductor device provided by this disclosure includes: a first semiconductor element having a first main surface facing one direction in the thickness direction and a first main surface electrode disposed on the first main surface; a second semiconductor element having a second main surface facing the same direction as the first main surface and a second main surface electrode disposed on the second main surface; a first die pad on which the first semiconductor element is mounted; a second die pad disposed on one side of the first die pad in a first direction perpendicular to the thickness direction and on which the second semiconductor element is mounted; a first terminal lead spaced apart from the first die pad and the second die pad; a first conductive member electrically connecting the first main surface electrode and the second die pad; a second conductive member electrically connecting the second main surface electrode and the first terminal lead; and a sealing resin covering the first semiconductor element and the second semiconductor element. [Effects of the Invention]
[0008] The semiconductor device described herein makes it possible to reduce the mounting area on a circuit board. [Brief explanation of the drawing]
[0009] [Figure 1] Figure 1 is a perspective view showing a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a plan view showing a semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a plan view of Figure 2, with the sealing resin indicated by dashed lines. [Figure 4] Figure 4 is a magnified view of a portion of Figure 3. [Figure 5] Figure 5 is a bottom view showing a semiconductor device according to the first embodiment. [Figure 6]FIG. 6 is a front view showing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a right side view showing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a partially enlarged view obtained by enlarging a part of FIG. 7, in which the sealing resin is shown by imaginary lines. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 3. [Figure 10] FIG. 10 is a cross-sectional view taken along line X-X in FIG. 3. [Figure 11] FIG. 11 is a partially enlarged view obtained by enlarging a part of FIG. 9. [Figure 12] FIG. 12 is a partially enlarged view obtained by enlarging a part of FIG. 9. [Figure 13] FIG. 13 is a partially enlarged view obtained by enlarging a part of FIG. 9. [Figure 14] FIG. 14 is a partially enlarged view obtained by enlarging a part of FIG. 10. [Figure 15] FIG. 15 is a partially enlarged view obtained by enlarging a part of FIG. 3. [Figure 16] FIG. 16 is a partially enlarged view obtained by enlarging a part of FIG. 3. [Figure 17] FIG. 17 is a partially enlarged view obtained by enlarging a part of FIG. 3. [Figure 18] FIG. 18 is a partially enlarged view obtained by enlarging a part of FIG. 3. [Figure 19] FIG. 19 is a diagram showing an example of a circuit configuration of the semiconductor device according to the first embodiment. [Figure 20] FIG. 20 is a plan view showing the semiconductor device according to a first modification of the first embodiment, in which the sealing resin is shown by imaginary lines. [Figure 21] FIG. 21 is a diagram showing an example of a circuit configuration of the semiconductor device according to the first modification of the first embodiment. [Figure 22] FIG. 22 is a plan view showing the semiconductor device according to a second modification of the first embodiment, in which the sealing resin is shown by imaginary lines. [Figure 23]FIG. 23 is a diagram showing an example circuit configuration of a semiconductor device according to a second modification of the first embodiment. [Figure 24] FIG. 24 is a plan view showing a semiconductor device according to a third modification of the first embodiment, where the sealing resin is indicated by an imaginary line. [Figure 25] FIG. 25 is a diagram showing an example circuit configuration of a semiconductor device according to a third modification of the first embodiment. [Figure 26] FIG. 26 is a plan view showing a semiconductor device according to a second embodiment, where the sealing resin is indicated by an imaginary line. [Figure 27] FIG. 27 is a plan view showing a semiconductor device according to a first modification of the second embodiment, where the sealing resin is indicated by an imaginary line. [Figure 28] FIG. 28 is a plan view showing a semiconductor device according to a third embodiment, where the sealing resin is indicated by an imaginary line. [Figure 29] FIG. 29 is a plan view showing a semiconductor device according to a fourth embodiment, where the sealing resin is indicated by an imaginary line. [Figure 30] FIG. 30 is a cross-sectional view taken along line XXX-XXX in FIG. 29, and corresponds to the cross-section of FIG. 9. [Figure 31] FIG. 31 is a cross-sectional view showing a semiconductor device according to a first modification of the fourth embodiment, and corresponds to the cross-section of FIG. 30. [Figure 32] FIG. 32 is a cross-sectional view showing a semiconductor device according to a second modification of the fourth embodiment, and corresponds to the cross-section of FIG. 30. MODE FOR CARRYING OUT THE INVENTION
[0010] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, the same or similar components are denoted by the same reference numerals, and duplicate descriptions are omitted. The terms "first", "second", "third", and the like in the present disclosure are merely used as labels, and are not necessarily intended to impose an order on their objects.
[0011] In this disclosure, "object A is formed on object B" and "object A is formed on object B" include, unless otherwise specified, "object A is directly formed on object B" and "object A is formed on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" and "object A is located on object B" include, unless otherwise specified, "object A is directly located on object B" and "object A is located on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" includes, unless otherwise specified, "object A is located on object B in contact with object B" and "object A is located on object B with another object interposed between object A and object B." Furthermore, "object A overlaps with object B when viewed from a certain direction" includes, unless otherwise specified, "object A overlaps with all of object B" and "object A overlaps with a part of object B." Also, "object A (or its material) contains material C" includes "object A (or its material) consists of material C" and "the main component of object A (or its material) is material C."
[0012] Figures 1 to 19 show a semiconductor device A10 according to the first embodiment. The semiconductor device A10 comprises a first die pad 10A, a second die pad 10B, a plurality of terminal leads 13, a first semiconductor element 21, a second semiconductor element 22, a first conductive member 31, a second conductive member 32, a pair of first connecting members 41A, 41B, a pair of second connecting members 42A, 42B, and a sealing resin 50. The plurality of terminal leads 13 include a first terminal lead 14, a second terminal lead 15, a third terminal lead 16, a fourth terminal lead 171, a fifth terminal lead 172, a sixth terminal lead 181, and a seventh terminal lead 182.
[0013] For the sake of explanation, the thickness direction of semiconductor device A10 is referred to as the "thickness direction z". In the following explanation, one direction in the thickness direction z may be referred to as "up" and the other as "down". Note that terms such as "up", "down", "upper direction", "downward", "upper surface", and "lower surface" indicate the relative positional relationship of each component in the thickness direction z, and do not necessarily define a relationship with the direction of gravity. Also, "planar view" refers to the view in the thickness direction z. The direction perpendicular to the thickness direction z is called the "first direction x". The direction perpendicular to both the thickness direction z and the first direction x is called the "second direction y".
[0014] The semiconductor device A10 converts the DC power supply voltage applied to the first terminal lead 14 and the second terminal lead 15 of the multiple terminal leads 13 into an AC voltage using the first semiconductor element 21 and the second semiconductor element 22. The converted AC voltage is input to a power supply target such as a motor through the third terminal lead 16 of the multiple terminal leads 13. The semiconductor device A10 is used in power conversion circuits such as inverters.
[0015] The first die pad 10A and the second die pad 10B are positioned apart from each other in a first direction x, as shown in Figures 3 and 9. The first die pad 10A, together with the second die pad 10B and the multiple terminal leads 13, is made from the same lead frame. This lead frame is made of copper (Cu) or a copper alloy. Therefore, the composition of the first die pad 10A, the second die pad 10B, and the multiple terminal leads 13 includes copper. Each of the first die pad 10A and the second die pad 10B is rectangular in shape, for example, in a plan view.
[0016] The first die pad 10A and the second die pad 10B each have a main surface 101 and a back surface 102. Unless otherwise specified, the main surface 101 and the back surface 102 described below are common to both the first die pad 10A and the second die pad 10B. The main surface 101 faces in the thickness direction z (upward). The main surface 101 is covered with sealing resin 50. The first semiconductor element 21 is mounted on the main surface 101 of the first die pad 10A. The back surface 102 of the first die pad 10A faces in the thickness direction z away from the side on which the first semiconductor element 21 is located. The second semiconductor element 22 is mounted on the main surface 101 of the second die pad 10B. The back surface 102 of the second die pad 10B faces in the thickness direction z away from the side on which the second semiconductor element 22 is located. The back surface 102 is exposed from the sealing resin 50. The back surface 102 is, for example, plated with tin (Sn).
[0017] As shown in Figures 3 and 8 to 10, the sealing resin 50 covers the first semiconductor element 21, the second semiconductor element 22, the first conductive member 31, the second conductive member 32, and at least a portion of each of the first die pad 10A and the second die pad 10B. Furthermore, the sealing resin 50 covers a portion of each of the plurality of terminal leads 13. The sealing resin 50 is electrically insulating. The sealing resin 50 includes, for example, a black epoxy resin. As shown in Figure 2, the dimension L1 of the sealing resin 50 in the first direction x is longer than the dimension L2 of the sealing resin 50 in the second direction y. The sealing resin 50 has a resin main surface 51, a resin back surface 52, a pair of first side surfaces 53, a second side surface 54, a third side surface 55, a plurality of recesses 56, grooves 57, and a plurality of recesses 581, 582.
[0018] As shown in Figure 9, the resin main surface 51 faces the same side as the main surfaces 101 of the first die pad 10A and the second die pad 10B in the thickness direction z. As shown in Figures 9 and 10, the resin back surface 52 faces the opposite side from the resin main surface 51 in the thickness direction z. As shown in Figure 5, the back surfaces 102 of the first die pad 10A and the second die pad 10B are exposed from the resin back surface 52.
[0019] As shown in Figures 2, 5, and 6, the pair of first sides 53 are positioned apart from each other in a first direction x. The pair of first sides 53 face the first direction x and extend in a second direction y. The pair of first sides 53 connect to the resin main surface 51 and the resin back surface 52.
[0020] As shown in Figures 2, 5, and 7, the second side surface 54 and the third side surface 55 are located apart from each other in the second direction y. The second side surface 54 and the third side surface 55 face opposite each other in the second direction y and extend in the first direction x. The second side surface 54 and the third side surface 55 connect to the resin main surface 51 and the resin back surface 52. As shown in Figure 6, multiple terminal leads 13 are exposed from the third side surface 55.
[0021] As shown in Figures 2, 5, and 6, the multiple recesses 56 are recessed from the third side surface 55 in the second direction y, and extend from the main resin surface 51 to the back surface 52 of the resin in the thickness direction z. In the first direction x, the multiple recesses 56 are individually located between the seventh terminal lead 182 and the third terminal lead 16, between the third terminal lead 16 and the first terminal lead 14, between the first terminal lead 14 and the second terminal lead 15, and between the second terminal lead 15 and the sixth terminal lead 181.
[0022] As shown in Figures 5, 6, 9, and 10, the groove 57 is recessed in the thickness direction z from the resin back surface 52 and extends along the second direction y. Both sides of the groove 57 in the second direction y connect to the second side surface 54 and the third side surface 55. Viewed along the thickness direction z, the groove 57 separates the back surface 102 of the first die pad 10A from the back surface 102 of the second die pad 10B.
[0023] As shown in Figures 6, 7, 9, and 10, each of the plurality of recesses 581, 582 is recessed in the thickness direction z from the resin main surface 51. The plan view shape of each of the plurality of recesses 581, 582 is not particularly limited, but in the illustrated example it is circular. Each of the plurality of recesses 581 overlaps the first die pad 10A in plan view. In the illustrated example, the plurality of recesses 581 are individually located near the four corners of the first die pad 10A in plan view. Each of the plurality of recesses 582 overlaps the second die pad 10B in plan view. In the illustrated example, the plurality of recesses 582 are individually located near the four corners of the second die pad 10B in plan view. Each of the plurality of recesses 581, 582 does not overlap either the first conductive member 31 or the second conductive member 32 in plan view. Furthermore, in a plan view, each of the multiple recesses 581, 582 does not overlap with either the pair of first connecting members 41A, 41B or the pair of second connecting members 42A, 42B. The multiple recesses 581 are formed by pins used to fix the first die pad 10A during the manufacturing of the semiconductor device A10. These pins are pressed against the first die pad 10A before the sealing resin 50 is formed, thereby fixing the first die pad 10A. In this state, the formation of the sealing resin 50 begins. The pins are then withdrawn before the formation of the sealing resin 50 is completed. As a result, the sealing resin 50 is formed in at least a portion of the area where the pins were located, so that the main surface 101 of the first die pad 10A is covered with the sealing resin 50. The multiple recesses 581 are marks formed by this molding process of the sealing resin 50. Similarly, the multiple recesses 582 are formed by pins used to fix the second die pad 10B during the manufacturing of the semiconductor device A10. The multiple recesses 582 are marks formed by the molding process of the sealing resin 50.
[0024] As shown in Figures 1, 2, and 5, the sealing resin 50 also has a plurality of marks 589. The plurality of marks 589 are, for example, marks left by ejector pins used to remove the sealing resin 50 from the mold during its formation. Each of the plurality of marks 589 is indented from either the main surface 51 of the resin or the back surface 52 of the resin. Note that none of the plurality of marks 589 are formed on the sealing resin 50. Also, as shown in Figure 5, the back surface 102 of the first die pad 10A and the back surface 102 of the second die pad 10B each have marks 109. The marks 109 formed on the first die pad 10A and the marks 109 formed on the second die pad 10B are, respectively, marks left by the ejector pins mentioned above. The trace 109 formed on the first die pad 10A is recessed from the back surface 102 of the first die pad 10A, and the trace 109 formed on the second die pad 10B is recessed from the back surface 102 of the second die pad 10B. Note that trace 109 may not be formed on either the first die pad 10A or the second die pad 10B. The depths of each of the multiple traces 589 and the multiple traces 109 are, for example, smaller than the depths of each of the multiple recesses 581, but may also be larger or the same.
[0025] As shown in Figures 3 and 5, the first die pad 10A and the second die pad 10B have a first end face 111, a second end face 112, a third end face 113, and a fourth end face 114. The first end face 111, the second end face 112, the third end face 113, and the fourth end face 114 are covered with a sealing resin 50. The first end face 111 faces in a first direction x and extends in a second direction y. The first end face 111 is closest to a pair of first side surfaces 53 of the sealing resin 50. The second end face 112 faces in a second direction y and extends in a first direction x. The second end face 112 is closest to a second side surface 54 of the sealing resin 50. The third end face 113 faces away from the second end face 112 in the second direction y and extends in a first direction x. The third end face 113 is located closest to the third side surface 55 of the sealing resin 50. The fourth end face 114 faces away from the first end face 111 in the first direction x and extends in the second direction y. As shown in Figure 9, a groove 57 is located between the fourth end face 114 of the first die pad 10A and the fourth end face 114 of the second die pad 10B.
[0026] As shown in Figures 5 and 8, the distance P2 between the third end face 113 and the third side surface 55 is longer than the distance P1 between the second end face 112 and the second side surface 54.
[0027] As shown in Figures 3, 5, and 8, the first die pad 10A and the second die pad 10B have a first corner end face 121. The first corner end face 121 is located between the first end face 111 and the second end face 112, and is located at the corner of either the first die pad 10A or the second die pad 10B. The first corner end face 121 is covered with sealing resin 50 and is a plane inclined with respect to the first end face 111 and the second end face 112. The first inclination angle α1 of the first corner end face 121 with respect to the first end face 111 and the second inclination angle α2 of the first corner end face 121 with respect to the second end face 112, as shown in Figure 15, are 60° or more and 85° or less. One of the multiple recesses 581 is located near the first corner end face 121 of the first die pad 10A in a plan view, and one of the multiple recesses 582 is located near the first corner end face 121 of the second die pad 10B in a plan view.
[0028] Furthermore, as shown in Figure 15, the longest normal Nmax of the first corner end face 121 is set. The longest normal Nmax is the maximum value of the normal of the first corner end face 121 from either the first corner end face 121 of the first die pad 10A or the second die pad 10B to the first side surface 53 of the pair of first side surfaces 53 of the sealing resin 50 that is closest to the first corner end face 121. The longest normal Nmax is 1.0 to 1.5 times the length of the intersection line C (see Figure 15) between the virtual plane with the first direction x and the second direction y as in-plane directions and the first corner end face 121.
[0029] As shown in Figures 3, 5, and 8, the first die pad 10A and the second die pad 10B have a second corner end face 122. The second corner end face 122 is located between the first end face 111 and the third end face 113, and is located at the corner of either the first die pad 10A or the second die pad 10B. The second corner end face 122 is covered with sealing resin 50 and is a plane inclined with respect to the first end face 111 and the third end face 113. The third inclination angle α3 of the second corner end face 122 with respect to the first end face 111, as shown in Figure 16, and the fourth inclination angle α4 of the second corner end face 122 with respect to the third end face 113 are either 60° or more and 85° or less. One of the multiple recesses 581 is located near the second corner end face 122 of the first die pad 10A in a plan view, and one of the multiple recesses 582 is located near the second corner end face 122 of the second die pad 10B in a plan view.
[0030] As shown in Figures 3 and 5, the first die pad 10A and the second die pad 10B have a third corner end face 123. The third corner end face 123 is located between the second end face 112 and the fourth end face 114, and is located at the corner of either the first die pad 10A or the second die pad 10B. The third corner end face 123 is covered with sealing resin 50 and is a plane inclined with respect to the second end face 112 and the fourth end face 114. The fifth inclination angle α5 of the third corner end face 123 with respect to the fourth end face 114, as shown in Figure 17, and the sixth inclination angle α6 of the third corner end face 123 with respect to the second end face 112 are either 60° or more and 85° or less. One of the multiple recesses 581 is located near the third corner end face 123 of the first die pad 10A in a plan view, and one of the multiple recesses 582 is located near the third corner end face 123 of the second die pad 10B in a plan view.
[0031] As shown in Figures 3 and 5, the first die pad 10A and the second die pad 10B have a fourth corner end face 124. The fourth corner end face 124 is located between the third end face 113 and the fourth end face 114, and is located at the corner of either the first die pad 10A or the second die pad 10B. The fourth corner end face 124 is covered with sealing resin 50 and is a plane inclined with respect to the third end face 113 and the fourth end face 114. The seventh inclination angle α7 of the fourth corner end face 124 with respect to the fourth end face 114, as shown in Figure 18, and the eighth inclination angle α8 of the fourth corner end face 124 with respect to the third end face 113 are both 60° or more and 85° or less. One of the multiple recesses 581 is located near the fourth corner end face 124 of the first die pad 10A in a plan view, and one of the multiple recesses 582 is located near the fourth corner end face 124 of the second die pad 10B in a plan view.
[0032] As shown in Figure 13, the second die pad 10B has a first seating surface 103 and a first upright surface 104. The first seating surface 103 faces the same side as the main surface 101 in the thickness direction z and is located between the main surface 101 and the back surface 102 in the thickness direction z. The first seating surface 103 connects to the fourth end surface 114. The first upright surface 104 faces a direction perpendicular to the thickness direction z and connects to the first seating surface 103 and the main surface 101. The first seating surface 103 and the first upright surface 104 form a step in the second die pad 10B.
[0033] Each of the first semiconductor element 21 and the second semiconductor element 22 is, for example, a transistor. As shown in Figure 19, the transistor in the semiconductor device A10 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), but other types such as bipolar transistors and IGBTs (Insulated Gate Bipolar Transistors) may also be used. In the circuit of Figure 19, the parasitic diode components built into each of the first semiconductor element 21 and the second semiconductor element 22 are also shown. Each of the first semiconductor element 21 and the second semiconductor element 22 is, for example, an n-channel type, but may also be a p-channel type. Each of the first semiconductor element 21 and the second semiconductor element 22 includes a compound semiconductor substrate. The composition of the compound semiconductor substrate includes silicon (Si) or silicon carbide (SiC).
[0034] The first semiconductor element 21 is mounted on the first die pad 10A, as shown in Figures 3 and 9. Preferably, in a plan view, the center of gravity of the first semiconductor element 21 coincides with the center of the first die pad 10A. The center of the first die pad 10A is the region that corresponds to the center when the first die pad 10A is divided into Nx (where Nx is a positive odd number) sections in the first direction x, and also the center when the first die pad 10A is divided into Ny (where Ny is a positive odd number) sections in the second direction y. Nx and Ny are not limited in any way, but for example, they are 3 or 5.
[0035] The first semiconductor element 21 has a first main surface 21a and a first back surface 21b. The first main surface 21a and the first back surface 21b are spaced apart from each other in the thickness direction z. The first main surface 21a faces the same direction as the main surface 101 of the first die pad 10A. The first back surface 21b faces the opposite direction from the first main surface 21a in the thickness direction z and faces the main surface 101 of the first die pad 10A.
[0036] As shown in Figures 3 and 9, the first semiconductor element 21 is mounted on the first die pad 10A. As shown in Figure 11, the first semiconductor element 21 has a first main surface electrode 211, a main surface electrode 212, and a back surface electrode 213.
[0037] The first main surface electrode 211 is positioned on the first main surface 21a. A current corresponding to the power converted by the first semiconductor element 21 flows through the first main surface electrode 211. In the example where the first semiconductor element 21 is a MOSFET, the first main surface electrode 211 is, for example, a source electrode. The first main surface electrode 211 includes a plurality of metal plating layers. The first main surface electrode 211 includes a nickel (Ni) plating layer and a gold (Au) plating layer laminated on the nickel plating layer. Alternatively, the first main surface electrode 211 may include a nickel plating layer, a palladium (Pd) plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer.
[0038] The main surface electrode 212 is positioned on the first main surface 21a. A first drive signal (gate voltage) for driving the first semiconductor element 21 is applied to the main surface electrode 212. In the example where the first semiconductor element 21 is a MOSEFT, the main surface electrode 212 is, for example, a gate electrode. In a plan view, the area of the main surface electrode 212 is smaller than the area of the first main surface electrode 211.
[0039] The back electrode 213 is positioned on the first back surface 21b. The back electrode 213 is provided facing the main surface 101 of the first die pad 10A. A current corresponding to the power before it is converted by the first semiconductor element 21 flows through the back electrode 213. In the example where the first semiconductor element 21 is a MOSFET, the back electrode 213 is, for example, a drain electrode.
[0040] The second semiconductor element 22 is mounted on the main surface 101 of the second die pad 10B. Preferably, in a plan view, the center of gravity of the second semiconductor element 22 coincides with the center of the second die pad 10B. The center of the second die pad 10B is the region that corresponds to the center when the second die pad 10B is divided into Lx (where Lx is a positive odd number) in the first direction x, and also the center when the second die pad 10B is divided into Ly (where Ly is a positive odd number) in the second direction y. Lx and Ly are not limited in any way, but for example, they are 3 or 5.
[0041] The second semiconductor element 22 has a second main surface 22a and a second back surface 22b. The second main surface 22a and the second back surface 22b are spaced apart from each other in the thickness direction z. The second main surface 22a faces the same direction as the main surface 101 of the second die pad 10B. The second back surface 22b faces the opposite direction from the second main surface 22a in the thickness direction z and faces the main surface 101 of the second die pad 10B.
[0042] As shown in Figures 3 and 9, the second semiconductor element 22 is mounted on the second die pad 10B. As shown in Figure 12, the second semiconductor element 22 has a second main surface electrode 221, a main surface electrode 222, and a back surface electrode 223.
[0043] The second main surface electrode 221 is positioned on the second main surface 22a. A current corresponding to the power converted by the second semiconductor element 22 flows through the second main surface electrode 221. In the example where the second semiconductor element 22 is a MOSFET, the second main surface electrode 221 is, for example, a source electrode. The second main surface electrode 221 includes multiple metal plating layers, similar to the first main surface electrode 211. The second main surface electrode 221 includes a nickel (Ni) plating layer and a gold (Au) plating layer laminated on top of the nickel plating layer. Alternatively, the second main surface electrode 221 may include a nickel plating layer, a palladium (Pd) plating layer laminated on top of the nickel plating layer, and a gold plating layer laminated on top of the palladium plating layer.
[0044] The main surface electrode 222 is positioned on the second main surface 22a. A second drive signal (gate voltage) for driving the second semiconductor element 22 is applied to the main surface electrode 222. In the example where the second semiconductor element 22 is a MOSEFT, the main surface electrode 222 is, for example, a gate electrode. In a plan view, the area of the main surface electrode 222 is smaller than the area of the second main surface electrode 221.
[0045] The back electrode 223 is located on the second back surface 22b. The back electrode 223 is provided facing the main surface 101 of the second die pad 10B. A current corresponding to the power before it is converted by the second semiconductor element 22 flows through the back electrode 223. In the example where the second semiconductor element 22 is a MOSFET, the back electrode 223 is, for example, a drain electrode.
[0046] The semiconductor device A10 further comprises two die bonding layers 231 and 232. Each of the two die bonding layers 231 and 232 is conductive. Each die bonding layer 231 and 232 is, for example, solder. Alternatively, each die bonding layer 231 and 232 may be sintered metal.
[0047] As shown in Figures 9 and 11, the die bonding layer 231 is interposed between the main surface 101 of the first die pad 10A and the back electrode 213 of the first semiconductor element 21. The die bonding layer 231 bonds the main surface 101 of the first die pad 10A to the back electrode 213 of the first semiconductor element 21. As a result, the back electrode 213 of the first semiconductor element 21 becomes electrically connected to the first die pad 10A.
[0048] As shown in Figures 9, 10, and 12, the die bonding layer 232 is interposed between the main surface 101 of the second die pad 10B and the back electrode 223 of the second semiconductor element 22. The die bonding layer 232 bonds the main surface 101 of the second die pad 10B and the back electrode 223 of the second semiconductor element 22. As a result, the back electrode 223 of the second semiconductor element 22 becomes electrically connected to the second die pad 10B.
[0049] As shown in Figure 3, the multiple terminal leads 13 are located in the second direction y on the side opposite to the side in which the second end face 112 faces the first die pad 10A and the second die pad 10B. At least one of the multiple terminal leads 13 is conductive to either the first semiconductor element 21 or the second semiconductor element 22. The multiple terminal leads 13 are arranged along the first direction x. The multiple terminal leads 13 include the first terminal lead 14, the second terminal lead 15, the third terminal lead 16, the fourth terminal lead 171, the fifth terminal lead 172, the sixth terminal lead 181, and the seventh terminal lead 182.
[0050] As shown in Figure 3, the first terminal lead 14 is located away from the first die pad 10A and the second die pad 10B in the second direction y, and between the second terminal lead 15 and the third terminal lead 16 in the first direction x. The first terminal lead 14 extends along the second direction y. The first terminal lead 14 is conductive to the second main surface electrode 221 of the second semiconductor element 22. The first terminal lead 14 includes a covering portion 14A and an exposed portion 14B. As shown in Figure 10, the covering portion 14A is covered by the sealing resin 50. As shown in Figures 2, 3, 5, and 6, the exposed portion 14B is connected to the covering portion 14A and is exposed from the third side surface 55 of the sealing resin 50. The exposed portion 14B extends away from the first die pad 10A and the second die pad 10B in the second direction y. The surface of the exposed portion 14B is, for example, tin-plated.
[0051] As shown in Figure 14, the covering portion 14A of the first terminal lead 14 has a second seating surface 14C and a second upright surface 14D. The second seating surface 14C faces the same side as the main surfaces 101 of the first die pad 10A and the second die pad 10B in the thickness direction z, and is located below the upper surface (the surface facing upward in the thickness direction z) of the covering portion 14A. The second upright surface 14D faces in a direction perpendicular to the thickness direction z and connects to the second seating surface 14C and the upper surface of the covering portion 14A. The second seating surface 14C and the second upright surface 14D form a step in the covering portion 14A of the first terminal lead 14.
[0052] As shown in Figure 3, the second terminal lead 15 includes a portion extending along the second direction y and is connected to the first die pad 10A. Therefore, the second terminal lead 15 conducts to the back electrode 213 of the first semiconductor element 21 via the first die pad 10A. The second terminal lead 15 is the P terminal (positive electrode) to which the DC power supply voltage to be converted is applied. The second terminal lead 15 includes a covered portion 15A and an exposed portion 15B. As shown in Figure 8, the covered portion 15A is connected to the third end face 113 of the first die pad 10A and is covered by the sealing resin 50. Viewed along the first direction x, the covered portion 15A is bent. As shown in Figures 2, 3, 5, and 6, the exposed portion 15B is connected to the covered portion 15A and is exposed from the third side surface 55 of the sealing resin 50. The exposed portion 15B extends away from the first die pad 10A in the second direction y. The surface of the exposed portion 15B is, for example, tin-plated.
[0053] As shown in Figure 3, the third terminal lead 16 includes a portion extending along the second direction y and is connected to the second die pad 10B. Therefore, the third terminal lead 16 conducts to the back electrode 223 of the second semiconductor element 22 via the second die pad 10B. AC power converted by the first semiconductor element 21 and the second semiconductor element 22 is output from the third terminal lead 16. The third terminal lead 16 includes a covered portion 16A and an exposed portion 16B. The covered portion 16A is connected to the third end face 113 of the second die pad 10B and is covered by the sealing resin 50. Viewed along the first direction x, the covered portion 16A is bent in the same way as the covered portion 15A of the second terminal lead 15. As shown in Figures 2, 3, 5, and 6, the exposed portion 16B is connected to the covered portion 16A and is exposed from the third side surface 55 of the sealing resin 50. The exposed portion 16B extends away from the second die pad 10B in the second direction y. The surface of the exposed portion 16B is, for example, tin-plated.
[0054] As shown in Figure 3, the fourth terminal lead 171 is located away from the first die pad 10A in the second direction y and on one side of the first direction x. As shown in Figure 3, the fifth terminal lead 172 is located away from the second die pad 10B in the second direction y and on the other side of the first direction x. The fourth terminal lead 171 is conductive to the main surface electrode 212 (gate electrode) of the first semiconductor element 21. A drive signal (gate voltage) for driving the first semiconductor element 21 is applied to the fourth terminal lead 171. The fifth terminal lead 172 is conductive to the main surface electrode 222 (gate electrode) of the second semiconductor element 22. A drive signal (gate voltage) for driving the second semiconductor element 22 is applied to the fifth terminal lead 172.
[0055] As shown in Figure 3, the fourth terminal lead 171 includes a covered portion 171A and an exposed portion 171B. The covered portion 171A is covered by a sealing resin 50. As shown in Figures 2, 3, 5, and 6, the exposed portion 171B is connected to the covered portion 171A and is exposed from the third side surface 55 of the sealing resin 50. The exposed portion 171B extends away from the first die pad 10A in the second direction y. The surface of the exposed portion 171B is, for example, tin-plated.
[0056] As shown in Figure 3, the fifth terminal lead 172 includes a covered portion 172A and an exposed portion 172B. The covered portion 172A is covered by a sealing resin 50. As shown in Figures 2, 3, 5, and 6, the exposed portion 172B is connected to the covered portion 172A and is exposed from the sealing resin 50. The exposed portion 172B extends away from the second die pad 10B in the second direction y. The surface of the exposed portion 172B is, for example, tin-plated.
[0057] As shown in Figure 3, the sixth terminal lead 181 is located away from the first die pad 10A in the second direction y, and between the second terminal lead 15 and the fourth terminal lead 171 in the first direction x. As shown in Figure 3, the seventh terminal lead 182 is located away from the second die pad 10B in the second direction y, and between the third terminal lead 16 and the fifth terminal lead 172 in the first direction x. The sixth terminal lead 181 is conductive to the first main surface electrode 211 (source electrode) of the first semiconductor element 21. A voltage corresponding to the current flowing through the first main surface electrode 211 of the first semiconductor element 21 is applied to the sixth terminal lead 181. The seventh terminal lead 182 is conductive to the second main surface electrode 221 (source electrode) of the second semiconductor element 22. A voltage corresponding to the current flowing through the second main surface electrode 221 (source electrode) of the second semiconductor element 22 is applied to the seventh terminal lead 182.
[0058] As shown in Figure 3, the sixth terminal lead 181 includes a covered portion 181A and an exposed portion 181B. The covered portion 181A is covered by a sealing resin 50. As shown in Figures 2, 3, 5, and 6, the exposed portion 181B is connected to the covered portion 181A and is exposed from the third side surface 55 of the sealing resin 50. The exposed portion 181B extends away from the first die pad 10A in the second direction y. The surface of the exposed portion 181B is, for example, tin-plated.
[0059] As shown in Figure 3, the seventh terminal lead 182 includes a covered portion 182A and an exposed portion 182B. The covered portion 182A is covered by a sealing resin 50. As shown in Figures 2, 3, 5, and 6, the exposed portion 182B is connected to the covered portion 182A and is exposed from the third side surface 55 of the sealing resin 50. The exposed portion 182B extends away from the second die pad 10B in the second direction y. The surface of the exposed portion 182B is, for example, tin-plated.
[0060] As shown in Figure 6, in semiconductor device A10, the height h of the exposed portion 14B of the first terminal lead 14, the exposed portion 15B of the second terminal lead 15, and the exposed portion 16B of the third terminal lead 16 are all the same. Furthermore, their respective thicknesses are all the same. Therefore, when viewed along the first direction x, at least a portion of the first terminal lead 14 (exposed portion 14B) overlaps with the second terminal lead 15 and the third terminal lead 16, respectively (see Figure 7).
[0061] As shown in Figure 3, the first conductive member 31 is joined to the first main surface electrode 211 and the second die pad 10B of the first semiconductor element 21. As a result, the first main surface electrode 211 is electrically connected to the second die pad 10B and the back surface electrode 223 of the second semiconductor element 22. The composition of the first conductive member 31 includes copper. In semiconductor device A10, the first conductive member 31 is a metal clip. The first conductive member 31 has a first main body portion 311, a first joint portion 312, and a second joint portion 313.
[0062] As shown in Figure 3, the first main body portion 311 constitutes the main part of the first conductive member 31. The first main body portion 311 extends in the first direction x. In the illustrated example, the first main body portion 311 extends linearly between the first semiconductor element 21 and the second semiconductor element 22 in a plan view. As shown in Figure 8, the first main body portion 311 straddles the space between the first die pad 10A and the second die pad 10B. In the illustrated example, the end of the first main body portion 311 connected to the first joint portion 312 is forked.
[0063] As shown in Figures 3, 4, and 11, the first junction 312 is joined to the first main surface electrode 211 of the first semiconductor element 21. The first junction 312 includes two first strip-shaped portions 312a. As shown in Figures 3, 4, and 8, the two first strip-shaped portions 312a are located apart from each other in the second direction y. Each of the two first strip-shaped portions 312a has its longitudinal direction in the first direction x. In a plan view, the two first strip-shaped portions 312a are arranged parallel to each other. In the illustrated example, the end of the first main body portion 311 connected to the first junction 312 is bifurcated and each ends connects to the corresponding one of the two first strip-shaped portions 312a. Unlike this example, the end of the first main body portion 311 connected to the first joint portion 312 may not be bifurcated, and the first joint portion 312 may be a single rectangular portion (a configuration in which two first strip-shaped portions 312a are connected). The area of the first joint portion 312 in plan view (the sum of the areas of the two first strip-shaped portions 312a) is, for example, 10% to 100% of the area of the first main surface electrode 211 in plan view.
[0064] As shown in Figures 3 and 13, the second joint 313 is joined to the first seating surface 103 of the second die pad 10B. The second joint 313 extends in the second direction y. At least a portion of the second joint 313 is housed in the area defined by the first seating surface 103 and the first upright surface 104 of the second die pad 10B. The second joint 313 connects to the first main body 311. The second joint 313 is located on the opposite side of the first joint 312, with the first main body 311 in between.
[0065] As shown in Figures 9 and 11, the semiconductor device A10 further comprises a first bonding layer 33. The first bonding layer 33 is interposed between the first main surface electrode 211 of the first semiconductor element 21 and the two first strip-shaped portions 312a of the first bonding portion 312. The first bonding layer 33 bonds the first main surface electrode 211 and the first bonding portion 312 (the two first strip-shaped portions 312a). The first bonding layer 33 is conductive. The first bonding layer 33 is, for example, solder. Alternatively, the first bonding layer 33 may be a sintered metal.
[0066] The thickness t of each of the pair of first strip-shaped portions 312a is 0.1 mm or more, and no more than twice the maximum thickness Tmax of the first bonding layer 33. The maximum thickness Tmax of the first bonding layer 33 is greater than the thickness of the first semiconductor element 21.
[0067] As shown in Figures 9 and 13, the semiconductor device A10 further comprises a second bonding layer 34. The second bonding layer 34 is interposed between the first seating surface 103 of the second die pad 10B and the second bonding portion 313. The second bonding layer 34 bonds the second die pad 10B and the second bonding portion 313. The second bonding layer 34 is conductive. The second bonding layer 34 is, for example, solder. Alternatively, the second bonding layer 34 may be sintered metal.
[0068] As shown in Figure 3, the second conductive member 32 is joined to the second main surface electrode 221 of the second semiconductor element 22 and to the covering portion 14A of the first terminal lead 14. As a result, the second main surface electrode 221 is electrically connected to the first terminal lead 14. The composition of the second conductive member 32 includes copper. In the semiconductor device A10, the second conductive member 32 is a metal clip. The second conductive member 32 has a second main body portion 321, a third joint portion 322, and a fourth joint portion 323.
[0069] As shown in Figure 3, the second main body portion 321 constitutes the main part of the second conductive member 32. Viewed along the thickness direction z, the second main body portion 321 is bent in a hook shape. Viewed along the thickness direction z, the first main body portion 311 overlaps the main surface 101 of the second die pad 10B.
[0070] As shown in Figure 4, the second main body 321 includes a first extension 321a, a second extension 321c, and a third extension 321e. The first extension 321a has a first base end 321b, which is an edge connected to the third joint 322. The first extension 321a extends from the first base end 321b in a second direction y. In this embodiment, a portion of the first extension 321a (the end including the first base end 321b) is bent in the thickness direction z. The second extension 321c has a second base end 321d, which is an edge connected to the first extension 321a. The second extension 321c extends from the second base end 321d in a first direction x. As shown in Figure 4, the second extension 321c intersects the fourth end face 114 of the second die pad 10B in a plan view. With this configuration, the second conductive member 32 does not overlap the fourth corner end face 124 of the second die pad 10B in a plan view. The third extension 321e has a third base end 321f. The third base end 321f is an edge that connects to the third extension 321e. The third extension 321e extends from the third base end 321f in the second direction y. In this embodiment, a part of the third extension 321e (the end opposite to the third base end 321f) is bent in the thickness direction z.
[0071] As shown in Figures 3 and 14, the third joint 322 is joined to the second seating surface 14C of the first terminal lead 14. The third joint 322 extends in the first direction x. At least a portion of the third joint 322 is housed in the region defined by the second seating surface 14C and the second upright surface 14D of the first terminal lead 14. The third joint 322 connects to the second main body 321 (first extension 321a). The third joint 322 is located on the opposite side of the fourth joint 323, with the second main body 321 in between.
[0072] As shown in Figures 3 and 12, the fourth junction 323 is joined to the second main surface electrode 221 of the second semiconductor element 22. The fourth junction 323 includes two second strip portions 323a. As shown in Figures 3 and 10, the two second strip portions 323a are located apart from each other in the second direction y. Each of the two second strip portions 323a has its longitudinal direction in the first direction x. In plan view, the two second strip portions 323a are arranged parallel to each other. In the illustrated example, the end of the aforementioned second main body portion 321 that connects to the fourth junction 323 is bifurcated and connects to the corresponding one of the two second strip portions 323a. Unlike this example, the end of the second main body 321 that connects to the fourth joint 323 may not be bifurcated, and the fourth joint 323 may be a single rectangular portion (a configuration in which two second strip-shaped portions 323a are connected). The area of the fourth joint 323 in plan view (the sum of the areas of the two second strip-shaped portions 323a) is, for example, 10% to 100% of the area of the second main surface electrode 221 in plan view.
[0073] As shown in Figures 9 and 14, the semiconductor device A10 further comprises a third bonding layer 35. The third bonding layer 35 is interposed between the second seating surface 14C of the first terminal lead 14 and the third bonding portion 322. The third bonding layer 35 bonds the covering portion 14A of the first terminal lead 14 to the third bonding portion 322. The third bonding layer 35 is conductive. The third bonding layer 35 is, for example, solder. Alternatively, the third bonding layer 35 may be sintered metal.
[0074] As shown in Figures 9 and 12, the semiconductor device A10 further comprises a fourth bonding layer 36. The fourth bonding layer 36 is interposed between the second main surface electrode 221 of the second semiconductor element 22 and the two second strip-shaped portions 323a of the fourth bonding portion 323. The fourth bonding layer 36 bonds the second main surface electrode 221 of the second semiconductor element 22 to the fourth bonding portion 323 (each of the two second strip-shaped portions 323a). The fourth bonding layer 36 is conductive. The fourth bonding layer 36 is, for example, solder. Alternatively, the fourth bonding layer 36 may be sintered metal.
[0075] The thickness t of the fourth junction 323 (each of the two second strip-shaped portions 323a) is 0.1 mm or more, and no more than twice the maximum thickness Tmax of the fourth junction layer 36. The maximum thickness Tmax of the fourth junction layer 36 is greater than the thickness of the second semiconductor element 22.
[0076] Each of the pair of first connecting members 41A, 41B and the pair of second connecting members 42A, 42B is, for example, a bonding wire. The composition of each of the pair of first connecting members 41A, 41B and the pair of second connecting members 42A, 42B includes gold. In addition, the composition of each of the pair of first connecting members 41A, 41B and the pair of second connecting members 42A, 42B may include copper or aluminum (Al).
[0077] As shown in Figure 3, the first connecting member 41A is joined to the main surface electrode 212 of the first semiconductor element 21 and to the covering portion 171A of the fourth terminal lead 171. As a result, the fourth terminal lead 171 is electrically connected to the main surface electrode 212 of the first semiconductor element 21. As shown in Figure 3, the first connecting member 41B is joined to the main surface electrode 222 of the second semiconductor element 22 and to the covering portion 172A of the fifth terminal lead 172. As a result, the fifth terminal lead 172 is electrically connected to the main surface electrode 222 of the second semiconductor element 22.
[0078] As shown in Figure 3, the second connecting member 42A is joined to the first main surface electrode 211 of the first semiconductor element 21 and to the covering portion 181A of the sixth terminal lead 181. As a result, the sixth terminal lead 181 is electrically connected to the first main surface electrode 211 of the first semiconductor element 21. As shown in Figure 3, the second connecting member 42B is joined to the second main surface electrode 221 of the second semiconductor element 22 and to the covering portion 182A of the seventh terminal lead 182. As a result, the seventh terminal lead 182 is electrically connected to the second main surface electrode 221 of the second semiconductor element 22.
[0079] As shown in Figure 19, the semiconductor device A10 configured as described above has an electrical connection between the first main surface electrode 211 of the first semiconductor element 21 and the back surface electrode 223 of the second semiconductor element 22. Therefore, the semiconductor device A10 constitutes a half-bridge circuit using two transistors (the first semiconductor element 21 and the second semiconductor element 22).
[0080] The operation and effects of the semiconductor device A10 according to the first embodiment are as follows.
[0081] The semiconductor device A10 comprises a first semiconductor element 21, a second semiconductor element 22, and a sealing resin 50. The sealing resin 50 covers the first semiconductor element 21 and the second semiconductor element 22. With this configuration, the semiconductor device A10 has two semiconductor elements (the first semiconductor element 21 and the second semiconductor element 22) packaged together with one sealing resin 50. Therefore, the semiconductor device A10 can reduce the mounting area on the circuit board on which it is mounted.
[0082] In the semiconductor device A10, the sealing resin 50 has a plurality of recesses 581. Each of the plurality of recesses 581 is recessed in the thickness direction z from the main resin surface 51. In a plan view, the plurality of recesses 581 overlap the first die pad 10A. As described above, the plurality of recesses 581 are marks formed when the first die pad 10A is fixed with a plurality of pins during the manufacturing of the semiconductor device A10. Therefore, since the first die pad 10A is held down by a plurality of pins during the manufacturing of the semiconductor device A10, oscillation of the first die pad 10A during the manufacturing process can be suppressed. This suppresses the occurrence of a gap between the back surface 102 of the first die pad 10A and the mold for forming the sealing resin 50, and thus suppresses the generation of resin burrs on the sealing resin 50.
[0083] In the semiconductor device A10, the sealing resin 50 has a plurality of recesses 582. Each of the plurality of recesses 582 is recessed in the thickness direction z from the main resin surface 51. In a plan view, the plurality of recesses 582 overlap the second die pad 10B. As described above, the plurality of recesses 582 are marks formed when the second die pad 10B is fixed with a plurality of pins during the manufacturing of the semiconductor device A10. Therefore, since the second die pad 10B is held down by a plurality of pins during the manufacturing of the semiconductor device A10, oscillation of the second die pad 10B during the manufacturing process can be suppressed. This prevents the formation of a gap between the back surface 102 of the second die pad 10B and the mold for forming the sealing resin 50, and thus prevents the formation of resin burrs on the sealing resin 50.
[0084] In semiconductor device A10, the second conductive member 32 includes a second main body portion 321 that connects the third joint portion 322 and the fourth joint portion 323. The second main body portion 321 is bent in plan view. As can be seen from Figure 3, if the third joint portion 322 and the fourth joint portion 323 were connected in a straight line, the second main body portion 321 would overlap one of the four corners of the second die pad 10B (the fourth corner end face 124 of the second die pad 10B) in plan view. In this case, it would be difficult for the pins used to fix the second die pad 10B during the manufacturing of semiconductor device A10 to hold down the four corners of the second die pad 10B. However, holding down the four corners of the second die pad 10B with pins is preferable for suppressing the oscillation of the second die pad 10B. On the other hand, in semiconductor device A10, by bending the second main body portion 321, it is possible to prevent the second main body portion 321 from overlapping with one of the four corners of the second die pad 10B (the fourth corner end face 124 of the second die pad 10B) in a plan view. In other words, semiconductor device A10 is preferable in suppressing oscillation of the second die pad 10B during manufacturing.
[0085] In semiconductor device A10, the second main body portion 321 of the second conductive member 32 includes a first extension portion 321a, a second extension portion 321c, and a third extension portion 321e. The first extension portion 321a extends from the third joint portion 322 in the second direction y, the second extension portion 321c extends from the first extension portion 321a in the first direction x, and the third extension portion 321e extends from the second extension portion 321c in the second direction y. In semiconductor device A10, by bending the second main body portion 321 multiple times in a plan view, as described above, it becomes possible to fix the four corners of the second die pad 10B with multiple pins during manufacturing, and it becomes possible to form the first main body portion 311 linearly between the first semiconductor element 21 and the second semiconductor element 22.
[0086] Other embodiments and modifications of the semiconductor device of the present disclosure are described below. The configurations of the parts in each embodiment and each modification are interchangeable to the extent that no technical inconsistencies arise.
[0087] Figures 20 and 21 show a semiconductor device A11 according to a first modification of the first embodiment. The semiconductor device A11 differs from the semiconductor device A10 in the following respect: the first semiconductor element 21 of the semiconductor device A11 is a diode, not a transistor.
[0088] The first semiconductor element 21 of semiconductor device A11 has a first main surface electrode 211 and a back surface electrode 213. As shown in Figure 20, the first semiconductor element 21 of semiconductor device A11 does not have a main surface electrode 212. As shown in Figure 21, the first semiconductor element 21 of semiconductor device A11 is a diode, where the first main surface electrode 211 is, for example, an anode electrode, and the back surface electrode 213 is, for example, a cathode electrode.
[0089] As shown in Figure 20, semiconductor device A11 does not have either the first connecting member 41A or the pair of second connecting members 42A and 42B. In this configuration, as shown in Figures 20 and 21, the fourth terminal lead 171, the sixth terminal lead 181, and the seventh terminal lead 182 do not conduct to either the first semiconductor element 21 or the second semiconductor element 22. Therefore, in semiconductor device A11, the fourth terminal lead 171, the sixth terminal lead 181, and the seventh terminal lead 182 are non-connecting terminals. In the example shown in Figure 20, semiconductor device A11 does not have either of the pair of second connecting members 42A and 42B, but in a configuration different from this example, semiconductor device A11 may have the same pair of second connecting members 42A and 42B as semiconductor device A10.
[0090] As shown in Figure 21, in semiconductor device A11, the first main surface electrode 211 (anode electrode) of the first semiconductor element 21 and the back surface electrode 223 (drain electrode) of the second semiconductor element 22 are electrically connected. In semiconductor device A11, with respect to the power supply voltage (DC voltage) applied between the first terminal lead 14 and the second terminal lead 15, the high-voltage side acts as a diode and the low-voltage side acts as a transistor. Semiconductor device A11 can be used, for example, as a boost chopper circuit.
[0091] Figures 22 and 23 show a semiconductor device A12 according to a second modification of the first embodiment. The semiconductor device A12 differs from the semiconductor device A10 in the following respect: the second semiconductor element 22 of the semiconductor device A12 is a diode, not a transistor.
[0092] The second semiconductor element 22 of semiconductor device A12 has a second main surface electrode 221 and a back surface electrode 223. As shown in Figure 22, the second semiconductor element 22 of semiconductor device A12 does not have a main surface electrode 222. As shown in Figure 23, the second semiconductor element 22 of semiconductor device A12 is a diode, where the second main surface electrode 221 is, for example, an anode electrode and the back surface electrode 223 is, for example, a cathode electrode.
[0093] As shown in Figure 22, the semiconductor device A12 does not have either the first connecting member 41B or the pair of second connecting members 42A and 42B. In this configuration, as shown in Figures 22 and 23, the fifth terminal lead 172, the sixth terminal lead 181, and the seventh terminal lead 182 do not conduct to either the first semiconductor element 21 or the second semiconductor element 22. Therefore, in the semiconductor device A12, the fifth terminal lead 172, the sixth terminal lead 181, and the seventh terminal lead 182 are non-connecting terminals. In the example shown in Figure 22, the semiconductor device A12 does not have either of the pair of second connecting members 42A and 42B, but in a configuration different from this example, the semiconductor device A12 may have the same pair of second connecting members 42A and 42B as the semiconductor device A10.
[0094] As shown in Figure 23, in semiconductor device A12, the first main surface electrode 211 (source electrode) of the first semiconductor element 21 and the back surface electrode 223 (cathode electrode) of the second semiconductor element 22 are electrically connected. In semiconductor device A12, with respect to the DC voltage applied between the first terminal lead 14 and the second terminal lead 15, the high-voltage side acts as a transistor and the low-voltage side acts as a diode. Semiconductor device A12 can be used, for example, as a step-down chopper circuit.
[0095] Figures 24 and 25 show a semiconductor device A13 according to a third modification of the first embodiment. The semiconductor device A13 differs from the semiconductor device A10 in the following respect: each of the first semiconductor element 21 and the second semiconductor element 22 of the semiconductor device A13 is a diode instead of a transistor.
[0096] The first semiconductor element 21 of semiconductor device A13 has a first main surface electrode 211 and a back surface electrode 213. As shown in Figure 24, the first semiconductor element 21 of semiconductor device A13 does not have a main surface electrode 212. As shown in Figure 25, the first semiconductor element 21 of semiconductor device A13 is a diode, with the first main surface electrode 211 being the anode electrode and the back surface electrode 213 being the cathode electrode. The second semiconductor element 22 of semiconductor device A13 has a second main surface electrode 221 and a back surface electrode 223. As shown in Figure 24, the second semiconductor element 22 of semiconductor device A13 does not have a main surface electrode 222. As shown in Figure 25, the second semiconductor element 22 of semiconductor device A13 is a diode, with the second main surface electrode 221 being the anode electrode and the back surface electrode 223 being the cathode electrode.
[0097] As shown in Figure 24, semiconductor device A13 does not have a pair of first connecting members 41A, 41B or a pair of second connecting members 42A, 42B. In this configuration, as shown in Figures 24 and 25, the fourth terminal lead 171, the fifth terminal lead 172, the sixth terminal lead 181, and the seventh terminal lead 182 do not conduct to either the first semiconductor element 21 or the second semiconductor element 22. Therefore, in semiconductor device A13, the fourth terminal lead 171, the fifth terminal lead 172, the sixth terminal lead 181, and the seventh terminal lead 182 are non-connecting terminals. In the example shown in Figure 24, semiconductor device A13 does not have a pair of second connecting members 42A, 42B, but in a configuration different from this example, semiconductor device A13 may have a pair of second connecting members 42A, 42B similar to those in semiconductor device A10.
[0098] As shown in Figure 25, in semiconductor device A13, the first main surface electrode 211 (anode electrode) of the first semiconductor element 21 and the back surface electrode 223 (cathode electrode) of the second semiconductor element 22 are electrically connected. In semiconductor device A13, both the high-voltage side and the low-voltage side are diodes with respect to the power supply voltage (DC voltage) applied between the first terminal lead 14 and the second terminal lead 15. Semiconductor device A13 is a diode bridge circuit.
[0099] Each of the modified semiconductor devices A11 to A13 according to the first embodiment, like semiconductor device A10, has two semiconductor elements (first semiconductor element 21 and second semiconductor element 22) packaged in one encapsulating resin 50. Therefore, each of the semiconductor devices A11 to A13, like semiconductor device A10, can reduce the mounting area on the circuit board on which it is mounted. In addition, each of the semiconductor devices A11 to A13 has a configuration common to semiconductor device A10 and therefore achieves the same effects as semiconductor device A10.
[0100] As can be understood from the semiconductor devices A10 to A13 described above, the semiconductor device of this disclosure can configure four types of power conversion circuits (a bridge circuit using transistors, a boost chopper circuit, a buck chopper circuit, and a bridge circuit using diodes) by combining the first semiconductor element 21 and the second semiconductor element 22. On the other hand, the configuration of each terminal lead 13 and the sealing resin 50 is common to each semiconductor device A10 to A13. Therefore, the semiconductor device of this disclosure can configure any of the four types of power conversion circuits while maintaining the same package appearance. Furthermore, even if the first semiconductor element 21 and the second semiconductor element 22 differ in whether they are transistors or diodes, the configuration of each terminal lead 13 and the sealing resin 50 can be used as is. As a result, the semiconductor device of this disclosure can use a common package structure regardless of which of the four types of power conversion circuits is used, which is preferable in terms of improving productivity.
[0101] As can be understood from the semiconductor devices A10 to A13 described above, in a plan view, the semiconductor device of this disclosure is arranged such that the center of gravity of the first semiconductor element 21 coincides with the center of the first die pad 10A. This configuration is preferable for common use of the first conductive member 31. Similarly, in a plan view, the semiconductor device of this disclosure is arranged such that the center of gravity of the second semiconductor element 22 coincides with the center of the second die pad 10B. This configuration is preferable for common use of the second conductive member 32.
[0102] Figure 26 shows a semiconductor device A20 according to a second embodiment. The semiconductor device A20 differs from the semiconductor device A10 in the following respects: The planar size of the first semiconductor element 21 of the semiconductor device A20 is smaller than the planar size of the first semiconductor element 21 of the semiconductor device A10. Also, the planar size of the second semiconductor element 22 of the semiconductor device A20 is smaller than the planar size of the second semiconductor element 22 of the semiconductor device A10.
[0103] In semiconductor device A20, the planar size of the first semiconductor element 21 has been reduced compared to semiconductor device A10, and consequently, the planar size of the first junction 312 of the first conductive member 31 has also been reduced. In semiconductor device A20, as in semiconductor device A10, the area of the first junction 312 in plan view (the sum of the areas of the two first strip-shaped portions 312a) is, for example, between 10% and 100% of the area of the first main surface electrode 211 in plan view. On the other hand, the width of the first main body portion 311 of the first conductive member 31 is the same as in semiconductor device A10.
[0104] Furthermore, in semiconductor device A20, the planar size of the second semiconductor element 22 is reduced compared to semiconductor device A10, and consequently, the planar size of the fourth joint 323 of the second conductive member 32 is also reduced. Note that, similar to semiconductor device A10, the area of the fourth joint 323 in plan view (the sum of the areas of the two second strip-shaped portions 323a) in semiconductor device A20 is, for example, between 10% and 100% of the area of the second main surface electrode 221 in plan view. On the other hand, the width of the second main body portion 321 of the second conductive member 32 is the same as in semiconductor device A10.
[0105] Figure 27 shows a semiconductor device A21 according to a modified example of the second embodiment. The semiconductor device A21 differs from the semiconductor device A10 in the following respects: The planar size of the first semiconductor element 21 of the semiconductor device A21 is larger than that of the first semiconductor element 21 of the semiconductor device A10. Also, the planar size of the second semiconductor element 22 of the semiconductor device A21 is larger than that of the second semiconductor element 22 of the semiconductor device A10.
[0106] In semiconductor device A21, the planar size of the first semiconductor element 21 has been enlarged compared to semiconductor device A10, and consequently, the planar size of the first junction 312 of the first conductive member 31 has also been enlarged. In semiconductor device A21, as in semiconductor device A10, the area of the first junction 312 in planar view (the sum of the areas of the two first strip-shaped portions 312a) is, for example, between 10% and 100% of the area of the first main surface electrode 211 in planar view. On the other hand, the width of the first main body portion 311 of the first conductive member 31 is the same as in semiconductor device A10.
[0107] Furthermore, in semiconductor device A21, the planar size of the second semiconductor element 22 is enlarged compared to semiconductor device A10, and consequently, the planar size of the fourth joint portion 323 of the second conductive member 32 is also enlarged. Note that, similar to semiconductor device A10, the area of the fourth joint portion 323 in plan view (the sum of the areas of the two second strip-shaped portions 323a) in semiconductor device A21 is, for example, between 10% and 100% of the area of the second main surface electrode 221 in plan view. On the other hand, the width of the second main body portion 321 of the second conductive member 32 is the same as in semiconductor device A10.
[0108] In the second embodiment and its modified versions, each semiconductor device A20, A21, similar to semiconductor device A10, has two semiconductor elements (first semiconductor element 21 and second semiconductor element 22) packaged together with one sealing resin 50. Therefore, each semiconductor device A20, A21, similar to semiconductor device A10, can reduce the mounting area on the circuit board on which it is mounted. In addition, each semiconductor device A20, A21 has a configuration common to semiconductor device A10 and thus achieves the same effects as semiconductor device A10.
[0109] As can be understood from the semiconductor devices A10, A20, and A21 described above, in the semiconductor device of this disclosure, the area of the first junction 312 in a plan view (the sum of the areas of the two first strip-shaped portions 312a) is, for example, 10% to 100% of the area of the first main surface electrode 211 in a plan view. With this configuration, the plan view size of the first junction 312 can be made to an appropriate size according to the plan view size of the first semiconductor element 21. Similarly, in the semiconductor device of this disclosure, the area of the fourth junction 323 in a plan view (the sum of the areas of the two second strip-shaped portions 323a) is, for example, 10% to 100% of the area of the second main surface electrode 221 in a plan view. With this configuration, the plan view size of the fourth junction 323 can be made to an appropriate size according to the plan view size of the second semiconductor element 22.
[0110] As can be understood from the semiconductor devices A10, A20, and A21 described above, in the semiconductor device of this disclosure, even if the planar dimensions of the first semiconductor element 21 and the second semiconductor element 22 are different, the first main body 311 of the first conductive member 31 and the second main body 321 of the second conductive member 32 have the same width. When transporting the first conductive member 31, it may be gripped by a transport hand or the like. In this case, by gripping the first main body 311 in the width direction of the first main body 311, adjustment of the transport hand or the like becomes unnecessary. This is preferable in terms of improving productivity because even if the planar dimensions of the first semiconductor element 21 and the second semiconductor element 22 are different, transport devices such as transport hands can be standardized.
[0111] Figure 28 shows a semiconductor device A30 according to a third embodiment. The semiconductor device A30 differs from the semiconductor device A10 in the following respect: The semiconductor device A30 comprises a plurality of first semiconductor elements 21 and a plurality of second semiconductor elements 22. In the example shown in Figure 28, the semiconductor device A30 comprises two first semiconductor elements 21 and two second semiconductor elements 22.
[0112] Each of the two first semiconductor elements 21 is mounted on the first die pad 10A. Each of the two first semiconductor elements 21 is, for example, a transistor. The two first semiconductor elements 21 are aligned along the second direction y. In semiconductor device A30, in a plan view, the centroids (composite centroids) of the two first semiconductor elements 21 coincide with the center of the first die pad 10A. In the example shown in Figure 28, the plan view sizes of the two first semiconductor elements 21 are the same, but they may be different.
[0113] Since semiconductor device A30 comprises two first semiconductor elements 21, it differs from semiconductor device A10 in the following respects. Firstly, the first conductive member 31 of semiconductor device A30 includes two first joints 312. The two first joints 312 are connected to the first main body 311. The ends of the first main body 311 that connect to the two first joints 312 are bifurcated. Each of the two first joints 312 is joined to the corresponding one of the two first semiconductor elements 21. In the illustrated example, each first joint 312 is rectangular in plan view, but like the first joint 312 of semiconductor device A10, it may be divided into two first strip-shaped portions 312a. Secondly, the first connecting member 41A of the semiconductor device A30 is joined to the main surface electrode 212 of one first semiconductor element 21, the main surface electrode 212 of the other first semiconductor element 21, and the covering portion 171A of the fourth terminal lead 171. The first connecting member 41A is joined, for example, by stitch bonding to the main surface electrode 212 of the first semiconductor element 21 that is closer to the plurality of terminal leads 13 in the second direction y of the two first semiconductor elements 21. Thirdly, the second connecting member 42A of the semiconductor device A30 is joined to the first main surface electrode 211 of one first semiconductor element 21, the first main surface electrode 211 of the other first semiconductor element 21, and the covering portion 181A of the sixth terminal lead 181. The second connecting member 42A is joined, for example, by stitch bonding to the first main surface electrode 211 of the first semiconductor element 21 that is closer to the plurality of terminal leads 13 in the second direction y, among the two first semiconductor elements 21. In semiconductor device A30, the first connecting member 41A is formed first, but the second connecting member 42A may be formed first.
[0114] Each of the two second semiconductor elements 22 is mounted on the second die pad 10B. Each of the two second semiconductor elements 22 is, for example, a transistor. The two second semiconductor elements 22 are aligned along the second direction y. In semiconductor device A30, in a plan view, the centroids (composite centroids) of the two second semiconductor elements 22 coincide with the center of the second die pad 10B. In the example shown in Figure 28, the plan view sizes of the two second semiconductor elements 22 are the same, but they may be different from each other.
[0115] Since semiconductor device A30 comprises two second semiconductor elements 22, it differs from semiconductor device A10 in the following respects. Firstly, the second conductive member 32 of semiconductor device A30 includes two fourth junctions 323. The two fourth junctions 323 are connected to the second main body 321. Each of the two fourth junctions 323 is connected to a third extension 321e. Each of the two fourth junctions 323 is joined to the corresponding one of the two second semiconductor elements 22. In the illustrated example, each fourth junction 323 is rectangular in plan view, but like the fourth junction 323 of semiconductor device A10, it may be divided into two second strip-shaped portions 323a. Secondly, the first connecting member 41B of the semiconductor device A30 is joined to the main surface electrode 222 of the other second semiconductor element 22, to the main surface electrode 222 of the other second semiconductor element 22, and to the covering portion 172A of the fifth terminal lead 172. The first connecting member 41B is joined, for example, by stitch bonding to the main surface electrode 222 of the second semiconductor element 22 that is closer to the plurality of terminal leads 13 in the second direction y of the two second semiconductor elements 22. Thirdly, the second connecting member 42B of the semiconductor device A30 is joined to the second main surface electrode 221 of one second semiconductor element 22, to the second main surface electrode 221 of the other second semiconductor element 22, and to the covering portion 182A of the seventh terminal lead 182. The second connecting member 42B is joined, for example, by stitch bonding to the second main surface electrode 221 of the second semiconductor element 22 that is closer to the plurality of terminal leads 13 in the second direction y, among the two second semiconductor elements 22. In semiconductor device A30, the first connecting member 41B is formed first, but the second connecting member 42B may be formed first.
[0116] Unlike the example shown in Figure 28, the semiconductor device A30 may be configured as follows: The semiconductor device A30 may have two first connecting members 41A, with one first connecting member 41A joined to the main surface electrode 212 of one first semiconductor element 21 and the covering portion 171A of the fourth terminal lead 171, and the other first connecting member 41A joined to the main surface electrode 212 of the other first semiconductor element 21 and the covering portion 171A of the fourth terminal lead 171. Similarly, the semiconductor device A30 may have two second connecting members 42A, with one second connecting member 42A joined to the first main surface electrode 211 of one first semiconductor element 21 and the covering portion 181A of the sixth terminal lead 181, and the other second connecting member 42A joined to the first main surface electrode 211 of the other first semiconductor element 21 and the covering portion 181A of the sixth terminal lead 181. Alternatively, the semiconductor device A30 may include two first connecting members 41B, where one first connecting member 41B is joined to the main surface electrode 222 of one second semiconductor element 22 and the covering portion 172A of the fifth terminal lead 172, and the other first connecting member 41B is joined to the main surface electrode 222 of the other second semiconductor element 22 and the covering portion 172A of the fifth terminal lead 172. Alternatively, the semiconductor device A30 may include two second connecting members 42B, where one second connecting member 42B is joined to the second main surface electrode 221 of one second semiconductor element 22 and the covering portion 182A of the seventh terminal lead 182, and the other second connecting member 42B is joined to the second main surface electrode 221 of the other second semiconductor element 22 and the covering portion 182A of the seventh terminal lead 182.
[0117] The semiconductor device A30 according to the third embodiment, like the semiconductor device A10, has two semiconductor elements (a first semiconductor element 21 and a second semiconductor element 22) packaged together in one encapsulating resin 50. Therefore, like the semiconductor device A10, the semiconductor device A30 can reduce the mounting area on the circuit board on which it is mounted. In addition, the semiconductor device A30 has a configuration common to the semiconductor device A10 and thus achieves the same effects as the semiconductor device A10.
[0118] As can be understood from the semiconductor devices A10 and A30 described above, in the semiconductor device of this disclosure, even if the number of first semiconductor elements 21 and second semiconductor elements 22 differs, the configuration of the first die pad 10A, the second die pad 10B, the multiple terminal leads 13, and the sealing resin 50 remains the same. Therefore, even if the number of first semiconductor elements 21 and second semiconductor elements 22 differs, the configuration of each terminal lead 13 and sealing resin 50 can be used as is in the semiconductor device of this disclosure. As a result, the package structure of the semiconductor device of this disclosure can be standardized regardless of the number of first semiconductor elements 21 and second semiconductor elements 22, which is preferable in terms of improving productivity.
[0119] As can be understood from the semiconductor devices A10, A20, and A30 described above, in the semiconductor device of this disclosure, even if the types of first semiconductor elements 21 and second semiconductor elements 22 (whether they are transistors or diodes), their planar size and number differ, it is possible to standardize the first die pad 10A, the second die pad 10B, the multiple terminal leads 13 and the sealing resin 50 by simply changing a part of the first conductive member 31 (for example, the first junction 312) and a part of the second conductive member 32 (for example, the fourth junction 323).
[0120] In semiconductor device A30, an example is shown where both first semiconductor elements 21 are transistors, but the device is not limited to this; one of the two first semiconductor elements 21 may be a transistor and the other a diode. In this case, the diode is connected in antiparallel to the transistor. In this antiparallel connection, in the example where the transistor is a MOSFET, the drain electrode and cathode electrode are connected, and the source electrode and anode electrode are connected. Similarly, one of the two second semiconductor elements 22 may be a transistor and the other a diode.
[0121] Figures 29 and 30 show a semiconductor device A40 according to a fourth embodiment. The semiconductor device A40 differs from the semiconductor device A10 in the following respect: The semiconductor device A40 further comprises a support substrate 6.
[0122] The support substrate 6 supports the first die pad 10A and the second die pad 10B. The support substrate 6 is, for example, a DBC (Direct Bonded Copper) substrate or an AMB (Active Metal Brazing) substrate, but is not limited to these. The support substrate 6 includes an insulating layer 61 and a pair of metal layers 62, 63.
[0123] The insulating layer 61 is interposed between the pair of metal layers 62 and 63 in the thickness direction z. The insulating layer 61 is, for example, a plate made of ceramics. The composition of the ceramics is, for example, alumina (Al2O3), aluminum nitride (AlN), or silicon nitride (SiN,Si3N4). In a plan view, the insulating layer 61 faces inward towards the metal layer 62.
[0124] The metal layer 62 is formed on the upper surface (the surface facing upward in the thickness direction z) of the insulating layer 61. The metal layer 62 contains, for example, copper or a copper alloy. In addition to copper or a copper alloy, the metal layer 62 may also contain other metals such as gold, silver, or aluminum. As shown in Figures 29 and 30, the metal layer 62 includes two pad portions 621 and 622.
[0125] The two pad portions 621 and 622 are spaced apart from each other. The two pad portions 621 and 622 are arranged along a first direction x. The first die pad 10A is joined to pad portion 621 by a bonding material 69. The second die pad 10B is joined to pad portion 622 by a bonding material 69. Each bonding material 69 is a conductive bonding material such as solder or sintered metal. Unlike this example, each bonding material 69 may be an insulating bonding material. Note that the pad portion 621 and the first die pad 10A, and the pad portion 622 and the second die pad 10B may be joined by solid-phase diffusion bonding, for example, instead of by the bonding material 69. In the example shown in Figure 29, in a plan view, pad portion 621 is slightly larger than the first die pad 10A, and pad portion 622 is slightly larger than the second die pad 10B.
[0126] The metal layer 63 is formed on the lower surface (the surface facing downward in the thickness direction z) of the insulating layer 61. Like the metal layer 62, the metal layer 63 contains, for example, copper or a copper alloy. In addition to copper or a copper alloy, the metal layer 63 may also contain other metals such as gold, silver, or aluminum. The metal layer 63 includes two pad portions 631 and 632.
[0127] The two pad portions 631 and 632 are spaced apart from each other. The two pad portions 631 and 632 are arranged along a first direction x. In a plan view, pad portion 631 overlaps with pad portion 621. In a plan view, pad portion 632 overlaps with pad portion 622. The two pad portions 631 and 632 (metal layer 63) are exposed on the resin back surface 52. In the illustrated example, the lower surfaces (surfaces facing downward in the thickness direction z) of the two pad portions 631 and 632 are flush with the resin back surface 52, but unlike this example, they may be located above or below the resin back surface 52 in the thickness direction.
[0128] The thickness (dimension in the z-direction) of the sealing resin 50 of semiconductor device A40 is approximately the same as the thickness (dimension in the z-direction) of the sealing resin 50 of semiconductor device A10. On the other hand, the thickness (dimension in the z-direction) of the first die pad 10A and the second die pad 10B of semiconductor device A40 is smaller than the thickness (dimension in the z-direction) of the first die pad 10A and the second die pad 10B of semiconductor device A10. The sum of the thickness of the first die pad 10A (second die pad 10B) in semiconductor device A40 and the thickness of the support substrate 6 corresponds to the thickness of the first die pad 10A (second die pad 10B) in semiconductor device A10.
[0129] In the illustrated example, the sealing resin 50 of semiconductor device A40 does not have grooves 57. In configurations different from this example, the sealing resin 50 may have grooves 57. However, the grooves 57 are shallower than the grooves 57 in semiconductor device A10 and are located below the lower surface of the insulating layer 61 in the thickness direction z.
[0130] The semiconductor device A40 according to the fourth embodiment, like the semiconductor device A10, has two semiconductor elements (a first semiconductor element 21 and a second semiconductor element 22) packaged together with one sealing resin 50. Therefore, like the semiconductor device A10, the semiconductor device A40 can reduce the mounting area on the circuit board on which it is mounted. In addition, the semiconductor device A40 has a configuration common to the semiconductor device A10 and thus achieves the same effects as the semiconductor device A10.
[0131] The semiconductor device A40 includes a support substrate 6 that supports the first die pad 10A and the second die pad 10B. The support substrate 6 includes an insulating layer 61 made of ceramics. When the first semiconductor element 21 and the second semiconductor element 22 are driven in the semiconductor device A40, the first semiconductor element 21 and the second semiconductor element 22 generate heat. This heat generation causes the first die pad 10A and the second die pad 10B to expand thermally. Such thermal expansion imparts thermal stress to other components (for example, the first semiconductor element 21 and the second semiconductor element 22). However, in the semiconductor device A40, the thermal expansion of the first die pad 10A and the second die pad 10B is limited by the support substrate 6 (particularly the insulating layer 61 made of ceramics). Therefore, the thermal stress caused by the thermal expansion of the first die pad 10A and the second die pad 10B can be mitigated in the semiconductor device A40. For example, in semiconductor device A40, the thermal stress applied to the first semiconductor element 21 and the second semiconductor element 22 is relieved, and internal failure of the first semiconductor element 21 and the second semiconductor element 22 (for example, internal interface delamination) is suppressed.
[0132] In semiconductor device A40, the thicknesses (dimensions in the z-direction) of the first die pad 10A and the second die pad 10B are smaller than the thicknesses (dimensions in the z-direction) of the first die pad 10A and the second die pad 10B in semiconductor device A10. With this configuration, thermal expansion of the first die pad 10A and the second die pad 10B is suppressed in semiconductor device A40 compared to semiconductor device A10. Therefore, semiconductor device A40 can alleviate thermal stress caused by the thermal expansion of the first die pad 10A and the second die pad 10B more effectively than semiconductor device A10.
[0133] Figure 31 shows a semiconductor device A41 according to a first modification of the fourth embodiment. The semiconductor device A41 differs from the semiconductor device A40 in the following respect: the metal layer 63 is not separated into two pad portions 631 and 632. The metal layer 63 of the semiconductor device A41 corresponds to the two pad portions 631 and 632 in the semiconductor device A40 being connected.
[0134] Figure 32 shows a semiconductor device A42 according to a second modification of the fourth embodiment. The semiconductor device A42 differs from the semiconductor device A40 in the following respect: the insulating layer 61 is separated into two plate materials 611 and 612. A pad portion 621 is formed on the upper surface of plate material 611, and a pad portion 631 is formed on the lower surface of plate material 611. A pad portion 622 is formed on the upper surface of plate material 612, and a pad portion 632 is formed on the lower surface of plate material 612. In the semiconductor device A42, the first die pad 10A and the second die pad 10B are individually bonded to two DBC substrates or AMB substrates, respectively.
[0135] In each modified example of the fourth embodiment, the semiconductor devices A41 and A42, like semiconductor device A40, have two semiconductor elements (first semiconductor element 21 and second semiconductor element 22) packaged together with one sealing resin 50. Therefore, like semiconductor device A40, each semiconductor device A41 and A42 can reduce the mounting area on the circuit board on which it is mounted. In addition, each semiconductor device A41 and A42 has a configuration common to semiconductor device A40 and thus provides the same effects as semiconductor device A40. For example, each semiconductor device A41 and A42 has an insulating layer 61 made of ceramics (two plate materials 611 and 612) that suppresses the thermal expansion of the first die pad 10A and the second die pad 10B, thereby mitigating the thermal stress applied to other components (for example, the first semiconductor element 21 and the second semiconductor element 22).
[0136] The package structure of the semiconductor device described herein is not limited to those exemplified in the first to fourth embodiments (including their variations). For example, the semiconductor device described herein can be applied to other TO (Transistor Outline) packages. Specifically, while the semiconductor devices A10, A20, A30, and A40 according to the first to fourth embodiments are extensions of a package structure called TO-247, they may also be extensions of other package structures such as TO-220, TO-252, and TO-263. In other words, the semiconductor device described herein makes it possible to package multiple semiconductor elements (first semiconductor element 21 and second semiconductor element 22) with a single sealing resin 50 while maintaining an appearance similar to that of a conventional TO package.
[0137] The semiconductor devices described herein are not limited to the embodiments described above. The specific configurations of each part of the semiconductor devices described herein can be modified in various ways. For example, the semiconductor devices described herein include embodiments relating to the following appendices. Note 1. A first semiconductor element having a first main surface facing one direction in the thickness direction and a first main surface electrode disposed on the first main surface, A second semiconductor element having a second main surface oriented in the same direction as the first main surface and a second main surface electrode disposed on the second main surface, A first die pad on which the first semiconductor element is mounted, A second die pad is positioned on one side of the first die pad in a first direction perpendicular to the thickness direction, and on which the second semiconductor element is mounted, A first terminal lead spaced apart from the first die pad and the second die pad, A first conductive member electrically connects the first main surface electrode and the second die pad, A second conductive member electrically connects the second main surface electrode and the first terminal lead, A semiconductor device comprising a sealing resin covering the first semiconductor element and the second semiconductor element. Note 2. The semiconductor device according to Appendix 1, wherein the first conductive member includes a first bonding portion bonded to the first main surface electrode, a second bonding portion bonded to the second die pad, and a first main body portion connecting the first bonding portion and the second bonding portion. Note 3. The first main body portion is a semiconductor device as described in Appendix 2, which extends along the first direction when viewed in the thickness direction. Note 4. The semiconductor device according to Appendix 2 or Appendix 3, wherein the area of the first joint when viewed in the thickness direction is 10% or more and 100% or less of the area of the first main surface electrode when viewed in the thickness direction. Note 5. The first joint portion includes two first strip-shaped portions, The edge of the first main body portion connected to the first joint portion is divided into two branches and connected to the two first strip-shaped portions, respectively. A semiconductor device as described in any of Appendix 2 to Appendix 4. Note 6. The semiconductor device according to any one of Appendix 1 to Appendix 5, wherein the second conductive member includes a third joint joined to the first terminal lead, a fourth joint joined to the second main surface electrode, and a second main body connecting the third joint and the fourth joint. Note 7. The semiconductor device described in Appendix 6, wherein the second main body is bent when viewed in the thickness direction. Note 8. The second main body includes a first extension portion that extends in a second direction perpendicular to the thickness direction and the first direction from an edge connected to the third joint portion, with the edge connected to the first extension portion as the first base end, a second extension portion that extends in the first direction from a second base end, with the edge connected to the first extension portion as the second base end, and a third extension portion that extends in the second direction from a third base end, with the edge connected to the second extension portion as the third base end. The semiconductor device described in Appendix 7, wherein the third extension is connected to the fourth joint. Note 9. The semiconductor device according to any one of Appendix 6 to Appendix 8, wherein the area of the fourth joint when viewed in the thickness direction is 10% or more and 100% or less of the area of the second main surface electrode when viewed in the thickness direction. Note 10. The fourth joint includes two second strip-shaped portions, The semiconductor device according to any one of the appendices 6 to 9, wherein the edge of the second main body connected to the fourth joint is divided into two branches and connected to the two second strip-shaped portions, respectively. Note 11. The second terminal lead connected to the first die pad, The device further includes a third terminal lead connected to the second die pad, The semiconductor device according to any one of the appendices 1 to 10, wherein the first terminal lead, the second terminal lead, and the third terminal lead are spaced apart from each other. Note 12. The semiconductor device according to Appendix 11, wherein the first terminal lead is located between the second terminal lead and the third terminal lead in the first direction. Note 13. The semiconductor device according to Appendix 11 or Appendix 12, further comprising a fourth terminal lead, a fifth terminal lead, a sixth terminal lead, and a seventh terminal lead, each spaced apart from the first terminal lead, the second terminal lead, and the third terminal lead, and spaced apart from each other. Note 14. The sealing resin has a resin main surface facing the same direction as the first main surface, and at least one recess that is recessed from the resin main surface. The semiconductor device according to any one of the appendices 1 to 13, wherein each of the at least one recess overlaps either the first die pad or the second die pad when viewed in the thickness direction. Note 15. The semiconductor device according to Appendix 14, wherein each of the at least one recesses does not overlap with either the first conductive member or the second conductive member when viewed in the thickness direction. Note 16. The semiconductor device according to any one of the appendices 1 to 15, wherein, when viewed in the thickness direction, the center of gravity of the first semiconductor element coincides with the center of the first die pad. Note 17. The semiconductor device according to any one of the appendices 1 to 16, wherein, when viewed in the thickness direction, the center of gravity of the second semiconductor element coincides with the center of the second die pad. Note 18. The system further comprises a support substrate that supports the first die pad and the second die pad, The first die pad and the second die pad are supported in the thickness direction by the support substrate from the side opposite to the side on which the first semiconductor element and the second semiconductor element are mounted. The semiconductor device according to any one of Appendix 1 to Appendix 17, wherein the support substrate includes a ceramic and a pair of metal layers formed on both sides of the ceramic in the thickness direction. Note 19. The first semiconductor device is either a transistor or a diode. The second semiconductor device is either a transistor or a diode. A semiconductor device as described in any of Appendix 1 to Appendix 18. [Explanation of Symbols]
[0138] A10~A13, A20, A21, A30, A40~A42: Semiconductor equipment 10A: First die pad 10B: Second die pad 101: Main surface 102: Back side 103: First seat 104:1st upright plane 109 :Trace 111: First end surface 112: 2nd end face 113: Third end surface 114: 4th end face 121: 1st corner end face 122: 2nd corner end face 123: 3rd corner end face 124: 4th corner end face 13: Terminal Leads 14: First terminal lead 14A: Covering part 14B:Exposed part 14C: Second seat 14D: 2nd upright surface 15: Second terminal lead 15A: Covering part 15B:Exposed part 16: Third terminal lead 16A: Covering part 16B:Exposed part 171: Fourth terminal lead 171A: Covering part 171B:Exposed part 172: Fifth terminal lead 172A: Covering part 172B:Exposed part 181: Terminal 6 lead 181A: Covering part 181B:Exposed part 182: Terminal 7 lead 182A: Covering part 182B:Exposed part 21: First semiconductor element 21a: 1st main surface 21b: 1st back side 211: First main surface electrode 212: Main surface electrode 213: Back surface electrode 22: Second semiconductor device 22a: Second main surface 22b: 2nd back side 221: Second main surface electrode 222: Main surface electrode 223: Back surface electrode 231,232: Die bonding layer 31: First conductive member 311: First main body 312: 1st joint 312a: First band-shaped section 313:Second joint 32: Second conductive member 321: Second main body 321a: 1st extension part 321b: 1st proximal end 321c: Second extension part 321d: 2nd proximal end 321e: Third extension part 321f: Third base 322: Third joint 323: 4th joint 323a: Second band-shaped area 33: 1st bonding layer 34:Second bonding layer 35:Third bonding layer 36: 4th bonding layer 41A, 41B: First connecting member 42A, 42B: Second connecting member 50: Sealing resin 51: Resin main surface 52: Resin back 53 :1st side 54:Second side 55:Third side 56: Recess 57: Groove 581, 582: recessed 589 :Trace 6: Support board 61: Insulating layer 611,612: Board material 62: Metal layer 621,622: Pad section 63: Metal layer 631, 632: Pad section 69: Bonding material
Claims
1. A first semiconductor element having a first main surface facing one direction in the thickness direction and a first main surface electrode disposed on the first main surface, A second semiconductor element having a second main surface oriented in the same direction as the first main surface and a second main surface electrode disposed on the second main surface, A first die pad on which the first semiconductor element is mounted, A second die pad is positioned on one side of the first die pad in a first direction perpendicular to the thickness direction, and the second semiconductor element is mounted on the second die pad, A first terminal lead spaced apart from the first die pad and the second die pad, A first conductive member electrically connects the first main surface electrode and the second die pad, A second conductive member electrically connects the second main surface electrode and the first terminal lead, A semiconductor device comprising a sealing resin covering the first semiconductor element and the second semiconductor element.
2. The semiconductor device according to claim 1, wherein the first conductive member includes a first bonding portion bonded to the first main surface electrode, a second bonding portion bonded to the second die pad, and a first main body portion connecting the first bonding portion and the second bonding portion.
3. The semiconductor device according to claim 2, wherein the first main body extends along the first direction when viewed in the thickness direction.
4. The semiconductor device according to claim 2, wherein the area of the first joint when viewed in the thickness direction is 10% or more and 100% or less of the area of the first main surface electrode when viewed in the thickness direction.
5. The first joint portion includes two first strip-shaped portions, The semiconductor device according to claim 2, wherein the edge of the first main body connected to the first joint is divided into two branches and connected to the two first strip-shaped portions, respectively.
6. The semiconductor device according to claim 1, wherein the second conductive member includes a third joint joined to the first terminal lead, a fourth joint joined to the second main surface electrode, and a second main body connecting the third joint and the fourth joint.
7. The semiconductor device according to claim 6, wherein the second main body is bent when viewed in the thickness direction.
8. The second main body includes a first extension portion that extends in a second direction perpendicular to the thickness direction and the first direction from an edge connected to the third joint portion, with the edge connected to the first extension portion as the first base end, a second extension portion that extends in the first direction from a second base end, with the edge connected to the first extension portion as the second base end, and a third extension portion that extends in the second direction from a third base end, with the edge connected to the second extension portion as the third base end. The semiconductor device according to claim 7, wherein the third extension is connected to the fourth joint.
9. The semiconductor device according to claim 6, wherein the area of the fourth joint when viewed in the thickness direction is 10% or more and 100% or less of the area of the second main surface electrode when viewed in the thickness direction.
10. The fourth joint portion includes two second strip-shaped portions, The semiconductor device according to claim 6, wherein the edge of the second main body portion connected to the fourth joint portion is divided into two branches and connected to the two second strip-shaped portions, respectively.
11. The second terminal lead connected to the first die pad, The device further comprises a third terminal lead connected to the second die pad, The semiconductor device according to claim 1, wherein the first terminal lead, the second terminal lead, and the third terminal lead are spaced apart from each other.
12. The semiconductor device according to claim 11, wherein the first terminal lead is located between the second terminal lead and the third terminal lead in the first direction.
13. The semiconductor device according to claim 12, further comprising a fourth terminal lead, a fifth terminal lead, a sixth terminal lead, and a seventh terminal lead, each spaced apart from the first terminal lead, the second terminal lead, and the third terminal lead, and spaced apart from each other.
14. The sealing resin has a resin main surface facing the same direction as the first main surface, and at least one recess that is recessed from the resin main surface. The semiconductor device according to claim 1, wherein each of the at least one recess overlaps either the first die pad or the second die pad when viewed in the thickness direction.
15. The semiconductor device according to claim 14, wherein each of the at least one recesses does not overlap with either the first conductive member or the second conductive member when viewed in the thickness direction.
16. The semiconductor device according to claim 1, wherein, when viewed in the thickness direction, the center of gravity of the first semiconductor element coincides with the center of the first die pad.
17. The semiconductor device according to claim 1, wherein, when viewed in the thickness direction, the center of gravity of the second semiconductor element coincides with the center of the second die pad.
18. The system further comprises a support substrate that supports the first die pad and the second die pad, The first die pad and the second die pad are supported in the thickness direction by the support substrate from the side opposite to the side on which the first semiconductor element and the second semiconductor element are mounted. The semiconductor device according to claim 1, wherein the support substrate includes a ceramic and a pair of metal layers formed on both sides of the ceramic in the thickness direction.
19. The first semiconductor device is either a transistor or a diode. The semiconductor device according to any one of claims 1 to 18, wherein the second semiconductor element is either a transistor or a diode.
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JP2011082523A