Semiconductor inspection equipment and inspection method

Abstract

To understand the inclination of dislocation lines within the wafer over a wide area. [Solution] The semiconductor inspection apparatus of the embodiment comprises an acquisition unit, a detection unit, an analysis unit, and a classification unit. The acquisition unit acquires an image of the wafer by photographing the wafer. The detection unit detects a first coordinate of a penetrating dislocation appearing on the back surface of the wafer and a second coordinate of a penetrating dislocation appearing on the front surface of the wafer based on the image. The analysis unit analyzes the slope of the dislocation line of the penetrating dislocation with respect to the thickness direction of the wafer based on the first and second coordinates and the thickness of the wafer. The classification unit classifies the penetrating dislocations based on the analysis results.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor inspection apparatus and an inspection method.

Background Art

[0002] In a semiconductor single crystal ingot, a plurality of dislocation lines propagate substantially linearly at various inclinations from the seed crystal side during crystal growth. Some of the dislocation lines are included in a wafer cut out from the single crystal ingot as various threading dislocations such as threading screw dislocations (TSDs) and mixed dislocations (TMDs) which are a type thereof. This type of threading dislocation is related to the quality of the semiconductor device formed on the wafer and may adversely affect the semiconductor device. Therefore, in a semiconductor inspection apparatus, the distribution and density of threading dislocations on the wafer are inspected before forming a semiconductor device on the wafer.

[0003] The semiconductor inspection apparatus as described above has no particular problem, but according to the study of the present inventor, from the viewpoint of classifying threading dislocations that are highly likely to adversely affect semiconductor devices among threading dislocations, it is desirable to be able to grasp the inclination of the dislocation line of the threading dislocation. Here, examples of a method capable of grasping the inclination of the dislocation line include cross-sectional TEM (Transmission Electron Microscope) and multiphoton-excitation photoluminescence (MPPL). Cross-sectional TEM is a method in which an electron beam is incident on a sample, and the electron beam transmitted through the sample is analyzed to obtain a cross-sectional image of the sample. A multiphoton excitation microscope is a technique in which pulsed laser light is incident on a sample while controlling the focal position to perform multiphoton excitation, and fluorescence emitted from the sample is analyzed to obtain a fluorescence image of a deep portion of the sample.

[0004] However, since all of these methods measure the deep part of the sample and thus have a narrow measurement range, it is difficult to grasp the inclination of the dislocation line in the wafer over a wide range.

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] Japanese Patent Publication No. 2015-12124 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] The problem that this invention aims to solve is to provide a semiconductor inspection apparatus and inspection method that can grasp the inclination of dislocation lines within a wafer over a wide range. [Means for solving the problem]

[0007] The semiconductor inspection apparatus of the embodiment comprises an acquisition unit, a detection unit, an analysis unit, and a classification unit. The acquisition unit acquires an image of the wafer by photographing the wafer. The detection unit detects a first coordinate of a penetrating dislocation appearing on the back surface of the wafer and a second coordinate of a penetrating dislocation appearing on the front surface of the wafer based on the image. The analysis unit analyzes the slope of the dislocation line of the penetrating dislocation with respect to the thickness direction of the wafer based on the first and second coordinates and the thickness of the wafer. The classification unit classifies the penetrating dislocations based on the analysis results. [Brief explanation of the drawing]

[0008] [Figure 1] A block diagram showing an example configuration of a semiconductor inspection apparatus according to the first embodiment. [Figure 2] A schematic diagram showing an example of an ingot. [Figure 3] A schematic diagram showing an example of a wafer. [Figure 4] A schematic diagram illustrating the orientation of the wafer. [Figure 5] A block diagram showing an example configuration of the imaging device in Figure 1. [Figure 6] A block diagram showing an example of the computer configuration in Figure 1. [Figure 7] A block diagram showing an example of the database configuration in Figure 1. [Figure 8]A flowchart for explaining an operation example in the first embodiment. [Figure 9] A schematic diagram for explaining an operation example in the first embodiment. [Figure 10] A schematic diagram for explaining an operation example in the first embodiment. [Figure 11] A schematic diagram for explaining an operation example in the first embodiment. [Figure 12] A schematic diagram for explaining an operation example in the first embodiment. [Figure 13] A schematic diagram for explaining an operation example in the first embodiment. [Figure 14] A block diagram showing the configuration of an imaging apparatus in a first modified example of the first embodiment. [Figure 15] A block diagram showing the configuration of an imaging apparatus in a second modified example of the first embodiment. [Figure 16A] A block diagram showing a configuration example of an imaging apparatus included in a semiconductor inspection apparatus according to a second embodiment. [Figure 16B] A block diagram showing another configuration example of the imaging apparatus included in the semiconductor inspection apparatus according to the second embodiment. [Figure 17] A schematic diagram for explaining an operation example in the second embodiment. [Figure 18] A schematic diagram for explaining an operation example in the second embodiment. [Figure 19] A schematic diagram for explaining a first modified example of the operation in the second embodiment. [Figure 20] A schematic diagram for explaining a second modified example of the operation in the second embodiment. [Figure 21] A schematic diagram for explaining a second modified example of the operation in the second embodiment. [Figure 22] A schematic diagram for explaining a third modified example of the operation in the second embodiment. [Figure 23] A schematic diagram for explaining a fourth modified example of the operation in the second embodiment. [Figure 24] A schematic diagram for explaining a fifth modified example of the operation in the second embodiment. [Description of Embodiments]

[0009] Hereinafter, each embodiment will be described by way of example with reference to the drawings. In the following description, elements having the same functions and configurations are denoted by the same reference numerals. Further, in each of the following embodiments, when there is no need to distinguish between constituent elements (for example, an imaging device, a wafer, etc.) assigned reference signs accompanied by numbers / letters at the end for differentiation, descriptions (reference signs) with the numbers / letters at the end omitted are used.

[0010] <First Embodiment> Figure 1 is a block diagram showing a configuration example of a semiconductor inspection apparatus according to the first embodiment. This semiconductor inspection apparatus 100 includes an imaging device 1, a computer 2, and a database 3.

[0011] The imaging device 1 images the wafer 9 subjected to non-destructive inspection, and generates an image of the wafer 9. The wafer 9 is a semiconductor wafer obtained from a semiconductor single crystal ingot, for example, a silicon carbide (SiC) wafer that transmits visible light. However, the wafer 9 may be a gallium nitride (GaN) or diamond (C) wafer. Further, the wafer 9 may be a silicon (Si) wafer.

[0012] Here, the wafer 9 and the ingot will be described in advance with reference to FIGS. 2 to 4. In FIG. 2, the ingot 900 is formed by growing the semiconductor crystal 90 on the seed crystal 99. The ingot 900 includes a plurality of threading dislocations 999. The threading dislocations 999 in the ingot 900 originate from defects in the seed crystal 99. As the semiconductor crystal 90 grows, the threading dislocations 999 extend from the side of the seed crystal 99 toward the growth end side of the ingot 900 at a certain angle relative to the surface of the seed crystal 99, and extend substantially linearly in accordance with the size of the diameter of the ingot 900 (the diameter of the wafer). By slicing the ingot 900, a plurality of wafers 9 (9A, 9B) are cut out from the ingot 900.

[0013] For example, wafer 9 has an identification number corresponding to its distance from the seed crystal 99 in order to determine its position within the ingot 900. For example, wafer 9A has an identification number ID <m>Wafer 9B has an identification number ID <n>It has the following properties: m and n are integers greater than or equal to 1, where m has a value different from n.

[0014] Identification number ID <m>The wafer 9A is used for inspection of through-dislocations 999 within the wafer. Furthermore, within the ingot 900 from which multiple wafers 9 are cut, a certain identification number ID <m>Other wafers besides wafer 9A do not need to be photographed by the imaging device 1. Identification number ID in ingot 900 <m>The portion of the wafer 9 that does not correspond to the specified location is called the uninspected area 910. The wafer 9 cut out from the uninspected area 910 is excluded from the imaging device 1.

[0015] Figure 3 is a schematic diagram illustrating wafer 9. In Figure 3, the top surface (XY plane) of wafer 9 is shown as viewed from the growth direction (Z direction) of the ingot (wafer). Wafer 9 may be either a bulk wafer (semiconductor substrate) cut and polished from an ingot 900, or an epitaxial wafer on which a semiconductor layer that will become part of a semiconductor device is formed by epitaxial growth. In Figure 3, a chip area 950 based on chip layout information and an orientation flat 9f indicating a predetermined direction are hypothetically shown. Orientation flat is an abbreviation for orientation flat. Wafer 9 contains multiple chip areas 950. A dicing area 959 is provided within wafer 9 so as to surround the chip areas 950. By dicing wafer 9 along the dicing area 959, the chip areas 950 become independent as individual semiconductor chips (semiconductor devices). Furthermore, through-dislocations 999 located directly beneath or near the active region where semiconductor devices (MOSFETs, IGBTs, etc.) are formed within the chip area 950 pose a high risk of causing semiconductor device failure. In contrast, through-dislocations 999 located within the wafer 9 in areas that do not contribute to the characteristics of the power device (e.g., the element isolation region or dicing area 959) pose a low risk of causing semiconductor device failure.

[0016] Figure 4 is a schematic diagram illustrating the orientation of wafer 9. In Figure 4(a), the wafer 9 is shown with its top surface (XY plane) viewed from the growth direction (Z direction), similar to Figure 3. In the SiC wafer 9, one X direction perpendicular to the Z direction is designated as [11-20], and the Y direction perpendicular to both the Z and X directions is designated as [-1100]. In this case, the angle with respect to the X direction on the XY plane and the direction within wafer 9 can be represented in correspondence. For example, an angle of 0° with respect to the X direction on the XY plane can be represented as the [11-20] direction. In Figure 4, the "-" symbol in the [11-20] direction indicates a bar placed above the number "2" immediately following the "-". This is also true for the notation of other directions.

[0017] Furthermore, an angle of 30° relative to the X direction on the XY plane can be represented as the [01-10] direction. Similarly, angles of 60°, 90°, 120°, 150°, 180°, 210°, 240°, 270°, 300°, and 330° relative to the X direction on the XY plane can be represented as the [-12-10] direction, the [-1100] direction, the "-2110" direction, the "-1010" direction, the "-1-120" direction, the "0-110" direction, the "1-210" direction, the "1-100" direction, the "2-1-10" direction, and the "10-10" direction, respectively. The "1-100" direction corresponding to the angle 270° is the direction indicated by orientation flat 9f. Also, the angle 360° can be represented as the [11-20] direction, just like the angle 0°. Such angles and directions can be converted as needed, for example, by pre-associating them and setting them in storage 24.

[0018] The direction [2-1-10] corresponding to the angle 300° may also be called the a1 axis direction. Similarly, the direction [-12-10] corresponding to the angle 60° may also be called the a2 axis direction. The direction [-1-120] corresponding to the angle 180° may also be called the a3 axis direction. The a1, a2, and a3 axes intersect each other at an angle of 120 degrees on the same plane. There is also a c axis (not shown) that is perpendicular to the intersections of the a1, a2, and a3 axes. In Figure 4(a), the notation a1, a2, a3 axes, and hexagons correspond to the fact that SiC is a hexagonal crystal.

[0019] In Figure 4(b), the direction

[0001] is tilted by an off-angle from the Z direction to the opposite side of the [11-20] direction. Since the off-angle is approximately 4°, the direction

[0001] is essentially aligned with the Z direction. This concludes the explanation of wafer 9 and ingot 900.

[0020] Returning to Figure 1, computer 2 performs various calculations based on the image of the captured wafer 9. Based on the image of the wafer 9, computer 2 uses various information in database 3 to inspect the wafer 9. Computer 2 can control the imaging device 1 and database 3.

[0021] Database 3 stores various types of information. For example, Database 3 can store information related to imaging by imaging device 1 and data related to calculations performed by computer 2. Database 3 is accessed by computer 2 for analysis and calculations. Database 3 is, for example, external storage for computer 2. Database 3 may also be provided from a server.

[0022] Figure 5 is a schematic diagram showing an example of the configuration of the imaging device 1.

[0023] In this embodiment, the imaging apparatus 1 includes a reflective X-ray topography (XRT) apparatus 1xrt. This X-ray topography apparatus 1xrt includes two X-ray sources 10, two sensors 12, two slits 15, a vacuum chuck 17, and a control unit 19. Of the two X-ray sources 10, two sensors 12, and two slits 15, the X-ray sources 10, sensors 12, and slits 15 located above the wafer 9 are mechanisms for performing reflective X-ray topography measurements on the surface of the wafer 9. The X-ray sources 10, sensors 12, and slits 15 located below the wafer 9 are mechanisms for performing reflective X-ray topography measurements on the back surface of the wafer 9.

[0024] The wafer 9 is placed on the vacuum chuck 17 and held in place by suction. The vacuum chuck 17 is controlled by the control unit 19 and maintains its position in the wafer 9 until the imaging of both the front and back surfaces of the wafer 9 is completed.

[0025] Each of the two slits 15 is located between each of the two X-ray sources 10 and the vacuum chuck 17. Each slit 15 focuses the X-rays from each X-ray source 10 into a sheet-like shape.

[0026] Each of the two X-ray sources 10 irradiates the wafer 9 on the vacuum chuck 17 with X-rays through its respective slit 15. The X-rays are incident on the wafer 9 at Bragg diffraction angles. The X-rays are diffracted in the wafer 9 to satisfy the Bragg diffraction conditions.

[0027] Each of the two sensors 12 detects diffracted X-rays from the wafer 9. For example, an X-ray CCD camera is used as each sensor 12. CCD is an abbreviation for charge-coupled device.

[0028] The control unit 19 is controlled by the computer 2 and controls two X-ray sources 10, two sensors 12, two slits 15, and a vacuum chuck 17. The control unit 19 scans the entire area of ​​the wafer 9 or a representative area within the wafer 9 by controlling each part. Based on the output of the sensor 12 regarding the area scanned on the back surface of the wafer 9, the control unit 19 generates an X-ray topography image of the back surface of the wafer 9. The control unit 19 also generates an X-ray topography image of the front surface of the wafer 9 based on the output of the sensor 12 regarding the area scanned on the front surface of the wafer 9. Each X-ray topography image shows the result of defect inspection of the X-ray reflection surfaces (front and back surfaces) of the wafer 9. The X-ray topography images may also be generated by the computer 2 after receiving the detection results from the imaging device 1.

[0029] The imaging device 1 detects through-dislocations 999 contained in the SiC wafer 9 based on an X-ray topography image. The through-dislocations 999 include various defects such as through-helical dislocations (TSDs) and mixed dislocations (TMDs). A mixed dislocation is a dislocation that is a mixture of a through-helical dislocation (TSD) and other dislocations. Other dislocations include through-edge dislocations (TEDs) or basal dislocations (BPDs).

[0030] Furthermore, if the imaging device 1 can detect defects in the wafer 9 (e.g., through-dislocations), the wafer 9 may be imaged by destructive testing. For example, the imaging device 1 may image the wafer 9 using the etch-pit method, in which the wafer 9 is etched in advance before imaging. Alternatively, in addition to the etch-pit method, the imaging device 1 may image the wafer 9 using an optical microscope instead of the X-ray topography device 1xrt.

[0031] Figure 6 is a block diagram showing an example configuration of the computer 2 of the semiconductor inspection apparatus 100. The computer 2 includes a processing circuit 21, ROM (Read Only Memory) 22, RAM (Random Access Memory) 23, storage 24, input interface 25, display 26, and communication interface 27.

[0032] The processing circuit 21 is a processor capable of executing various programs (software, applications). The processing circuit 21 performs computational processing using various information, various data, various signals, and various parameters. The processing circuit 21 controls the operation of ROM 22, RAM 23, storage 24, input interface 25, display 26, and communication interface 27. The processing circuit 21 includes, for example, a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit). By executing a program, such a processing circuit 21 performs processing for each function, such as acquisition function 211, detection function 212, analysis function 213, classification function 214, and management function 215. Note that the division of processing for each function is an example and may be changed as appropriate. For example, part or all of the classification function 214 may be included in the analysis function 213 or the management function 215. In other words, since the processing of each function is still performed by the processing circuit 21, the division of processing may be changed as appropriate.

[0033] Here, the acquisition function 211 acquires an image of the wafer 9 by photographing the wafer 9 with the imaging device 1. The image of the wafer 9 includes an X-ray topographic image of the back surface of the wafer 9 and an X-ray topographic image of the front surface of the wafer 9. The acquisition function 211 may acquire images of the back surface and the front surface by maintaining the state in which the imaging device 1 holds the wafer 9 and photographing the back surface and the front surface of the wafer 9, respectively. The imaging device 1 and the acquisition function 211 are examples of an acquisition unit. The acquisition unit referred to here includes an X-ray topography device 1xrt, and is configured so that the acquisition function 211 acquires an image of the wafer 9 when the X-ray topography device 1xrt photographs the wafer 9. Furthermore, the acquisition function 211 may, as appropriate, save the acquired image of the wafer 9 to memory such as RAM 23 or storage 24, or to database 3.

[0034] The detection function 212 detects the first coordinate of a penetrating dislocation appearing on the back surface of the wafer 9 and the second coordinate of a penetrating dislocation appearing on the front surface of the wafer 9, based on the image acquired by the acquisition function 211. The detection function 212 may detect the first coordinate based on an image of the front surface of the wafer 9, or it may detect the second coordinate based on an image of the back surface of the wafer 9. The detection function 212 is an example of a detection unit.

[0035] The analysis function 213 analyzes the inclination of the dislocation line of the penetrating dislocation 999 with respect to the thickness direction of the wafer 9, based on the first and second coordinates detected by the detection function 212 and the thickness of the wafer 9. The analysis function 213 may further analyze the extension direction of the dislocation line based on the first and second coordinates. The analysis function 213 may predict the third coordinate of the penetrating dislocation 999 appearing on the back surface of another wafer 9 cut from the same ingot 900 from which wafer 9 was cut, and the fourth coordinate of the penetrating dislocation 999 appearing on the front surface of the other wafer 9, based on the first and second coordinates and the extension direction of the dislocation line. The analysis function 213 is an example of an analysis unit.

[0036] The classification function 214 classifies the penetration dislocations 999 based on the analysis results of the analysis function 213. The classification function 214 may classify the penetration dislocations according to whether the slope indicated by the analysis results is within a threshold range. The classification function 214 may further classify the penetration dislocations 999 according to which of several directional ranges the extension direction indicated by the analysis results falls into. The classification function 214 may classify whether the penetration dislocations 999 are mixed dislocations based on an image of the wafer 9, and further classify the penetration dislocations 999 by combining the classification result indicating the mixed dislocation with the classification result based on the analysis results. The classification function 214 may determine abnormal areas within the wafer 9 based on the classification result of each penetration dislocation 999 within the wafer 9. The classification function 214 may classify penetration dislocations 999 having a third coordinate and a fourth coordinate according to the classification result of penetration dislocations 999 having a first coordinate and a second coordinate. The classification function 214 is an example of a classification unit.

[0037] The management function 215 manages information about the wafer 9 by storing information about the through-dislocations 999, such as the detection results from the detection function 212, the analysis results from the analysis function 213, and the classification results from the classification function 214, in the database 3. The management function 215 may also manage the distribution and density of the through-dislocations 999 on the wafer 9 by statistically processing the information about the through-dislocations 999 in the database 3.

[0038] ROM22 is a non-volatile semiconductor memory. ROM22 stores programs and control data for controlling computer 2.

[0039] RAM23 is a volatile semiconductor memory. RAM23 is used as a working area for the processing circuit 21. RAM23 temporarily stores various data and parameters used in the processing of the processing circuit 21.

[0040] The storage device 24 is a non-volatile storage device such as an HDD (Hard Disk Drive), SSD (Solid State), or memory card. The storage device 24 stores various types of information, data, and parameters. The storage device 24 has a database composed of a collection of certain types of data. Program and control data may also be stored in the storage device 24. For example, the storage device 24 stores a program PG about an inspection method performed by the semiconductor inspection apparatus 100. The inspection method here includes, for example, acquiring an image of the wafer 9 by photographing the wafer 9, detecting the first coordinates of the penetration dislocations 999 appearing on the back surface of the wafer 9 and the second coordinates of the penetration dislocations 999 appearing on the front surface of the wafer 9 based on the image, analyzing the slope of the dislocation lines of the penetration dislocations 999 with respect to the thickness direction of the wafer 9 based on the first and second coordinates and the thickness of the wafer 9, and classifying the penetration dislocations 999 based on the analysis results. The program PG may be stored in the ROM 22. In any case, the program (PG) is stored on a non-transitory computer-readable storage medium.

[0041] The input interface 25 receives various operation inputs from the user. The input interface 25 can include a keyboard, mouse, various switches, touchpad, touch panel display, etc. Electrical signals corresponding to the received operation inputs (hereinafter referred to as operation signals) are supplied to the processing circuit 21.

[0042] The display 26 displays various data, such as an image of the wafer 9, according to the control of the processing circuit 21. The display 26 can be a CRT (Cathode-Ray Tube) display, a liquid crystal display, an organic EL (Electro-Luminescence) display, an LED (Light-Emitting Diode) display, a plasma display, or any other suitable display.

[0043] The communication interface 27 includes various connectors, various ports, signal processing circuits, and communication modules. The communication interface 27 connects the computer 2 to the imaging device 1 and the database 3. The communication interface 27 sends control signals from the processing circuit 21 to the imaging device 1 and the database 3. The communication interface 27 sends information from the imaging device 1 (e.g., images of wafer 9) and information from the database 3 to the processing circuit 21.

[0044] Figure 7 shows an example of the configuration of the database 3 of the semiconductor inspection apparatus 100. The database 3 includes chip layout information 31, pattern layout information 32, process information 33, distance information 34, and wafer information 35.

[0045] The chip layout information 31 is information regarding the layout of chip areas within the wafer 9. A chip area is a region within the wafer 9 that corresponds to chips that are individualized by dicing the wafer 9.

[0046] The pattern layout information 32 includes information about the layout (coordinates) of various patterns arranged within the chip area on the wafer 9. For example, the pattern layout information 32 includes information about the layout of active regions (e.g., diffusion layer patterns or impurity semiconductor region patterns), information about the layout of gate patterns, and information about the layout of wiring patterns.

[0047] Process information 33 includes information on manufacturing processes such as ion implantation, film deposition, and etching. The various manufacturing process information included in the process information is linked to the pattern layout included in the pattern layout information.

[0048] Distance information 34 is information regarding the distance from the seed crystal side end of the ingot to the target wafer 9 in the growth plane direction of the ingot. For example, the distance from the end of the ingot to the target wafer 9 is determined based on the thickness of the wafer 9 and the position of the wafer 9 within the ingot.

[0049] The wafer information 35 includes the ingot number, the identification number of the wafer 9, the dislocation coordinates on the back surface, the dislocation coordinates on the front surface, the slope of the dislocation line, the extension direction of the dislocation line, grouping information for each feature, the distribution of killer TSDs, and the density of killer TSDs. The ingot number is the number that identifies the ingot from which the wafer 9 was cut. The identification number of the wafer 9 is the number that identifies each wafer 9 cut from the ingot. The dislocation coordinates on the back surface are the coordinates (first coordinates) that indicate the location of the penetrating dislocations that appeared on the back surface of the wafer 9. The dislocation coordinates on the front surface are the coordinates (second coordinates) that indicate the location of the penetrating dislocations that appeared on the front surface of the wafer 9. The back surface of the wafer 9 is the side of the wafer 9 that faces the seed crystal side in the ingot. The front surface of the wafer 9 is the side opposite to the back surface of the wafer 9, and is the side that was formed by crystal growth later than the back surface of the wafer 9. Therefore, penetrating dislocations in the wafer 9 are formed by propagation in a substantially linear manner from the back surface to the front surface of the wafer 9 with various slopes. The dislocation line slope is the slope of the through-dislocation with respect to the thickness direction of the wafer 9. The thickness direction of the wafer 9 is the direction of crystal growth of the ingot and the direction of the shortest distance connecting identical coordinates between the back and front surfaces of the wafer 9. The extension direction of the dislocation line may be the direction in which the dislocation line of the through-dislocation extends within the ingot, but in this embodiment, it is managed as the direction projected onto the surface of the wafer 9 from the direction in which the dislocation line extends within the ingot. The grouping information for each feature is information that groups through-dislocations into specific patterns for each feature, such as specific patterns indicating the magnitude of the dislocation line slope or specific patterns indicating the extension direction. A killer TSD is a through-helix dislocation (TSD) that has killer properties that have a fatal adverse effect on the semiconductor device formed on the wafer 9. Fatal adverse effects include, for example, failure or malfunction due to current leakage. According to the inventor's research, the locations where current leakage occurs tend to coincide approximately with a specific range of slopes with respect to the thickness direction of the wafer 9. In other words, through-dislocations that propagate perpendicular to the surface and back surfaces of wafer 9 with an inclination ranging from +θ1 to -θ2 tend to be related to current leakage. Therefore, from the viewpoint of identifying killer TSDs among various through-dislocations, it is preferable to classify, for example, through-dislocations whose dislocation line inclination falls within a specific threshold range.The distribution of killer TSDs is information indicating a certain region within wafer 9 or the entire wafer where killer TSDs are distributed. The density of killer TSDs is a value indicating the density of killer TSDs (cm⁻²) (^ is a symbol representing exponentiation), and is the number of killer TSDs per square centimeter on wafer 9. Note that the density of killer TSDs may be included in the distribution of killer TSDs. In this case, the distribution of killer TSDs will be information indicating the density of killer TSDs in a certain region within wafer 9 or the entire wafer. Furthermore, the distribution of killer TSDs may be represented by mapping it onto wafer 9, as shown in Figure 3, by combining it with chip layout information 31, for example. The distribution and density of killer TSDs are generated by the management function 215 of the processing circuit 21 statistically processing information regarding the number and coordinates of penetration dislocations 999 that indicate a specific pattern of killer TSDs in the database 3.

[0050] Database 3 may also be stored in the internal storage 24 of computer 2.

[0051] Next, an example of the operation of the semiconductor inspection apparatus 100 configured as described above will be explained using the flowchart in Figure 8 and the schematic diagrams in Figures 9 to 13.

[0052] (Step ST10) The imaging device 1 of the semiconductor inspection apparatus 100 starts imaging the wafer 9 upon receiving a control signal from the computer. The control unit 19 of the imaging device 1 scans the entire area of ​​the wafer 9 or a representative area within the wafer 9 held in the vacuum chuck 17 by controlling the two X-ray sources 10, two sensors 12, and two slits 15. The vacuum chuck 17 maintains its position holding the wafer 9 until imaging of both the front and back surfaces of the wafer 9 is completed.

[0053] After scanning, the control unit 19 generates an image g1 of the back surface of the wafer 9 based on the output of the sensor 12 regarding the scanned area on the back surface of the wafer 9, as shown in Figure 9. The control unit 19 also generates an image g2 of the front surface of the wafer 9 based on the output of the sensor 12 regarding the scanned area on the front surface of the wafer 9. The control unit 19 then sends the generated images g1 and g2 to the computer 2. The processing circuit 21 of the computer 2 acquires the image of the wafer 9. Note that the image g1 of the back surface and the image g2 of the front surface have the same Y direction and opposite X directions in the XY plane.

[0054] (Step ST20) The processing circuit 21 detects the coordinates of the through-dislocations 999 on both sides of the wafer 9 based on the images g1 and g2 acquired in step ST10. For example, the processing circuit 21 aligns the coordinate systems of images g1 and g2 by inverting the image g1 of the back side around the Y-axis along the Y direction. Then, based on image g1, the processing circuit 21 detects the first coordinate P1(x1, y1) of the through-dislocation 999 that appeared on the back side of the wafer 9. The processing circuit 21 also detects the second coordinate P2(x2, y2) of the through-dislocation 999 that appeared on the front side of the wafer 9 based on image g2. Then, the processing circuit 21 generates a composite image g3 by combining images g1 and g2 of the same coordinate system. Note that the processing from step ST30 onward can be performed based on the first and second coordinates, so it is not always necessary to generate the composite image g3. The following illustration of the composite image g3 is provided for ease of understanding. Furthermore, the processing circuit 21 stores the detection result from step ST20 in the wafer information 35 of the database 3.

[0055] (Step ST30) Based on the detection results of step ST20, the processing circuit 21 analyzes the slope and extension direction of the dislocation lines of the penetrating dislocations in the wafer 9. For example, as shown in the upper part of Figure 10 and equation (1), the processing circuit 21 calculates the length L between the first coordinate P1(x1,y1) and the second coordinate P2(x2,y2) in the XY plane of the wafer 9.

[0056] L={(x2-x1)^2+(y2-y1)^2}^(1 / 2) ···(1) Furthermore, the processing circuit 21 calculates the slope θ of the dislocation line of the penetrating dislocation 999 with respect to the thickness direction Td of the wafer 9, based on the length L and the thickness d of the wafer 9, as shown in the lower part of Figure 10 and equation (2).

[0057] θ = tan⁻¹(L / d) ... (2) Furthermore, the processing circuit 21 calculates the angle φ of the penetrating dislocation with respect to the X direction on the XY plane, based on the first coordinate P1(x1,y1) and the second coordinate P2(x2,y2), as shown in Figure 11 and equation (3).

[0058] φ=tan^-1{(y2-y1) / (x2-x1)} ···(3) The angle φ of the penetrating dislocation corresponds to the extension direction of the penetrating dislocation and can be expressed, for example, as the [01-10] direction within the wafer 9. Based on this, the processing circuit 21 analyzes the extension direction of the penetrating dislocation 999 projected onto the XY plane from the angle φ of the penetrating dislocation 999 projected onto the XY plane. The processing circuit 21 may analyze either the slope θ of the dislocation line or the extension direction first. Furthermore, the analysis of the extension direction is not necessarily required and may be omitted. The processing circuit 21 also saves the analysis results of step ST30 to the wafer information 35 in the database 3.

[0059] (Step ST40) The processing circuit 21 classifies the through-dislocations 999 in the wafer 9 based on the analysis results of step ST30. For example, as shown in Figure 12, the processing circuit 21 may classify the through-dislocations 999a to 999d depending on whether the slope θ shown in the analysis results is within a threshold range. In this case, the processing circuit 21 classifies the through-dislocations 999b and 999c, which have a small slope θ, into a specific pattern Pt1. The processing circuit 21 may classify the remaining through-dislocations 999a and 999d into other specific patterns, or it may not classify them at all.

[0060] Furthermore, the processing circuit 21 may further classify the through-dislocations 999 according to which of the multiple directional ranges the stretching direction indicated by the analysis result falls into. The processing circuit 21 may also classify whether the through-dislocations 999 are mixed dislocations based on an image of the wafer 9, and further classify the through-dislocations 999 by combining the classification result indicating a mixed dislocation with the classification result based on the analysis result. The processing circuit 21 may also identify abnormal areas within the wafer 9 based on the classification result of each through-dislocation 999 within the wafer 9. Finally, the processing circuit 21 stores the classification result from step ST40 in the wafer information 35 of the database 3.

[0061] (Step ST50) The processing circuit 21 predicts the coordinates of the through-dislocation 999 on another wafer 9 based on the results of steps ST20 and ST30 on one wafer 9. For example, based on the first coordinates P1(x1,y1) and second coordinates P2(x2,y2) of the through-dislocation 999 on one wafer 9 and the direction of extension of the dislocation line of the through-dislocation 999, the processing circuit 21 predicts the third coordinates P3(x3,y3) of the through-dislocation 999 appearing on the back surface of another wafer 9 and the fourth coordinates P4(x4,y4) of the through-dislocation 999 appearing on the front surface of the other wafer 9.

[0062] For example, as shown on the left side of Figure 13, suppose one wafer 9 is wafer 9A and another wafer 9 is wafer 9B. Also, in the ingot 900, suppose that the distance D between the front surface of wafer 9A and the back surface of wafer 9B is n times the thickness d of wafer 9A.

[0063] On the other hand, when wafer 9A has a thickness of d, as shown on the right side of Figure 13, the distance between the first coordinate P1(x1,y1) and the second coordinate P2(x2,y2) in the XY plane of wafer 9A is L. That is, when wafer 9 has a thickness of d, the penetrating dislocation 999 propagates by a length of L. Consequently, when the distance between wafers 9A and 9B is D (=d·n), the penetrating dislocation 999 is stretched by a length of E. In this case, since d:L=D:E, the stretched length E is given by equation (4).

[0064] E = L·n ···(4) Here, length E represents the length between the second coordinate P2(x2,y2) on the surface of wafer 9A and the third coordinate P3(x3,y3) on the back surface of wafer 9B when the penetrating dislocation 999 is extended along the stretching direction [01-10] or angle φ on wafer 9. That is, the third coordinate P3(x3,y3) on the back surface of another wafer 9B is predicted to be the position extended by length E along the stretching direction from the second coordinate P2(x2,y2) on the surface of a certain wafer 9A. Specifically, for example, the third coordinate P3(x3,y3) may be calculated as x3=x2+E·cosφ and y3=y2+E·sinφ. Alternatively, from the viewpoint of reducing calculation errors related to the angle φ, the third coordinate P3(x3,y3) may be calculated as shown in equation (5).

[0065] x3 = (x2 - x1) * n + x2 y3 = (y2 - y1)·n + y2 ···(5) Furthermore, the fourth coordinate P4(x4,y4) on the surface of wafer 9B is predicted to be the position obtained by extending a length L along the stretching direction from the third coordinate P3(x3,y3). The fourth coordinate P4(x4,y4) may also be determined as shown in equation (6).

[0066] x4=(x2-x1)+x3 y4 = (y2 - y1) + y3 ... (6) Furthermore, the processing circuit 21 associates the prediction results (third and fourth coordinates) from step ST50 with the identification number of another wafer 9B and stores them in the wafer information 35 of the database 3. Note that the slope and extension direction of the dislocation lines for the third and fourth coordinates on another wafer 9B are the same as the slope and extension direction of the dislocation lines for the first and second coordinates on a certain wafer 9A, so there is no need to analyze them. Therefore, the processing circuit 21 stores the analysis results for another wafer 9B in the wafer information 35 by copying the analysis results for a certain wafer 9A. After that, the processing circuit 21 terminates the process.

[0067] As described above, according to the first embodiment, the processing circuit 21 acquires images g1 and g2 of the wafer 9 when the imaging device 1 photographs the wafer 9. Based on the images g1 and g2, the processing circuit 21 detects the first coordinate P1(x1, y1) of the penetrating dislocation 999 appearing on the back surface of the wafer 9 and the second coordinate P2(x2, y2) of the penetrating dislocation 999 appearing on the front surface of the wafer 9. Based on the first and second coordinates and the thickness d of the wafer 9, the processing circuit 21 analyzes the slope φ of the dislocation line of the penetrating dislocation 999 with respect to the thickness direction Td of the wafer 9. Based on the analysis results, the processing circuit 21 classifies the penetrating dislocation 999. In this way, by analyzing the slope of the dislocation line from the first coordinate of the penetrating dislocation appearing on the back surface of the wafer and the second coordinate of the penetrating dislocation appearing on the front surface of the wafer based on images of the wafer, the slope of the dislocation line in the wafer can be grasped over a wide range because the depth of the sample is not measured.

[0068] Furthermore, according to the first embodiment, the processing circuit 21 may classify through-dislocations according to whether the slope θ shown in the analysis result is within the range of thresholds θ1 to θ2. In this case, for example, through-dislocations whose slope θ of the dislocation line is within the threshold range can be classified as highly killer specific patterns that have a fatal impact on semiconductor devices. Also, since it is possible to classify through-dislocations that are within the threshold range, it becomes possible to manage the distribution of specific highly killer through-dislocations rather than the distribution of all through-dislocations. This can be used for quality evaluation and defect inspection during the manufacturing of semiconductor devices to improve yield. For example, by discarding semiconductor devices using chip areas where highly killer through-dislocations are located during pre-shipment inspection, the occurrence of defective semiconductor devices can be reduced. This is not limited to classification results based on analysis results showing that the slope θ is within the threshold range, but is also true for other analysis results that correspond to the classification results of specific highly killer patterns.

[0069] Furthermore, according to the first embodiment, the processing circuit 21 may further analyze the extension direction of the dislocation line based on the first and second coordinates. In this case, through dislocations can be classified with respect to the extension direction of the dislocation line. Also, through dislocations can be classified with respect to the combination of the slope of the dislocation line and the extension direction of the dislocation line.

[0070] Furthermore, according to the first embodiment, the processing circuit 21 may further classify the through-dislocations according to which of the multiple directional ranges the extension direction indicated by the analysis result falls into. In this case, the through-dislocations can be managed according to each of the multiple directional ranges.

[0071] Furthermore, according to the first embodiment, the processing circuit 21 may classify whether or not a through-dislocation is a mixed dislocation based on the image, and further classify the through-dislocation by combining the classification result indicating a mixed dislocation with the classification result based on the analysis result. In this case, for example, by combining the classification result indicating a mixed dislocation with the classification result indicating that the slope of the dislocation line is within a threshold range, the through-dislocation can be classified into a specific pattern with extremely high killer properties.

[0072] Furthermore, according to the first embodiment, the processing circuit 21 may determine abnormal areas within the wafer based on the classification result of each penetration dislocation within the wafer. In this case, for example, an area can be identified as an abnormal area if the number of penetration dislocations with a highly killer classification result exceeds a threshold.

[0073] Furthermore, according to the first embodiment, the processing circuit 21 may predict the third coordinate of a penetrating dislocation appearing on the back surface of a different wafer 9B, which is cut from the same ingot 900 as wafer 9A, and the fourth coordinate of a penetrating dislocation appearing on the front surface of the other wafer 9B, based on the first and second coordinates and the extension direction of the dislocation line. In this case, the burden of photographing and analyzing the wafer to be predicted among all wafers 9 can be reduced. In addition, the wafer 9 to be photographed can be subjected to destructive testing as well as non-destructive testing. Furthermore, wafer 9A may be the side farther from the seed crystal 99, not just the side closer to the seed crystal 99. In this case, the other wafer 9B will be the side closer to the seed crystal 99. That is, the third and fourth coordinates of the penetrating dislocation 999 on the other wafer 9B, which is closer to the seed crystal 99, may be predicted from the first and second coordinates of the penetrating dislocation 999 on wafer 9A, which is farther from the seed crystal 99. Alternatively, the third and fourth coordinates of a penetrating dislocation 999 in another wafer between the two wafers 9A and 9B may be predicted from the first and second coordinates of the penetrating dislocation 999 in each of the two wafers 9A and 9B, which are cut from separate locations.

[0074] Furthermore, according to the first embodiment, the processing circuit 21 may classify through-dislocations having third and fourth coordinates in another wafer 9B in accordance with the classification results of through-dislocations having first and second coordinates in a certain wafer 9A. In this case, analysis of the slope and extension direction of the dislocation line based on the third and fourth coordinates can be omitted. To elaborate, due to the property of through-dislocations to propagate in a substantially linear manner, it is estimated that the slope and extension direction of the predicted through-dislocations having third and fourth coordinates are substantially the same as the slope and extension direction of the through-dislocations having first and second coordinates used in the prediction. Therefore, it is not necessary to analyze the slope and extension direction of the dislocation line with respect to the predicted third and fourth coordinates, and such analysis can be omitted.

[0075] Furthermore, according to the first embodiment, the imaging device 1 maintains a state of holding the wafer 9 and images the back surface and front surface of the wafer 9, thereby enabling the processing circuit 21 to acquire images of the back surface and the front surface of the wafer 9. The processing circuit 21 may detect a first coordinate based on the back surface image and a second coordinate based on the front surface image. In this case, since the wafer 9 is not released and re-held during imaging, the positional shift of the coordinate system between the back surface image and the front surface image can be reduced. In addition, by measuring both sides of the wafer with reflective XRT while the wafer 9 is held in place by suction, the coordinate accuracy necessary for calculating the slope of dislocation lines can be maintained. For example, the positional shift of the coordinate system between the back surface image and the front surface image can be expected to be 10 μm or less, preferably 1 μm or less. In contrast, in conventional reflective XRT, if the surface of a suction-fixed wafer is measured, the suction fixation is released, the wafer is transported and turned over, and then the wafer is suction-fixed again and the surface of the wafer is measured, the positional shift of the coordinate system becomes approximately 100 μm. In other words, conventional reflection XRT has a large displacement of the coordinate system, making it impossible to maintain the coordinate accuracy necessary for calculating the slope of the displacement line.

[0076] Furthermore, according to the first embodiment, the acquisition unit including the imaging device 1 and the acquisition function 211 may include an X-ray topography device 1xrt, and images g1 and g2 of the wafer 9 may be acquired by the X-ray topography device 1xrt imaging the wafer 9. In this case, images of the wafer can be captured and acquired using an X-ray topography device, which is one of any imaging devices capable of imaging a wafer.

[0077] <First modified example of the first embodiment> The first embodiment includes, but is not limited to, an X-ray topography apparatus 1xrt with two X-ray sources 10, two sensors 12, and two slits 15. For example, as shown in Figure 14, the X-ray topography apparatus 1xrt may be configured with one X-ray source 10, one sensor 12, and one slit 15. In this case, the control unit 19 may switch between the first and second configurations by rotating the X-ray source 10, sensor 12, and slit 15 around a rotation axis Ry along the Y direction in the wafer 9, for example, via a drive unit (not shown). Here, the first configuration is one in which the X-ray source 10, sensor 12, and slit 15 located above the wafer 9 perform reflective X-ray topography measurements on the surface of the wafer 9. The second configuration is one in which the X-ray source 10, sensor 12, and slit 15 located below the wafer 9 perform reflective X-ray topography measurements on the back surface of the wafer 9. Furthermore, the control unit 19 may raise or lower the vacuum chuck 17 as appropriate in conjunction with the change in arrangement. According to the first modified example, since only one X-ray source 10, sensor 12, and slit 15 are needed, the cost of the X-ray topography apparatus 1xrt can be reduced.

[0078] <Second variation of the first embodiment> In the first embodiment, the X-ray topography apparatus 1xrt is equipped with two X-ray sources 10, two sensors 12, and two slits 15, but is not limited thereto. For example, as shown in Figure 15, the X-ray topography apparatus 1xrt may be configured with one X-ray source 10, one sensor 12, and one slit 15. In this case, the control unit 19 may switch between imaging the front and back surfaces of the wafer 9 by inverting the vacuum chuck 17 around a rotation axis Ry along the Y direction in the wafer 9, for example, via a drive unit (not shown). The control unit 19 may also raise or lower the vacuum chuck 17 as appropriate in conjunction with the switching of the imaging surface. According to the second modification, since only one X-ray source 10, one sensor 12, and one slit 15 are needed, the cost of the X-ray topography apparatus 1xrt can be reduced. Note that the second modification assumes that the X-rays output by one X-ray source 10 are radiation, but is not limited thereto. For example, the X-rays output by one X-ray source 10 may be synchrotron radiation. In this case, the X-ray topography apparatus 1xrt can be, for example, the large synchrotron radiation facility SPring-8, which can be used as appropriate. Accordingly, the acquisition function 211 is configured not to include the imaging device 1, and is implemented as a function of the processing circuit 21 that performs the process of reading the image taken of the wafer 9 from the RAM 23 or storage 24 where the image is stored. Even with this modification, the same effects as in the first embodiment can be obtained. Note that the configuration in which the acquisition function 211 does not include the imaging device 1 may be applied to the first embodiment and its first modified example, as well as to each of the following embodiments and their modified examples.

[0079] <Second Embodiment> Next, a semiconductor inspection apparatus according to the second embodiment will be described.

[0080] The second embodiment is a modified version of the wafer image and imaging apparatus, in which a wafer 9 on which etch pits have been formed on the surface by the etch pit method is imaged with an optical microscope.

[0081] Figure 16A is a block diagram showing an example configuration of an imaging apparatus in a semiconductor inspection apparatus according to a second embodiment. This imaging apparatus 1 includes an reflected illumination type optical microscope apparatus 1pm instead of an X-ray topography apparatus 1xrt. The optical microscope apparatus 1pm includes a light source unit 41, a half mirror 42, a light receiving unit 44, a sample stage 45, and a control unit 46. The sample stage 45 holds a wafer 9 that has been treated with a chemical solution by the etch pit method.

[0082] The light source unit 41 outputs light generated by the light source and transmitted through the lens to the half mirror 42, and the light bent by the half mirror is irradiated onto the wafer 9 on the sample stage 45. The light reflected from the wafer 9 passes through the half mirror 42 and enters the light receiving unit 44. The light receiving unit 44 focuses the incident light with an objective lens, detects the resulting transmitted light with an image sensor, and outputs the detection result to the control unit 46.

[0083] The optical microscope 1pm may also be a transmitted illumination type, as shown in Figure 16B. In this case, the optical microscope apparatus 1pm comprises a light source unit 43, a light receiving unit 44, a sample stage 45, and a control unit 46. The light source unit 43 outputs parallel light generated by the light source and transmitted through a condenser lens, and irradiates the wafer 9 on the sample stage 45 with the parallel light. The parallel light transmitted through the wafer 9 is incident on the light receiving unit 44. The light receiving unit 44 focuses the incident light with an objective lens, detects the obtained transmitted light with an image sensor, and outputs the detection result to the control unit 46. However, in this embodiment, the case in which an epi-illumination type is used, as shown in Figure 16A, will be described as an example.

[0084] The control unit 46 is controlled by the computer 2 and controls the light source unit 41 (or 43), the light receiving unit 44, and the sample stage 45. The control unit 46 scans the entire area of ​​the wafer 9 or a representative area within the wafer 9 by controlling each unit. Based on the output of the light receiving unit 44 regarding the scanned area within the wafer 9, the control unit 46 generates an optical image of the wafer 9. The optical image shows the results of defect inspection on the back and front surfaces of the wafer 9. The X-ray topography image may be generated by the computer 2 after receiving the detection results from the imaging device 1.

[0085] Meanwhile, the acquisition function 211 of the processing circuit 21 acquires an image of the wafer 9 by having the optical microscope device 1pm photograph the wafer 9. The imaging device 1 and the acquisition function 211 are an example of an acquisition unit. The acquisition unit referred to here includes the optical microscope device 1pm, and is configured so that the acquisition function 211 acquires an image of the wafer 9 by having the optical microscope device 1pm photograph the wafer 9.

[0086] Here, wafer 9 has a state in which, due to etching by the etch-pit method, point-shaped first etch pits corresponding to the threading dislocations 999 are formed on the back surface, and hexagonal-shaped second etch pits corresponding to the threading dislocations 999 are formed on the front surface. The first and second etch pits are crystal defects that have been expanded by chemical treatment in the etch-pit method. The hexagonal shape of the second etch pit represents the contour of the second etch pit created by anisotropic etching. Accordingly, the optical image of wafer 9 is an image that shows the point-shaped first etch pits and the hexagonal-shaped second etch pits corresponding to the threading dislocations 999. To add to this, the X-ray topography image of wafer 9 in the first embodiment is two images in the same scan area: an image showing the front surface and an image showing the back surface. In contrast, the optical image of wafer 9 in the second embodiment is a single image that shows the front and back surfaces superimposed in the same scan area. That is, the optical image of wafer 9 is a single image in which the front and back surfaces of wafer 9 are captured together in the same coordinate system.

[0087] The detection function 212 detects the position of the first etch pit indicated by the image of the wafer 9 as the first coordinate, and the position of the second etch pit indicated by the same image as the second coordinate. For example, the detection function 212 detects the position of the midpoint of the diagonal in the hexagon as the second coordinate, and the position of the point shape as the first coordinate. If the detection function 212 does not detect the first coordinate but detects the second coordinate, it may output a detection result that includes the second coordinate but does not include the first coordinate.

[0088] In addition to the functions described above, the analysis function 213, when it receives a detection result that includes the second coordinate but does not include the first coordinate, outputs an analysis result that does not include the slope θ of the dislocation line based on that detection result.

[0089] In addition to the functions described above, the classification function 214 classifies through dislocations of dislocation lines as having insufficient etching if the analysis results do not include the slope θ of the dislocation line. The management function 215 may adjust the observation conditions, such as the focus of the optical microscope 1pm, within a predetermined range based on the classification result of insufficient etching, and send the adjustment results to the control unit 46. The control unit 46 controls each part according to the observation conditions.

[0090] The other configurations are the same as in the first embodiment.

[0091] Next, an example of the operation of the semiconductor inspection apparatus 100 configured as described above will be explained using the flowchart in Figure 8 and the schematic diagrams in Figures 17 to 24. In the following explanation, redundant parts will be omitted as appropriate.

[0092] (Step ST10) In the imaging device 1 of the semiconductor inspection apparatus 100, the control unit 19 controls the light source unit 41, the light receiving unit 44, and the sample stage 45 to scan the entire area of ​​the wafer 9 held on the sample stage 45, or a representative area within the wafer 9. The sample stage 45 maintains its position holding the wafer 9 until the imaging of the wafer 9 is complete.

[0093] After scanning, the control unit 46 generates an image of the wafer 9 based on the output of the light receiving unit 44 and sends the image to the computer 2. The processing circuit 21 of the computer 2 acquires the image of the wafer 9.

[0094] (Step ST20) The processing circuit 21 detects the coordinates of the through-dislocations 999 on both sides of the wafer 9 based on the image acquired in step ST10. For example, as shown in Figure 17, the processing circuit 21 detects the position of the first etch pit shown in image g4 of the wafer 9 as the first coordinate, and detects the position of the second etch pit shown in the same image as the second coordinate. For example, one etch pit region in image g4 is enlarged and shown in image g41, and another etch pit region is enlarged and shown in image g42. For each of images g41 and g42, the processing circuit 21 detects the position of the midpoint of the diagonal in the hexagon as the second coordinate P2(x2,y2) and the position of the point shape as the first coordinate P1(x1,y1). The first and second coordinates are detected similarly for the other etch pits in image g4. The processing circuit 21 also stores the detection results from step ST20 in the wafer information 35 of the database 3.

[0095] (Step ST30) Based on the detection results of step ST20, the processing circuit 21 analyzes the slope and extension direction of the dislocation lines of the penetrating dislocations in the wafer 9. For example, the processing circuit 21 calculates the length L between the first coordinate P1(x1,y1) and the second coordinate P2(x2,y2) in the XY plane of the wafer 9 using the equation (1) described above.

[0096] Similarly, the processing circuit 21 calculates the slope θ of the dislocation line of the penetrating dislocation 999 with respect to the thickness direction Td of the wafer 9, based on the length L and the thickness d of the wafer 9, using Figure 18 and the equation (2) described above.

[0097] In other words, even if there are etch pits on the surface of the wafer 9, as shown in Figure 18, the slope θ of the dislocation line is calculated based on the thickness d of the wafer 9 at the first coordinate P1(x1,y1) and the second coordinate P2(x2,y2), as described above. However, this is not the only method; as shown in Figure 19 and equation (2a), the slope θ of the dislocation line may also be calculated based on the value obtained by subtracting the depth Δe of the etch pit from the thickness d of the wafer 9 (d-Δe).

[0098] θ=tan^-1(L / (d-Δe)) ···(2a) The depth Δe of the etch pit is the value obtained by multiplying the etching rate by the etching time.

[0099] Next, the processing circuit 21 analyzes the extension direction of the penetrating dislocation 999 based on the first coordinate P1(x1,y1) and the second coordinate P2(x2,y2), as described above. The processing circuit 21 also saves the analysis result of step ST30 to the wafer information 35 in the database 3.

[0100] (Step ST40) The processing circuit 21 classifies the through-dislocations 999 in the wafer 9 based on the analysis results of step ST30. For example, as shown in Figures 20 and 21, the processing circuit 21 may classify the through-dislocations in the image g5 of the wafer 9 according to whether the slope θ shown in the analysis results is within a threshold range. In this case, the processing circuit 21 classifies the through-dislocations 999 with a small slope θ into specific pattern Pt1 and the through-dislocations 999 with a large slope θ into specific pattern Pt2. Furthermore, based on the detection results that include the second coordinate but do not include the first coordinate, if the analysis results do not include the slope θ of the dislocation line, the processing circuit 21 classifies the through-dislocation of that dislocation line into specific pattern Pt3. Specific pattern Pt3 is a pattern without etch pits on the back surface, indicating insufficient etching.

[0101] Furthermore, the processing circuit 21 may further classify the penetration dislocations 999 depending on which of the multiple directional ranges the extension direction indicated by the analysis result falls into. For example, as shown in Figure 22, the processing circuit 21 calculates the angle φ of the penetration dislocation extending from the first coordinate P1(x1,y1) to the second coordinate P2(x2,y2) in image g51, which is an enlarged portion of image g5, using the aforementioned equation (3). The processing circuit 21 also classifies the penetration dislocation into a specific pattern Pt12 because the extension direction [11-20] corresponding to the angle φ falls within the range between the a1 axis direction and the a2 axis direction. If the extension direction corresponding to the angle φ falls within the range between the a2 axis direction and the a3 axis direction, the processing circuit 21 classifies the penetration dislocation into a specific pattern Pt23. Similarly, if the extension direction corresponding to the angle φ falls within the range between the a3 axis direction and the a1 axis direction, the processing circuit 21 classifies the penetration dislocation into a specific pattern Pt31.

[0102] Furthermore, as shown in Figure 23, the processing circuit 21 may combine specific patterns Pt12 and Pt23 of the classification results related to the extension direction with the specific pattern Pt2 of the classification results related to the slope θ mentioned above.

[0103] Furthermore, the processing circuit 21 classifies whether the through-dislocations 999 are mixed dislocations based on the image of the wafer 9. For example, as shown in Figure 24, the processing circuit 21 determines from the shape of the etch pit in image g61, which is an enlarged portion of image g6, that the through-dislocation is a mixed dislocation TMD of a through-edge dislocation TED and a through-helic dislocation TSD, and classifies the said through-dislocation into a specific pattern Pt30. Note that the shape of the etch pit shown in Figure 24 is a contour shape that is a mixture of a roughly hexagonal shape and a roughly semicircular shape. Subsequently, the processing circuit 21 further classifies the through-dislocations 999 by combining the classification result indicating the mixed dislocation with the classification result based on the analysis result. The processing circuit 21 may also identify abnormal areas within the wafer 9 based on the classification result of each through-dislocation 999 within the wafer 9. The processing circuit 21 also stores the classification result of step ST40 in the wafer information 35 of the database 3.

[0104] (Step ST50) After step ST40, the processing circuit 21 executes step ST50 as described above and terminates the process.

[0105] As described above, according to the second embodiment, the wafer 9 has a state in which a point-shaped first etch pit corresponding to the through-dislocation 999 is formed on the back surface by etching using the etch pit method, and a hexagon-shaped second etch pit corresponding to the through-dislocation 999 is formed on the front surface. The processing circuit 21 detects the position of the first etch pit shown in the image as the first coordinate P1(x1,y1) and detects the position of the second etch pit shown in the image as the second coordinate P2(x2,y2). Therefore, even when using the etch pit method, the same effects as in the first embodiment can be obtained by having a configuration that can detect the first and second coordinates of the through-dislocation from the wafer image.

[0106] Furthermore, according to the second embodiment, the processing circuit 21 detects the position of the midpoint of the diagonal in the hexagonal shape as the second coordinate and the position of the point shape as the first coordinate. Therefore, when using the etch pit method, the variation in the detection of the second coordinate for each etch pit can be reduced by using the same method for detecting the second coordinate.

[0107] Furthermore, according to the second embodiment, if the processing circuit 21 detects the second coordinate but does not detect the first coordinate, it outputs a detection result that includes the second coordinate but does not include the first coordinate. Based on this detection result, the processing circuit 21 outputs an analysis result that does not include the slope θ of the dislocation line. If the analysis result does not include the slope θ, the processing circuit 21 classifies the through dislocation as having insufficient etching. Therefore, in the etch pit method, if there is insufficient etching, the insufficient etching can be detected.

[0108] Furthermore, according to the second embodiment, the acquisition unit including the imaging device 1 and the acquisition function 211 may include an optical microscope device 1pm, and images g4, g5, and g6 of the wafer 9 may be acquired by the optical microscope device 1pm imaging the wafer 9. In this case, images of the wafer can be captured and acquired using an optical microscope device, which is one of any imaging devices capable of imaging a wafer.

[0109] <Modified form of the second embodiment> The second embodiment uses the etch pit method and an optical microscope device 1pm, but is not limited thereto. For example, the second embodiment may be modified to use an X-ray topography device 1xrt instead of the optical microscope device 1pm while still using the etch pit method. Other configurations are the same as in the second embodiment. In this case, the processing circuit 21 detects the position of the midpoint of the diagonal in the hexagonal shape as the second coordinate based on the image of the surface of the wafer 9. The processing circuit 21 also detects the position of the point shape as the first coordinate based on the image of the back surface of the wafer 9. Even with this modification, the same effects as in the second embodiment can be obtained. Similarly, if the processing circuit 21 does not detect the first coordinate but detects the second coordinate, it outputs an analysis result that does not include the slope θ of the dislocation line based on this detection result and classifies the through dislocation as etching insufficient. Therefore, etching insufficiency in the etch pit method can be detected as described above.

[0110] According to the at least one embodiment described above, the inclination of dislocation lines within the wafer can be determined over a wide range. This is also true for the at least one modified example described above.

[0111] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0112] 1: Imaging device, 1xrt: X-ray topography device, 1pm: Optical microscope device, 2: Computer, 3: Database, 9,9A,9B: Wafer, 21: Processing circuit, 211: Acquisition function, 212: Detection function, 213: Analysis function, 214: Classification function, 215: Management function, 100: Semiconductor inspection device, 900: Ingot, 999: Penetrating dislocation, g1,g2,g4~g6: Image.< / m> < / m> < / m> < / n> < / m>

Claims

1. An acquisition unit that acquires an image of the wafer by photographing the wafer, A detection unit that detects, based on the aforementioned image, the first coordinate of a penetrating dislocation appearing on the back surface of the wafer and the second coordinate of a penetrating dislocation appearing on the front surface of the wafer, An analysis unit that analyzes the inclination of the dislocation line of the through-dislocation with respect to the thickness direction of the wafer based on the first coordinate and the second coordinate and the thickness of the wafer, Based on the analysis results, a classification unit classifies the through dislocations. A semiconductor inspection device equipped with the following features.

2. The semiconductor inspection apparatus according to claim 1, wherein the classification unit classifies the penetrating dislocations according to whether or not the slope indicated by the analysis result is within a threshold range.

3. The semiconductor inspection apparatus according to claim 1 or 2, wherein the analysis unit further analyzes the extension direction of the dislocation line based on the first coordinate and the second coordinate.

4. The semiconductor inspection apparatus according to claim 3, wherein the classification unit further classifies the through dislocations according to which of a plurality of directional ranges the extension direction indicated by the analysis result falls into.

5. The semiconductor inspection apparatus according to claim 3, wherein the classification unit classifies whether the through dislocation is a mixed dislocation based on the image, and further classifies the through dislocation by combining the classification result indicating the mixed dislocation with the classification result based on the analysis result.

6. The semiconductor inspection apparatus according to claim 3, wherein the classification unit determines an abnormal area in the wafer based on the classification result of each of the through-dislocations in the wafer.

7. The semiconductor inspection apparatus according to claim 3, wherein the analysis unit predicts, based on the first coordinates, the second coordinates, and the extension direction of the dislocation lines, a third coordinate of a through-dislocation appearing on the back surface of a wafer other than the wafer, which is cut from the same ingot as the wafer from which the wafer was cut, and a fourth coordinate of a through-dislocation appearing on the front surface of the other wafer.

8. The semiconductor inspection apparatus according to claim 7, wherein the classification unit classifies the through dislocations having the third coordinate and the fourth coordinate in accordance with the classification results of the through dislocations having the first coordinate and the second coordinate.

9. The acquisition unit acquires an image of the back surface and an image of the front surface by maintaining the wafer in a holding position and photographing the back surface and the front surface of the wafer, respectively. The detection unit detects the first coordinates based on the image of the back surface and detects the second coordinates based on the image of the front surface. The semiconductor inspection apparatus according to claim 1.

10. The wafer has a state in which, by etching by the etch pit method, point-shaped first etch pits corresponding to the through-dislocations are formed on the back surface, and hexagonal-shaped second etch pits corresponding to the through-dislocations are formed on the front surface. The detection unit detects the position of the first etch pit shown in the image as the first coordinate, and detects the position of the second etch pit shown in the image as the second coordinate. The semiconductor inspection apparatus according to claim 1.

11. The semiconductor inspection apparatus according to claim 10, wherein the detection unit detects the position of the midpoint of the diagonal in the hexagonal shape as the second coordinate and detects the position of the point shape as the first coordinate.

12. If the detection unit does not detect the first coordinate but detects the second coordinate, it outputs a detection result that includes the second coordinate but does not include the first coordinate. The analysis unit outputs an analysis result that does not include the slope, based on the detection result. The classification unit classifies the through dislocation as having insufficient etching if the analysis result does not include the slope. The semiconductor inspection apparatus according to claim 10.

13. The acquisition unit includes an X-ray topography apparatus, and the X-ray topography apparatus acquires an image of the wafer by photographing the wafer. The semiconductor inspection apparatus according to any one of claims 9 to 12.

14. The acquisition unit includes an optical microscope, and the optical microscope acquires an image of the wafer by photographing the wafer. A semiconductor inspection apparatus according to any one of claims 10 to 12.

15. A testing method performed by a semiconductor testing device, By photographing the wafer, an image of the wafer is obtained, Based on the aforementioned image, the first coordinate of the penetration dislocation appearing on the back surface of the wafer and the second coordinate of the penetration dislocation appearing on the front surface of the wafer are detected. Based on the first coordinate and the second coordinate and the thickness of the wafer, the inclination of the dislocation line of the through-dislocation with respect to the thickness direction of the wafer is analyzed, Based on the above analysis results, classify the through dislocations. A testing method that includes [a specific feature / feature].

Images