Signal generation circuit and Class AB push-pull amplifier circuit

Abstract

To generate a signal that enables Class AB push-pull operation in the output stage of an amplification circuit without using a pair of transistors with opposite polarities. [Solution] The signal generation circuit 10 includes a diode D1 to which a voltage V1 is applied to the anode, a diode D2 to which a voltage V2 is applied to the cathode, a current input node Ni provided in the current path from the cathode of diode D1 to the anode of diode D2, a voltage control unit 30 that controls voltages V1 and V2, a current detection unit 21 that outputs a signal S1 that detects the current Id1 of diode D1, and a current detection unit 22 that outputs a signal S2 that detects the current Id2 of diode D2. The voltage control unit 30 controls voltages V1 and V2 such that when the input current Ii is zero, idle currents flow as currents Id1 and Id2, and when one of currents Id1 and Id2 increases, the other decreases, and the difference between these currents becomes the input current Ii.

Description

TECHNICAL FIELD

[0001] The present invention relates to a class AB push-pull amplifier circuit.

BACKGROUND ART

[0002] A push-pull amplifier circuit performs a push-pull operation in which current flows alternately through the positive-side transistor and the negative-side transistor in the output stage, thereby amplifying and outputting each of the positive and negative half-cycles of an input signal. In the case of a class AB push-pull operation, when the positive and negative of the output signal are reversed, both the positive-side transistor and the negative-side transistor are operated, and a small idle current is caused to flow through these transistors, so that crossover distortion is reduced. This enables high-efficiency and low-distortion amplification.

[0003] Patent Document 1 describes a class AB push-pull amplifier in which bipolar transistors of different polarities are used in a circuit that generates two signals for causing two output transistors on the positive side and the negative side to perform a push-pull operation (class AB signal generation circuit). Patent Document 2 describes an example in which, in a push-pull output power amplifier provided with the class AB signal generation circuit described in Patent Document 1, single-polarity amplification elements are used as the amplification elements of the output stage instead of complementary amplification elements.

PRIOR ART DOCUMENTS

PATENT DOCUMENTS

[0004]

PATENT DOCUMENT 1

PATENT DOCUMENT 2

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] In the push-pull amplifier described in the aforementioned patent document, bipolar transistors with different polarities (npn type transistors and pnp type transistors) are used in the Class AB signal generation circuit. However, the number of available pnp type transistors (especially those with leaded terminals) is decreasing year by year, and if production of a component is discontinued, there is a problem in that new component selection and performance evaluation will be necessary.

[0006] Furthermore, bipolar transistors generally have problems such as high power loss and susceptibility to temperature drift. The collector loss of a bipolar transistor is expressed as "collector-emitter voltage × collector current," but since the collector-emitter voltage often exceeds several volts, the heat generated due to collector loss tends to be large. In the case of the Class AB signal generation circuit described in Patent Document 1, it is necessary to bring the temperatures of bipolar transistors with different polarities as close to the same as possible, but if the heat generated due to collector loss is large, it becomes difficult to match the temperatures through thermal coupling. In addition, the cost of suppressing heat generation in components and thermally coupling components together increases. This point is also true for other semiconductor elements with amplification functions such as FETs.

[0007] Furthermore, when using npn and pnp transistors as complementary transistors, as in the Class AB signal generation circuit described in Patent Document 1, the characteristics of these transistors are not perfectly symmetrical, which makes them prone to errors due to characteristic asymmetry. This is also true for semiconductor devices such as FETs.

[0008] The present invention has been made in view of these circumstances, and its object is to provide a signal generation circuit capable of generating a signal that causes a Class AB push-pull operation in the output stage of an amplifier circuit without using a pair of transistors with different polarities, and a Class AB push-pull amplifier circuit equipped with such a signal generation circuit. [Means for solving the problem]

[0009] A signal generation circuit according to a first aspect of the present invention is a signal generation circuit that generates a first signal and a second signal according to an input current, comprising: a first diode to which a first voltage is applied to the anode; a second diode to which a second voltage is applied to the cathode; a current input node provided in the current path from the cathode of the first diode to the anode of the second diode, to which input current flows in or out; a voltage control unit that controls the first voltage and the second voltage; a first current detection unit that outputs a first signal when it detects the first diode current flowing through the first diode; and a second current detection unit that outputs a second signal when it detects the second diode current flowing through the second diode, wherein the voltage control unit, when the input current is zero, controls the first diode current and This is a signal generation circuit that controls the first and second voltages so that a predetermined idle current flows through each of the two diodes as current. When the input current flowing from the current input node to the second diode increases, the first and second voltages are controlled so that the second diode current increases and the first diode current decreases, and the difference between the second diode current and the first diode current becomes the incoming input current. When the input current flowing out from the first diode to the current input node increases, the first and second voltages are controlled so that the first diode current increases and the second diode current decreases, and the difference between the first diode current and the second diode current becomes the outgoing input current.

[0010] A signal generation circuit according to a second aspect of the present invention is a signal generation circuit that generates a first signal and a second signal corresponding to an input current, comprising: a first diode to which a first voltage is applied to the anode and whose cathode is held at a reference voltage; a second diode to which the anode is held at a reference voltage and whose cathode is applied at a second voltage; a current input node to which input current flows in or out; a voltage control unit that controls the first voltage and the second voltage; a first current detection unit that outputs a first signal for detecting the first diode current flowing through the first diode; and a second current detection unit that outputs a second signal for detecting the second diode current flowing through the second diode, wherein the voltage control unit, when the input current is zero, sets the first diode current and the second diode current to predetermined values, respectively. This is a signal generation circuit that controls the first and second voltages so that an idle current flows, and controls the first and second voltages so that when the input current flowing in the first direction at the current input node increases, the second diode current increases and the first diode current decreases, and the difference between the second diode current and the first diode current is a current proportional to the input current flowing in the first direction, and controls the first and second voltages so that when the input current flowing in the second direction opposite to the first direction at the current input node increases, the first diode current increases and the second diode current decreases, and the difference between the first diode current and the second diode current is a current proportional to the input current flowing in the second direction.

[0011] A signal generation circuit according to a third aspect of the present invention, which generates a first signal and a second signal according to an input voltage, comprising a first signal output unit that outputs a first signal and a second signal output unit that outputs a second signal, wherein the first signal output unit includes a first diode provided in the forward direction in the path of current flowing from a first voltage node to which a first voltage is applied to a reference voltage node held at a reference voltage, a positive first resistor provided in series with the first diode in the path of current flowing from the first voltage node to the reference voltage node, a first voltage control unit that controls the first voltage, and a first current detection unit that outputs a first signal that detects the first diode current flowing through the first diode, wherein the second signal output unit includes a second diode provided in the forward direction in the path of current flowing from a reference voltage node to a second voltage node to which a second voltage is applied, and a resistor provided in series with the second diode in the path of current flowing from the reference voltage node to the second voltage node The signal generation circuit includes a negative first resistor, a second voltage control unit that controls a second voltage, and a second current detection unit that outputs a second signal that detects the second diode current flowing through the second diode. The first voltage control unit controls the first voltage so that a predetermined idle current flows as the first diode current when the input voltage is zero, controls the first voltage so that the first diode current increases proportionally to the input voltage when the input voltage increases in the positive direction, and controls the first voltage so that the first diode current decreases and approaches zero when the input voltage increases in the negative direction. The second voltage control unit controls the second voltage so that an idle current flows as the second diode current when the input voltage is zero, controls the second voltage so that the second diode current decreases and approaches zero when the input voltage increases in the positive direction, and controls the second voltage so that the second diode current increases proportionally to the input voltage when the input voltage increases in the negative direction.

[0012] A signal generation circuit according to a fourth aspect of the present invention, which generates a first signal and a second signal corresponding to an input current, comprising a first signal output unit that outputs a first signal and a second signal output unit that outputs a second signal, wherein the first signal output unit comprises a first diode provided in the forward direction in the path of current flowing from a first voltage node to which a first voltage is applied to a reference voltage node held at a reference voltage, a positive diode provided in the forward direction in the path of current flowing from the first voltage node to the anode of the first diode, a first current input node provided in the path of current flowing from the cathode of the positive diode to the anode of the first diode, through which a first input current flows in or out, a first current detection unit that outputs a first signal that detects the first diode current flowing through the first diode, and a first voltage supply unit that, when the first input current is zero, supplies a first voltage to the first voltage node set to flow a predetermined idle current as the first diode current. The second signal output section includes a second diode provided in the forward direction in the current path from a reference voltage node to a second voltage node to which a second voltage is applied, a negative diode provided in the forward direction in the current path from the cathode of the second diode to the second voltage node, a second current input node provided in the current path from the cathode of the second diode to the anode of the negative diode to which the second input current flows in or out, a second current detection section that outputs a second signal that detects the second diode current flowing through the second diode, and a second voltage supply section that supplies a second voltage to the second voltage node set so that an idle current flows as the second diode current when the second input current is zero, and is a signal generation circuit in which the second input current flows in the second current input node when the first input current flows in to the first current input node, and the second input current flows out from the second current input node when the first input current flows out from the first current input node.

[0013] A fifth aspect of the present invention is a Class AB push-pull amplifier circuit comprising: a signal generation circuit according to the first or second aspect of the present invention; a current output node into which output current flows in or out; a first output section that generates a current corresponding to one of the first and second signals of the signal generation circuit and causes it to flow out from the current output node; and a second output section that generates a current corresponding to the other of the first and second signals of the signal generation circuit and causes it to flow into the current output node. [Effects of the Invention]

[0014] According to the present invention, it is possible to provide a signal generation circuit capable of generating a signal that causes Class AB push-pull operation in the output stage of an amplifier circuit using diodes without using a pair of transistors with different polarities, and a Class AB push-pull amplifier circuit equipped with such a signal generation circuit. Because diodes are used, the components are readily available, the temperature can be easily matched due to the low loss, and since diodes of the same type can be used, asymmetry like that of complementary transistors does not occur. [Brief explanation of the drawing]

[0015] [Figure 1] Figure 1 shows an example of a Class AB push-pull amplifier circuit according to this embodiment. [Figure 2] Figures 2A to 2F show an example of a voltage-to-current conversion unit. [Figure 3] Figure 3 shows an example of a signal generation circuit according to the first embodiment. [Figure 4] Figures 4A to 4C show an example of a current detection unit. [Figure 5] Figures 5A to 5F show the results of simulations performed on the signal generation circuit shown in Figure 3. [Figure 6] Figure 6 shows an example of a signal generation circuit according to the second embodiment. [Figure 7] Figures 7A to 7F show the results of simulations performed on the signal generation circuit shown in Figure 6. [Figure 8]Figure 8 is a diagram showing a modification of the signal generation circuit according to the second embodiment. [Figure 9] Figure 9 is a diagram showing a modification of the signal generation circuit according to the second embodiment. [Figure 10] Figure 10 is a diagram showing an example of the signal generation circuit according to the third embodiment. [Figure 11] Figures 11A to 11F are diagrams showing the results of a simulation performed on the signal generation circuit shown in Figure 10. [Figure 12] Figure 12 is a diagram showing a modification of the signal generation circuit according to the third embodiment. [Figure 13] Figure 13 is a diagram showing a modification of the signal generation circuit according to the third embodiment. [Figure 14] Figure 14 is a diagram showing a modification of the signal generation circuit according to the third embodiment. [Figure 15] Figure 15 is a diagram showing a modification of the signal generation circuit according to the third embodiment. [Figure 16] Figure 16 is a diagram showing an example of the signal generation circuit according to the fourth embodiment. [Figure 17] Figure 17 is a diagram showing an example of the signal generation circuit according to the fifth embodiment. [Figure 18] Figure 18 is a diagram showing a modification of the signal generation circuit according to the fifth embodiment. [Figure 19] Figure 19 is a diagram showing a modification of the signal generation circuit according to the fifth embodiment. [Figure 20] Figure 20 is a diagram showing a modification of the signal generation circuit according to the fifth embodiment. [Figure 21] Figure 21 is a diagram showing a modification of the signal generation circuit according to the fifth embodiment. [Figure 22] Figure 22 is a diagram showing an example of the signal generation circuit according to the sixth embodiment. [Figure 23] Figures 23A to 23F are diagrams showing an example of a current detection unit. [Figure 24] Figure 24 is a diagram showing an example of the signal generation circuit according to the seventh embodiment. [Figure 25] Figures 25A to 25F show the results of simulations performed on the signal generation circuit shown in Figure 24. [Figure 26] Figure 26 shows a modified example of the signal generation circuit according to the seventh embodiment. [Figure 27] Figure 27 shows a modified example of the signal generation circuit according to the seventh embodiment. [Figure 28] Figure 28 shows an example of a signal generation circuit according to the eighth embodiment. [Figure 29] Figures 29A to 29F show the results of simulations performed on the signal generation circuit shown in Figure 28. [Figure 30] Figure 30 shows a modified example of the signal generation circuit according to the eighth embodiment. [Figure 31] Figure 31 shows a modified example of the signal generation circuit according to the eighth embodiment. [Figure 32] Figure 32 shows a modified example of the signal generation circuit according to the eighth embodiment. [Figure 33] Figure 33 shows a modified example of the signal generation circuit according to the eighth embodiment. [Figure 34] Figure 34 shows an example of a Class AB push-pull amplifier circuit according to the ninth embodiment. [Figure 35] Figure 35 shows an example of a signal generation circuit according to the ninth embodiment. [Figure 36] Figures 36A to 36F show the results of simulations performed on the signal generation circuit shown in Figure 35. [Figure 37] Figure 37 shows a modified example of the signal generation circuit according to the ninth embodiment. [Figure 38] Figures 38A to 38F show the results of simulations performed on the signal generation circuit shown in Figure 37. [Figure 39] Figure 39 shows a modified example of the signal generation circuit according to the ninth embodiment. [Figure 40]Figures 40A to 40F show the results of simulations performed on the signal generation circuit shown in Figure 39. [Figure 41] Figure 41 shows a modified example of the signal generation circuit according to the ninth embodiment. [Figure 42] Figures 42A to 40F show the results of simulations performed on the signal generation circuit shown in Figure 41. [Figure 43] Figure 43 shows an example of a Class AB push-pull amplifier circuit equipped with a signal generation circuit according to the tenth embodiment. [Figure 44] Figure 44 shows an example of a signal generation circuit according to the tenth embodiment. [Figure 45] Figures 45A to 45F show the results of simulations performed on the signal generation circuit shown in Figure 44. [Figure 46] Figure 46 shows a modified example of the signal generation circuit according to the tenth embodiment. [Figure 47] Figure 47 shows a modified example of the signal generation circuit according to the tenth embodiment. [Figure 48] Figures 48A to 48F show the results of simulations performed on the signal generation circuit shown in Figure 47. [Figure 49] Figure 49 shows a modified example of the signal generation circuit according to the tenth embodiment. [Figure 50] Figures 50A to 50F show the results of simulations performed on the signal generation circuit shown in Figure 49. [Figure 51] Figure 51 shows a modified example of the signal generation circuit according to the tenth embodiment. [Figure 52] Figures 52A to 52F show the results of simulations performed on the signal generation circuit shown in Figure 51. [Figure 53] Figure 53 shows an example of a signal generation circuit according to the 11th embodiment. [Figure 54] Figures 54A to 54F show the results of simulations performed on the signal generation circuit shown in Figure 53. [Figure 55] Figure 55 shows an example of a signal generation circuit according to the 11th embodiment. [Figure 56] Figure 56 shows an example of a signal generation circuit according to the 11th embodiment. [Figure 57] Figures 57A to 57F show the results of simulations performed on the signal generation circuit shown in Figure 55. [Figure 58] Figure 58 is a diagram illustrating the improvement of nonlinearity in the signal generation circuit according to the twelfth embodiment. [Figure 59] Figure 59A shows an example of a signal generation circuit according to the twelfth embodiment. Figures 59B and 59C show an example of the configuration of the voltage supply unit. [Figure 60] Figures 60A to 60F show the results of simulations performed on the signal generation circuit shown in Figure 59A. [Figure 61] Figure 61 shows an example of a signal generation circuit according to the twelfth embodiment. [Figure 62] Figures 62A to 62F show the results of simulations performed on the signal generation circuit shown in Figure 61. [Figure 63] Figure 63 shows an example of a signal generation circuit according to the twelfth embodiment. [Figure 64] Figures 64A to 64F show the results of simulations performed on the signal generation circuit shown in Figure 63. [Figure 65] Figure 65 shows an example of a signal generation circuit according to the twelfth embodiment. [Figure 66] Figures 66A to 66F show the results of simulations performed on the signal generation circuit shown in Figure 65. [Figure 67] Figures 67A to 67C show an example of the configuration of the current detection unit in the signal generation circuit according to the 13th embodiment. [Figure 68]Figure 68 shows an example of a signal generation circuit according to the 13th embodiment, and illustrates an example in which the configuration of the current detection unit in the signal generation circuit shown in Figure 16 has been changed. [Figure 69] Figure 69 is a diagram showing an example of a signal generation circuit according to the 13th embodiment, and shows an example in which the configuration of the current detection unit in the signal generation circuit shown in Figure 16 has been changed. [Figure 70] Figures 70A to 70D show an example of the configuration of the current detection unit in the signal generation circuit according to the 13th embodiment. [Figure 71] Figure 71 shows an example of a Class AB push-pull amplifier circuit equipped with a signal generation circuit according to the 14th embodiment. [Figure 72] Figure 72 shows an example of a Class AB push-pull amplifier circuit equipped with a signal generation circuit according to the 14th embodiment. [Figure 73] Figure 73 shows an example of a Class AB push-pull amplifier circuit equipped with a signal generation circuit according to the 14th embodiment. [Figure 74] Figure 74 shows an example of a Class AB push-pull amplifier circuit equipped with a signal generation circuit according to the 14th embodiment. [Figure 75] Figure 75A shows an example of an analog arithmetic circuit. Figure 75B shows an example of simulation results (C graph, D graph, F graph) of a signal generation circuit according to the 14th embodiment. [Figure 76] Figure 76A shows the simulation results of the signal generation circuit shown in Figure 3. Figures 76B and 76C show the simulation results of the signal generation circuit according to this embodiment, including the aforementioned signal generation circuit. [Figure 77] Figure 77A shows the simulation results of the signal generation circuit shown in Figure 44. Figures 77B and 77C show the simulation results of the signal generation circuit according to this embodiment, which includes the aforementioned signal generation circuit. [Figure 78]Figure 78A shows the simulation results of the signal generation circuit shown in Figure 37. Figures 78B and 78C show the simulation results of the signal generation circuit according to this embodiment, which includes the aforementioned signal generation circuit. [Figure 79] Figures 79A and 79B show an example of the configuration of a signal generation circuit according to this embodiment. [Figure 80] Figure 80A shows the simulation results of the signal generation circuit shown in Figure 89. Figures 80B and 80C show the simulation results of the signal generation circuit according to this embodiment, including the said signal generation circuit. [Figure 81] Figure 81 shows an example of a Class AB push-pull amplifier circuit equipped with a signal generation circuit according to the 15th embodiment. [Figure 82] Figure 82 shows an example of a Class AB push-pull amplifier circuit equipped with a signal generation circuit according to the 15th embodiment. [Figure 83] Figure 83A shows an example of an analog arithmetic circuit. Figure 83B shows an example of simulation results (C graph, D graph, F graph) of a signal generation circuit according to the 15th embodiment. [Figure 84] Figure 84A shows the simulation results of the signal generation circuit shown in Figure 3. Figure 84B shows the simulation results of the signal generation circuit according to this embodiment, which includes the said signal generation circuit. [Figure 85] Figure 85A shows the simulation results of the signal generation circuit shown in Figure 44. Figure 85B shows the simulation results of the signal generation circuit according to this embodiment, which includes the said signal generation circuit. [Figure 86] Figure 86A shows the simulation results of the signal generation circuit shown in Figure 37. Figure 86B shows the simulation results of the signal generation circuit according to this embodiment, which includes the said signal generation circuit. [Figure 87] Figure 87 shows an example of the configuration of a signal generation circuit according to this embodiment. [Figure 88]Figure 88A shows the simulation results of the signal generation circuit shown in Figure 89. Figure 88B shows the simulation results of the signal generation circuit according to this embodiment, which includes the said signal generation circuit. [Figure 89] Figure 89 shows an example of a Class AB push-pull amplifier circuit. [Figure 90] Figures 90A to 90F show the results of simulations performed on the comparative example shown in Figure 89. [Modes for carrying out the invention]

[0016] <First Embodiment> Hereinafter, the Class AB push-pull amplifier circuit and its signal generation circuit according to the first embodiment will be described with reference to the drawings. Figure 1 is a diagram showing an example of the Class AB push-pull amplifier circuit 1 according to this embodiment. The Class AB push-pull amplifier circuit 1 shown in Figure 1 has an input amplifier section 2, an output amplifier section 3, and negative feedback resistors Rf and Rg.

[0017] The Class AB push-pull amplifier circuit 1 in the example shown in Figure 1 is a voltage-input, voltage-output non-inverting amplifier circuit. However, the input and output configurations of the amplifier circuit in this embodiment are not limited to this example, and any configuration may be selected. For example, an inverting amplifier circuit or a voltage-input, current-output amplifier circuit may also be used.

[0018] The input amplification unit 2 includes a differential amplifier 4 and a voltage-to-current conversion unit 5. The differential amplifier 4 amplifies the voltage difference between the inverting and non-inverting inputs and outputs it as voltage Vi. The inverting input of the differential amplifier 4 is connected to a reference voltage (ground) via resistor Rg and to the output terminal Tout of the signal Sout via resistor Rf. The non-inverting input of the differential amplifier 4 is connected to the input terminal Tin of the signal Sin. The voltage-current conversion unit 5 outputs a current proportional to the voltage Vi. The current converted from the voltage Vi in the voltage-current conversion unit 5 is supplied as an input current Ii to the signal generation circuit 10 of the output control unit 3, which will be described later.

[0019] Figures 2A to 2D show examples of voltage-current conversion units 5 that perform voltage-to-current conversion using operational amplifiers. Figures 2A and 2C show circuits that perform inverting voltage-to-current conversion, while Figures 2B and 2D show circuits that perform non-inverting voltage-to-current conversion.

[0020] The voltage-to-current conversion unit 5 shown in Figure 2A comprises an operational amplifier Ua, a resistor Ra with a voltage Vi applied to one end and the other end connected to the inverting input of the operational amplifier Ua, a resistor Rb connected between the inverting input and output of the operational amplifier Ua, a resistor Rk connected between the output of the operational amplifier Ua and node No, a resistor Rj connected between the non-inverting input of the operational amplifier Ua and node No, and a resistor Rh connected between the non-inverting input of the operational amplifier Ua and the reference voltage (ground). Assuming that the resistance values ​​of resistors Ra, Rb, and Rh~Rk are represented by their respective signs, the current Ii output to node No can be roughly expressed by the following equation.

[0021] [Formula 1] Ii = -(Rb / (Ra·Rk))·Vi …(1-1) However, Rj / Rh = Rb / Ra …(1-2)

[0022] The voltage-current conversion unit 5 shown in Figure 2B is the same as the voltage-current conversion unit 5 shown in Figure 2A, but with one end of resistor Ra to which voltage Vi is applied connected to a reference voltage, and voltage Vi applied to one end of resistor Rh connected to the reference voltage. The other configurations are the same as the voltage-current conversion unit 5 shown in Figure 2A. The current Ii output to node No in the voltage-current conversion unit 5 shown in Figure 2B can be expressed by roughly the following formula.

[0023] [Formula 2] Ii = (Rb / (Ra·Rk))·Vi …(2-1) However, Rj / Rh = Rb / Ra …(2-2)

[0024] The voltage-current conversion unit 5 shown in Figures 2C and 2D is the same as the voltage-current conversion unit 5 shown in Figures 2A and 2B, respectively, with the addition of an operational amplifier Ub. The operational amplifier Ub constitutes a buffer circuit inserted between one end of resistor Rj and node No. The non-inverting input of the operational amplifier Ub is connected to node No, and the inverting input and output of the operational amplifier Ub are connected to one end of resistor Rj. By providing the buffer circuit of the operational amplifier Ub, errors from equations (1-1) and (2-1) caused by the current flowing from node No to resistor Rj are suppressed.

[0025] Figure 2E shows an example in which the voltage-to-current conversion unit 5 is implemented using a resistor Rs. A voltage Vi is applied to one end of resistor Rs, and the other end of resistor R is connected to node No. When the resistance value of resistor Rs is sufficiently large compared to the input impedance Zin of the signal generation circuit 10 that receives the current Ii, the current Ii flowing through resistor Rs is approximately proportional to the voltage Vi.

[0026] Furthermore, a circuit in which a resistor Rs is connected in series with a voltage source Vi (Figure 2F) is equivalent to a circuit in which a resistor Rs is connected in parallel with a current source Is (=Vi / Rs) (Figure 2G). Therefore, this circuit has the disadvantage that when the change in input impedance Zin becomes large, the current Ii changes even if the voltage Vi is constant, so the error between the current that is intended to flow with voltage Vi and the current Ii that actually flows becomes large. In addition, when the input impedance Zin changes in accordance with the current Ii, the linearity of the current Ii with respect to voltage Vi decreases. On the other hand, resistors have the advantage of being usable at high frequencies because they have good frequency characteristics, and they also have the advantage of being low cost due to the small number of components. In the signal generation circuit of the present invention, the circuit described as a current input can be used as a voltage input by adding a resistor Rs as shown in Figure 2E. For example, the current input in Figure 2G when the current Is is ±1mA and the resistor Rs is 10kΩ is equivalent to the voltage input in Figure 2F when the voltage Vi is ±1V and the resistor Rs is 1kΩ.

[0027] Return to Figure 1. The output amplifier section 3 is a circuit that generates an output current Ix by amplifying the input current Ii from the input amplifier section 2. In the example shown in Figure 1, it includes a signal generation circuit 10 that generates signals S1 and S2 used in Class AB push-pull operation, and a first output section 6 and a second output section 7 that operate in accordance with these signals.

[0028] The first output unit 6 generates a current Ip corresponding to one of the signals S1 and S2 output from the signal generation circuit 10, and discharges it from the current output node Nx. The second output unit 7 generates a current In corresponding to the other of the signals S1 and S2 output from the signal generation circuit 10, and allows it to flow in from the current output node Nx.

[0029] The difference between the current Ip of the first output section 6 and the current In of the second output section 7 is the output current Ix, which flows in or out at the current output node Nx. The output current Ix either flows out from the current output node Nx to node Nout (the node connecting one end of resistor Rf to the output terminal Tout), or flows in from node Nout to the current output node Nx.

[0030] The first output unit 6 includes a first drive unit 8, an operational amplifier Up, a pnp transistor Qp, and a resistor Rp. The operational amplifier Up, the pnp transistor Qp, and the resistor Rp constitute a voltage-to-current conversion circuit that generates a current Ip corresponding to the drive signal Sp supplied from the first drive unit 8. The emitter of the pnp transistor Qp is connected to a positive voltage V+ via the resistor Rp, the collector is connected to a current output node Nx, and the base is connected to the output of the operational amplifier Up. The inverting input of the operational amplifier Up is connected to the emitter of the pnp transistor Qp, and the drive signal Sp is input to the non-inverting input. The first drive unit 8 generates a drive signal Sp based on the push-pull operation signal (one of S1 and S2) generated by the signal generation circuit 10. Specifically, the first drive unit 8 decreases the voltage of the drive signal Sp when the push-pull operation signal (one of S1 and S2) changes in a direction that increases the current Ip, and increases the voltage of the drive signal Sp when the push-pull operation signal (one of S1 and S2) changes in a direction that decreases the current Ip.

[0031] The second output section 7 includes a second drive section 9, an operational amplifier Un, an npn transistor Qn, and a resistor Rn. The operational amplifier Un, the npn transistor Qn, and the resistor Rn constitute a voltage-to-current conversion circuit that generates a current In corresponding to the drive signal Sn supplied from the second drive unit 9. The emitter of the npn transistor Qn is connected to a negative voltage V- via the resistor Rn, the collector is connected to the current output node Nx, and the base is connected to the output of the operational amplifier Un. The inverting input of the operational amplifier Un is connected to the emitter of the npn transistor Qn, and the drive signal Sn is input to the non-inverting input. The second drive unit 9 generates a drive signal Sn based on the push-pull operation signal (the other of S1 and S2) generated by the signal generation circuit 10. Specifically, the second drive unit 9 increases the voltage of the drive signal Sn when the push-pull operation signal (the other of S1 and S2) changes in a direction that increases the current In, and decreases the voltage of the drive signal Sn when the push-pull operation signal (the other of S1 and S2) changes in a direction that decreases the current In.

[0032] In Figure 1, complementary bipolar transistors are shown as the positive and negative output elements in the first output section 6 and the second output section 7, but this embodiment is not limited to this example. That is, other types of output elements (for example, FETs, power MOS FETs, IGBTs) may be used in the first and second output sections, or semiconductor elements other than silicon (for example, SiC, GaN, gallium oxide, germanium, germanium oxide, diamond) may be used. Furthermore, the positive and negative output elements are not limited to complementary transistors, and transistors with the same polarity may be used. For example, either an npn type transistor or a pnp type transistor may be used, or either an N-channel FET or a P-channel FET may be used (see Patent Document 2).

[0033] In Figure 1, the first output unit 6 and the second output unit 7 generate currents Ip and In proportional to the signals S1 and S2 generated by the signal generation circuit 10 via the voltage signals, which are drive signals Sp and Sn. However, this embodiment is not limited to this. For example, if the signal generation circuit 10 generates signals S1 and S2 as current signals, the first output unit 6 and the second output unit 7 may be circuits that generate currents Ip and In proportional to the current signals S1 and S2 (current input-current output amplification circuits), and may be configured without using voltage signals such as drive signals Sp and Sn.

[0034] Furthermore, in the example shown in Figure 1, the power supply voltage (positive voltage VL+, negative voltage VL-) supplied to the signal generation circuit 10 may be different from the power supply voltage (positive voltage V+, negative voltage V-) supplied to the first output unit 6 and the second output unit 7. In this case, the first drive unit 8 of the first output unit 6 and the second drive unit 9 of the second output unit 7 may have a level shift function that converts the voltage levels of signals S1 and S2.

[0035] [Signal generation circuit 10] Next, an example of the signal generation circuit 10 according to this embodiment will be described with reference to Figure 3. The signal generation circuit 10 is a circuit that generates signals S1 and S2 that cause the first output unit 6 and the second output unit 7 to perform Class AB push-pull operation in response to the input current Ii supplied from the input amplifier unit 2. In the example shown in Figure 3, the signal generation circuit 10 includes a current input node Ni, diodes D1 and D2, current detection units 21 and 22, and a voltage control unit 30. Diode D1 is an example of the first diode of the present invention. Diode D2 is an example of the second diode of the present invention.

[0036] The diode used in the signal generation circuit in this embodiment and other embodiments described later may be a general PN junction silicon diode, a Schottky diode, or a diode made of a material other than silicon (for example, SiC, GaN, gallium oxide, germanium, germanium oxide, or diamond). The type of diode may be selected as appropriate to improve the performance of the amplification circuit (response speed, distortion, etc.).

[0037] A voltage V1 controlled by the voltage control unit 30 is applied to the anode of diode D1. A voltage V2 controlled by the voltage control unit 30 is applied to the cathode of diode D2. The current input node Ni is located in the path of the current flowing from the cathode of diode D1 to the anode of diode D2, and the input current Ii flows in or out through it.

[0038] The current detection unit 21 outputs a signal S1 that detects the diode current Id1 flowing through the diode D1. The current detection unit 22 outputs a signal S2 that detects the diode current Id2 flowing through the diode D2.

[0039] Figures 4A to 4C show examples of current detection units 21 and 22. As shown in Figure 4A, the current detection units 21 and 22 detect the current (Id1, Id2) flowing through the diodes (D1, D2) and generate signals (S1, S2). When the ends of the diodes are not connected to a reference voltage, the current detection units 21 and 22 have a current detection amplifier SA and a shunt resistor SH, as shown in Figures 4B and 4C, for example. The shunt resistor SH is provided in the path of the current (Id1, Id2) flowing through the diodes (D1, D2). Figures 4B and 4C show two examples of circuits in which the current detection amplifier SA generates signals (S1, S2) with a positive voltage corresponding to the current (Id1, Id2). To generate signals (S1, S2) with negative voltages corresponding to currents (Id1, Id2), the polarity of the connection between the shunt resistor SH and the current sensing amplifier SA in the circuits shown in Figures 4B and 4C should be reversed. The positive and negative polarity of the signals S1 and S2 output from the current sensing units 21 and 22 may be appropriately selected according to the configuration of the circuits (first drive unit 8, second drive unit 9) to which these signals are supplied.

[0040] The current sense amplifier SA amplifies the voltage across the shunt resistor SH and outputs it as signal S1 or signal S2. The current sense amplifier SA may be a voltage differential amplifier composed of one or more operational amplifiers, or an instrumentation amplifier with high input impedance.

[0041] Return to Figure 3. The voltage control unit 30 controls voltages V1 and V2 so that predetermined idle currents flow as diode currents Id1 and Id2, respectively, when the input current Ii is zero. Furthermore, the voltage control unit 30 controls voltages V1 and V2 such that when the input current Ii flowing from the current input node Ni to the diode D2 increases, the diode current Id2 increases and the diode current Id1 decreases, and the difference between the diode current Id1 and the diode current Id2 (Id2-Id1) becomes the incoming input current Ii. Furthermore, the voltage control unit 30 controls voltages V1 and V2 such that when the input current Ii flowing out from diode D1 to current input node Ni increases, the diode current Id1 increases and the diode current Id2 decreases, and the difference between diode current Id1 and diode current Id2 (Id1-I2) becomes the outflowing input current Ii.

[0042] When the input current Ii is zero, the voltage control unit 30 controls voltages V1 and V2, so that predetermined idle currents flow as diode current Id1 and diode current Id2, respectively. Therefore, when the input current Ii is zero, the first output unit 6 and the second output unit 7 are controlled based on the signals (S1 and S2) that detect the diode currents (Id1 and Id2), so that when the input current Ii is zero, predetermined idle currents flow as current Ip flowing out of the first output unit 6 and current In flowing into the second output unit 7, respectively.

[0043] Furthermore, when the input current Ii flowing into or out of the current input node Ni increases due to the control of voltages V1 and V2 by the voltage control unit 30, one of the diode currents Id1 and Id2 increases while the other decreases, and the difference between the increasing diode current and the decreasing diode current becomes the input current Ii flowing into the current input node Ni in the direction of increase (inflow or outflow). Therefore, when the input current Ii flowing into or out of the current input node Ni increases due to the control of the first output unit 6 and the second output unit 7 based on the signals (S1, S2) that detect the diode currents (Id1, Id2), one of the currents Ip and In increases while the other decreases, and the difference between the increasing current and the decreasing current becomes the current Ix flowing into the current output node Nx in one direction (inflow or outflow) corresponding to the direction (inflow or outflow) of the increasing input current Ii.

[0044] Therefore, in response to the input current Ii flowing through the current input node Ni, the first output unit 6 and the second output unit 7 perform a Class AB push-pull operation.

[0045] In the example shown in Figure 3, the voltage control unit 30 includes a diode D3 provided in the forward direction in the current path from node N3 to intermediate node M1, a diode D4 provided in the forward direction in the current path from intermediate node M1 to node N4, a resistor R1 provided in the current path between node N3 and node N4, and a constant current supply unit 31. The anode of diode D3 is connected to node N3 and its cathode is connected to intermediate node M1. The anode of diode D4 is connected to intermediate node M1 and its cathode is connected to node N4. The resistor R1 is connected between node N3 and node N4. Diode D3 is an example of the third diode of the present invention. Diode D4 is an example of the fourth diode of the present invention. Resistor R1 is an example of the first resistor of the present invention.

[0046] In the example shown in Figure 3, the constant current supply unit 31 includes a constant current circuit CS1 that supplies a constant current Ic1 flowing from the positive voltage VL+ to node N3, and a constant current circuit CS2 that supplies a constant current Ic2 flowing from node N4 to the negative voltage VL-. The constant current Ic1 of constant current circuit CS1 and the constant current Ic2 of constant current circuit CS2 are set to approximately the same current.

[0047] The constant current circuits CS1 and CS2 may be composed of circuits using operational amplifiers, etc., or they may be composed of active elements (transistors, etc.), or they may be high resistances that can approximate a constant current source.

[0048] In the signal generation circuit 10 shown in Figure 3, when the input current Ii is zero, voltages V1 and V2 are determined according to the voltage-current characteristics of diodes D1 to D4, the resistance value of resistor R1, and the current values ​​of constant currents Ic1 and Ic2. Here, assuming that the current values ​​of constant currents Ic1 and Ic2 are the same and that diodes D1 to D4 have the same characteristics, the diode currents Id1 to Id4 flowing through diodes D1 to D4 will be the same, and this current will be the "idle current". The resistance value of resistor R is set so that the idle current has a predetermined value when the input current Ii is zero.

[0049] In the signal generation circuit 10 shown in Figure 3, the current flowing into node N3 and the current flowing out of node N4 are controlled to constant currents (Ic1, Ic2), respectively. Therefore, even if input current Ii flows in or out at the current input node Ni, this does not change the current flowing into node N3 or the current flowing out of node N4. Focusing on the current path between the current input node Ni and the intermediate node M1, the input current Ii that flows in or out at the current input node Ni (the change in current relative to the bias current when input current Ii is zero) does not flow out from nodes N3 and N4 to the power supply voltage side (VL+, VL-), but all flows to the intermediate node M1. That is, when input current Ii flows into the current input node Ni, the same current as this input current Ii flows out from the intermediate node M1 to the reference voltage, and when input current Ii flows out from the current input node Ni, the same current as this input current Ii flows from the reference voltage to the intermediate node M1.

[0050] When an input current Ii flows into the current input node Ni, this input current Ii increases the diode current Id2, while the diode current Id3 increases by the same amount. As a result, diode currents Id2 and Id3 become equal, and the voltages across diodes D2 and D3 become equal. When the voltages across diodes D2 and D3 become equal, the voltages across diodes D1 and D4 also become equal, and therefore the diode currents Id1 and Id4 also become equal.

[0051] When input current Ii flows into the current input node Ni, diode currents Id2 and Id3 increase by the amount of the inflow. On the other hand, the current flowing into node N3 and the current flowing out of node N4 remain unchanged (Id1 and Id2). As a result, the current Ir1 across resistor R1 decreases, the voltage drop across resistor R1 decreases, the difference between voltages V1 and V2 decreases, the voltages across diodes D1 and D4 decrease, and diode currents Id1 and Id4 decrease. When the incoming input current Ii increases, diode currents Id1 and Id4 eventually become zero, and the diode current Id3 flowing from constant current circuit CS1 to diode D3 and the diode current Id2 flowing from diode D2 to constant current circuit CS2 become dominant. Therefore, when the input current Ii flowing from current input node Ni to diode D2 increases, diode current Id2 increases and diode current Id1 decreases. The difference between the diode current Id1 and the diode current Id2 (Id2-Id1) is the input current Ii that flows into the current input node Ni.

[0052] When input current Ii flows out of the current input node Ni, the diode currents Id2 and Id3 become equal, and diode currents Id1 and Id4 become equal, similar to the inflow described above. In this case, as the outflowing input current Ii increases, diode currents Id1 and Id4 increase, while diode currents Id2 and Id3 decrease. Therefore, when the input current Ii flowing out from diode D1 to the current input node Ni increases, diode current Id1 increases and diode current Id2 decreases. The difference between diode current Id1 and diode current Id2 (Id2-Id1) is the outflowing input current Ii.

[0053] As described above, according to this embodiment, by using a circuit configuration that combines diodes (D1 to D4) connected in series, signals S1 and S2 that cause the output stage of the amplification circuit (first output section 6, second output section 7) to perform a Class AB push-pull operation can be generated without using a pair of transistors with different polarities (complementary transistors, etc.).

[0054] Because diodes are discontinued relatively less frequently than complementary transistors, etc., it is less likely that the selection and evaluation of alternative parts, and the redesign of circuit configurations will occur due to the focus on component production.

[0055] Furthermore, because diodes have a low forward voltage, they have lower power loss compared to transistors and are less susceptible to the effects of temperature drift. The loss in a diode is expressed as "anode-cathode voltage × current," but since the anode-cathode voltage of a diode is usually low, at several hundred mV, for the same current value, diodes have significantly lower losses than bipolar transistors and generate less heat. To suppress temperature drift, it is preferable to thermally couple the components to match the temperatures of the transistors and diodes used as closely as possible, but since circuit configurations using diodes generate less heat, it is possible to simplify the thermal coupling process, contributing to cost reduction. In addition, because less heat is generated, it is easier to avoid circuit malfunctions caused by transient increases in power consumption, etc.

[0056] Diodes of the same type exhibit smaller variation errors in characteristics compared to complementary transistors with different polarities. Therefore, for example, in series-connected diodes (D1 and D2, D3 and D4, etc.), using the same type for the high-side and low-side diodes significantly reduces the asymmetry error caused by the difference in characteristics between the two, compared to using complementary transistors. Furthermore, by using diodes of the same type and thermally coupling them, temperature drift can be suppressed, enabling higher-performance Class AB push-pull operation.

[0057] According to this embodiment, by adjusting the resistor R1, it is possible to adjust the idle current of diodes D1 and D2 near zero of the input current Ii, and by increasing (or omitting) the resistor R, it is also possible to enable Class A operation in which current flows constantly through diodes D1 and D2.

[0058] Next, we will explain the simulation results for the signal generation circuit 10 shown in Figure 3 and the simulation results for the comparative example circuit (Figure 89). Here, we will first explain the circuit configuration of the comparative example Class AB push-pull amplifier circuit 100 shown in Figure 89 and its simulation results (Figures 90A to 90F), and then explain the simulation results for the signal generation circuit 10 shown in Figure 3 (Figures 5A to 5F).

[0059] [Circuit configuration of the comparative example shown in Figure 89] The Class AB push-pull amplifier circuit 100 shown in Figure 89 includes an input amplifier section 102, an output amplifier section 103, and negative feedback resistors Rf and Rg. The input amplifier section 102 includes a differential amplifier 4 and a voltage-to-current conversion section 5, similar to the input amplifier section 2 in the Class AB push-pull amplifier circuit 1 of Figure 1. The output amplifier section 103 includes a first output section 106, a second output section 107, and the signal generation circuit 110 that was simulated in this study.

[0060] The first output unit 106 includes a voltage conversion circuit (Qp, Up, Rp) similar to that of the first output unit 6, and also includes a resistor R113, which corresponds to the first drive unit 8 in Figure 1, for generating a signal Sp that drives the voltage conversion circuit. The current Iq1 generated in the signal generation circuit 110 flows through the resistor R113. The second output section 107 includes a voltage conversion circuit (Qn, Un, Rn) similar to that of the second output section 7, and also includes a resistor R114, which corresponds to the second drive section 9 in Figure 1, for generating a signal Sn that drives the voltage conversion circuit. The current Iq2 generated in the signal generation circuit 110 flows through the resistor R114.

[0061] The signal generation circuit 110 shown in Figure 89 generally corresponds to the circuit described in Figure 4(A) of Patent Document 1. A constant bias voltage generated by the npn transistor Q111 and the constant current circuit CS111 is applied to the base of the npn transistor Q113. Similarly, a constant bias voltage generated by the pnp transistor Q112 and the constant current circuit CS112 is applied to the base of the pnp transistor Q114. Due to these bias voltages, the current Iq1 flowing through the collector of the npn transistor Q113 and the current Iq2 flowing through the collector of the pnp transistor Q114 are set to a predetermined idle current when the input current Ii is zero. When the input current Ii flowing into the current input node Ni increases, the current Iq2 of the pnp transistor Q114 increases and the emitter-base voltage increases, while the emitter-base voltage of the npn transistor Q113 decreases and the current Iq1 decreases. Conversely, when the input current Ii flowing out of the current input node Ni increases, the current Iq1 of the npn transistor Q113 increases while the current Iq2 of the pnp transistor Q114 decreases.

[0062] [Simulation conditions and graph explanation] Figures 90A to 90F show the results of simulations performed on the comparative example shown in Figure 89.

[0063] The six simulation conditions shown in Figures 90A to 90F, along with explanations of each graph, are as follows. In the following explanation, the graphs in each figure will be referred to as "Graph A," "Graph B," ... "Graph F," using the suffix (A-F) of the figures. (Example: Graph C in Figure 90C is "Graph C.")

[0064] ■Simulation Condition 1 In the simulation, three temperature settings were used: 0°C, +27°C, and +54°C. In each graph, +27°C is represented by a solid line, 0°C by a dotted line, and +54°C by a dashed line.

[0065] ■Simulation Condition 2 The variable range of the current Is (see Figure 2G) of the current source supplying the input current Ii was set to -1mA to +1mA.

[0066] ■Simulation Condition 3 The circuit constants were set so that the currents Iq1 and Iq2 (idle currents) when the current Is is 0mA are approximately 1 / 10 of the currents Iq1 and Iq2 when the current Is is ±1mA.

[0067] ■Simulation Condition 4 Graphs A, C, and E (the three figures on the left) show the simulation results when the output resistance Rs of the current source supplying the input current Ii (see Figures 2E to 2G) is set to infinite. When the output resistance Rs is infinite, the input current Ii is equal to the current Is of the current source (see Figure 2G). In the voltage input signal generation circuit described later (Figure 35, etc.), the simulation results are shown when the output resistance Rs (see Figures 2E and 2F) of the voltage source supplying the input voltage Vi is zero Ω. When the output resistance Rs is zero Ω, the input voltage Vi of the signal generation circuit is equal to the voltage Vi of the voltage source (see Figure 2F).

[0068] ■Simulation Condition 5 Graphs B, D, and F (the three figures on the right) show the simulation results when the output resistance Rs (see Figures 2E to 2G) of the current source supplying the input current Ii is 10kΩ. In the voltage input signal generation circuit described later (Figure 35, etc.), the simulation results are shown when the output resistance Rs of the voltage source supplying the input voltage Vi (see Figures 2E and 2F) is set to 50Ω.

[0069] ■Graph Explanation 1 The horizontal axis of the F graph (bottom right figure) represents the current Is (see Figure 2G). The horizontal axis of the other graphs represents the input current Ii.

[0070] ■Graph Explanation 2 Graphs A and B (the two figures in the upper row) are superimposed simulation results for three currents, "-Iq1", "Iq2", and "Iq2-Iq1", with the vertical axis showing the current value for each current.

[0071] ■Graph Explanation 3 Graphs C and D (the two figures in the middle) show the error between "Iq2-Iq1" and its approximate straight line (*1), with the vertical axis indicating the current value of the error. (*1) Approximate straight line At +27℃, we found a value of ki such that the value of (Iq2-Iq1)-(Ii×ki) is approximately the same for Ii:-1mA and +1mA, and used (Ii×ki) as the approximate straight line.

[0072] ■Graph Explanation 4 Graph E (bottom left) shows the input resistance (=input voltage Vi / input current Ii), with the vertical axis representing the resistance value. The input resistance does not change depending on the output resistance Rs of the current source supplying the input current Ii (see Figures 2E to 2G). If the input voltage Vi is not zero when the input current Ii is near zero, the input resistance becomes discontinuous around zero input current Ii. Therefore, the input voltage Vi when the input current Ii is zero is subtracted to prevent discontinuity. Circuits in which the input voltage Vi is not zero when the input current Ii is near zero include the circuit in Figure 89 (due to the difference in characteristics between PNP and NPN transistors) and circuits such as Figure 43 described later, which generate signals on the positive and negative sides respectively (due to positive / negative asymmetry).

[0073] ■Graph Explanation 5 Graph F (bottom right) shows the error between "Iq2-Iq1" and its approximate straight line (*2), with the vertical axis representing the current value of the error. (※2) Approximate straight line At +27℃, we found the value of ks such that the value of (Iq2-Iq1)-(Is×ks) is approximately the same for Is:-1mA and Is:+1mA, and used (Is×ks) as the approximate straight line.

[0074] [Simulation results of the comparative example shown in Figure 89: Figures 90A to 90F] Looking at graphs A and B (the two figures in the upper row) which show the three currents "-Iq1", "Iq2", and "Iq2-Iq1", it appears that there is no distinction between 0℃ / +27℃ / +54℃, and the difference in the output resistance Rs of the current source (infinity / 10kΩ) has almost no effect.

[0075] In graphs C and D (the two figures in the middle panel), which show the error relative to the approximate straight line (Ii×ki) of "Iq2-Iq1", it can be seen that the slope of "Iq2-Iq1" differs slightly depending on the sign of the input current Ii, which is the cause of the error. Furthermore, the direction of change of the current "Iq2-Iq1" due to temperature also differs depending on the sign of the input current Ii. Both of these are thought to be due to the asymmetry of the characteristics of complementary transistors (npn type transistors, pnp type transistors).

[0076] In the F-graph (bottom right figure) showing the error relative to the approximate straight line (Is×ks) of "Iq2-Iq1", it can be seen that the effect of the finite resistance Rs of the current source is greater than the asymmetry effect of the complementary transistor. This is because the input resistance changes depending on the value of the input current Ii.

[0077] In the E-graph (bottom left diagram) showing the input resistance, the input resistance is generally in the range of several tens of ohms to 200 ohms.

[0078] [Simulation results of the signal generation circuit 10 shown in Figure 3: Figures 5A to 5F] Figures 5A to 5F show the simulation results performed on the signal generation circuit 10 shown in Figure 3.

[0079] The simulation conditions and graph descriptions in Figures 5A to 5F are the same as those described above in "Simulation Condition 1" to "Simulation Condition 5" and "Graph Explanation 1" to "Graph Explanation 5". However, "Iq1" and "Iq2" in "Graph Explanation 1" to "Graph Explanation 5" should be read as "Id1" and "Id2", respectively. The simulation conditions and graph descriptions in Figures 5A to 5F also apply to the simulations described later, unless otherwise noted.

[0080] Looking at graphs A and B (the two figures in the upper row), which show the three currents "-Id1", "Id2", and "Id2-Id1", it can be seen that the current flowing through each diode changes with temperature. For this reason, in this example, the idle current is easily affected by temperature.

[0081] On the other hand, graphs C and D (the two figures in the middle panel), which show the error with respect to the approximate straight line (Ii×ki) of "Id2-Id1", show that the sum of the currents flowing through each diode, "Iq2-Iq1", and the input current Ii are in an almost perfect proportional relationship. This is because the input current Ii is divided from the current input node Ni to diodes D1 and D2 and does not flow anywhere else, so "Ii=Id2-Id1" holds true.

[0082] The E-graph (bottom left figure), which shows the input resistance, indicates that the input resistance changes relatively significantly depending on the input current Ii and temperature.

[0083] In the F graph (lower right figure), which shows the error relative to the approximate straight line (Is × ks) of "Id2 - Id1", it can be seen that the proportional relationship between "Id2 - Id1", the sum of the currents flowing through each diode, and the current Is is disrupted due to the influence of the change in input resistance shown in the E graph. Therefore, in this embodiment, it is preferable to increase the output resistance Rs of the current source that supplies the input current Ii. As an example, if Schottky diodes are used for each diode in the signal generation circuit 10, the distortion of nonlinearity due to the influence of changes in input resistance is more easily improved.

[0084] <Second Embodiment> Next, a second embodiment of the present invention will be described. Figure 6 is a diagram showing an example of a signal generation circuit according to the second embodiment. The configuration of the Class AB push-pull amplifier circuit 1, including the signal generation circuit 10A shown in Figure 6, is the same as in Figure 1.

[0085] The signal generation circuit 10A shown in Figure 6 is the same as the signal generation circuit 10 shown in Figure 3, but with the voltage control unit 30 replaced by a voltage control unit 30A. The voltage control unit 30A has the same configuration as the voltage control unit 30 (diodes D3, D4, constant current supply unit 31, resistor R1), plus a bias voltage supply unit 33.

[0086] The bias voltage supply unit 33 supplies a bias voltage Vb to the intermediate node M1 that controls the voltage at the current input node Ni to be close to the reference voltage. The bias voltage supply unit 33 controls the bias voltage Vb so that it increases when the voltage at the current input node Ni decreases relative to the reference voltage, and decreases when the voltage at the current input node Ni increases relative to the reference voltage.

[0087] In the example in Figure 6, the bias voltage supply unit 33 includes an operational amplifier U33. The operational amplifier U33 has a non-inverting input connected to a reference voltage, an inverting input connected to a current input node Ni, and an output connected to an intermediate node M1.

[0088] In the case of the signal generation circuit 10 shown in Figure 3, the same current that flows in (out) at the current input node Ni is the same current that flows out (in) at the intermediate node M1. Similarly, in the case of the signal generation circuit 10A shown in Figure 6, the same current that flows in (in) at the intermediate node M1 is the same as the input current Ii. Therefore, in the signal generation circuit 10A as well, the diode current Id2 is the same as the diode current Id3, and the diode currents Id1 and Id4 are the same. However, in the case of the signal generation circuit 10A, the current at the intermediate node M1 is supplied by the bias voltage supply unit 33.

[0089] As the input current Ii flowing from the current input node Ni to diode D2 increases, diode currents Id2 and Id3 increase, while diode currents Id1 and Id4 decrease. In this case, the voltage across diode D2 rises and the voltage across diode D1 decreases, causing the voltage at the current input node Ni to rise. However, the bias voltage Vb decreases to suppress this voltage rise, and diode current Id3 is drawn into the bias voltage supply unit 33. As a result, as the incoming input current Ii increases, the bias voltage Vb at the intermediate node M1 decreases, but the voltage at the current input node Ni is maintained at the reference voltage. When input current Ii flows out from diode D1 to current input node Ni, the bias voltage Vb at intermediate node M1 increases as the outflowing input current Ii increases, the opposite of the inflow case described above, but the voltage at current input node Ni is maintained at the reference voltage. Therefore, as the incoming input current Ii increases, the diode current Id2 increases and the diode current Id1 decreases, and as the outgoing input current Ii increases, the diode current Id1 increases and the diode current Id2 decreases, but the voltage at the current input node Ni is always maintained at the reference voltage.

[0090] Thus, according to this embodiment, a bias voltage Vb is supplied to the intermediate node M1 so that the current input node Ni is maintained at the reference voltage regardless of changes in the input current Ii. As a result, the input resistance of the current input node Ni becomes very small, so even if the output resistance Rs (Figures 2E to 2G) of the voltage-to-current conversion unit 5 that supplies the input current Ii is relatively small, the current Is (Figure 2G) that the voltage-to-current conversion unit 5 tries to output in proportion to the voltage Vi becomes almost equal to the input current Ii. Therefore, even if the output resistance Rs is relatively small, the distortion of nonlinearity due to fluctuations in the input resistance of the current input node Ni can be kept to a minimum.

[0091] Since the bias voltage Vb changes together with the input current Ii, it is desirable to use a fast-operating operational amplifier U33 in the bias voltage supply unit 33 when the input current Ii changes rapidly (when the frequency of the signal Sin is high).

[0092] [Simulation results of the signal generation circuit 10A shown in Figure 6: Figures 7A to 7F] Figures 7A to 7F show the simulation results performed on the signal generation circuit 10A shown in Figure 6.

[0093] Graphs A and B (top two figures), which show the three currents "-Id1", "Id2", and "Iq2-Iq1", and graphs C and D (middle two figures), which show the error relative to the approximate straight line (Ii×ki) of "Iq2-Iq1", exhibit almost the same characteristics as the signal generation circuit 10 in Figure 3, which does not perform constant voltage control of the current input node Ni by controlling the bias voltage Vb.

[0094] On the other hand, looking at the E graph (lower left figure) showing the input resistance, it can be seen that in the signal generation circuit 10A, which performs constant voltage control of the current input node Ni, the input resistance of the current input node Ni is brought sufficiently close to the ideal zero ohm. While the input resistance of the signal generation circuit 10 shown in Figure 3 was several hundred ohms to slightly over 1 kΩ, the input resistance of the signal generation circuit 10A shown in Figure 6 is several hundred microohms to slightly over 1 mΩ, an improvement of about six orders of magnitude. This is due to the open-loop gain of the operational amplifier U33 being 120 dB. As a result, in the F graph (lower right figure) showing the error with respect to the approximate straight line (Is × ks) of "Iq2 - Iq1", the error is almost zero, and the current Is and "Iq2 - Iq1" are in a nearly perfect proportional relationship.

[0095] (Modification 1 of the second embodiment) Figure 8 shows a modified example of the signal generation circuit according to the second embodiment. The signal generation circuit 10B shown in Figure 8 has the same configuration as the signal generation circuit 10A shown in Figure 6 (diodes D1, D2, current input node Ni), in addition to a voltage control unit 30B. The voltage control unit 30B replaces the constant current supply unit 31 in the voltage control unit 30A with a constant current supply unit 31B. The constant current supply unit 31B includes a constant current circuit CS2 that supplies a constant current Ic2 to node N4, while the constant current circuit CS1 that supplies a constant current Ic1 to node N3 is omitted. In the voltage control unit 30B, the bias voltage Vb of the bias voltage supply unit 33 is supplied to node N3.

[0096] In the case of the signal generation circuit 10B shown in Figure 8, a current equivalent to the sum of the input current Ii flowing in or out at the current input node Ni and the constant current Ic2 flowing out to the negative voltage VL- at node N4 flows into node N3 via the bias voltage supply unit 33.

[0097] When the input current Ii is zero, the same diode current Id1 to Id4 flows through diodes D1 to D4 with matching characteristics.

[0098] As the input current Ii flowing from the current input node Ni to the diode D2 increases, the sum of the current Ir1 across resistor R1 and the diode current Id3 (=Id4) decreases by the amount of the increase in input current Ii, because node N4 is controlled to a constant current Ic2. As a result, the voltage across diode D1 decreases, and the diode current Id1 decreases. At this time, the voltage across the current input node Ni tends to rise due to the increase in diode current Id2, but the bias voltage Vb decreases to suppress this voltage rise, so the voltage across the current input node Ni is maintained at the reference voltage. When input current Ii flows out from diode D1 to current input node Ni, the diode current Id1 increases and diode current Id2 decreases, as in the case of inflow described above. The bias voltage Vb increases so that the voltage at current input node Ni is maintained at the reference voltage. Therefore, as the incoming input current Ii increases, the diode current Id2 increases and the diode current Id1 decreases, and as the outgoing input current Ii increases, the diode current Id1 increases and the diode current Id2 decreases, but the voltage at the current input node Ni is always maintained at the reference voltage.

[0099] According to this modified configuration, similar to the signal generation circuit 10A described above, one of the diode currents Id1 and Id2 can be increased and the other decreased in accordance with the input current Ii, thereby enabling the generation of signals (S1, S2) for push-pull operation. Furthermore, by using constant voltage control to maintain the current input node Ni at a reference voltage, the input resistance of the current input node Ni becomes very small, thus minimizing nonlinear distortion caused by fluctuations in input resistance.

[0100] (Modification 2 of the second embodiment) Figure 9 shows another modified example of the signal generation circuit according to the second embodiment. The signal generation circuit 10C shown in Figure 9 has the same configuration as the signal generation circuit 10A shown in Figure 6 (diodes D1, D2, current input node Ni), in addition to a voltage control unit 30C. The voltage control unit 30C replaces the constant current supply unit 31 in the voltage control unit 30A with a constant current supply unit 31C. The constant current supply unit 31C includes a constant current circuit CS1 that supplies a constant current Ic1 to node N3, while the constant current circuit CS2 that supplies a constant current Ic2 to node N4 is omitted. In the voltage control unit 30C, the bias voltage Vb of the bias voltage supply unit 33 is supplied to node N4.

[0101] In the signal generation circuit 10C shown in Figure 9, a current equivalent to the sum of the input current Ii flowing in or out at the current input node Ni and the constant current Ic1 flowing in from the positive voltage VL+ at node N3 is discharged from node N4 by the bias voltage supply unit 33. In the signal generation circuit 10C, as with the signal generation circuit 10B described above, as the input current Ii increases, the sum of the current Ir1 across resistor R1 and the diode current Id3 (=Id4) decreases, and the voltage difference between voltage V1 and voltage V2 decreases, so that one of the diode currents Id1 and Id2 increases while the other decreases. Therefore, it is possible to generate signals (S1, S2) for push-pull operation corresponding to the input current Ii. In addition, since the current input node Ni is maintained at the reference voltage, nonlinear distortion due to fluctuations in input resistance can be kept to a minimum.

[0102] <Third Embodiment> Next, a third embodiment of the present invention will be described. Figure 10 is a diagram showing an example of a signal generation circuit according to the third embodiment. The configuration of the Class AB push-pull amplifier circuit 1, including the signal generation circuit 10D shown in Figure 10, is the same as in Figure 1.

[0103] The signal generation circuit 10D shown in Figure 10 is the same as the signal generation circuit 10 shown in Figure 3, but with the voltage control unit 30 replaced by a voltage control unit 30D.

[0104] The voltage control unit 30D maintains the voltage difference between voltage V1 and voltage V2 when idle current flows through diode D1 and diode D2, respectively (when the input current Ii is zero).

[0105] When the input current Ii flowing from the current input node Ni to diode D2 increases, the voltage across diode D2 rises due to the increase in diode current Id1. However, because the voltage difference between voltage V1 and voltage V2 is maintained, the voltage across diode D1 decreases by the amount of the increase in the voltage across diode D2, and the diode current Id1 decreases. Conversely, when the input current Ii flowing out from diode D1 to the current input node Ni increases, the voltage across diode D2 decreases as the voltage across diode D1 rises due to the increase in diode current Id1, and the diode current Id2 decreases. Therefore, in accordance with the input current Ii, one of the diode currents Id1 and Id2 can be increased and the other decreased, making it possible to generate signals (S1, S2) for push-pull operation.

[0106] In the example shown in Figure 10, the voltage control unit 30D includes a constant current supply unit 31D, a diode circuit 32, and a voltage generation unit 34.

[0107] The diode circuit 32 includes diodes D5 and D6 connected in series in the forward direction. Diode D5 is provided in the forward direction in the current path from node N5 to intermediate node M2. The anode of diode D5 is connected to node N5 and the cathode is connected to intermediate node M2. Diode D6 is provided in the forward direction in the current path from intermediate node M2 ​​to node N6. The anode of diode D6 is connected to intermediate node M2 ​​and the cathode is connected to node N6. Intermediate node M2 ​​is held at a reference voltage. Diodes D4 and D5 are preferably diodes (for example, diodes of the same type) with characteristics (voltage-current characteristics, temperature characteristics, etc.) that match those of diodes D1 and D2. Diode D5 is an example of the fifth diode of the present invention. Diode D6 is an example of the sixth diode of the present invention.

[0108] The constant current supply unit 31D supplies a constant current Ic1 flowing into the anode of diode D5 at one end of the diode circuit 32, and a constant current Ic2 flowing out from the cathode of diode D6 at the other end of the diode circuit 32, so that the same current as the idle current (diode currents Id1 and Id2 when the input current Ii is zero) flows through diodes D5 and D6 of the diode circuit 32. In the example in Figure 10, the constant current supply unit 31D includes a constant current circuit CS1 that supplies a constant current Ic1 flowing into node N5 from the positive voltage VL+, and a constant current circuit CS2 that supplies a constant current Ic2 flowing out from node N6 to the negative voltage VL-. The constant current Ic1 of constant current circuit CS1 and the constant current Ic2 of constant current circuit CS2 are set to approximately the same current.

[0109] The voltage generation unit 34 generates voltages V1 and V2 based on the voltages generated in diodes D5 and D6 included in the diode circuit 32. In the example in Figure 10, the voltage generation unit 34 includes buffer circuits BF1 and BF2. Buffer circuit BF1 receives voltage V5 generated at node N5 and outputs voltage V1 which is approximately the same as voltage V5. Buffer circuit BF2 receives voltage V6 generated at node N6 and outputs voltage V2 which is approximately the same as voltage V6.

[0110] Because the input impedances of buffer circuits BF1 and BF2 are very high, a constant current Ic1 flows through diode D5 and a constant current Ic2 flows through diode D6. Therefore, the idle currents of diodes D1 and D2 when the input current Ii is zero can be arbitrarily set by the current values ​​of constant currents Ic1 and Ic2.

[0111] [Simulation results of the signal generation circuit 10D shown in Figure 10: Figures 11A to 11F] Figures 11A to 11F show the simulation results performed on the signal generation circuit 10D shown in Figure 10.

[0112] Looking at graphs A and B (the two figures in the upper row) showing the three currents "-Id1", "Id2", and "Iq2-Iq1", it can be seen that the change in diode current due to ambient temperature is very small compared to the simulation results of the signal generation circuit 10 shown in Figure 3 (Figures 5A and 5B). Therefore, the idle current is stable with respect to temperature. In addition, there is almost no change in diode current due to the effect of the output resistance Rs of the current source that supplies the input current Ii.

[0113] Graphs C and D (the two figures in the middle), which show the error relative to the approximate straight line (Ii×ki) of "Iq2-Iq1", can be seen that "Iq2-Iq1", which is the sum of the currents flowing through each diode, and the input current Ii are in an almost perfect proportional relationship.

[0114] In the E-graph (lower left figure) showing the input resistance, the input resistance is smaller compared to the signal generation circuit 10 shown in Figure 3 (see Figure 5E), and the change in input resistance due to the effects of input current Ii and ambient temperature is also smaller.

[0115] In the F-graph (bottom right figure), which shows the error relative to the approximate straight line (Is×ks) of "Iq2-Iq1", the proportional relationship between "Iq2-Iq1" and the current Is is improved compared to the signal generation circuit 10 shown in Figure 3 (see Figure 5F).

[0116] Next, some modified versions of the signal generation circuit according to the third embodiment are shown. In these modified versions as well, since the voltage difference between voltages V1 and V2 is kept constant, it is possible to generate signals (S1, S2) for push-pull operation, similar to the signal generation circuit 10D shown in Figure 10.

[0117] (Modification 1 of the third embodiment) Figure 12 shows a modified example of the signal generation circuit according to the third embodiment. The signal generation circuit 10E shown in Figure 12 is obtained by replacing the voltage control unit 30D in the signal generation circuit 10D shown in Figure 10 with a voltage control unit 30E. The voltage control unit 30E is obtained by replacing the constant current supply unit 31D and diode circuit 32 in the voltage control unit 30D (Figure 10) with a constant current supply unit 31E and diode circuit 32E, respectively.

[0118] The constant current supply unit 31E is modified by replacing the constant current circuit CS1 in the constant current supply unit 31D with a resistor Rc1. The diode circuit 32E is modified by disconnecting the connection between the intermediate node M2 ​​and the reference voltage in the diode circuit 32 (Figure 10). As a result, the currents through diodes D5 and D6 become equal to the constant current Ic2. In this modified example, the idle currents of diodes D1 and D2 when the input current Ii is zero can be arbitrarily set by the current value of the constant current Ic2.

[0119] (Modification 2 of the third embodiment) Figure 13 shows a modified example of a signal generation circuit according to the third embodiment. The signal generation circuit 10F shown in Figure 13 is obtained by replacing the voltage control unit 30D in the signal generation circuit 10D shown in Figure 10 with a voltage control unit 30F. The voltage control unit 30F is obtained by replacing the constant current supply unit 31D and diode circuit 32 in the voltage control unit 30D (Figure 10) with a constant current supply unit 31F and diode circuit 32F, respectively.

[0120] The constant current supply unit 31F is modified by replacing the constant current circuit CS2 in the constant current supply unit 31D with a resistor Rc2. The diode circuit 32F is modified by disconnecting the connection between the intermediate node M2 ​​and the reference voltage in the diode circuit 32 (Figure 10). As a result, the currents through diodes D5 and D6 become the same as the constant current Ic1. In this modified example, the idle currents of diodes D1 and D2 when the input current Ii is zero can be arbitrarily set by the current value of the constant current Ic1.

[0121] It is preferable to select resistors Rc1 and Rc2 such that the potential at intermediate node M2 ​​is approximately equal to the reference voltage. Alternatively, a constant voltage source can be used instead of resistors Rc1 and Rc2. Similarly, when using a constant voltage source, it is preferable to select it such that the potential at intermediate node M2 ​​is approximately equal to the reference voltage.

[0122] (Modification 3 of the third embodiment) Figure 14 shows a modified example of the signal generation circuit according to the third embodiment. The signal generation circuit 10G shown in Figure 14 is obtained by replacing the voltage control unit 30D in the signal generation circuit 10D shown in Figure 10 with a voltage control unit 30G. In the voltage control unit 30G, the constant current supply unit 31D, diode circuit 32, and voltage generation unit 34 in the voltage control unit 30D (Figure 10) are replaced with a constant current supply unit 31G, diode circuit 32G, and voltage generation unit 34G, respectively.

[0123] Diode circuit 32G includes one diode D5. Diode D5 is positioned forward in the current path from node N5 to the reference voltage. The anode of diode D5 is connected to node N5, and its cathode is connected to the reference voltage.

[0124] The constant current supply unit 31G supplies a constant current Ic1 to the anode of diode D5 in the diode circuit 32G so that the same current as the idle current flows through diode D5 in the diode circuit 32G. In the example in Figure 14, the constant current supply unit 31G includes a constant current circuit CS1 that supplies a constant current Ic1 flowing from the positive voltage VL+ to node N5.

[0125] The voltage generation unit 34G generates voltages V1 and V2 based on the voltage V5 generated in diode D5 included in diode circuit 32G. In the example in Figure 14, the voltage generation unit 34G includes buffer circuits BF1 and BF2G. Buffer circuit BF1 receives the voltage V5 generated at node N5 and outputs a voltage V1 that is approximately the same as voltage V5. Buffer circuit BF2G receives the voltage V5 generated at node N5 and outputs a voltage V2 that is approximately the same as voltage V5 but with the sign reversed. Buffer circuit BF2G can be configured, for example, by providing an inverting amplifier circuit with a gain of -1 after a buffer circuit with high input impedance.

[0126] In this modified example, the idle currents of diodes D1 and D2 when the input current Ii is zero can be arbitrarily set by the current value of the constant current Ic1.

[0127] (Modification 4 of the third embodiment) Figure 15 shows a modified example of the signal generation circuit according to the third embodiment. The signal generation circuit 10H shown in Figure 15 is obtained by replacing the constant current supply unit 31D, diode circuit 32, and voltage generation unit 34 in the signal generation circuit 10D shown in Figure 10 with a constant current supply unit 31H, diode circuit 32H, and voltage generation unit 34H, respectively.

[0128] The diode circuit 32H includes one diode D6. Diode D6 is positioned forward in the current path from the reference voltage to node N5. The anode of diode D6 is connected to the reference voltage, and its cathode is connected to node N6.

[0129] The constant current supply unit 31H supplies a constant current Ic1 to the anode of diode D6 in the diode circuit 32H so that the same current as the idle current flows through diode D6 in the diode circuit 32H. In the example in Figure 15, the constant current supply unit 31H includes a constant current circuit CS2 that supplies a constant current Ic2 that flows out from node N6 to the negative voltage VL-.

[0130] The voltage generation unit 34H generates voltages V1 and V2 based on the voltage V6 generated in diode D6 included in diode circuit 32H. In the example in Figure 15, the voltage generation unit 34H includes buffer circuits BF1H and BF2. Buffer circuit BF2 receives the voltage V6 generated at node N6 and outputs a voltage V2 that is approximately the same as voltage V6. Buffer circuit BF1H receives the voltage V6 generated at node N6 and outputs a voltage V1 that is approximately the same as voltage V6 but with the sign reversed. Buffer circuit BF2H is constructed, for example, by providing an inverting amplifier circuit with a gain of -1 after a buffer circuit with high input impedance.

[0131] In this modified example, the idle currents of diodes D1 and D2 when the input current Ii is zero can be arbitrarily set by the current value of the constant current Ic2.

[0132] <Fourth Embodiment> Next, a fourth embodiment of the present invention will be described. Figure 16 is a diagram showing an example of a signal generation circuit according to the fourth embodiment. The configuration of the Class AB push-pull amplifier circuit 1, including the signal generation circuit 10J shown in Figure 16, is the same as in Figure 1.

[0133] The signal generation circuit 10J shown in Figure 16 is the same as the signal generation circuit 10D shown in Figure 10, but with the voltage control unit 30D replaced by the voltage control unit 30J. The voltage control unit 30J is the same as the voltage control unit 30D shown in Figure 10, but with the voltage generation unit 34J replaced by the voltage generation unit 34J.

[0134] In the example shown in Figure 16, the current detection unit 21 includes a shunt resistor SH1 provided in the current path between the output of the buffer circuit BF1J of the voltage generation unit 34J (described later) and the anode of the diode D1, and a current detection amplifier SA1 that amplifies the voltage generated across the shunt resistor SH and outputs it as a signal S1. The current detection unit 22 also includes a shunt resistor SH2 provided in the current path between the output of the buffer circuit BF2J of the voltage generation unit 34J (described later) and the cathode of the diode D2, and a current detection amplifier SA2 that amplifies the voltage generated across the shunt resistor SH2 and outputs it as a signal S2.

[0135] The voltage generation unit 34J includes buffer circuits BF1J and BF2J. The buffer circuit BF1J outputs a voltage to the shunt resistor SH1 that is an amplified voltage obtained by amplifying the difference between the voltage V1 at the anode of diode D1 and the voltage V5 at node N5. This voltage increases when the anode voltage V1 is lower than the voltage V5 and decreases when the anode voltage V1 is higher than the voltage V5. In the example in Figure 16, the buffer circuit BF1J is an operational amplifier that amplifies the difference between the voltage V1 at the anode of diode D1, which is input to the inverting input, and the voltage V5 at node N5, which is input to the non-inverting input, and applies the amplified voltage to one end of the shunt resistor SH1. Due to the buffer circuit BF1J, the voltage V1 at the anode of diode D1 becomes approximately equal to the voltage V5 at node N5. The buffer circuit BF2J outputs a voltage to the shunt resistor SH2 that is an amplified voltage obtained by amplifying the difference between the cathode voltage V2 of diode D2 and the voltage V6 of node N6. This voltage increases when the cathode voltage V2 is lower than the voltage V6 and decreases when the cathode voltage V2 is higher than the voltage V6. In the example in Figure 16, the buffer circuit BF2J is an operational amplifier that amplifies the difference between the cathode voltage V2 of diode D2, which is input to the inverting input, and the voltage V6 of node N6, which is input to the non-inverting input, and applies the amplified voltage to one end of the shunt resistor SH2. Due to the buffer circuit BF2J, the cathode voltage V2 of diode D2 becomes approximately equal to the voltage V6 of node N6.

[0136] According to this embodiment, even if a voltage drop occurs across the shunt resistor SH1 in response to the diode current Id1, the voltage V1 applied to the anode of diode D1 will be approximately equal to the voltage V5 at node N5. Similarly, even if a voltage drop occurs across the shunt resistor SH2 in response to the diode current Id2, the voltage V2 applied to the cathode of diode D2 will be approximately equal to the voltage V6 at node N6. Therefore, even if the voltage drops across shunt resistors SH1 and SH2 change in response to the input current Ii, the voltage difference between voltages V1 and V2 can be kept approximately the same as the voltage difference between voltages V5 and V6. This makes it possible to avoid temperature drift and a decrease in linearity of the idle current due to the effects of the voltage drops across shunt resistors SH1 and SH2.

[0137] Furthermore, the voltage generation unit 34 shown in Figures 12 and 13 above, and in Figures 17 to 19, 28, 30, and 31 described later, can be replaced with a voltage generation unit 34J having the buffer circuits BF1J and BF2J described above.

[0138] <Fifth Embodiment> Next, a fifth embodiment of the present invention will be described. Figure 17 is a diagram showing an example of a signal generation circuit according to the fifth embodiment. The configuration of the Class AB push-pull amplifier circuit 1, including the signal generation circuit 10K shown in Figure 17, is the same as in Figure 1.

[0139] The signal generation circuit 10K shown in Figure 17 is the same as the signal generation circuit 10D shown in Figure 10, but with the voltage control unit 30D replaced by the voltage control unit 30K. The voltage control unit 30K replaces the diode circuit 32 in the voltage control unit 30D (Figure 10) with the diode circuit 32K and adds a bias voltage supply unit 33.

[0140] Diode circuit 32K disconnects the connection between the intermediate node M2 ​​and the reference voltage in diode circuit 32 (Figure 10), and instead supplies the bias voltage Vb of the bias voltage supply unit 33 to the intermediate node M2.

[0141] The bias voltage supply unit 33 supplies a bias voltage Vb to the intermediate node M2 ​​that controls the voltage at the current input node Ni to be close to the reference voltage. The bias voltage supply unit 33 controls the bias voltage Vb so that it increases when the voltage at the current input node Ni decreases relative to the reference voltage, and decreases when the voltage at the current input node Ni increases relative to the reference voltage.

[0142] In this signal generation circuit 10K, as the input current Ii flowing from the current input node Ni to diode D2 increases, the voltage across diode D2 rises, and consequently the voltage across current input node Ni rises. To prevent the voltage across current input node Ni from rising relative to the reference voltage, the bias voltage Vb of intermediate node M2 ​​decreases. Also, as the input current Ii flowing out from diode D1 to current input node Ni increases, the voltage across diode D1 rises, and consequently the voltage across current input node Ni decreases. To prevent the voltage across current input node Ni from falling relative to the reference voltage, the bias voltage Vb of intermediate node M2 ​​increases. Therefore, as the incoming input current Ii increases, the diode current Id2 increases and the diode current Id1 decreases, and as the outgoing input current Ii increases, the diode current Id1 increases and the diode current Id2 decreases, but the voltage at the current input node Ni is always maintained at the reference voltage.

[0143] Thus, according to this embodiment, a bias voltage Vb is supplied to the intermediate node M2 ​​so that the current input node Ni is maintained at the reference voltage regardless of changes in the input current Ii. As a result, the input resistance of the current input node Ni becomes very small, so even when the output resistance Rs (Figures 2E to 2G) of the voltage-to-current conversion unit 5 that supplies the input current Ii is relatively small, the current Is (Figure 2G) that the voltage-to-current conversion unit 5 tries to output in proportion to the voltage Vi becomes almost equal to the input current Ii. Therefore, even when the output resistance Rs is relatively small, the distortion of nonlinearity due to fluctuations in the input resistance of the current input node Ni can be kept to a minimum.

[0144] (Modification 1 of the fifth embodiment) Figure 18 shows a modified example of the signal generation circuit according to the fifth embodiment. The signal generation circuit 10L shown in Figure 18 is obtained by replacing the voltage control unit 30K in the signal generation circuit 10K shown in Figure 17 with a voltage control unit 30L. The voltage control unit 30L is obtained by replacing the constant current supply unit 31D and the diode circuit 32K in the voltage control unit 30K (Figure 17) with a constant current supply unit 31L and a diode circuit 32L, respectively.

[0145] The constant current supply unit 31L has a constant current circuit CS2 that supplies a constant current Ic2 that flows out from node N6 to the negative voltage VL-.

[0146] Diode circuit 32K is created by disconnecting the connection between the intermediate node M2 ​​and the reference voltage in diode circuit 32 (Figure 10). As a result, a constant current Ic2 flows through diodes D5 and D6. The bias voltage Vb from the bias voltage supply unit 33 is supplied to node N5.

[0147] In this signal generation circuit 10K, the bias voltage Vb of node N5 is controlled so that the voltage at current input node Ni approaches the reference voltage, and the voltage at current input node Ni is maintained at the reference voltage regardless of the input current Ii, so the input resistance of current input node Ni becomes very small. Therefore, even if the output resistance Rs of the current source (voltage-to-current conversion unit 5) that supplies the input current Ii is relatively small, the nonlinear distortion due to fluctuations in the input resistance of current input node Ni can be kept to a minimum.

[0148] (Modification 2 of the fifth embodiment) Figure 19 shows a modified example of the signal generation circuit according to the fifth embodiment. The signal generation circuit 10M shown in Figure 19 is obtained by replacing the voltage control unit 30K in the signal generation circuit 10K shown in Figure 17 with a voltage control unit 30M. The voltage control unit 30M is obtained by replacing the constant current supply unit 31D and the diode circuit 32K in the voltage control unit 30K (Figure 17) with a constant current supply unit 31M and a diode circuit 32M, respectively.

[0149] The constant current supply unit 31M has a constant current circuit CS1 that supplies a constant current Ic1 flowing from the positive voltage VL+ to node N5.

[0150] Diode circuit 32M is obtained by disconnecting the connection between the intermediate node M2 ​​and the reference voltage in diode circuit 32 (Figure 10). Therefore, a constant current Ic1 flows through diodes D5 and D6. The bias voltage Vb from the bias voltage supply unit 33 is supplied to node N6.

[0151] In this signal generation circuit 10M, the bias voltage Vb of node N6 is controlled so that the voltage at current input node Ni approaches the reference voltage, and the voltage at current input node Ni is maintained at the reference voltage regardless of the input current Ii, so the input resistance of current input node Ni becomes very small. Therefore, even if the output resistance Rs of the current source (voltage-to-current conversion unit 5) that supplies the input current Ii is relatively small, the nonlinear distortion due to fluctuations in the input resistance of current input node Ni can be kept to a minimum.

[0152] (Modification 3 of the fifth embodiment) Figure 20 shows a modified example of the signal generation circuit according to the fifth embodiment. The signal generation circuit 10N shown in Figure 20 is obtained by replacing the voltage control unit 30K in the signal generation circuit 10K shown in Figure 17 with a voltage control unit 30N. In the voltage control unit 30N, the constant current supply unit 31D, diode circuit 32K, and voltage generation unit 34 in the voltage control unit 30K (Figure 17) are replaced with a constant current supply unit 31N, diode circuit 32N, and voltage generation unit 34N, respectively.

[0153] The constant current supply unit 31N has a constant current circuit CS1 that supplies a constant current Ic1 flowing from the positive voltage VL+ to node N5.

[0154] The diode circuit 32N has one diode D5. Diode D5 is positioned forward in the current path from node N5 to the output of the bias voltage supply unit 33. The anode of diode D5 is connected to node N5, and the bias voltage Vb of the bias voltage supply unit 33 is applied to its cathode.

[0155] The voltage generation unit 34N generates voltages V1 and V2 based on the voltage V5 generated in diode D5 included in diode circuit 32N. In the example in Figure 20, the voltage generation unit 34N includes buffer circuits BF1 and BF2N. Buffer circuit BF1 receives the voltage V5 generated at node N5 and outputs a voltage V1 that is approximately the same as voltage V5. Buffer circuit BF2N receives the voltage V5 generated at node N5 and outputs a voltage V2 that is approximately the same as voltage V5 but with the sign reversed. Buffer circuit BF2G can be configured, for example, by providing an inverting amplifier circuit with a gain of -1 after a buffer circuit with high input impedance.

[0156] In this signal generation circuit 10N, the bias voltage Vb of node N5 is controlled so that the voltage at current input node Ni approaches the reference voltage, and the voltage at current input node Ni is maintained at the reference voltage regardless of the input current Ii, so the input resistance of current input node Ni becomes very small. Therefore, even if the output resistance Rs of the current source (voltage-to-current conversion unit 5) that supplies the input current Ii is relatively small, the nonlinear distortion due to fluctuations in the input resistance of current input node Ni can be kept to a minimum.

[0157] (Modification 4 of the fifth embodiment) Figure 21 shows a modified example of the signal generation circuit according to the fifth embodiment. The signal generation circuit 10P shown in Figure 21 is obtained by replacing the voltage control unit 30K in the signal generation circuit 10K shown in Figure 17 with a voltage control unit 30P. The voltage control unit 30P is obtained by replacing the constant current supply unit 31D, diode circuit 32K, and voltage generation unit 34 in the voltage control unit 30K (Figure 17) with a constant current supply unit 31P, diode circuit 32P, and voltage generation unit 34P, respectively.

[0158] The constant current supply unit 31P has a constant current circuit CS2 that supplies a constant current Ic2 that flows out from node N6 to the negative voltage VL-.

[0159] The diode circuit 32P has one diode D6. Diode D6 is positioned in the forward direction in the current path from the output of the bias voltage supply unit 33 to node N6. The cathode of diode D6 is connected to node N6, and the bias voltage Vb from the bias voltage supply unit 33 is applied to the anode.

[0160] The voltage generation unit 34P generates voltages V1 and V2 based on the voltage V6 generated in diode D6 included in diode circuit 32P. In the example in Figure 21, the voltage generation unit 34P includes buffer circuits BF1P and BF2. Buffer circuit BF2 receives the voltage V6 generated at node N6 and outputs a voltage V2 that is approximately the same as voltage V6. Buffer circuit BF1P receives the voltage V6 generated at node N6 and outputs a voltage V1 that is approximately the same as voltage V6 but with the sign reversed. Buffer circuit BF2P is configured, for example, by providing an inverting amplifier circuit with a gain of -1 after a buffer circuit with high input impedance.

[0161] In this signal generation circuit 10P, the bias voltage Vb of node N6 is controlled so that the voltage of current input node Ni approaches the reference voltage, and the voltage of current input node Ni is maintained at the reference voltage regardless of the input current Ii, so the input resistance of current input node Ni becomes very small. Therefore, even if the output resistance Rs of the current source (voltage-to-current conversion unit 5) that supplies the input current Ii is relatively small, the nonlinear distortion due to fluctuations in the input resistance of current input node Ni can be kept to a minimum.

[0162] <Sixth Embodiment> Next, a sixth embodiment of the present invention will be described. Figure 22 is a diagram showing an example of a signal generation circuit according to the sixth embodiment. The configuration of the Class AB push-pull amplifier circuit 1 including the signal generation circuit 10Q shown in Figure 22 is the same as in Figure 1.

[0163] The signal generation circuit 10Q shown in Figure 22 includes a current input node Ni, diodes D1 and D2, current detection units 23 and 24, and a voltage control unit 30Q. Diode D1 is an example of the first diode of the present invention. Diode D2 is an example of the second diode of the present invention.

[0164] A voltage V1 controlled by the voltage control unit 30Q is applied to the anode of diode D1. A voltage V2 controlled by the voltage control unit 30Q is applied to the cathode of diode D2. The current input node Ni is located in the path of the current flowing from the cathode of diode D1 to the anode of diode D2, and the input current Ii flows in or out through it.

[0165] The current detection unit 23 outputs a signal S1 that detects the diode current Id1 flowing through the diode D1. The current detection unit 24 outputs a signal S2 that detects the diode current Id2 flowing through the diode D2.

[0166] Figures 23A to 23C show an example of a current detection unit 23 that detects the current of a diode D1 whose cathode is held at a reference voltage.

[0167] The current detection unit 23 of diode D1 (Figure 23A) includes an operational amplifier U23 and a negative feedback resistor R23, as shown in Figure 23B, for example. The operational amplifier U23 is an example of the first operational amplifier of the present invention. The negative feedback resistor R23 is an example of the first negative feedback resistor of the present invention.

[0168] The operational amplifier U23 amplifies the difference between the cathode voltage of diode D1 and the reference voltage. When the cathode voltage of diode D1 decreases relative to the reference voltage, the output voltage of the operational amplifier U23 increases, and when the cathode voltage of diode D1 increases relative to the reference voltage, the output voltage decreases. In the example in Figure 23B, the reference voltage is input to the non-inverting input of the operational amplifier U23, and the cathode voltage of diode D1 is input to the inverting input. The negative feedback resistor R23 is provided in the current path between the cathode of diode D1 and the output of the operational amplifier U23.

[0169] In the current detection unit 23 shown in Figure 23B, when the open-loop gain of the operational amplifier U23 is sufficiently large, the operational amplifier U23 outputs a signal S1 with a negative voltage corresponding to the diode current Id1 flowing through the diode D1, and the cathode voltage of the diode D1 is maintained at a voltage sufficiently close to the reference voltage.

[0170] On the other hand, the current detection unit 23 shown in Figure 23C has a shunt resistor SH23 and a voltage amplification circuit SA23.

[0171] The shunt resistor SH23 is placed in the current path between the cathode of diode D1 and the reference voltage. The voltage amplification circuit SA23 amplifies the voltage across the shunt resistor SH23 and outputs it as signal S1.

[0172] In the current detection unit 23 shown in Figure 23C, when the voltage drop across the shunt resistor SH23 is sufficiently small, a signal S1 with a voltage corresponding to the diode current Id1 flowing through the diode D1 is output by the voltage amplification circuit SA23, and the cathode voltage of diode D1 is maintained at a voltage close to the reference voltage.

[0173] The current detection unit 24 of diode D2 (Figure 23D) includes an operational amplifier U24 and a negative feedback resistor R24, as shown in Figure 23E, for example. The operational amplifier U24 is an example of the second operational amplifier of the present invention. The negative feedback resistor R24 ​​is an example of a second negative feedback resistor according to the present invention.

[0174] The operational amplifier U24 amplifies the difference between the voltage at the anode of diode D2 and the reference voltage. The output voltage of the operational amplifier U24 increases when the voltage at the anode of diode D2 decreases relative to the reference voltage, and decreases when the voltage at the cathode of diode D2 increases relative to the reference voltage. In the example shown in Figure 23E, the operational amplifier U24 receives the reference voltage as its non-inverting input and the voltage at the anode of diode D2 as its inverting input. A negative feedback resistor R24 ​​is placed in the current path between the anode of diode D2 and the output of the operational amplifier U24.

[0175] In the current detection unit 24 shown in Figure 23E, when the open-loop gain of the operational amplifier U24 is sufficiently large, the operational amplifier U24 outputs a signal S2 with a positive voltage corresponding to the diode current Id2 flowing through the diode D2, and the voltage at the anode of the diode D2 is maintained at a voltage sufficiently close to the reference voltage.

[0176] On the other hand, the current detection unit 24 shown in Figure 23F has a shunt 'v resistor SH24 and a voltage amplification circuit SA24.

[0177] The shunt resistor SH24 is placed in the current path between the anode of diode D2 and the reference voltage. The voltage amplification circuit SA24 amplifies the voltage across the shunt resistor SH24 and outputs it as signal S2.

[0178] In the current detection unit 24 shown in Figure 23F, when the voltage drop across the shunt resistor SH24 is sufficiently small, a signal S2 with a voltage corresponding to the diode current Id2 flowing through the diode D2 is output by the voltage amplification circuit SA24, and the voltage at the anode of diode D2 is maintained at a voltage close to the reference voltage.

[0179] The circuits shown in Figure 23B, relating to the current detection unit 23, and Figure 23E, relating to the current detection unit 24, are preferable because they do not produce errors due to voltage across the shunt resistors (SH, SH23, SH24). Note that since these two circuits are inverting current-voltage conversion circuits, attention must be paid to the polarity of the signals.

[0180] Return to Figure 22. The voltage control unit 30Q controls voltages V1 and V2 so that predetermined idle currents flow as diode current Id and diode current Id2, respectively, when the input current Ii is zero. Furthermore, the voltage control unit 30Q controls voltages V1 and V2 such that when the input current Ii flowing in the first direction (e.g., outflow direction) at the current input node Ni increases, the diode current Id2 increases and the diode current Id1 decreases, and the difference between the diode current Id2 and the diode current Id1 becomes a current proportional to the input current Ii flowing in the first direction (e.g., outflow direction). Furthermore, the voltage control unit 30Q controls voltages V1 and V2 such that when the input current Ii increases in a second direction opposite to the first direction (for example, the inflow direction), the diode current Id1 increases and the diode current Id2 decreases, and the difference between the diode current Id1 and the diode current Id2 becomes a current proportional to the input current Ii flowing in the second direction (for example, the inflow direction).

[0181] When the input current Ii is zero, a predetermined idle current flows as diode current Id1 and diode current Id2, respectively, through the control of voltages V1 and V2 by the voltage control unit 30Q. Therefore, when the input current Ii is zero, the first output unit 6 and the second output unit 7 are controlled based on the signals (S1 and S2) that detect the diode currents (Id1 and Id2), and a predetermined idle current flows as current Ip flowing out of the first output unit 6 and current In flowing into the second output unit 7, respectively.

[0182] Furthermore, when the input current Ii flowing into or out of the current input node Ni increases due to the control of voltages V1 and V2 by the voltage control unit 30, one of the diode currents Id1 and Id2 increases while the other decreases, and the difference between the increasing diode current and the decreasing diode current becomes a current proportional to the input current Ii flowing into the current input node Ni in the direction of increase (inflow or outflow). Therefore, when the input current Ii flowing into or out of the current input node Ni increases due to the control of the first output unit 6 and the second output unit 7 based on the signals (S1, S2) that detect the diode currents (Id1, Id2), one of the currents Ip and In increases while the other decreases, and the difference between the increasing current and In and the decreasing current becomes the current Ix flowing into the current output node Nx in one direction (inflow or outflow) corresponding to the direction (inflow or outflow) of the increasing input current Ii.

[0183] Therefore, in response to the input current Ii flowing through the current input node Ni, the first output unit 6 and the second output unit 7 perform a Class AB push-pull operation.

[0184] In the example shown in Figure 22, the voltage control unit 30Q includes a diode D7 provided in the forward direction in the current path from node N7 to current input node Ni, a diode D8 provided in the forward direction in the current path from current input node Ni to node N8, a resistor R2 provided in the current path between nodes N7 and N8, and a constant current supply unit 31. The anode of diode D7 is connected to node N7 and its cathode is connected to current input node Ni. The anode of diode D8 is connected to current input node Ni and its cathode is connected to node N8. The resistor R2 is connected between nodes N7 and N8. Diode D7 is an example of the seventh diode of the present invention. Diode D8 is an example of the eight diodes of the present invention. Resistor R2 is an example of the second resistor of the present invention.

[0185] In the example shown in Figure 22, the constant current supply unit 31 includes a constant current circuit CS1 that supplies a constant current Ic1 flowing from the positive voltage VL+ to node N7, and a constant current circuit CS2 that supplies a constant current Ic2 flowing from node N8 to the negative voltage VL-. The constant current Ic1 of constant current circuit CS1 and the constant current Ic2 of constant current circuit CS2 are set to approximately the same current.

[0186] The signal generation circuit 10Q shown in Figure 22 is equivalent to the signal generation circuit 10 shown in Figure 3, except for the current detection units 23 and 24. That is, if diodes D1, D2, D7, D8, and resistor R2 in the signal generation circuit 10Q are replaced with diodes D3, D4, D1, D2, and resistor R1, respectively, then the signal generation circuit 10Q, excluding the current detection units 23 and 24, is identical to the signal generation circuit 10, excluding the current detection units 21 and 22.

[0187] Therefore, in the signal generation circuit 10Q shown in Figure 22, diode currents Id8 and Id1 are the same, and diode currents Id7 and Id2 are the same. Also, when the input current Ii is zero, the idle currents flowing through diodes D7 and D8 are the same as the idle currents flowing through diodes D1 and D2.

[0188] When the input current Ii flowing from the current input node Ni to diode D8 increases, the diode current Id1 increases and the diode current Id2 decreases. The difference between diode current Id1 and diode current Id2 becomes a current proportional to the incoming input current Ii (the same current). Similarly, when the input current Ii flowing out from diode D7 to the current input node Ni increases, the diode current Id2 increases and the diode current Id1 decreases. The difference between diode current Id2 and diode current Id1 becomes a current proportional to the outgoing input current Ii (the same current).

[0189] Thus, according to this embodiment, signals S1 and S2 can be generated to cause the output stage (first output section 6, second output section 7) of the amplification circuit to perform a Class AB push-pull operation, similar to the signal generation circuit 10 shown in Figure 3.

[0190] <Seventh Embodiment> Next, a seventh embodiment of the present invention will be described. Figure 24 is a diagram showing an example of a signal generation circuit according to the seventh embodiment. The configuration of the Class AB push-pull amplifier circuit 1, including the signal generation circuit 10R shown in Figure 24, is the same as in Figure 1.

[0191] The signal generation circuit 10R shown in Figure 24 is the same as the signal generation circuit 10Q shown in Figure 22, but with the voltage control unit 30Q replaced by the voltage control unit 30R.

[0192] The voltage control unit 30R includes a diode circuit 32R, a constant current supply unit 31R, a voltage amplification unit 35, and voltage divider resistors Rd1 to Rd4.

[0193] Diode circuit 32R includes multiple diodes connected in series. In the example in Figure 24, diode circuit 32R includes diodes D9 and D10. Diode D9 is forward-facing in the current path from node N9 to intermediate node M3. Diode D10 is forward-facing in the current path from intermediate node M3 to node N10. Diode D9 is an example of the ninth diode of the present invention. Diode D10 is an example of the 10 diodes of the present invention.

[0194] In the example shown in Figure 24, the intermediate node M3 is held at the reference voltage.

[0195] Furthermore, in the example in Figure 24, the diode circuit 32R includes resistors R3 and R4 connected in series with diodes D9 and D10. Resistor R3 is connected in series with diode D9 in the current path from node N9 to intermediate node M3. Resistor R4 is connected in series with diode D10 in the current path from intermediate node M3 to node N10. Resistors R3 and R4 have equal resistance values. Resistor R3 is an example of the third resistor of the present invention. Resistor R4 is an example of the fourth resistor of the present invention.

[0196] The constant current supply unit 31R supplies a constant current Irc3 flowing into the anode of diode D9 at one end of the diode circuit 32R, and a constant current Irc4 flowing out from the cathode of diode D10 at the other end of the diode circuit 32R, so that a current corresponding to the idle current flows through each diode (D9, D10) of the diode circuit 32R. Constant currents Irc3 and Irc4 are equal currents.

[0197] In the example shown in Figure 24, the constant current supply unit 31R includes a resistor Rc3 through which a constant current Irc3 flows from the positive voltage VL+ to node N9, and a resistor Rc4 through which a constant current Irc4 flows out from node N10 to the negative voltage VL-. If the resistance values ​​of resistors Rc3 and Rc4 are sufficiently large compared to the change in the resistance values ​​of diodes D9 and D10, the constant currents Irc3 and Irc4 can be considered as constant currents that do not depend on the resistance values ​​(voltage-current characteristics) of diodes D9 and D10.

[0198] The voltage amplification unit 35 amplifies the voltages generated in diodes D9 and D10 included in the diode circuit 32R, thereby generating a voltage Va1 that is positive with respect to the reference voltage and a voltage Va2 that is negative with respect to the reference voltage.

[0199] The voltage amplification unit 35 generates voltage Va1 by amplifying the voltage V9 generated at node N9, and generates voltage Va2 by amplifying the voltage V10 generated at node N10. The amplification factor of voltage Va1 relative to voltage V9 is equal to the amplification factor of voltage Va2 relative to voltage V10.

[0200] In the example of FIG. 24, the voltage amplification section 35 includes a voltage amplification section AV1 that amplifies voltage V9 and outputs voltage Va1, and a voltage amplification section AV2 that amplifies voltage V10 and outputs voltage Va2. The voltage amplification section AV1 outputs a positive voltage Va1 obtained by amplifying the positive voltage V9 relative to the reference voltage with an amplification factor A, and the voltage amplification section AV2 outputs a negative voltage Va2 obtained by amplifying the negative voltage V10 relative to the reference voltage with the amplification factor A.

[0201] The voltage dividing resistor Rd1 is provided in the current path between the output of the voltage amplification section 35 where the voltage Va1 is generated (the output of the voltage amplification section AV1) and the anode of the diode D1. The voltage dividing resistor Rd2 is provided in the current path between the anode of the diode D1 and the current input node Ni. The voltage dividing resistor Rd3 is provided in the current path between the output of the voltage amplification section 35 where the voltage Va2 is generated (the output of the voltage amplification section AV2) and the cathode of the diode D2. The voltage dividing resistor Rd3 is provided in the current path between the cathode of the diode D3 and the current input node Ni. The resistance value of the voltage dividing resistor Rd1 is equal to the resistance value of the voltage dividing resistor Rd3, and the resistance value of the voltage dividing resistor Rd2 is equal to the resistance value of the voltage dividing resistor Rd4. The voltage dividing resistor Rd1 is an example of the first voltage dividing resistor of the present invention. The voltage dividing resistor Rd2 is an example of the second voltage dividing resistor of the present invention. The voltage dividing resistor Rd3 is an example of the third voltage dividing resistor of the present invention. The voltage dividing resistor Rd4 is an example of the fourth voltage dividing resistor of the present invention.

[0202] In the signal generation circuit 10R shown in Figure 24, when input current Ii flows into the current input node Ni, the voltage Vn at the current input node Ni increases, and consequently, voltages V1 and V2 rise to the positive side, causing the voltage across diode D1 to increase and the voltage across diode D2 to decrease. As a result, diode current Id1 increases and diode current Id2 decreases. Conversely, when input current Ii flows out from the current input node Ni, diode current Id1 decreases and diode current Id2 increases.

[0203] The anode voltage V1 and diode current Id1 of diode D1 satisfy a relationship (expressed as a linear function) based on the currents Ird1 and Ird2 flowing through resistors Rd1 and Rd2 and their voltages Va1 and Vn, as well as a relationship (approximated by an exponential function) based on the voltage-current characteristics of diode D1. Therefore, the voltage V1 and diode current Id1 are determined at the operating point where the straight line of the former linear function intersects with the curve of the latter voltage-current function. The same applies to the voltage V2 and diode current Id2 of diode D2; they are determined at the operating point where the straight line of the linear function based on resistors Rd2 and Rd2 and their voltages Va2 and Vn intersects with the curve of the voltage-current function of diode D2.

[0204] Since the resistance values ​​of voltage divider resistors Rd1 and Rd3 are equal, and the resistance values ​​of voltage divider resistors Rd2 and Rd4 are equal, the slope of the linear function satisfied by (V1, Id1) is equal to the slope of the linear function satisfied by (V2, Id2). Also, since diodes D1 and D2 have the same voltage-current characteristics, the voltage-current function of (V1, Id1) is equal to the voltage-current function of (V2, Id2).

[0205] When the voltage Vn is equal to the reference voltage and is zero (i.e., when the input current Ii is zero), the operating points of diodes D1 and D2 are the same. Let Vds be the forward voltage of diodes D1 and D2 and Ids be the forward current of diodes D1 and D2 at Vn=0 (Ii=0). When Vn=0, V1=-V2=Vds and Id1=Id2=Ids.

[0206] When the voltage Vn at the current input node Ni changes from zero due to the inflow or outflow of input current Ii, the linear function described above shifts in parallel while maintaining its slope. That is, when the voltage Vn changes from zero in response to the input current Ii, the linear function line satisfied by (V1, Id1) and the linear function line satisfied by (V2, Id2) shift in parallel by the same amount of distance in opposite directions from the operating point (Vds, Ids) where Vn=0. As the linear function lines shift, the operating points of diodes D1 and D2 change, respectively.

[0207] In the vicinity of the operating point (Vds, Ids) where Vn=0, the slope of the linear function may be made to approximate the slope of the function curves of diodes D1 and D2 at the operating point (Vds, Ids) so that the changes in diode currents Id1 and Id2 with respect to the diode current Ids at the operating point are approximately the same.

[0208] If the resistance values ​​of the voltage divider resistors Rd1 and Rd3 are "r1", and the resistance values ​​of the voltage divider resistors Rd2 and Rd4 are "r2", then the diode current Id1 is expressed by the following formula.

[0209] [Formula 3] Id1 = (Va1 / r1)+(Vn / r2)-(V1 / rp) …(3)

[0210] Here, "Rp" is the resistance value when the voltage divider resistors Rd1 and Rd2 are connected in parallel, and is expressed by the following formula.

[0211] [Formula 4] rp = r1·r2 / (r1+r2) …(4)

[0212] The resistance value rp in equation (4) corresponds to the slope of the linear function described above. In one example, the resistance values ​​r1 and r2 may be set so that this resistance value rp corresponds to (is equal to or approximates) the differential resistance of the diodes (D1 and D2) at the operating point (Vds and Ids).

[0213] From Equation (1), the voltage V1 is expressed by the following equation.

[0214] [Equation 5] V1 = k2·Va1+k1·Vn-rp·Id1 …(5)

[0215] Here, "k1" and "k2" are expressed by the following equations.

[0216] [Equation 6] k1 = r1 / (r1+r2) …(6-1) k2 = r2 / (r1+r2) …(6-2)

[0217] Here, assuming that the current Irc3 supplied from the constant current supply unit 31R to the diode D9 is the current Ids at the operating point, the voltage of the diode D9 becomes the voltage Vds at the operating point. In this case, when the resistance value of the resistor R3 is defined as "r3", the voltage Va1 is expressed by the following equation.

[0218] [Equation 7] Va1 = A·(Vds+r3·Ids) …(7)

[0219] At Vn=0, V1=Vds, so substituting Equation (7) into Equation (5) gives the following equation.

[0220] [Equation 8] Vds = k2·A·Vds+(k2·A·r3-rp)·Ids …(8)

[0221] In order to establish the relationship of Equation (8), the voltage amplification factor A and the resistance value r3 of the resistor R3 may be set as follows, for example.

[0222] [Equation 9] A = 1 / k2 = (r1+r2) / r2 …(9-1) r3 = rp = r1·r2 / (r1+r2) …(9-2)

[0223] By setting the amplification factor A and the resistance value r3 of resistor R3 so that the voltages generated across diodes D9 and D10 are equal to the voltages (V1 and V2) generated across diodes D1 and D2 at Vn=0 (Ii=0), the idle current Ids flowing through diodes D1 and D2 at Vn=0 (Ii=0) can be set to be equal to the constant currents Irc3 and Irc4 supplied from the constant current supply unit 31R. This effectively suppresses fluctuations in the idle current Ids due to temperature influences.

[0224] As described above, in this embodiment as well, one of the diode currents Id1 and Id2 can be increased and the other decreased according to the input current Ii, so that signals for push-pull operation (S1, S2) can be generated.

[0225] According to this embodiment, by generating constant currents Irc3 and Irc4 using resistors in the constant current supply unit 31R, the number of components can be reduced and costs can be lowered.

[0226] In this embodiment, the voltage amplification unit 35 is an amplification circuit that outputs constant voltages Va1 and Va2 based on constant voltages V9 and V10, and can be constructed using a relatively slow and simple operational amplifier. Furthermore, the current detection units 23 and 24 can be constructed using the simple circuits shown in Figures 23A to 23F. Therefore, the overall number of components can be reduced, thereby lowering costs.

[0227] [Simulation results of the signal generation circuit 10R shown in Figure 24: Figures 25A to 25F] Figures 25A to 25F show the simulation results performed on the signal generation circuit 10R shown in Figure 24.

[0228] Looking at graphs A and B (the two figures in the upper row), which show the three currents "-Id1", "Id2", and "Iq2-Iq1", it can be seen that the idle current is set smaller compared to the simulations in Figures 5, 7, and 11. In this simulation, the ratio of the idle current to the maximum current (±1mA) is about 1 / 30.

[0229] Furthermore, in graphs A and B (the two figures in the upper section), the temperature-dependent changes of "-Id1", "Id2", and "Iq2-Iq1" are improved compared to signal generation circuit 10 (Figures 5A and 5B) and signal generation circuit 10A (Figures 7A and 7B).

[0230] In the F-graph (bottom right figure), which shows the error relative to the approximate straight line (Is×ks) of "Iq2-Iq1", the nonlinearity and temperature-dependent changes are improved compared to the signal generation circuit 10A (Figure 5F).

[0231] In graphs C and D (the two figures in the middle), which show the error relative to the approximate straight line (Ii×ki) of "Iq2-Iq1", the proportional relationship between "Iq2-Iq1" and the input current Ii is slightly worse compared to the simulation of a signal generation circuit with a current input node Ni at the midpoint of the connection between diodes D1 and D2 (Figures 5, 7, and 11). However, this error is only about 0.3% of the full scale (about ±3μA for ±1mA), which can be considered an acceptable level.

[0232] In the E graph (lower left figure) showing the input resistance, the change in input resistance due to input current Ii and temperature is significantly improved compared to the signal generation circuit 10 (Figure 5E). In the F graph (lower right figure) showing the error relative to the approximate straight line (Is × ks) of "Iq2 - Iq1", the proportional relationship between "Iq2 - Iq1" and current Is is improved due to the improvement in the input resistance fluctuation shown in the E graph, and the change due to temperature is particularly suppressed.

[0233] (Modification 1 of the 7th embodiment) Figure 26 shows a modified example of the signal generation circuit according to the seventh embodiment. The signal generation circuit 10S shown in Figure 26 is obtained by replacing the voltage control unit 30R in the signal generation circuit 10R shown in Figure 24 with a voltage control unit 30S. The voltage control unit 30S is obtained by replacing the constant current supply unit 31R, diode circuit 32R, and voltage amplification unit 35R in the voltage control unit 30R (Figure 24) with a constant current supply unit 31S, diode circuit 32S, and voltage amplification unit 35S, respectively.

[0234] The diode circuit 32S includes one diode D9. Diode D9 is forward-facing in the current path from node N9 to the reference voltage. The diode circuit 32S also includes a resistor R3 connected in series with diode D9 in the current path from node N9 to the reference voltage.

[0235] The constant current supply unit 31S supplies a constant current Irc3 to flow into the anode of diode D9 in the diode circuit 32S, such that a current corresponding to the idle current flows through diode D9 in the diode circuit 32S. In the example in Figure 26, the constant current supply unit 31G includes a resistor Rc3 as a constant current circuit that supplies a constant current Irc3 flowing from the positive voltage VL+ to node N9.

[0236] The voltage amplification unit 35S generates voltages Va1 and Va2, which are positive and negative voltages with respect to a reference voltage, by amplifying the voltage V9 generated in diode D9 included in diode circuit 32S. The voltage amplification unit 35S generates a positive voltage Va1 by amplifying the positive voltage V9 at node N9 with a positive gain, and generates a negative voltage Va2 by amplifying the positive voltage V9 with a negative gain.

[0237] In the example shown in Figure 26, the voltage amplifier 35S includes a voltage amplifier AV1 that amplifies a positive voltage V9 with a gain of A and outputs a positive voltage Va1, and a voltage amplifier AV2S that amplifies the voltage V9 with a gain of -A and outputs a negative voltage Va2. A pair of amplifier circuits (AV1, AV2S) that output voltages with the same gain but inverted phase can be made using a well-known differential output amplifier circuit.

[0238] Thus, even with a configuration that generates positive and negative voltages Va1 and Va2 from the voltage of a single diode D9, the same operation as the signal generation circuit 10R shown in Figure 24 is possible. In this modified example, the idle currents of diodes D1 and D2 when the input current Ii is zero can be arbitrarily set by the resistance value of resistor Rc3.

[0239] (Modification 2 of the 7th embodiment) Figure 27 shows a modified example of the signal generation circuit according to the seventh embodiment. The signal generation circuit 10T shown in Figure 27 is obtained by replacing the voltage control unit 30R in the signal generation circuit 10R shown in Figure 24 with a voltage control unit 30T. The voltage control unit 30T is obtained by replacing the constant current supply unit 31R, diode circuit 32R, and voltage amplification unit 35R in the voltage control unit 30R (Figure 24) with a constant current supply unit 31T, diode circuit 32T, and voltage amplification unit 35T, respectively.

[0240] The diode circuit 32T includes one diode D10. Diode D10 is forward-facing in the current path from the reference voltage to node N10. The diode circuit 32T also includes a resistor R4 connected in series with diode D10 in the current path from the reference voltage to node N10.

[0241] The constant current supply unit 31T supplies a constant current Irc4 flowing out from the cathode of diode D10 in the diode circuit 32T so that a current corresponding to the idle current flows through diode D10 in the diode circuit 32T. In the example in Figure 27, the constant current supply unit 31T includes a resistor Rc4 as a constant current circuit that supplies the constant current Irc4 flowing out from node N10 to the negative voltage VL-.

[0242] The voltage amplification unit 35T generates voltages Va1 and Va2, which are positive and negative voltages with respect to a reference voltage, by amplifying the voltage V10 generated in diode D10 included in diode circuit 32T. The voltage amplification unit 35T generates a positive voltage Va1 by amplifying the negative voltage V10 at node N10 with a negative gain, and generates a negative voltage Va2 by amplifying the negative voltage V10 with a positive gain.

[0243] In the example shown in Figure 26, the voltage amplifier 35S includes a voltage amplifier AV1T that amplifies a negative voltage V10 with a gain of -A to output a positive voltage Va1, and a voltage amplifier AV2 that amplifies the negative voltage V10 with a gain of A to output a negative voltage Va2. A pair of amplifier circuits (AV1T, AV2) that output voltages with the same gain but inverted phase can be made using a well-known differential output amplifier circuit.

[0244] In this modified example, the idle currents of diodes D1 and D2 when the input current Ii is zero can be arbitrarily set by the resistance value of resistor Rc4.

[0245] <Eighth Embodiment> Next, an eighth embodiment of the present invention will be described. Figure 28 is a diagram showing an example of a signal generation circuit according to the eighth embodiment. The configuration of the Class AB push-pull amplifier circuit 1, including the signal generation circuit 10U shown in Figure 28, is the same as in Figure 1.

[0246] The voltage control unit 30U shown in Figure 28 is a replacement of the voltage control unit 30Q in the signal generation circuit 10Q shown in Figure 22.

[0247] The voltage control unit 30U has the same configuration as the signal generation circuit 10K shown in Figure 17, but with the current detection units 21 and 22 omitted. In other words, the voltage control unit 30U is the same as the signal generation circuit 10K shown in Figure 17, but with the current detection units 21 and 22 omitted and diodes D1 and D2 renamed to diodes D11 and D12, respectively. Therefore, the diode currents Id11 and Id12 flowing through diodes D11 and D12 in the voltage control unit 30U in response to the input current Ii are the same as the diode currents Id1 and Id2 flowing through diodes D1 and D2 in response to the input current Ii in the signal generation circuit 10K shown in Figure 17. Diode D11 is an example of the 11th diode of the present invention. Diode D12 is an example of the 12 diodes of the present invention.

[0248] In the voltage control unit 30U shown in Figure 28, the voltage at the current input node Ni is controlled to be equal to the reference voltage. Therefore, the diode current Id1 of diode D1 becomes the same as the diode current Id11 of diode D11, and the diode current Id2 of diode D2 becomes the same as the diode current Id11 of diode D11. Consequently, the signal S1 detecting the diode current Id1 and the signal S2 detecting the diode current Id2 are approximately the same as the signals S1 and S2 of the signal generation circuit 10K shown in Figure 17.

[0249] According to this embodiment, since the cathode of diode D1 and the anode of diode D2 are held at a reference voltage, more accurate current detection units 23 and 24 shown in Figures 23A to 23F can be used.

[0250] [Simulation results of the signal generation circuit 10U shown in Figure 28: Figures 29A to 29F] Figures 29A to 29F show the simulation results performed on the signal generation circuit 10U shown in Figure 28.

[0251] In graphs A and B (the two upper figures) showing the three currents "-Id1", "Id2", and "Iq2-Iq1", there is almost no change in the current flowing through each diode due to ambient temperature, compared to signal generation circuit 10 (Figures 5A and 5B) and signal generation circuit 10A (Figures 7A and 7B). Therefore, in this embodiment, the idle current is less affected by ambient temperature. Furthermore, it is hardly affected by the impedance of the current source supplying the input current Ii.

[0252] In graphs C and D (the two figures in the middle), which show the error relative to the approximate straight line (Ii×ki) of "Iq2-Iq1", "Iq2-Iq1" and the input current Ii are proportional with good accuracy, and there is no degradation of the proportional relationship due to the impedance of the current source supplying the input current Ii.

[0253] In the F-graph (bottom right figure), which shows the error relative to the approximate straight line (Is × ks) of "Iq2 - Iq1", "Iq2 - Iq1" and the current Is are accurately proportional, and the impedance of the current source supplying the input current Ii does not appear to have any effect.

[0254] Graphs C, D, and F show slight nonlinearity compared to the signal generation circuit 10A (Figures 7C, 7D, and 7F), but the error is more than six orders of magnitude smaller than the full-scale ±1mA, so it should not be a problem.

[0255] In the E-graph showing the input resistance (lower left figure), the resistance value is even lower than that of the signal generation circuit 10A (Figure 7E). Therefore, it is possible to reduce the nonlinear distortion caused by the impedance of the current source supplying the input current Ii.

[0256] (Modification 1 of the 8th embodiment) Figure 30 shows a modified example of the signal generation circuit according to the eighth embodiment. The signal generation circuit 10V shown in Figure 30 is obtained by replacing the voltage control unit 30Q in the signal generation circuit 10Q shown in Figure 22 with a voltage control unit 30V.

[0257] The voltage control unit 30V has the same configuration as the signal generation circuit 10L shown in Figure 18, but with the current detection units 21 and 22 omitted. That is, the voltage control unit 30V is the same as the signal generation circuit 10L shown in Figure 18, but with the current detection units 21 and 22 omitted and diodes D1 and D2 renamed to diodes D11 and D12, respectively. Therefore, the diode currents Id11 and Id12 that flow through diodes D11 and D12 in the voltage control unit 30V in response to the input current Ii are the same as the diode currents Id1 and Id2 that flow through diodes D1 and D2 in response to the input current Ii in the signal generation circuit 10L shown in Figure 18. Therefore, in this modified example, the signals S1 and S2 obtained in response to the input current Ii are approximately the same as the signals S1 and S2 of the signal generation circuit 10L shown in Figure 18, respectively.

[0258] (Modification 2 of the 8th embodiment) Figure 31 shows a modified example of the signal generation circuit according to the eighth embodiment. The signal generation circuit 10W shown in Figure 31 is obtained by replacing the voltage control unit 30Q in the signal generation circuit 10Q shown in Figure 22 with a voltage control unit 30W.

[0259] The voltage control unit 30W has the same configuration as the signal generation circuit 10M shown in Figure 19, but with the current detection units 21 and 22 omitted. That is, the voltage control unit 30W is the same as the signal generation circuit 10M shown in Figure 19, but with the current detection units 21 and 22 omitted and diodes D1 and D2 renamed to diodes D11 and D12, respectively. Therefore, the diode currents Id11 and Id12 flowing through diodes D11 and D12 in the voltage control unit 30W in response to the input current Ii are the same as the diode currents Id1 and Id2 flowing through diodes D1 and D2 in response to the input current Ii in the signal generation circuit 10M shown in Figure 19. Therefore, in this modified example, the signals S1 and S2 obtained in response to the input current Ii are approximately the same as the signals S1 and S2 of the signal generation circuit 10M shown in Figure 19, respectively.

[0260] (Modification 3 of the 8th embodiment) Figure 32 shows a modified example of the signal generation circuit according to the eighth embodiment. The signal generation circuit 10X shown in Figure 32 is obtained by replacing the voltage control unit 30Q in the signal generation circuit 10Q shown in Figure 22 with a voltage control unit 30X.

[0261] The voltage control unit 30X has the same configuration as the signal generation circuit 10N shown in Figure 20, but with the current detection units 21 and 22 omitted. That is, the voltage control unit 30X is the same as the signal generation circuit 10N shown in Figure 20, but with the current detection units 21 and 22 omitted and diodes D1 and D2 renamed to diodes D11 and D12, respectively. Therefore, the diode currents Id11 and Id12 flowing through diodes D11 and D12 in the voltage control unit 30X in response to the input current Ii are the same as the diode currents Id1 and Id2 flowing through diodes D1 and D2 in response to the input current Ii in the signal generation circuit 10N shown in Figure 20. Therefore, in this modified example, the signals S1 and S2 obtained in response to the input current Ii are approximately the same as the signals S1 and S2 of the signal generation circuit 10N shown in Figure 20, respectively.

[0262] (Modification 4 of the 8th embodiment) Figure 33 shows a modified example of the signal generation circuit according to the eighth embodiment. The signal generation circuit 10Y shown in Figure 33 is obtained by replacing the voltage control unit 30Q in the signal generation circuit 10Q shown in Figure 22 with a voltage control unit 30Y.

[0263] The voltage control unit 30Y has the same configuration as the signal generation circuit 10P shown in Figure 21, but with the current detection units 21 and 22 omitted. That is, the voltage control unit 30Y is the same as the signal generation circuit 10P shown in Figure 21, but with the current detection units 21 and 22 omitted and diodes D1 and D2 renamed to diodes D11 and D12, respectively. Therefore, the diode currents Id11 and Id12 flowing through diodes D11 and D12 in the voltage control unit 30Y in response to the input current Ii are the same as the diode currents Id1 and Id2 flowing through diodes D1 and D2 in response to the input current Ii in the signal generation circuit 10P shown in Figure 21. Therefore, in this modified example, the signals S1 and S2 obtained in response to the input current Ii are approximately the same as the signals S1 and S2 of the signal generation circuit 10P shown in Figure 21, respectively.

[0264] <Ninth Embodiment> Next, a ninth embodiment of the present invention will be described. While the signal generation circuits in each of the embodiments described so far generate signals S1 and S2 in response to an input current Ii, the signal generation circuit in this embodiment generates signals S1 and S2 in response to an input voltage Vi. In the following description, a signal generation circuit that generates signals S1 and S2 in response to an input voltage Vi may be referred to as a "voltage input type," and a signal generation circuit that generates signals S1 and S2 in response to an input current Ii may be referred to as a "current input type."

[0265] In the case of an ideal current input, the input impedance of the signal generation circuit becomes zero, so it can also be used as a voltage input by placing a resistor between the voltage signal source and the current input. For example, a 10kΩ resistor can be used to convert a ±10V voltage signal into a ±1mA current signal. In circuits where the operational amplifier U33 brings the input potential closer to the reference potential and lowers the impedance (circuits in Figures 6, 8, 9, 17-21, 28, 30-33), the input impedance is sufficiently small and can be considered an ideal current input, so it can be used as a voltage input by placing a resistor between the voltage signal source and the current input. Furthermore, even with a current input that has a higher input impedance, it may be possible to use it as a voltage input by reducing the resistance value between the voltage signal source and the current input. The voltage input described below does not convert the signal from the voltage signal source into a current signal using a resistor, but rather applies a voltage signal to one end of the diode in the voltage control unit.

[0266] Figure 34 shows an example of a Class AB push-pull amplifier circuit equipped with a signal generation circuit according to the ninth embodiment. The Class AB push-pull amplifier circuit 1A shown in Figure 34 replaces the signal generation circuit 10 in the Class AB push-pull amplifier circuit 1 shown in Figure 1 with the signal generation circuit 10Z according to this embodiment, and replaces the input amplifier section 2 with the input amplifier section 2A. The input amplifier section 2A replaces the current output type voltage-to-current conversion section 5 in the input amplifier section 2 with a voltage output type amplifier section 5A.

[0267] Figure 35 shows an example of a signal generation circuit according to this embodiment. The signal generation circuit 10Z shown in Figure 35 has a first signal output unit 41 that outputs signal S1 and a second signal output unit 42 that outputs signal S2. The first signal output unit 41 and the second signal output unit 42 generate signals S1 and S2 according to the voltage Vi input to the voltage input node Nv.

[0268] [First signal output section 41] The first signal output unit 41 includes a diode D1 provided in the forward direction in the current path from node N1 to which voltage V1 is applied, to a reference voltage node held at a reference voltage, a resistor Rp1 provided in series with diode D1 in the current path from node N1 to the reference voltage node, a first voltage control unit 410 for controlling voltage V1, and a first current detection unit 411 for outputting a signal S1 that detects the diode current Id1 flowing through diode D1. In this example, the resistor Rp1 is provided in the current path between the anode of diode D1 and node N1. Diode D1 is an example of the first diode of the present invention. Resistor Rp1 is an example of the positive first resistor of the present invention. The first voltage control unit 410 is an example of the first voltage control unit of the present invention. The first current detection unit 411 is an example of the first current detection unit of the present invention.

[0269] The first current detection unit 411 has a configuration similar to that of the current detection unit 23 described earlier (see Figures 23B and 23C).

[0270] The first voltage control unit 410 controls the voltage V1 so that a predetermined idle current flows through diode D1 as diode current Id1 when the input voltage Vi is zero. When the input voltage Vi increases in the positive direction, the first voltage control unit 410 controls the voltage V1 so that the diode current Id1 increases proportionally to the input voltage Vi. On the other hand, when the input voltage Vi increases in the negative direction, the first voltage control unit 410 controls the voltage V1 so that the diode current Id1 decreases and approaches zero.

[0271] In the example shown in Figure 35, the first voltage control unit 410 includes a diode D13 provided in the forward direction in the current path from node N1 to voltage input node Nv, and a first constant current supply unit 412 that supplies a constant current to flow into diode D13. The first constant current supply unit 412 includes a constant current circuit CS1 that supplies a constant current Ic1 to node N1, for example, as shown in Figure 35.

[0272] A portion of the constant current Ic1 supplied by the first constant current supply unit 412 flows through diode D1 as diode current Id1. Even when the input voltage Vi is zero, diode current Id1 flows as idle current. The magnitude of the idle current is determined by the constant current Ic1 supplied by the first constant current supply unit 412, the value of resistor Rp1, and the current-voltage characteristics of diodes D1 and D13.

[0273] As the input voltage Vi increases in the positive direction (rises above zero), the forward voltage of diode D13 decreases, and the diode current Id13 of diode D13 decreases. At the same time, the diode current Id1, which is the difference between the constant current Ic1 and the diode current Id13, increases, the voltage drop across resistor Rp1 increases, and the voltage V1 rises. Assuming that the resistance Rp1 is sufficiently large compared to the DC resistance of diodes D1 and D13, the increase in voltage V1 due to the increase in input voltage Vi is approximately equal to the increase in the voltage drop across resistor Rp1. Therefore, as the input voltage Vi rises above zero, the diode current Id1 increases proportionally to the input voltage Vi.

[0274] As the input voltage Vi increases in the negative direction (falls below zero), the forward voltage of diode D13 increases, and the diode current Id13 of diode D13 increases, while the diode current Id1, which is the difference between the constant current Ic1 and the diode current Id13, decreases. When the diode current Id13 becomes approximately equal to the constant current Ic1, the diode current Id1 becomes approximately zero, and even if the input voltage Vi decreases further, the diode current Id1 remains approximately zero.

[0275] [Second signal output section 42] The second signal output unit 42 includes a diode D2 provided in the forward direction in the current path from the reference voltage node to node N2 to which voltage V2 is applied, a resistor Rn1 provided in series with diode D2 in the current path from the reference voltage node to node N2, a second voltage control unit 420 for controlling voltage V2, and a second current detection unit 421 for detecting the diode current Id2 flowing through diode D2 and outputting a signal S2. In this example, resistor Rn1 is provided in the current path between the cathode of diode D2 and node N2. Diode D2 is an example of the second diode of the present invention. Resistor Rn1 is an example of the negative first resistor of the present invention. The second voltage control unit 420 is an example of the second voltage control unit of the present invention. The second current detection unit 421 is an example of the second current detection unit of the present invention.

[0276] The second current detection unit 421 has a configuration similar to that of the current detection unit 24 described earlier (see Figures 23E and 23F).

[0277] The second voltage control unit 420 controls the voltage V2 so that a predetermined idle current flows through diode D2 as the diode current Id2 when the input voltage Vi is zero. It is preferable that the idle currents flowing through diode D1 and diode D2 are approximately the same. When the input voltage Vi increases in the positive direction, the second voltage control unit 420 controls the voltage V2 so that the diode current Id2 decreases and approaches zero. On the other hand, when the input voltage Vi increases in the negative direction, the second voltage control unit 420 controls the voltage V2 so that the diode current Id2 increases in proportion to the input voltage Vi.

[0278] In the example shown in Figure 35, the second voltage control unit 420 includes a diode D14 provided in the forward direction in the current path from the voltage input node Nv to node N2, and a second constant current supply unit 422 that supplies a constant current flowing out from the diode D14. The second constant current supply unit 422 includes a constant current circuit CS2 that supplies a constant current Ic2 to node N2, for example, as shown in Figure 35.

[0279] A portion of the constant current Ic2 supplied by the second constant current supply unit 422 flows through diode D2 as diode current Id2. Even when the input voltage Vi is zero, diode current Id2 flows as idle current. The magnitude of the idle current is determined by the constant current Ic2 supplied by the second constant current supply unit 422, the value of resistor Rn1, and the current-voltage characteristics of diodes D2 and D14. It is preferable that resistors Rp1 and Rn1, and constant currents Ic1 and Ic2 be set to equal values ​​so that the idle currents of diode D1 and diode D2 are approximately equal. Furthermore, it is preferable to use diodes with matching characteristics for diodes D1 and D2, and diodes D13 and D14.

[0280] As the input voltage Vi increases in the negative direction (falls below zero), the forward voltage of diode D14 decreases, and the diode current Id14 of diode D14 decreases. At the same time, the diode current Id2, which is the difference between the constant current Ic2 and the diode current Id14, increases, the voltage drop across resistor Rn1 increases, and the voltage V2 decreases. Assuming that resistor Rn1 is sufficiently large compared to the DC resistance of diodes D2 and D14, the decrease in voltage V1 due to the decrease in input voltage Vi is approximately equal to the increase in the voltage drop across resistor Rn1. Therefore, as the input voltage Vi falls below zero, the diode current Id2 increases in proportion to the input voltage Vi.

[0281] As the input voltage Vi increases in the positive direction (rises above zero), the forward voltage of diode D14 increases, and the diode current Id14 of diode D14 increases, while the diode current Id2, which is the difference between the constant current Ic2 and the diode current Id14, decreases. When the diode current Id14 becomes approximately equal to the constant current Ic2, the diode current Id2 becomes approximately zero, and even if the input voltage Vi decreases further, the diode current Id2 remains approximately zero.

[0282] In the signal generation circuit 10Z having the above configuration, when the input voltage Vi is zero, predetermined idle currents flow as diode current Id1 and diode current Id2, respectively. Therefore, in the Class AB push-pull amplifier circuit 1A shown in Figure 34, the first output unit 6 and the second output unit 7 are controlled based on the signals (S1, S2) that detect the diode currents (Id1, Id2), so that when the input voltage Vi is zero, predetermined idle currents flow as current Ip flowing out of the first output unit 6 and current In flowing into the second output unit 7, respectively.

[0283] When the input voltage Vi increases in the positive direction, the diode current Id1 increases proportionally to the input voltage Vi, while the diode current Id2 approaches zero. Conversely, when the input voltage Vi increases in the negative direction, the diode current Id2 increases proportionally to the input voltage Vi, while the diode current Id1 approaches zero. Therefore, the first output unit 6 and the second output unit 7 are controlled based on the signals (S1, S2) that detect the diode currents (Id1, Id2). As a result, when the input voltage Vi increases in the positive or negative direction, one of the currents Ip and In increases while the other decreases. The difference between the increasing current Ip and the decreasing current In becomes the current Ix flowing to the current output node Nx in one direction (inflow or outflow) corresponding to the direction (positive or negative) of the increasing input voltage Vi. Consequently, the first output unit 6 and the second output unit 7 perform a class AB push-pull operation according to the input voltage Vi applied to the voltage input node Nv.

[0284] Thus, according to this embodiment, by controlling the diode current Id1 flowing through diode D1 and the diode current Id2 flowing through diode D2 according to the input voltage Vi, signals S1 and S2 that cause the output stage of the amplification circuit (first output section 6, second output section 7) to perform a Class AB push-pull operation can be generated without using a pair of transistors with different polarities (complementary transistors, etc.).

[0285] Furthermore, in this embodiment, by connecting one end of diodes D1 and D2 to a reference potential node, the circuit configuration in the first current detection unit 411 and the second current detection unit 421 can be simplified.

[0286] [Simulation results of the signal generation circuit 10Z shown in Figure 35: Figures 36A to 36F] Figures 36A to 36F show the results of simulations performed on the signal generation circuit 10Z shown in Figure 35.

[0287] Furthermore, the simulation results for voltage-input type signal generation circuits (Figures 35, 37, 41, 55, 63, 65, etc.) differ from those for current-input type circuits in the following respects. Graphs A, C, and E show the simulation results when the output impedance of the voltage source supplying the input voltage Vi is set to zero. Graphs B, D, and F show the simulation results when the output impedance of the voltage source supplying the input voltage Vi is set to 50Ω. The horizontal axis of graphs A through E represents the input voltage Vi. The horizontal axis of graph F represents the voltage (Vs) of the voltage source supplying the input voltage Vi. Graphs A and B are superimposed simulation results for "Id1", "-Id2", and "Id1-Id2".

[0288] The simulation results in Figures 36A to 36F show that the temperature dependence of the diode currents Id1 and Id2 is relatively small, and the temperature dependence of the input resistance is also relatively small. Furthermore, these simulation results show almost no effect from the difference in output impedance of the voltage source (zero / 50Ω). On the other hand, a change in the linearity of "Id1-Id2" occurs near zero of the input voltage Vi, and the errors due to this change in linearity are shown in graphs C, D, and F.

[0289] (Modification 1 of the 9th embodiment) Figure 37 shows a modified example of the signal generation circuit according to the ninth embodiment. The signal generation circuit 10ZA shown in Figure 37 is obtained by replacing the first signal output section 41 and the second signal output section 42 in the signal generation circuit 10Z shown in Figure 35 with the first signal output section 41A and the second signal output section 42A, respectively.

[0290] [First signal output section 41A] The first signal output unit 41A has a configuration almost identical to that of the first signal output unit 41, but the position of the resistor Rp1 relative to the diode D1 is changed compared to the first signal output unit 41. That is, in the first signal output unit 41A, the resistor Rp1 is provided in the current path between the cathode of the diode D1 and the reference voltage node.

[0291] Furthermore, in the first signal output unit 41A, the first current detection unit 411 outputs the voltage generated across resistor Rp1 as signal S1. In other words, resistor Rp1 also functions as the first current detection unit 411. Note that the first current detection unit 411 may also include a voltage amplification circuit that amplifies the voltage across resistor Rp1, similar to the voltage amplification circuit SA23 in the current detection unit 23 shown in Figure 23C.

[0292] [Second signal output section 42A] The second signal output section 42A has a configuration almost identical to that of the second signal output section 42, but the position of the resistor Rn1 relative to the diode D2 is changed compared to the second signal output section 42. That is, in the second signal output section 42A, the resistor Rn1 is provided in the current path between the anode of the diode D2 and the reference voltage node.

[0293] Furthermore, in the second signal output unit 42A, the second current detection unit 421 outputs the voltage generated across resistor Rn1 as signal S2. In other words, resistor Rn1 also functions as the second current detection unit 421. Note that the second current detection unit 421 may also include a voltage amplification circuit that amplifies the voltage across resistor Rn1, similar to the voltage amplification circuit SA24 in the current detection unit 24 shown in Figure 23F.

[0294] In the signal generation circuit 10ZA shown in Figure 37, signals S1 and S2 can be generated by the voltages generated across resistors Rp1 and Rn1, thus simplifying the circuit configuration of the first current detection unit 411 and the second current detection unit 421.

[0295] [Simulation results of the signal generation circuit 10ZA shown in Figure 37: Figures 38A to 38F] Figures 38A to 38F show the results of simulations performed on the signal generation circuit 10Z shown in Figure 37.

[0296] The simulation results in Figures 38A to 38F show that, similar to the signal generation circuit 10Z shown in Figure 35, the temperature changes of the diode currents Id1 and Id2 are relatively small, and the temperature changes of the input resistance are also relatively small. Furthermore, these simulation results show almost no effect from the difference in output impedance of the voltage source (zero / 50Ω). On the other hand, a change in the linearity of "Vo1 + Vo2" occurs near zero of the input voltage Vi, and the errors due to this change in linearity are shown in graphs C, D, and F.

[0297] (Modification 2 of the 9th embodiment) Figure 39 shows a modified example of the signal generation circuit according to the ninth embodiment. The signal generation circuit 10ZB shown in Figure 39 is obtained by replacing the first signal output unit 41 and the second signal output unit 42 in the signal generation circuit 10Z shown in Figure 35 with the first signal output unit 41B and the second signal output unit 42B, respectively.

[0298] [First signal output section 41B] The first signal output unit 41B is a modified version of the first signal output unit 41, in which the first voltage control unit 410 is replaced with the first voltage control unit 410B, and a buffer circuit BF3 is added. The first voltage control unit 410B includes a diode D13 and a first constant current supply unit 412B. The diode D13 is provided in the forward direction in the current path flowing from node N13 to voltage input node Nv. The first constant current supply unit 412B is a circuit that supplies a constant current flowing into node N13, and in the example of Figure 39, it has a resistor Rc5 provided in the current path between the positive voltage VL+ and node N13. The buffer circuit BF3 receives the voltage generated at node N13 as input and outputs a voltage V1 corresponding to the input voltage to node N1.

[0299] [Second signal output section 42B] The second signal output unit 42B is a modified version of the second signal output unit 42, in which the second voltage control unit 420 is replaced by the second voltage control unit 420B, and a buffer circuit BF4 is added. The second voltage control unit 420B includes a diode D14 and a second constant current supply unit 422B. Diode D14 is provided in the forward direction in the current path from the voltage input node Nv to node N14. The second constant current supply unit 422B is a circuit that supplies a constant current flowing out from node N14, and in the example of Figure 39, it has a resistor Rc6 provided in the current path between the negative voltage VL- and node N14. The buffer circuit BF4 receives the voltage generated at node N14 as input and outputs a voltage V2 corresponding to the input voltage to node N2.

[0300] When the input voltage Vi is zero, voltage V1 becomes the voltage corresponding to the forward voltage of diode D13, and voltage V2 becomes the voltage corresponding to the forward voltage of diode D14. Diode currents Id1 and Id2 corresponding to these voltages V1 and V2 flow as idle currents, respectively. These idle currents can be adjusted according to the currents Ir5 and Ir6 supplied by the first constant current supply unit 412B and the second current detection unit 421B when the input voltage Vi is zero, and specifically, they can be adjusted according to the resistance values ​​of resistors Rc5 and Rc6. When the input voltage Vi increases in the positive direction, the voltages at nodes N13 and N14 rise, and voltages V1 and V2 rise accordingly. As a result, the diode current Id1 increases in accordance with the input voltage Vi, while the diode current Id2 decreases and approaches zero. On the other hand, when the input voltage Vi increases in the negative direction, the voltages at nodes N13 and N14 decrease, and voltages V1 and V2 decrease accordingly. As a result, the diode current Id2 increases in accordance with the input voltage Vi, while the diode current Id1 decreases and approaches zero.

[0301] In this modified example 2, when the input voltage Vi is zero, diode currents Id1 and Id2 flow as idle currents. When the input voltage Vi increases in the positive direction, the current "Id1-Id2" (Id1 minus Id2) increases in the positive direction, and when the input voltage Vi increases in the negative direction, "Id1-Id2" increases in the negative direction. Therefore, the signals S1 and S2, which detect the diode currents Id1 and Id2, can be used as signals for push-pull operation.

[0302] [Simulation results of the signal generation circuit 10ZA shown in Figure 39: Figures 40A to 40F] Figures 40A to 40F show the results of simulations performed on the signal generation circuit 10ZB shown in Figure 39.

[0303] The simulation results in Figures 40A to 40F show that, similar to the signal generation circuit 10Z shown in Figure 35, the temperature changes of the diode currents Id1 and Id2 are relatively small, and the temperature changes of the input resistance are also relatively small.

[0304] The input resistance in Graph E is higher than that of the signal generation circuits in Figures 35 and 37, due to the inclusion of buffer circuits BF3 and BF4. Because of the high input resistance, the effect of the difference in output impedance of the voltage source (zero / 50Ω) is almost negligible. Furthermore, the input resistance in the signal generation circuit 10ZB in Figure 39 and the signal generation circuit 10ZC in Figure 41 (described later) is close to the resistance of the parallel connection of resistors Rc5 and Rc6, assuming that forward current always flows through diodes D13 and D14. By replacing resistors Rc5 and Rc6 with constant current circuits, it is possible to further increase the input resistance. Note that if resistors Rc5 and Rc6 are ideal constant current circuits, and the input resistances of buffer circuits BF3 and BF4 are infinite, the input resistance will be infinite.

[0305] Furthermore, as shown in Figures 40A and 40B, in the signal generation circuit 10ZB shown in Figure 39, a change in the linearity of "Id1-Id2" occurs near zero of the input voltage Vi, and the resulting error is shown in graphs C, D, and F.

[0306] (Modification 3 of the 9th embodiment) Figure 41 shows a modified example of the signal generation circuit according to the ninth embodiment. The signal generation circuit 10ZC shown in Figure 41 is obtained by replacing the first signal output section 41B and the second signal output section 42B in the signal generation circuit 10ZB shown in Figure 39 with the first signal output section 41C and the second signal output section 42C, respectively.

[0307] [First signal output section 41C] The first signal output section 41C is modified so that the positional relationship between diode D1 and resistor Rp1 in the first signal output section 41B is the same as that of the first signal output section 41A of Modified Example 1 (Figure 37), and the other configurations are the same as those of the first signal output section 41B. That is, in the first signal output section 41C, resistor Rp1 is provided in the current path between the cathode of diode D1 and the reference voltage node.

[0308] [Second signal output section 42C] The second signal output section 42C is modified so that the positional relationship between diode D2 and resistor Rn1 in the second signal output section 42B is the same as that of the second signal output section 42A of Modified Example 1 (Figure 37), and the other configurations are the same as those of the second signal output section 42B. That is, in the second signal output section 42C, resistor Rn1 is provided in the current path between the anode of diode D2 and the reference voltage node.

[0309] In the signal generation circuit 10ZC shown in Figure 41, signals S1 and S2 can be generated by the voltages generated across resistors Rp1 and Rn1, similar to the first signal output unit 41A (Figure 37), thus simplifying the circuit configuration of the first current detection unit 411 and the first constant current supply unit 412.

[0310] [Simulation results of the signal generation circuit 10ZC shown in Figure 41: Figures 42A to 42F] Figures 42A to 42F show the results of simulations performed on the signal generation circuit 10ZC shown in Figure 41.

[0311] The simulation results in Figures 42A to 42F show that, similar to the signal generation circuit 10Z shown in Figure 35, the temperature dependence of the diode currents Id1 and Id2 and the input resistance is relatively small. The input resistance in graph E is higher than that of the signal generation circuits in Figures 35 and 37, similar to the signal generation circuit 10ZB (Figure 39), and there is almost no effect from the difference in output impedance of the voltage source (zero / 50Ω). In the signal generation circuit 10ZC shown in Figure 41, a change in the linearity of "Vo1 + Vo2" occurs near zero of the input voltage Vi, and the resulting error is shown in graphs C, D, and F.

[0312] In this embodiment, the constant current supply units (412, 412B, 422, 422B) may each be composed of a constant current circuit, or they may be composed of resistors with resistance values ​​high enough to be considered constant current sources compared to the impedance of the circuit to which the constant current is supplied.

[0313] <Tenth Embodiment> Next, a tenth embodiment of the present invention will be described. In the current-input type signal generation circuits of the embodiments described so far, two signals S1 and S2 are generated by a single input current Ii. However, in the signal generation circuit of this embodiment, two signals S1 and S2 are generated based on independent input currents. A current-input type signal generation circuit in which the circuit that generates signal S1 and the circuit that generates signal S2 are independent is sometimes called a "single-output type".

[0314] Figure 43 shows an example of a Class AB push-pull amplifier circuit equipped with a signal generation circuit according to the tenth embodiment. The Class AB push-pull amplifier circuit 1B shown in Figure 43 is obtained by replacing the signal generation circuit 10 in the Class AB push-pull amplifier circuit 1 shown in Figure 3 with the signal generation circuit 10ZD according to this embodiment, and replacing the input amplifier section 2 with the input amplifier section 2B.

[0315] The input amplifier section 2B is an improved version of the input amplifier section 2, with the single voltage-to-current conversion section 5 being replaced by two voltage-to-current conversion sections 5a and 5b. The voltage-to-current conversion sections 5a and 5b convert the voltage Vi of the differential amplifier 4 into currents Ii1 and Ii2, respectively. Currents Ii1 and Ii2 are approximately equal in magnitude and flow direction (inflow and outflow direction) are also approximately the same.

[0316] Figure 44 shows an example of a signal generation circuit according to the tenth embodiment. The signal generation circuit 10ZD shown in Figure 44 has a first signal output unit 51 and a second signal output unit 52. The first signal output unit 51 generates a signal S1 corresponding to the current Ii1 input to the current input node Ni1. The second signal output unit 52 generates a signal S1 corresponding to the current Ii2 input to the current input node Ni2.

[0317] [First signal output section 51] The first signal output unit 51 includes a diode D1 provided in the forward direction in the current path from node N1 to the reference voltage node to which voltage V1 is applied, a positive diode Dp provided in the forward direction in the current path from node N1 to the anode of diode D1, a current input node Ni1 provided in the current path from the cathode of positive diode Dp to the anode of diode D1, through which input current Ii1 flows in or out, a first current detection unit 511 that outputs a signal S1 detecting the diode current Id1 flowing through diode D1, and a first voltage supply unit 510 that supplies a voltage V1 to node N1 set so that a predetermined idle current flows as the diode current Id1 when the input current Ii1 is zero. In the example in Figure 44, the first signal output unit 51 includes a resistor Rp2 provided in the current path from node N1 to the reference voltage node. Diode D1 is an example of the first diode of the present invention. The positive diode Dp is an example of the positive diode of the present invention. The first current detection unit 511 is an example of the first current detection unit of the present invention. The first voltage supply unit 510 is an example of the first voltage supply unit of the present invention. Resistor Rp2 is an example of the positive-side second resistor of the present invention.

[0318] The first current detection unit 511 has a configuration similar to that of the current detection unit 23 described earlier (see Figures 23B and 23C).

[0319] In the example shown in Figure 44, the first voltage supply unit 510 includes a first diode circuit 513 and a first constant current supply unit 512. The first diode circuit 513 includes diodes D15 and D16 connected in series in the forward direction. Current flows from the cathode of diode D16 at one end to the reference voltage node, generating a voltage V1 at the anode of diode D15 at the other end.

[0320] The first diode circuit 513 supplies a constant current to the anode of diode D15 at the other end of the first diode circuit 513 so that when the input current Ii1 is zero, a current corresponding to the idle current flows through each diode (D15, D16) of the first diode circuit 513. The first diode circuit 513 includes a constant current circuit CS1 that supplies a constant current Ic1 to the anode of diode D15, as shown in Figure 44, for example. The magnitude of the idle current is determined by the constant current Ic1 supplied by the first constant current supply unit 512, the value of the resistor Rp2, and the current-voltage characteristics of each diode (D1, Dp, D15, D16).

[0321] When the input current Ii1 increases in the direction of inflow, the diode current Id1 increases as the input current Ii1 flows into diode D1. On the other hand, when the input current Ii1 increases in the direction of outflow, a portion of the current Idp flowing through the positive diode Dp flows out to the current input node Ni1, causing the diode current Id1 to decrease and approach zero. When the input current Ii1 becomes approximately equal to the current Idp, the diode current Id1 becomes approximately zero, and even if the input current Ii1 increases further in the direction of outflow, the diode current Id1 remains zero.

[0322] [Second signal output section 52] The second signal output unit 52 includes a diode D2 provided in the forward direction in the current path from the reference voltage node to node N2 to which voltage V2 is applied, a negative diode Dn provided in the forward direction in the current path from the cathode of diode D2 to node N2, a current input node Ni2 provided in the current path from the cathode of diode D2 to the anode of the negative diode Dn, to which input current Ii2 flows in or out, a second current detection unit 521 that outputs a signal S2 detecting the diode current Id2 flowing through diode D2, and a second constant current supply unit 522 that supplies a voltage V2 to node N2 set so that a predetermined idle current (preferably the same idle current as diode D1) flows as the diode current Id2 when the input current Ii2 is zero. In the example in Figure 44, the second signal output unit 52 includes a resistor Rn2 provided in the current path from the reference voltage node to node N2. Diode D2 is an example of the second diode of the present invention. The negative diode Dn is an example of the negative diode of the present invention. The second current detection unit 521 is an example of the second current detection unit of the present invention. The second voltage supply unit 520 is an example of the second voltage supply unit of the present invention. Resistor Rn2 is an example of the negative second resistor of the present invention.

[0323] The second current detection unit 521 has a configuration similar to that of the current detection unit 23 described earlier (see Figures 23E and 23F).

[0324] In the example shown in Figure 44, the second voltage supply unit 520 includes a second diode circuit 523 and a second constant current supply unit 522. The second diode circuit 523 includes diodes D17 and D18 connected in series in the forward direction. Current flows from the reference voltage node to the anode of diode D18 at one end, generating a voltage V2 at the cathode of diode D17 at the other end.

[0325] The second diode circuit 523 supplies a constant current flowing out from the cathode of diode D17 at the other end of the second diode circuit 523 so that when the input current Ii2 is zero, a current corresponding to the idle current flows through each diode (D17, D18) of the second diode circuit 523. The second diode circuit 523 includes a constant current circuit CS2 that supplies a constant current Ic2 to the cathode of diode D17, as shown in Figure 44, for example. The magnitude of the idle current is determined by the constant current Ic2 supplied by the second constant current supply unit 522, the value of the resistor Rn2, and the current-voltage characteristics of each diode (D2, Dn, D17, D18). It is preferable that resistors Rp2 and Rn2, and constant currents Ic1 and Ic2 are set to equal values ​​so that the idle currents of diode D1 and diode D2 are approximately equal. Furthermore, it is preferable to use diodes with matching characteristics for diodes D1 and D2, positive diode Dp and negative diode Dn, and the first diode circuit 513 and the second diode circuit 523.

[0326] When the input current Ii2 increases in the outflow direction, the diode current Id2 increases as the input current Ii2 flows out of diode D1. On the other hand, when the input current Ii2 increases in the inflow direction, a portion of the input current Ii2 flows into the negative diode Dn, causing the diode current Id2 to decrease and approach zero. When the input current Ii2 becomes approximately equal to the current Idn, the diode current Id2 becomes approximately zero, and even if the input current Ii2 increases further in the inflow direction, the diode current Id2 remains zero.

[0327] In the signal generation circuit 10ZD having the above configuration, when the input currents Ii1 and Ii2 are zero, predetermined idle currents flow as diode current Id1 and diode current Id2, respectively. Therefore, in the Class AB push-pull amplifier circuit 1B shown in Figure 43, the first output unit 6 and the second output unit 7 are controlled based on the signals (S1 and S2) that detect the diode currents (Id1 and Id2). As a result, when the input voltage Vi is zero, predetermined idle currents flow as current Ip flowing out of the first output unit 6 and current In flowing into the second output unit 7, respectively. When input currents Ii1 and Ii2 increase in the inflow direction, diode current Id1 increases in accordance with input current Ii1, and diode current Id2 approaches zero. Conversely, when input currents Ii1 and Ii2 increase in the outflow direction, diode current Id2 increases in accordance with input current Ii2, and diode current Id1 approaches zero. Therefore, when the first output unit 6 and the second output unit 7 are controlled based on signals (S1, S2) that detect the diode currents (Id1, Id2), when input currents Ii1 and Ii2 increase in the inflow direction or outflow direction, one of currents Ip and In increases while the other decreases, and the difference between the increasing current Ip and the decreasing current In becomes the current Ix that flows to the current output node Nx in one direction (inflow direction or outflow direction) corresponding to the direction (inflow direction or outflow direction) of the increasing input currents Ii1 and Ii2. Therefore, depending on the input voltage Vi supplied to the voltage input node Nv, the first output unit 6 and the second output unit 7 perform a Class AB push-pull operation.

[0328] Thus, according to this embodiment, by controlling the diode current Id1 flowing through diode D1 according to the input current Ii1, and controlling the diode current Id2 flowing through diode D2 according to the input current Ii2, signals S1 and S2 that cause the output stage of the amplification circuit (first output section 6, second output section 7) to perform a Class AB push-pull operation can be generated without using a pair of transistors with different polarities (complementary transistors, etc.).

[0329] Furthermore, in this embodiment, by connecting one end of diodes D1 and D2 to a reference potential node, the circuit configuration in the first current detection unit 511 and the second current detection unit 521 can be simplified.

[0330] [Simulation results of the signal generation circuit 10ZD shown in Figure 44: Figures 45A to 45F] Figures 45A to 45F show the results of simulations performed on the signal generation circuit 10ZD shown in Figure 44.

[0331] Furthermore, the simulation results for single-output signal generation circuits (Figures 44, 46, 47, 49, 51, 53, 61, etc.) differ from the simulation results for other current-input types in the following respects. Graphs A and B are superimposed simulation results for "Id1", "-Id2", and "Id1-Id2".

[0332] The simulation results in Figures 45A to 45F show that the temperature changes of the diode currents Id1 and Id2, and the input resistance, are relatively large compared to the voltage-input type signal generation circuit 10Z described earlier. In addition, a change in the linearity of "Id1-Id2" occurs near zero for the input currents Ii1 and Ii2, and the errors due to this change in linearity are shown in graphs C, D, and F.

[0333] (Modification 1 of the 10th embodiment) Figure 46 shows a modified example of the signal generation circuit according to the tenth embodiment. The signal generation circuit 10ZE shown in Figure 46 is obtained by replacing the first signal output section 51 and the second signal output section 52 in the signal generation circuit 10ZD shown in Figure 44 with the first signal output section 51A and the second signal output section 52A, respectively.

[0334] [First signal output section 51A] The first signal output unit 51A is modified by omitting the resistor Rp2 in the first signal output unit 51 (Figure 44) and replacing the first voltage supply unit 510 with the first voltage supply unit 510A. The first voltage supply unit 510A includes the same first diode circuit 513 as the first voltage supply unit 510 and a first constant current supply unit 512A that supplies a constant current to the first diode circuit 513. The first constant current supply unit 512A includes a resistor Rc7 provided in the current path between the positive voltage VL+ and node N1.

[0335] [Second signal output section 52A] The second signal output unit 52A is modified by omitting the resistor Rn2 in the second signal output unit 52 (Figure 44) and replacing the second voltage supply unit 520 with the second voltage supply unit 520A. The second voltage supply unit 520A includes the same second diode circuit 523 as the second voltage supply unit 520 and a second constant current supply unit 522A that supplies a constant current to the second diode circuit 523. The second constant current supply unit 522A includes a resistor Rc8 provided in the current path between the negative voltage VL- and node N2.

[0336] The resistor Rp2 and constant current circuit CS1 in the first signal output section 51 can be considered as a parallel connection of a resistor and a current source, which is equivalent to a series connection of a resistor and a voltage source. Therefore, the resistor Rc7 connected between the positive voltage VL+ and node N1 in the first signal output section 51A can be considered equivalent to the resistor Rp2 and constant current circuit CS1 in the first signal output section 51. Similarly, the resistor Rc8 in the first signal output section 51A can be considered equivalent to the resistor Rn2 and constant current circuit CS2 in the first signal output section 51. Consequently, the signal generation circuit 10ZE shown in Figure 46 operates similarly to the signal generation circuit 10ZD shown in Figure 44, and the simulation results are similar.

[0337] According to this modified example, the constant current circuits (CS1, CS2) in the first signal output section 51 can be replaced with resistors (Rc7, Rc8), and resistors Rp2 and Rn2 can be omitted, thus simplifying the circuit configuration.

[0338] (Modification 2 of the 10th embodiment) Figure 47 shows a modified example of the signal generation circuit according to the tenth embodiment. The signal generation circuit 10ZF shown in Figure 47 is obtained by replacing the first signal output unit 51 and the second signal output unit 52 in the signal generation circuit 10ZD shown in Figure 44 with the first signal output unit 51B and the second signal output unit 52B, respectively.

[0339] [First signal output section 51B] The first signal output unit 51B is modified by replacing the positive diode Dp in the first signal output unit 51 with a resistor Rp1, and replacing the first voltage supply unit 510 with the first voltage supply unit 510B. The resistor Rp1 is provided in the path of the current flowing from node N1 to the anode of diode D1. The first voltage supply unit 510B has the same first constant current supply unit 512 as the first voltage supply unit 510, and a first diode circuit 513B to which the constant current from the first constant current supply unit 512 is supplied. The first diode circuit 513B is modified by omitting one of the diodes D16 in the first diode circuit 513. Resistor Rp1 is an example of the positive first resistor in the present invention.

[0340] [Second signal output section 52B] The second signal output unit 52B is modified by replacing the negative diode Dn in the second signal output unit 52 with a resistor Rn1, and replacing the second voltage supply unit 520 with a second voltage supply unit 520B. The resistor Rn1 is provided in the path of the current flowing from the cathode of diode D2 to node N2. The second voltage supply unit 520B has the same second constant current supply unit 522 as the second voltage supply unit 520, and a second diode circuit 523B to which the constant current from the second constant current supply unit 522 is supplied. The second diode circuit 523B is modified by omitting one of the diodes D18 in the second diode circuit 523. Resistor Rn1 is an example of the negative first resistor in the present invention.

[0341] When input currents Ii1 and Ii2 are zero, a diode current Id1 corresponding to a voltage V1 equivalent to the forward voltage of diode D15 flows through diode D1 as an idle current, and a diode current Id2 corresponding to a voltage V2 equivalent to the forward voltage of diode D17 flows through diode D2 as an idle current. The magnitude of the idle current of diode D1 is determined according to the constant current Ic1 of the first constant current supply unit 512, the value of the resistor Rp1, and the current-voltage characteristics of diodes D1 and D15. Similarly, the magnitude of the idle current of diode D2 is determined according to the constant current Ic2 of the second constant current supply unit 522, the value of the resistor Rn1, and the current-voltage characteristics of diodes D2 and D17. When input currents Ii1 and Ii2 increase in the inflow direction, diode current Id1 increases in accordance with input current Ii1, and diode current Id2 approaches zero. When input currents Ii1 and Ii2 increase in the outflow direction, diode current Id2 increases in accordance with input current Ii2, and diode current Id1 approaches zero. Therefore, in this modified example 1 as well, when the input currents Ii1 and Ii2 are zero, the diode currents Id1 and Id2 flow as idle currents, respectively. When the input currents Ii1 and Ii2 increase in the inflow direction, "Id1-Id2" increases in the positive direction, and when the input currents Ii1 and Ii2 increase in the outflow direction, "Id1-Id2" increases in the negative direction. Therefore, the signals S1 and S2 that detect the diode currents Id1 and Id2 can be used as signals for push-pull operation.

[0342] [Simulation results of the signal generation circuit 10ZF shown in Figure 47: Figures 48A to 48F] Figures 48A to 48F show the results of simulations performed on the signal generation circuit 10ZF shown in Figure 47.

[0343] The simulation results in Figures 48A to 48F show that the temperature dependence of diode currents Id1 and Id2 is smaller compared to the signal generation circuits in Figures 44 and 46. Furthermore, while the linearity of "Id1-Id2" changes near zero for input currents Ii1 and Ii2, the change is slightly smaller compared to the signal generation circuits in Figures 44 and 46 due to the smaller temperature dependence.

[0344] (Modification 3 of the 10th embodiment) Figure 49 shows a modified example of the signal generation circuit according to the tenth embodiment. The signal generation circuit 10ZG shown in Figure 49 is obtained by replacing the first signal output unit 51 and the second signal output unit 52 in the signal generation circuit 10ZD shown in Figure 44 with the first signal output unit 51C and the second signal output unit 52C, respectively.

[0345] [First signal output section 51C] The first signal output section 51C omits the resistor Rp2 in the first signal output section 51 and includes a buffer circuit BF5, while the other configurations are the same as the first signal output section 51. The buffer circuit BF5 receives the voltage generated in the first diode circuit 513 (the voltage at node N15 connected to the anode of diode D15) and outputs a voltage V1 corresponding to the input voltage to node N1. Buffer circuit BF5 is an example of a fifth buffer circuit in the present invention.

[0346] [Second signal output section 52C] The second signal output section 52C omits the resistor Rn2 in the second signal output section 52 and includes a buffer circuit BF6, while the other configurations are the same as the second signal output section 52. The buffer circuit BF6 receives the voltage generated in the second diode circuit 523 (the voltage at node N17 connected to the cathode of diode D17) and outputs a voltage V2 corresponding to the input voltage to node N2. Buffer circuit BF6 is an example of a sixth buffer circuit in the present invention.

[0347] In the signal generation circuit 10ZG, the buffer circuits BF5 and BF6 keep voltages V1 and V2 constant, but the basic operation is the same as that of the signal generation circuit 10ZD (Figure 44). That is, when the input currents Ii1 and Ii2 are zero, idle current flows through diodes D1 and D2, respectively. When the input currents Ii1 and Ii2 increase in the inflow direction, "Id1-Id2" increases in the positive direction, and when the input currents Ii1 and Ii2 increase in the outflow direction, "Id1-Id2" increases in the negative direction.

[0348] [Simulation results of the signal generation circuit 10ZG shown in Figure 49: Figures 50A to 50F] Figures 50A to 50F show the results of simulations performed on the signal generation circuit 10ZG shown in Figure 49.

[0349] The simulation results in Figures 50A to 50F show that the temperature dependence of diode currents Id1 and Id2, and the temperature dependence of input resistance are smaller compared to the signal generation circuits in Figures 44, 46, and 47. Furthermore, the change in linearity of "Id1-Id2" shown in Graphs C, D, and E is also smaller compared to the signal generation circuits in Figures 44, 46, and 47.

[0350] Since the error in graph C is smaller than the errors in graphs D and E, it can be seen that the linearity error can be reduced by increasing the output impedance of the voltage-to-current conversion units 5a and 5b that output the input currents Ii1 and Ii2.

[0351] (Modification 4 of the 10th embodiment) Figure 51 shows a modified example of the signal generation circuit according to the tenth embodiment. The signal generation circuit 10ZH shown in Figure 51 is obtained by replacing the first signal output section 51B and the second signal output section 52B in the signal generation circuit 10ZF shown in Figure 47 with the first signal output section 51D and the second signal output section 52D, respectively.

[0352] [First signal output section 51D] The first signal output unit 51D is the same as the first signal output unit 51B (Figure 47) but with a buffer circuit BF5 added. The other configurations are the same as the first signal output unit 51B. The buffer circuit BF5 receives the voltage generated in the first diode circuit 513B (the voltage at node N15 connected to the anode of diode D15) and outputs a voltage V1 corresponding to the input voltage to node N1. Buffer circuit BF5 is an example of a fifth buffer circuit in the present invention. Resistor Rp1 is an example of the positive first resistor in the present invention. [Second signal output section 52D] The second signal output unit 52D is the same as the second signal output unit 52B (Figure 47) but with a buffer circuit BF6 added. The other configurations are the same as the second signal output unit 52B. The buffer circuit BF6 receives the voltage generated in the second diode circuit 523B (the voltage at node N17 connected to the cathode of diode D17) and outputs a voltage V2 corresponding to the input voltage to node N2. Buffer circuit BF6 is an example of a sixth buffer circuit in the present invention. Resistor Rn1 is an example of the negative first resistor in the present invention.

[0353] In the signal generation circuit 10ZH, the buffer circuits BF5 and BF6 keep voltages V1 and V2 constant, but the basic operation is the same as the signal generation circuit 10ZF (Figure 47). That is, when the input currents Ii1 and Ii2 are zero, idle current flows through diodes D1 and D2, respectively. When the input currents Ii1 and Ii2 increase in the inflow direction, "Id1-Id2" increases in the positive direction, and when the input currents Ii1 and Ii2 increase in the outflow direction, "Id1-Id2" increases in the negative direction.

[0354] [Simulation results of the signal generation circuit 10ZG shown in Figure 51: Figures 52A to 52F] Figures 52A to 52F show the results of simulations performed on the signal generation circuit 10ZH shown in Figure 51.

[0355] The simulation results in Figures 52A to 52F show that the temperature dependence of diode currents Id1 and Id2, and the temperature dependence of input resistance are smaller compared to the signal generation circuits in Figures 44 and 46. In addition, a change in the linearity of "Id1-Id2" occurs near zero for input currents Ii1 and Ii2, and the errors due to this change in linearity are shown in graphs C, D, and F.

[0356] <Embodiment 11> Next, an eleventh embodiment of the present invention will be described. This embodiment relates to improving the nonlinearity in the current-input type and voltage-input type signal generation circuits described above.

[0357] In the signal generation circuit according to this embodiment, voltages V1 and V2 are supplied from nodes N1 and N2 to diodes D1 and D2 through which currents corresponding to signals S1 and S2 flow. Furthermore, the nonlinearity related to signals S1 and S2 is improved by connecting resistors to nodes N1 and N2. Improving nonlinearity by connecting resistors to nodes N1 and N2 is sometimes referred to as "adding resistors".

[0358] Figure 53 shows an example of a signal generation circuit according to the 11th embodiment. The signal generation circuit 10ZJ shown in Figure 53 is obtained by replacing the first signal output section 51B and the second signal output section 52B in the signal generation circuit 10ZF shown in Figure 47 with the first signal output section 51E and the second signal output section 52E, respectively.

[0359] [First signal output section 51E] The first signal output unit 51E is the same as the first signal output unit 51B (Figure 47) with the addition of a resistor Rp2, and the other configurations are the same as the first signal output unit 51B. The resistor Rp2 is provided in the path of the current flowing from node N1 to the reference voltage node. Resistor Rp2 is an example of the positive-side second resistor of the present invention.

[0360] [Second signal output section 52E] The second signal output section 52E is the same as the second signal output section 52B (Figure 47) with the addition of a resistor Rn2, and the other configurations are the same as the second signal output section 52B. The resistor Rn2 is provided in the path of the current flowing from the reference voltage node to node N2. Resistor Rn2 is an example of the negative second resistor of the present invention.

[0361] [Simulation results of the signal generation circuit 10ZJ shown in Figure 53: Figures 54A to 54F] Figures 54A to 54F show the results of a simulation performed on the signal generation circuit 10ZJ shown in Figure 53. In this simulation, the idle currents of diodes D1 and D2 are set to 5% of the full scale.

[0362] Graphs C, D, and F show that the error is smaller at certain temperatures, indicating an improvement in nonlinearity. The temperature dependence of diode currents Id1 and Id2, as well as the temperature dependence of the input resistance, is slightly larger compared to the signal generation circuit 10ZF before the addition of the resistor (Figure 47).

[0363] (Modification 1 of the 11th embodiment) Figure 55 shows an example of a signal generation circuit according to the 11th embodiment. The signal generation circuit 10ZK shown in Figure 55 is obtained by replacing the first signal output section 41 and the second signal output section 42 in the signal generation circuit 10Z shown in Figure 35 with the first signal output section 41D and the second signal output section 42D, respectively.

[0364] [First signal output section 41D] The first signal output section 41D is the same as the first signal output section 41 (Figure 35) with the addition of a resistor R5, and the other configurations are the same as the first signal output section 41. The resistor R5 is provided in the current path between node N1 and voltage input node Nv. Resistor R5 is an example of the fifth resistor of the present invention.

[0365] [Second signal output section 42D] The second signal output section 42D is the same as the second signal output section 42 (Figure 35) with the addition of a resistor R6, and the other configurations are the same as the second signal output section 42. The resistor R6 is provided in the current path between node N2 and voltage input node Nv. Resistor R6 is an example of the sixth resistor of the present invention.

[0366] Figure 56 shows another example of a signal generation circuit according to the eleventh embodiment. The signal generation circuit 10ZL shown in Figure 56 is the same as the signal generation circuit 10Z shown in Figure 35, with the addition of a resistor R7, and the other configurations are the same as the signal generation circuit 10Z. The resistor R7 is provided in the current path between node N1 of the first signal output section 41 and node N2 of the second signal output section 42. If the resistance values ​​of diodes D13 and D14 are sufficiently smaller than the value of resistor R7, resistors R5 and R6 of the signal generation circuit 10ZK can be replaced with resistor R7.

[0367] [Simulation results of the signal generation circuit 10ZJ shown in Figure 55: Figures 57A to 57F] Figures 57A to 57F show the results of a simulation performed on the signal generation circuit 10ZK shown in Figure 55. In this simulation, the idle currents of diodes D1 and D2 are set to 6% of the full scale.

[0368] Graphs C, D, and F show that the error is smaller at certain temperatures, indicating an improvement in nonlinearity. The temperature dependence of diode currents Id1 and Id2, as well as the temperature dependence of the input resistance, is larger compared to the signal generation circuit 10Z before the addition of the resistor (Figure 35).

[0369] In addition, in the signal generation circuit 10ZK shown in Figure 55 and the signal generation circuit 10ZL shown in Figure 56, the resistor Rp1 connected to the anode side of diode D1 may be provided in the current path between the cathode of diode D1 and the reference voltage node, and the resistor Rn1 connected to the cathode side of diode D2 may be provided in the current path between the anode of diode D2 and the reference voltage node. In this case as well, nonlinearity can be improved in the same way as in the signal generation circuit 10ZK shown in Figure 55 and the signal generation circuit 10ZL shown in Figure 56. Furthermore, since signals S1 and S2 can be generated by the voltages generated in resistors Rp1 and Rn1, the circuit configuration of the first current detection unit 411 and the second current detection unit 421 can be simplified, similar to the signal generation circuit 10ZA shown in Figure 37.

[0370] <Twelfth Embodiment> Next, a twelfth embodiment of the present invention will be described. This embodiment relates to improving the nonlinearity in the current-input type and voltage-input type signal generation circuits described above.

[0371] Figure 58 is a diagram illustrating the improvement of nonlinearity in the signal generation circuit according to the twelfth embodiment. Each graph in Figure 58 is Graph A of the simulation results described above, and as an example, Graph A for a single-output signal generation circuit is shown. The first Graph A from the top is before the nonlinearity improvement was applied. Looking at this, the slope of the central plot (the plot showing the sum of the two diode currents) is different near zero of the input current Ii and in the rest of the range. That is, the slope near zero of the input current Ii is larger than the slope in the rest of the range.

[0372] To improve this nonlinearity, the plot of the positive diode current in graph A can be shifted to the right, and the plot of the negative diode current can be shifted to the left. By shifting the diode current plots, the central plot (the sum of the two diode currents) can be made to have a roughly constant slope over the entire range of input current Ii, as shown in graph A, the second from the top. To shift the plot of the positive diode current to the right, the rightward input acting on the positive diode in graph A (the input current or input voltage of the signal generation circuit) can be reduced by a certain offset. Similarly, to shift the plot of the negative diode current to the left, the leftward input acting on the negative diode in graph A (the input current or input voltage of the signal generation circuit) can be reduced by a certain offset.

[0373] To improve the nonlinearity of the central plot, an offset can be applied to the input (input current or input voltage) by adding a voltage source in series with the diodes in the reference diode circuit (a series circuit of one or more diodes) that serves as the reference for voltages V1 and V2 (voltages supplied to the signal-generating diodes D1 and D2). This process of improving nonlinearity by adding a voltage source to a diode circuit may be referred to as "adding a voltage source" below.

[0374] As shown in graph A, the second from the top, adding a voltage source reduces the idle current when the input is zero. The reduced idle current can be increased to a desired value by adjusting predetermined constants in the circuits that generate voltages V1 and V2 (for example, the magnitude of the constant current supplied to the diode circuit).

[0375] Figure 59A shows an example of a signal generation circuit according to the twelfth embodiment. The signal generation circuit 10ZM shown in Figure 59A is the same as the signal generation circuit 10 shown in Figure 3, but with the addition of a positive voltage supply unit 36p and a negative voltage supply unit 36n to the voltage control unit 30. The other configurations are the same as the signal generation circuit 10 shown in Figure 3. The positive voltage supply unit 36p is an example of the positive voltage supply unit of the present invention. The negative voltage supply unit 36n is an example of the negative voltage supply unit of the present invention.

[0376] The positive voltage supply unit 36p is provided in series with diode D3 in the current path between node N3 and intermediate node M1. The negative voltage supply unit 36n is provided in series with diode D4 in the current path between intermediate node M1 and node N4.

[0377] The positive voltage supply unit 36p supplies a voltage that increases the forward voltage of diode D3, thereby increasing the current flowing through diode D3. In the example shown in Figure 59A, the positive terminal of the positive voltage supply unit 36p is connected to the reference voltage node, and the negative terminal is connected to the cathode of diode D3. The positive voltage supply unit 36p may be provided in series with the cathode side of diode D3 as shown in Figure 59A, or it may be provided in series with the anode side of diode D3.

[0378] The negative voltage supply unit 36n supplies a voltage that increases the forward voltage of diode D4, thereby increasing the current flowing through diode D4. In the example shown in Figure 59A, the negative terminal of the negative voltage supply unit 36n is connected to the reference voltage node, and the positive terminal is connected to the anode of diode D4. The negative voltage supply unit 36n may be provided in series with the anode side of diode D4, as shown in Figure 59A, or it may be provided in series with the cathode side of diode D4.

[0379] Figures 59B and 59C show examples of the configuration of the positive voltage supply unit 36p and the negative voltage supply unit 36n, respectively, and illustrate examples configured using resistor circuits. The positive voltage supply unit 36p shown in Figure 59B has a resistor Rv1 in the current path between the cathode of diode D3 and the reference voltage node, and a resistor Rv2 in the current path between the cathode of diode D3 and the negative voltage VL-'. The negative voltage VL-' may be the same as the negative voltage VL-. The negative voltage supply unit 36n shown in Figure 59C has a resistor Rv3 in the current path between the reference voltage node and the anode of diode D4, and a resistor Rv4 in the current path between the positive voltage VL+' and the anode of diode D4. The positive voltage VL+' may be the same as the positive voltage VL+.

[0380] In the examples in Figures 59B and 59C, resistors Rv1 and Rv3 are preferably relatively low resistance, and resistors Rv2 and Rv4 are preferably relatively high resistance. Resistors Rv2 and Rv4 may also be constant current sources.

[0381] In the signal generation circuit 10ZM having the above configuration, the diode current Id1 of diode D1 and the diode current Id2 of diode D2 decrease by the amount by which the current of diodes D3 and D4 increases due to the provision of the positive voltage supply unit 36p and the negative voltage supply unit 36n. If we call the decrease in diode currents Id1 and Id2 "offset current Iofs", then this decrease in offset current Iofs can be considered as a decrease in input current Ii. That is, the input current Ii can be considered to be less than the offset current Iofs compared to the current required to restore diode currents Id1 and Id2 to their original levels. The decrease in input current Ii by the amount of offset current Iofs corresponds to shifting the plot of the positive diode current to the right and the plot of the negative diode current to the left in graph A shown in Figure 58. Therefore, by setting the voltages of the positive voltage supply unit 36p and the negative voltage supply unit 36n so that an appropriate reduction in the offset current Iofs occurs, the nonlinearity of "Id2-Id1" with respect to the input current Ii can be improved.

[0382] Furthermore, it is preferable that the voltages of the positive voltage supply unit 36p and the negative voltage supply unit 36n are set such that the decrease in diode current Id1 due to the voltage of the positive voltage supply unit 36p is equal to the decrease in diode current Id2 due to the voltage of the negative voltage supply unit 36n. This makes it easier to improve the nonlinearity of "Id2-Id1" because the offset currents Iofs of diodes D1 and D2 become equal.

[0383] [Simulation results of the signal generation circuit 10ZM shown in Figure 59A: Figures 60A to 60F] Figures 60A to 60F show the results of simulations performed on the signal generation circuit 10ZM shown in Figure 59A.

[0384] As seen in the simulation results in Figures 60A to 60F, the linearity of "Id2-Id1" is good. Compared to the simulation results before adding the voltage source (Figures 5A to 5F), the linearity of "Id2-Id1" was relatively good even in the original simulation results, but after adding the voltage source, the linearity has improved by another order of magnitude. In the comparison of the graphs shown, the linearity error of "Id2-Id1" with respect to the current signal source Is (current signal source when input current Ii is supplied through a 10kΩ resistor) (Graph E) has become noticeably smaller.

[0385] Furthermore, compared with the simulation results before the addition of the voltage source (Figures 5A to 5F), the temperature-dependent changes in each characteristic have also improved with the addition of the voltage source. In particular, the temperature dependence of the input resistance shown in Graph F and the temperature dependence of the linearity error shown in Graph E have been significantly reduced with the addition of the voltage source.

[0386] (Modification 1 of the 12th embodiment) Figure 61 shows a modified example of the signal generation circuit according to the twelfth embodiment. The signal generation circuit 10ZN shown in Figure 61 is obtained by replacing the first signal output section 51 and the second signal output section 52 in the single-output type signal generation circuit 10ZD shown in Figure 44 with the first signal output section 51F and the second signal output section 52F, respectively.

[0387] [First signal output section 51F] The first signal output unit 51F is the same as the first signal output unit 51 (Figure 44), but with the first diode circuit 513 replaced by the first diode circuit 513F. The other configurations are the same as the first signal output unit 51. The first diode circuit 513F has the same diodes D15 and D16 as the first diode circuit 513, and also has a positive voltage supply unit 514 connected in series with these diodes. The positive voltage supply unit 514 supplies a voltage that increases the forward voltage of diodes D15 and D16, respectively. In the example in Figure 61, the negative terminal of the positive voltage supply unit 514 is connected to the cathode of diode D16, and the positive terminal is connected to the reference voltage node. The positive voltage supply unit 514 may be connected in series with the cathode side of diode D16 as shown in Figure 61, or in series with the anode side of diode D16 (the cathode side of diode D15), or in series with the anode side of diode D15.

[0388] [Second signal output section 52F] The second signal output unit 52F is the same as the second signal output unit 52 (Figure 44), but with the second diode circuit 523 replaced by the second diode circuit 523F. The other configurations are the same as the second signal output unit 52. The second diode circuit 523F has the same diodes D17 and D18 as the second diode circuit 523, and also has a negative voltage supply unit 524 connected in series with these diodes. The negative voltage supply unit 524 supplies a voltage that increases the forward voltage of diodes D17 and D18, respectively. In the example in Figure 61, the negative terminal of the negative voltage supply unit 524 is connected to the reference voltage node, and the positive terminal is connected to the anode of diode D18. The negative voltage supply unit 524 may be connected in series with the anode side of diode D18 as shown in Figure 61, or in series with the cathode side of diode D18 (the anode side of diode D17), or in series with the cathode side of diode D17.

[0389] In the signal generation circuit 10ZN having the above configuration, when the current Id15 of the first diode circuit 513F increases due to the voltage of the positive voltage supply unit 514, the diode current Id1 of diode D1 decreases in proportion to the increase in current. Also, when the current Id17 of the second diode circuit 523F increases due to the voltage of the negative voltage supply unit 524, the diode current Id2 of diode D2 decreases in proportion to the increase in current. The decrease in diode current Id1 can be considered as a decrease in the input current Ii1 flowing into the current input node Ni1, and the decrease in diode current Id2 can be considered as a decrease in the input current Ii2 flowing out from the current input node Ni2. Therefore, by appropriately setting the voltages of the positive voltage supply unit 514 and the negative voltage supply unit 524, the nonlinearity of "Id2-Id1" with respect to the input currents Ii1 and Ii2 can be improved.

[0390] Furthermore, it is preferable that the voltages of the positive voltage supply unit 514 and the negative voltage supply unit 524 be set such that the decrease in diode current Id1 due to the voltage of the positive voltage supply unit 514 is equal to the decrease in diode current Id2 due to the voltage of the negative voltage supply unit 524. This makes it easier to improve the nonlinearity of "Id1-Id2" because the current decreases (offset current Iofs) of diodes D1 and D2 become equal.

[0391] Furthermore, the positive voltage supply unit 514 and the negative voltage supply unit 524 may be configured by circuits using low resistance and high resistance (or current sources), as shown in Figures 59B and 59C, for example.

[0392] [Simulation results of the signal generation circuit 10ZN shown in Figure 61: Figures 62A to 62F] Figures 62A to 62F show the results of simulations performed on the signal generation circuit 10ZN shown in Figure 61.

[0393] Comparing the simulation results in Figures 62A to 62F with the simulation results before adding the voltage source (Figures 45A to 45F), the nonlinearity of "Id1-Id2" has improved, and the temperature-dependent changes in each characteristic have also decreased. Furthermore, the input resistance has decreased compared to before adding the voltage source, making it less susceptible to the influence of the output impedance of the current signal source.

[0394] (Modification 2 of the 12th embodiment) Figure 63 shows an example of a signal generation circuit according to the twelfth embodiment. The signal generation circuit 10ZP shown in Figure 63 is obtained by replacing the first signal output section 41 and the second signal output section 42 in the voltage input type signal generation circuit 10Z shown in Figure 35 with the first signal output section 41E and the second signal output section 42E, respectively.

[0395] [First signal output section 41E] The first signal output unit 41E is the same as the first signal output unit 41 (Figure 35), but with the first voltage control unit 410 replaced by the first voltage control unit 410E. The other configurations are the same as the first signal output unit 41. The first voltage control unit 410E has the same first constant current supply unit 412 and diode D13 as the first voltage control unit 410, as well as a positive voltage supply unit 414. The positive voltage supply unit 414 is provided in series with the diode D13 in the current path between node N1 and voltage input node Nv. The positive voltage supply unit 414 supplies a voltage that increases the forward voltage of diode D13. In the example in Figure 63, the negative terminal of the positive voltage supply unit 414 is connected to the cathode of diode D13, and the positive terminal is connected to the voltage input node Nv. The positive voltage supply unit 414 may be provided in series with the cathode side of diode D13 as shown in Figure 63, or it may be provided in series with the anode side of diode D13.

[0396] [Second signal output section 42E] The second signal output unit 42E is the same as the second signal output unit 42 (Figure 35), but with the second voltage control unit 420 replaced by the second voltage control unit 420E. The second voltage control unit 420E has the same second constant current supply unit 422 and diode D14 as the second voltage control unit 420, as well as a negative voltage supply unit 424. The negative voltage supply unit 424 is provided in series with the diode D14 in the current path between the voltage input node Nv and node N2. The negative voltage supply unit 424 supplies a voltage that increases the forward voltage of the diode D14. In the example in Figure 63, the negative terminal of the negative voltage supply unit 424 is connected to the voltage input node Nv, and the positive terminal is connected to the anode of the diode D14. The negative voltage supply unit 424 may be provided in series with the anode side of the diode D14 as shown in Figure 63, or it may be provided in series with the cathode side of the diode D14.

[0397] In the signal generation circuit 10ZP having the above configuration, when the voltage from the positive voltage supply unit 414 increases the current Id13 of diode D13, the diode current Id1 of diode D1 decreases in proportion to the increase in current. Similarly, when the voltage from the negative voltage supply unit 424 increases the current Id14 of diode D14, the diode current Id2 of diode D2 decreases in proportion to the increase in current. The decrease in diode current Id1 can be considered as a decrease in the positive input voltage Vi, and the decrease in diode current Id2 can be considered as a decrease in the negative input voltage Vi. Therefore, by appropriately setting the voltages of the positive voltage supply unit 414 and the negative voltage supply unit 424, the nonlinearity of "Id1-Id2" with respect to the input voltage Vi can be improved.

[0398] Furthermore, it is preferable that the voltages of the positive voltage supply unit 414 and the negative voltage supply unit 424 be set such that the decrease in diode current Id1 due to the voltage of the positive voltage supply unit 414 is equal to the decrease in diode current Id2 due to the voltage of the negative voltage supply unit 424. This makes it easier to improve the nonlinearity of "Id1-Id2" because the current decreases (offset current Iofs) of diodes D1 and D2 become equal. Furthermore, the positive voltage supply unit 414 and the negative voltage supply unit 424 may be configured by circuits using low resistance and high resistance (or current sources), as shown in Figures 59B and 59C, for example.

[0399] [Simulation results of the signal generation circuit 10ZP shown in Figure 63: Figures 64A to 64F] Figures 64A to 64F show the results of simulations performed on the signal generation circuit 10ZP shown in Figure 63. Comparing the simulation results in Figures 64A to 64F with the simulation results before adding the voltage source (Figures 36A to 36F), we see that the nonlinearity of "Id1-Id2" has improved, and the fluctuation of the input resistance in response to the input voltage Vi has also been suppressed.

[0400] (Modification 3 of the 12th embodiment) Figure 65 shows an example of a signal generation circuit according to the twelfth embodiment. The signal generation circuit 10ZQ shown in Figure 65 is obtained by replacing the first signal output section 41B and the second signal output section 42B in the voltage input type signal generation circuit 10ZB shown in Figure 39 with the first signal output section 41F and the second signal output section 42F, respectively.

[0401] [First signal output section 41F] The first signal output unit 41F is the same as the first signal output unit 41B (Figure 39), but with the first voltage control unit 410B replaced by the first voltage control unit 410F. The other configurations are the same as the first signal output unit 41B. The first voltage control unit 410F has the same first constant current supply unit 412B and diode D13 as the first voltage control unit 410B, as well as a positive voltage supply unit 414. The positive voltage supply unit 414 is provided in series with diode D13 in the current path between node N13 and voltage input node Nv. The positive voltage supply unit 414 supplies a voltage that increases the forward voltage of diode D13. In the example in Figure 65, the negative terminal of the positive voltage supply unit 414 is connected to the cathode of diode D13, and the positive terminal is connected to voltage input node Nv. The positive voltage supply unit 414 may be provided in series with the cathode side of diode D13, as shown in Figure 65, or it may be provided in series with the anode side of diode D13.

[0402] [Second signal output section 42F] The second signal output unit 42F is a replacement of the second voltage control unit 420B in the second signal output unit 42B (Figure 39), with the other configurations being the same as the second signal output unit 42B. The second voltage control unit 420F has the same second constant current supply unit 422B and diode D14 as the second voltage control unit 420B, as well as a negative voltage supply unit 424. The negative voltage supply unit 424 is provided in series with diode D14 in the current path between the voltage input node Nv and node N14. The negative voltage supply unit 424 supplies a voltage that increases the forward voltage of diode D14. In the example in Figure 65, the negative terminal of the negative voltage supply unit 424 is connected to the voltage input node Nv, and the positive terminal is connected to the anode of diode D14. The negative voltage supply unit 424 may be provided in series with the anode side of diode D14, as shown in Figure 65, or it may be provided in series with the cathode side of diode D14.

[0403] In the signal generation circuit 10ZQ having the above configuration, when the voltage from the positive voltage supply unit 414 increases the current Id13 of diode D13, the voltage V1 decreases in proportion to the increase in current, and the diode current Id1 of diode D1 decreases. Also, when the voltage from the negative voltage supply unit 424 increases the current Id14 of diode D14, the voltage V2 rises to the positive side in proportion to the increase in current, and the diode current Id2 of diode D2 decreases. The decrease in diode current Id1 can be considered as a decrease in the positive input voltage Vi, and the decrease in diode current Id2 can be considered as a decrease in the negative input voltage Vi. Therefore, by appropriately setting the voltages of the positive voltage supply unit 414 and the negative voltage supply unit 424, the nonlinearity of "Id1-Id2" with respect to the input voltage Vi can be improved.

[0404] Furthermore, it is preferable that the voltages of the positive voltage supply unit 414 and the negative voltage supply unit 424 be set such that the decrease in diode current Id1 due to the voltage of the positive voltage supply unit 414 is equal to the decrease in diode current Id2 due to the voltage of the negative voltage supply unit 424. This makes it easier to improve the nonlinearity of "Id1-Id2" because the current decreases (offset current Iofs) of diodes D1 and D2 become equal. Furthermore, the positive voltage supply unit 414 and the negative voltage supply unit 424 may be configured by circuits using low resistance and high resistance (or current sources), as shown in Figures 59B and 59C, for example.

[0405] [Simulation results of the signal generation circuit 10ZQ shown in Figure 65: Figures 66A to 66F] Figures 66A to 66F show the results of simulations performed on the signal generation circuit 10ZQ shown in Figure 65. Comparing the simulation results in Figures 66A to 66F with the simulation results before adding the voltage source (Figures 40A to 40F), it can be seen that the nonlinearity of "Id1-Id2" has improved.

[0406] In addition, in the signal generation circuit 10ZP shown in Figure 63 and the signal generation circuit 10ZQ shown in Figure 65, the resistor Rp1 connected to the anode side of diode D1 may be provided in the current path between the cathode of diode D1 and the reference voltage node, and the resistor Rn1 connected to the cathode side of diode D2 may be provided in the current path between the anode of diode D2 and the reference voltage node. In this case as well, nonlinearity can be improved in the same way as in the signal generation circuit 10ZP shown in Figure 63 and the signal generation circuit 10ZQ shown in Figure 65. Furthermore, since signals S1 and S2 can be generated by the voltages generated in resistors Rp1 and Rn1, the circuit configuration of the first current detection unit 411 and the second current detection unit 421 can be simplified, similar to the signal generation circuit 10ZA shown in Figure 37.

[0407] <13th Embodiment> Next, a thirteenth embodiment of the present invention will be described. This embodiment prevents the push-pull operation signal generated in the signal generation circuit from crossing zero and becoming reverse polarity.

[0408] The push-pull operation signals used in a Class AB push-pull amplifier circuit must not cross zero and have their polarity reversed. For example, in the Class AB push-pull amplifier circuit 1 shown in Figure 1, if the polarity of signals S1 and S2 reverses, the output elements (Qp, Qn, etc.) in the first output section 6 and the second output section 7 will be cut off, and the frequency characteristics of the amplifier circuit may be impaired due to the time required to recover from the cutoff state to the operating state. Also, when signals S1 and S2 are close to zero, the output elements may be cut off or on the verge of cutoff due to the influence of the amplifier's offset voltage in the current detection section 1, current detection section 2, first output section 6, second output section 7, etc., which may also impair the frequency characteristics of the amplifier circuit.

[0409] For diodes carrying current corresponding to signals used in push-pull operation, it is desirable that current flows only in the forward direction. However, in some of the signal generation circuits according to the embodiments described above, a reverse voltage is applied to the diode as well as a forward voltage. When a reverse voltage is applied, a small reverse current flows through the diode. Reverse current is easily affected by ambient temperature and generally increases as the temperature rises. When a reverse current flows through the diode, the polarity of signals S1 and S2 is reversed accordingly, and the output elements in the first output section 6 and the second output section 7 may temporarily enter a cutoff state. Furthermore, even when no reverse current flows, if the forward current becomes extremely close to zero, the output elements may come to a state just before cutoff, or the output elements may enter a cutoff state due to the influence of the offset voltage of the amplifier used in the first output section 106 and the second output section 107.

[0410] Therefore, in this embodiment, in the signal generation circuit, the circuit that detects and outputs the diode current corresponding to the signal for push-pull operation outputs a current as the detection result that is a certain offset current larger than the actual diode current. As a result, even if the actual diode current is very close to zero or a reverse current flows, the diode current in the detection result will not be of reverse polarity, nor will it be very close to zero, thus avoiding the cutoff state of the output element described above. In the following description, outputting a current larger than the actual diode current as the detection result in the circuit that detects the diode current may be referred to as "boosting".

[0411] Furthermore, raising the detected diode current results will increase the current flowing through the output elements of the Class AB push-pull amplifier circuit and the power consumption. Therefore, it is preferable to set the amount of the raising to the minimum necessary to sufficiently avoid the cutoff state of the output elements.

[0412] The diode current boosting according to this embodiment can be applied to the current detection units (21, 22, 23, 24, 411, 421, 511, 521, etc.) in each of the embodiments described above. In other words, the first current detection unit (21, 23, 411) that detects the diode current Id1 of diode D1 outputs a signal S1 that indicates a current that is larger than the diode current Id1 by a predetermined first offset current. The second current detection unit (23, 24, 421, 521), which detects the diode current Id2 of diode D2, outputs a signal S2 that is larger than the diode current Id2 by a predetermined second offset current. In this case, it is preferable that the first offset current of the first current detection unit and the second offset current of the second current detection unit are equal.

[0413] Figures 67A and 67B show an example of the configuration of the current detection unit in the signal generation circuit according to the 13th embodiment. The current detection unit (21, 22) shown in Figure 67A is the same as the circuit shown in Figure 4B, but with the addition of a constant current source 201. The constant current source 201 supplies a constant current to the terminals connected to the cathodes of the diodes (D1, D2) in the shunt resistor SH. The current detection unit (21, 22) shown in Figure 67B is the same as the circuit shown in Figure 4C, but with the addition of a constant current source 202. The constant current source 202 outputs a constant current from the terminals connected to the anodes of the diodes (D1, D2) in the shunt resistor. By providing constant current sources 201 and 202 in the current detection units (21 and 22), signals S1 and S2 indicating a current larger than the actual diode current can be output.

[0414] The diode current boosting in the current detection section is not limited to supplying a constant current to the shunt resistor SH, as shown in Figures 67A and 67B. It can also be achieved, for example, by adding a DC signal to the detection signal inside the current detection amplifier SA that amplifies the voltage generated across the shunt resistor SH.

[0415] Figure 67C shows an example of the configuration of a current sense amplifier SA used to boost the diode current detection result. The current sense amplifier SA shown in Figure 67C is an instrumentation amplifier composed of operational amplifiers, and a constant current is input to the input terminal of the operational amplifier that performs current summation by a constant current source 204. As a result, a DC offset current component corresponding to the input constant current is added to the output signal of the current sense amplifier SA.

[0416] Figure 68 shows an example of a signal generation circuit according to the 13th embodiment, and illustrates an example in which the configuration of the current detection units 21 and 22 in the signal generation circuit 10J shown in Figure 16 has been changed. The signal generation circuit 10J shown in Figure 68 is the same as the signal generation circuit 10J shown in Figure 16, but with the addition of constant current sources 201 and 202 for raising the current level, as shown in Figures 67A and 67B. In this example, the constant current source 202 shown in Figure 67B is added to the current detection unit 21, and the constant current source 201 shown in Figure 67A is added to the current detection unit 22.

[0417] Figure 69 shows an example of a signal generation circuit according to the 13th embodiment, in which the constant current from the two constant current sources 201 and 202 in the signal generation circuit 10J shown in Figure 68 is supplied by a single constant current source 203. In this example, a constant current in the current flowing out from the shunt resistor SH1 of the current detection unit 21 flows into the shunt resistor SH2 of the current detection unit 22 via the constant current source 203. As a result, the same offset current flows through the shunt resistors SH1 and SH2, so that the same offset component can be added to signals S1 and S2.

[0418] Figures 70A to 70D show an example of the configuration of the current detection unit in the signal generation circuit according to the 13th embodiment. The current detection unit 23 shown in Figure 70A is the same as the circuit shown in Figure 23B, but with the addition of a constant current source 205. The constant current source 205 supplies a constant current to the inverting input of the operational amplifier U23, thereby adding a constant offset current component to the output signal S1 of the operational amplifier U23, which indicates the detection result of the diode current Id1. The current detection unit 24 shown in Figure 70C is the same as the circuit shown in Figure 23E, but with the addition of a constant current source 207. The constant current source 207 outputs a constant current from the inverting input of the operational amplifier U24, thereby adding a constant offset current component to the output signal S2 of the operational amplifier U24, which indicates the detection result of the diode current Id2.

[0419] The current detection unit 23 shown in Figure 70B is the same as the circuit shown in Figure 23C, but with the addition of a constant current source 206. The constant current source 206 adds a constant offset current component to the signal S1, which indicates the detection result of the diode current Id1, by supplying a constant current to one end of the shunt resistor SH23 connected to the cathode of the diode D1. The current detection unit 24 shown in Figure 70D is the same as the circuit shown in Figure 23F, but with the addition of a constant current source 208. The constant current source 208 adds a constant offset current component to the signal S2, which indicates the detection result of the diode current Id2, by discharging a constant current from one end of the shunt resistor SH24 connected to the anode of the diode D2.

[0420] Furthermore, the circuit configuration of the current detection units 21-24 that raise the current level as described above can also be applied to the first current detection units 411 and 511 and the second current detection units 421 and 521. Furthermore, the constant current sources 201 to 208 in each of the circuits described above are not limited to constant current circuits; they may also be resistors with relatively high resistance values.

[0421] Furthermore, the above-mentioned boosting technique can be applied to signal generation circuits other than those using diodes for signal generation. For example, in the case of the signal generation circuit 110 shown in Figure 89, an offset current may be added to the collector current Iq1 by supplying a constant current from a constant current source to the negative power supply voltage through the path through which the collector current Iq1 of the npn transistor Q113 flows. Alternatively, an offset current may be added to the collector current Iq2 of the pnp transistor Q114 by supplying a constant current from a constant current source to the path through which the collector current Iq2 flows from the path through which the collector current Iq1 flows. Furthermore, the same offset current may be added to both the collector current Iq1 and the collector current Iq2 by supplying a constant current from a constant current source to the path through which the collector current Iq2 flows, from the path through which the collector current Iq1 flows. The constant current source used for adding the offset current may be a constant current circuit or a resistor. By adding such offset currents, it is possible to avoid the cutoff state of the output elements (Qp, Qn) when the collector currents Iq1 and Iq2 approach zero.

[0422] <Embodiment 14> Next, a fourteenth embodiment of the present invention will be described. In this embodiment, one signal generated in the signal generation circuit is used to generate the other signal.

[0423] In a Class AB push-pull amplifier circuit, the signals S1 and S2 used to initiate the push-pull operation do not cross zero and reverse polarity, as described in the 13th embodiment, and typically have opposite polarities. That is, if one of signals S1 and S2 is positive, the other is negative. Typically, one of signals S1 and S2 is proportional to the positive output of the Class AB push-pull amplifier circuit, and the other is proportional to the negative output. The sum of signals S1 and S2 is proportional to the total output signal obtained by combining the positive and negative outputs of the Class AB push-pull amplifier circuit.

[0424] On the other hand, the input signal (voltage or current) of the signal generation circuit that generates signals S1 and S2 is proportional to the output signal of the Class AB push-pull amplifier circuit, and the gain of the output signal with respect to this input signal is fixed. From this, the sum of signals S1 and S2, "S1 + S2", is proportional to the input signal of the signal generation circuit, and the gain of the sum "S1 + S2" with respect to the input signal is fixed. Therefore, given a certain input signal, ideally, the result of multiplying this input signal by a predetermined gain should match the sum "S1 + S2". That is, based on the input signal (by multiplying the input signal by a predetermined gain), a signal showing the ideal target value of the sum "S1 + S2" can be obtained. Hereafter, this signal showing the target value may be referred to as "signal Si". Ideally, Si = S1 + S2 holds true.

[0425] Therefore, in the signal generation circuit according to this embodiment, the other signal S1 and S2 is generated by subtracting one of the signals S1 and S2 generated using the signal generation circuits according to the above-described embodiments from a signal Si (a signal indicating the target value of the sum "S1+S2") which is proportional to the input signal of the signal generation circuit. As a result, the sum "S1+S2" is approximately equal to the signal Si, and the nonlinearity of the sum "S1+S2" with respect to the input signal of the signal generation circuit can be improved. Generating the other signal using one of the signals S1 and S2 is sometimes called a "single-signal generation method".

[0426] Figures 71 to 74 show examples of Class AB push-pull amplifier circuits equipped with a signal generation circuit according to the 14th embodiment.

[0427] The signal generation circuit 10ZR in the Class AB push-pull amplifier circuit 1C shown in Figure 71 has current-input type signal generation circuits (10, 10A~10H, 10J~10N, 10P~10Y, 10ZD~10ZH, 10ZJ, 10ZM, 10ZN) according to each of the above-described embodiments, and a first signal generation unit 61.

[0428] The first signal generation unit 61 generates a signal S1A corresponding to the value obtained by subtracting signal S2 from the target value of the sum "S1+S2", based on a signal Si corresponding to the target value of the sum "S1+S2" and a signal S2 output from the current detection units (22, 24, 521) of the signal generation circuit. The circuit that generates signal S1A in the first signal generation unit 61 may be an analog arithmetic circuit configured using an operational amplifier, for example, as shown in Figure 75A. The signal S1A generated in the first signal generation unit 61 is supplied to the first output unit 6 and the second output unit 7 in place of the signal S1 generated in the signal generation circuit described above.

[0429] In the Class AB push-pull amplifier circuit 1D shown in Figure 72, 10ZS has current-input type signal generation circuits (10, 10A~10H, 10J~10N, 10P~10Y, 10ZD~10ZH, 10ZJ, 10ZM, 10ZN) according to the above-described embodiments, and a second signal generation unit 62.

[0430] The second signal generation unit 62 generates a signal S2A corresponding to the value obtained by subtracting signal S1 from the target value of the sum "S1 + S2", based on a signal Si corresponding to the target value of the sum "S1 + S2" and a signal S1 output from the current detection units (21, 23, 511) of the signal generation circuit. The circuit that generates signal S2A in the second signal generation unit 62 may be an analog arithmetic circuit configured using an operational amplifier, for example, as shown in Figure 75A. The signal S2A generated in the second signal generation unit 62 is supplied to the first output unit 6 and the second output unit 7 in place of the signal S2 generated in the signal generation circuit described above.

[0431] Furthermore, if the signal generation circuits included in the signal generation circuits 10ZR and 10ZS shown in Figures 71 and 72 are of the single-output type, the input currents Ii1 and Ii2 can be generated by the two voltage-current conversion units 5a and 5b of the input amplifier unit 2B (Figure 43).

[0432] Furthermore, if the signal generation circuits included in the signal generation circuits 10ZR and 10ZS shown in Figures 71 and 72 are of the single-output type, the part of the first signal output section and the second signal output section that is not used for signal generation may be omitted. That is, if the signal generation circuit 10ZR shown in Figure 71 includes a single-output type signal generation circuit, the first signal output section (51, 51A~51F) may be omitted. If the signal generation circuit 10ZS shown in Figure 72 includes a single-output type signal generation circuit, the second signal output section (52, 52A~52F) may be omitted.

[0433] The signal generation circuit 10ZT in the Class AB push-pull amplifier circuit 1E shown in Figure 73 has voltage input type signal generation circuits (10Z, 10ZA~10ZC, 10ZK, 10ZL, 10ZP, 10ZQ) according to each embodiment described above, and a first signal generation unit 61. The first signal generation unit 61 is the same as the one shown in Figure 71, which has already been described.

[0434] The signal generation circuit 10ZU in the Class AB push-pull amplifier circuit 1F shown in Figure 74 has voltage input type signal generation circuits (10Z, 10ZA~10ZC, 10ZK, 10ZL, 10ZP, 10ZQ) according to the above-described embodiments, and a second signal generation unit 62. The second signal generation unit 62 is the same as the one shown in Figure 72, which has already been described.

[0435] In addition, in the voltage-input type signal generation circuits included in the signal generation circuits 10ZT and 10ZU shown in Figures 73 and 74, the part of the first signal output section and the second signal output section that is not used for signal generation may be omitted. That is, in the voltage-input type signal generation circuit included in the signal generation circuit 10ZT shown in Figure 73, the first signal output section (41, 41A~41F) may be omitted. In the voltage-input type signal generation circuit included in the signal generation circuit 10ZS shown in Figure 72, the second signal output section (42, 42A~42F) may be omitted.

[0436] In the examples shown in Figures 71 to 74, the signal Si is generated by amplifying the voltage Vi output from the differential amplifier 4 with an amplifier of gain A, but it may also be generated based on any other signal proportional to the signal Si. The first signal generation unit 61 and the second signal generation unit 62 may generate signals S1A and S2A by receiving other signals proportional to signal Si, rather than inputting signal Si, and performing necessary calculations (multiplication, addition, etc.) using analog arithmetic circuits or the like. Furthermore, the signal Si is not limited to a voltage signal; it may also be a current signal.

[0437] Next, we will describe the results of some simulations performed on the signal generation circuit according to this embodiment.

[0438] As mentioned earlier, in this embodiment, a signal Si indicating the target value of the sum "S1 + S2" is used to generate one signal from the other S1 and S2. Since the signal Si is proportional to the input (voltage, current) of the signal generation circuit, and the sum "S1A + S2" and the sum "S1 + S2A" coincide with the signal Si, this sum does not produce a nonlinear error with respect to the input (voltage, current) of the signal generation circuit. Therefore, in the simulation results of the signal generation circuit according to this embodiment, graph C, which shows the linearity error of the sum "S1(S1A)+S2A(S2)" with respect to the inputs of the signal generation circuit (input current Ii, input voltage Vi), is an error-free graph as shown in Figure 75B. Similarly, for graphs D and F, where a finite resistor is connected to the output of the signal source, if the signal Si is proportional to the signal level at the signal source, the graphs are error-free as shown in Figure 75B. Below, graphs C to F are omitted, and only graphs A and B are shown.

[0439] [Simulation results when a single-signal generation method is applied to the signal generation circuit 10 in Figure 3] Figure 76A shows the simulation results of the signal generation circuit 10 from Figure 3, reproduced for comparison, and is the same as Figures 5A and 5B. Figure 76B shows the simulation results when the signal generation circuit 10 (Figure 3) is used in the signal generation circuit 10ZR shown in Figure 71. Figure 76C shows the simulation results when the signal generation circuit 10 (Figure 3) is used in the signal generation circuit 10ZS shown in Figure 72.

[0440] The signal generation circuit 10 in Figure 3 exhibits relatively small linearity errors even without applying the single-signal generation method, so there is little difference between graphs A and B. However, the F graph (Figure 5F: not reproduced), which shows the linearity error with respect to the signal source, becomes zero when the single-signal generation method is applied, as shown in graph F in Figure 75B.

[0441] [Simulation results when a single-signal generation method is applied to the signal generation circuit 10ZD in Figure 44] Figure 77A shows the simulation results of the signal generation circuit 10ZD from Figure 44, which are reproduced for comparison and are the same as those in Figures 45A and 45B. Figure 77B shows the simulation results when a single-output type signal generation circuit 10ZD (Figure 44) is used in addition to the signal generation circuit 10ZR shown in Figure 71. Figure 77C shows the simulation results when a single-output type signal generation circuit 10ZD (Figure 44) is used in addition to the signal generation circuit 10ZS shown in Figure 72.

[0442] As can be seen in Figure 77A, in the signal generation circuit 10ZD of Figure 44, the slope of the line representing the sum "Id1-Id2" is steep near zero of the input currents Ii1 and Ii2, indicating that a nonlinearity error is occurring. In contrast, in the signal generation circuits 10ZR and 10ZS, which apply the single-signal generation method, as shown in Figures 77B and 77C, no change in the slope of the sum "Id1-Id2" is observed, and the nonlinearity error is eliminated. Furthermore, looking at graphs A and B when the single-signal generation method is applied, the levels of the generated "S1A" and "S2A" do not approach zero sufficiently, so power consumption may increase when the absolute value of the input current Ii is large.

[0443] [Simulation results when a single-signal generation method is applied to the signal generation circuit 10ZA in Figure 37] Figure 78A shows the simulation results of the signal generation circuit 10ZA from Figure 37, reproduced for comparison, and is the same as Figures 38A and 38B. Figure 78B shows the simulation results when the voltage input type signal generation circuit 10ZA (Figure 37) is used in the signal generation circuit 10ZT shown in Figure 73. Figure 78C shows the simulation results when a voltage-input type signal generation circuit 10ZA (Figure 37) is used in the signal generation circuit 10ZU shown in Figure 74.

[0444] As can be seen in Figure 78A, in the signal generation circuit 10ZA in Figure 37, the slope of the line of the sum "Id1-Id2" clearly changes near zero of the input voltage Vi, indicating that the nonlinearity error is quite large. In contrast, in the signal generation circuits 10ZT and 10ZU, which apply the single-signal generation method, as shown in Figures 78B and 78C, no change in the slope of the sum "Vo1+Vo2" is observed, and the nonlinearity error is eliminated. Furthermore, looking at graphs A and B when the single-signal generation method is applied, the levels of the generated "S1A" and "S2A" do not approach zero sufficiently, so power consumption may increase when the absolute value of the input voltage Vi is large.

[0445] Figures 79A and 79B show an example of the configuration of a signal generation circuit according to this embodiment. Other signal generation circuits included in the signal generation circuit according to this embodiment are not limited to those that output signals S1 and S2 corresponding to the currents of diodes D1 and D2, but may be signal generation circuits of other types.

[0446] The signal generation circuit 12A shown in Figure 79A includes a signal generation circuit 11A that generates a signal S1 corresponding to an input signal (input current Ii, input voltage Vi), and the above-mentioned second signal generation unit 62 that generates a signal S2A based on signal Si and signal S1. The signal generation circuit 11A generates a signal S1 that increases in the positive direction in proportion to the signal Si when the input signal (input current Ii, input voltage Vi) increases in the positive direction, and changes from the positive side towards zero when the input signal (input current Ii, input voltage Vi) increases in the negative direction.

[0447] The signal generation circuit 12B shown in Figure 79B includes a signal generation circuit 11B that generates a signal S2 corresponding to an input signal (input current Ii, input voltage Vi), and the above-described first signal generation unit 61 that generates a signal S1A based on signal Si and signal S2. The signal generation circuit 11B generates a signal S2 that increases in the negative direction in proportion to the signal Si when the input signal (input current Ii, input voltage Vi) increases in the negative direction, and changes from the negative side to approach zero when the input signal (input current Ii, input voltage Vi) increases in the positive direction.

[0448] [Simulation results when a single-signal generation method is applied to the signal generation circuit 11 in Figure 89] Figure 80A shows the simulation results of the signal generation circuit 110 from Figure 89, which are reproduced for comparison and are the same as those in Figures 90A and 90B. Figure 80B shows the simulation results when the signal generation circuit 110 (Figure 89) is used in the signal generation circuit 12B shown in Figure 79B. Figure 80C shows the simulation results when the signal generation circuit 110 (Figure 89) is used in the signal generation circuit 12A shown in Figure 79A.

[0449] The signal generation circuit 110 in Figure 89 exhibits relatively small linearity errors even without applying the single-signal generation method, so there is little difference when comparing graphs A and B. However, when comparing graphs C, D, and F, which show linearity errors, an improvement in linearity can be observed because the error is eliminated by applying the single-signal generation method.

[0450] <Embodiment 15> Next, a fifteenth embodiment of the present invention will be described. In this embodiment, both of the two signals generated in the signal generation circuit are used to correct each signal.

[0451] In the signal generation circuit according to the 14th embodiment described above, one of the two signals S1 and S2 is used to generate the other signal, but the generated signal may not approach zero sufficiently. Therefore, in the signal generation circuit according to this embodiment, the two signals S1 and S2 are corrected (regenerated) based on the two signals S1 and S2 and a signal Si that indicates the target value of the sum "S1 + S2". Generating each signal using both signals S1 and S2 is sometimes called the "dual signal generation method".

[0452] For example, signal S1 is corrected using signals S2 and Si as follows. S1B = {(Si-S2)+S1} / 2 = (S1A+S1) / 2 …(1) Equation (1) represents the average of "S1A" and "S1" generated based on the signals Si and S2.

[0453] Furthermore, signal S2 is corrected using signal S1 and signal Si as follows. S2B = {(Si-S1)+S2} / 2 = (S2A+S2) / 2 …(2) Equation (2) represents the average of "S2A" and "S2" generated based on the signal Si and signal S1.

[0454] From equations (1) and (2), it can be seen that the sum of the corrected signal S1B and the corrected signal S2B is equal to the signal Si. Therefore, the linearity error of the sum "S1B + S2B" with respect to the input (input current Ii, input voltage Vi) is zero.

[0455] Figures 81 and 82 show examples of Class AB push-pull amplifier circuits equipped with a signal generation circuit according to the 15th embodiment.

[0456] The signal generation circuit 10ZV in the Class AB push-pull amplifier circuit 1G shown in Figure 81 includes current-input type signal generation circuits (10, 10A~10H, 10J~10N, 10P~10Y, 10ZD~10ZH, 10ZJ, 10ZM, 10ZN) according to the above-described embodiments, a first signal generation unit 61B, and a second signal generation unit 62B.

[0457] The first signal generation unit 61B generates a corrected signal S1B based on a signal Si corresponding to the target value of the sum "S1+S2", a signal S1 output from the current detection units (21, 23, 511) of the signal generation circuit, and a signal S2 output from the current detection units (22, 24, 521) of the signal generation circuit, and the average of the value obtained by subtracting signal S2 from the target value of the sum "S1+S2" and signal S1. The circuit that generates signal S1B in the first signal generation unit 61B may be an analog arithmetic circuit configured using an operational amplifier, for example, as shown in Figure 83A. When using the analog arithmetic circuit shown in Figure 83A, for example, "V(+1)" may be signal Si, "V(+2)" may be signal S1, and "V(-)" may be signal S2. The signal S1B generated in the first signal generation unit 61B is supplied to the first output unit 6 and the second output unit 7 in place of signal S1.

[0458] The second signal generation unit 62B generates a corrected signal S2B based on a signal Si corresponding to the target value of the sum "S1+S2", a signal S1 output from the current detection units (21, 23, 511) of the signal generation circuit, and a signal S2 output from the current detection units (22, 24, 521) of the signal generation circuit, and the average of the value obtained by subtracting signal S1 from the target value of the sum "S1+S2" and signal S2. The circuit that generates signal S2B in the second signal generation unit 62B may be an analog arithmetic circuit configured using an operational amplifier, for example, as shown in Figure 83A. When using the analog arithmetic circuit shown in Figure 83A, for example, "V(+1)" may be signal Si, "V(+2)" may be signal S2, and "V(-)" may be signal S1. The signal S2B generated in the second signal generation unit 62B is supplied to the first output unit 6 and the second output unit 7 in place of signal S2.

[0459] Furthermore, if the signal generation circuit included in the signal generation circuit 10ZV shown in Figure 81 is a single-output type, the input currents Ii1 and Ii2 can be generated by the two voltage-current conversion units 5a and 5b of the input amplifier unit 2B (Figure 43).

[0460] The signal generation circuit 10ZW in the Class AB push-pull amplifier circuit 1H shown in Figure 82 includes current-input type signal generation circuits (10, 10A~10H, 10J~10N, 10P~10Y, 10ZD~10ZH, 10ZJ, 10ZM, 10ZN) according to the above-described embodiments, a first signal generation unit 61B, and a second signal generation unit 62B. The first signal generation unit 61B and the second signal generation unit 62B are the same as those shown in Figure 81.

[0461] In the examples shown in Figures 81 and 82, the signal Si is generated by amplifying the voltage Vi output from the differential amplifier 4 with an amplifier of gain A, but it may also be generated based on any other signal proportional to the signal Si. The first signal generation unit 61B and the second signal generation unit 62B may generate signals S1B and S2B by receiving another signal proportional to signal Si, rather than inputting signal Si, and performing necessary calculations (multiplication, addition, etc.) using an analog arithmetic circuit or the like. Furthermore, the signal Si is not limited to a voltage signal; it may also be a current signal.

[0462] Next, we will describe the results of some simulations performed on the signal generation circuit according to this embodiment.

[0463] As mentioned above, the linearity error of the sum "S1B+S1B" with respect to the inputs (input current Ii, input voltage Vi, etc.) is almost zero, as shown in graphs C, D, and F of Figure 83B. Therefore, in the simulation results of the signal generation circuit according to this embodiment, graph C, which shows the linearity error of the sum "S1B + S2B" with respect to the inputs of the signal generation circuit (input current Ii, input voltage Vi), is an error-free graph as shown in Figure 83B. Similarly, for graphs D and F, where a finite resistor is connected to the output of the signal source, if the signal Si is proportional to the signal level at the signal source, the graphs are error-free as shown in Figure 83B. Below, graphs C to F for this embodiment are omitted, and only graphs A and B are shown.

[0464] [Simulation results when both signal generation methods are applied to the signal generation circuit 10 in Figure 3] Figure 84A shows the simulation results of the signal generation circuit 10 in Figure 3, reproduced for comparison, and is the same as Figures 5A, 5B, and 5F. Figure 84B shows the simulation results when the signal generation circuit 10 (Figure 3) is used in the signal generation circuit 10ZV shown in Figure 81.

[0465] The signal generation circuit 10 in Figure 3 exhibits relatively small linearity errors even without applying both signal generation methods, so there is little difference between graphs A and B. However, the F graph (Figure 5F), which shows the linearity error with respect to the signal source, eliminates the error when both signal generation methods are applied, thus confirming an improvement over the original signal generation circuit 10.

[0466] [Simulation results when both signal generation methods are applied to the signal generation circuit 10ZD in Figure 44] Figure 85A shows the simulation results of the signal generation circuit 10ZD from Figure 44, which are reproduced for comparison and are the same as those in Figures 45A, 45B, 45C, and 45D. Figure 85B shows the simulation results when a single-output type signal generation circuit 10ZD (Figure 44) is used in addition to the signal generation circuit 10ZV shown in Figure 81.

[0467] Comparing graphs A and B before applying both signal generation methods, shown in Figure 85A, with graphs A and B after applying both signal generation methods, shown in Figure 85B, the absolute value of the output current Io (vertical axis) and the temperature characteristics in the region of 0.3 mA or higher are improved by applying both signal generation methods. Furthermore, the linearity error in graphs C and D becomes almost zero with the application of both signal generation methods, indicating an improvement in performance due to improved linearity.

[0468] [Simulation results when both signal generation methods are applied to the signal generation circuit 10ZA in Figure 37] Figure 86A shows the simulation results of the signal generation circuit 10ZA from Figure 37, reproduced for comparison, and is the same as Figures 38A, 38B, 38C, and 38D. Figure 86B shows the simulation results when the voltage input type signal generation circuit 10ZA (Figure 37) is used in the signal generation circuit 10ZW shown in Figure 82.

[0469] As can be seen in Figure 86A, in the signal generation circuit 10ZA in Figure 37, the slope of the line representing the sum "Id1-Id2" clearly changes near zero of the input voltage Vi, indicating a considerably large nonlinearity error. In contrast, in the signal generation circuit 10ZW, which applies the single-signal generation method, as shown in Figure 86B, no change in the slope of the sum "Id1-Id2" is observed, and the nonlinearity error is eliminated.

[0470] Figure 87 shows an example of the configuration of a signal generation circuit according to this embodiment. Other signal generation circuits included in the signal generation circuit according to this embodiment are not limited to those that output signals S1 and S2 corresponding to the currents of diodes D1 and D2, but may be signal generation circuits of other types.

[0471] The signal generation circuit 12C shown in Figure 87 includes a signal generation circuit 11C that generates signals S1 and S2 corresponding to the input signal (input current Ii, input voltage Vi), the first signal generation unit 61B described above that generates signal S1B based on signal Si, signal S1 and signal S2, and the second signal generation unit 62B described above that generates signal S2B based on signal Si, signal S1 and signal S2. The signal generation circuit 11C generates a signal S1 that increases in the positive direction in proportion to the signal Si when the input signal (input current Ii, input voltage Vi) increases in the positive direction, and changes from the positive side towards zero when the input signal (input current Ii, input voltage Vi) increases in the negative direction. Furthermore, the signal generation circuit 11C generates a signal S2 that increases in the negative direction in proportion to the signal Si when the input signal (input current Ii, input voltage Vi) increases in the negative direction, and changes from the negative side to approach zero when the input signal (input current Ii, input voltage Vi) increases in the positive direction.

[0472] [Simulation results when both signal generation methods are applied to the signal generation circuit 11 in Figure 89] Figure 88A shows the simulation results of the signal generation circuit 110 in Figure 89, which are reproduced for comparison and are the same as those in Figures 90A, 90B, 90C, and 90D. Figure 88B shows the simulation results when the signal generation circuit 110 (Figure 89) is used instead of the signal generation circuit 11C shown in Figure 87.

[0473] The signal generation circuit 110 in Figure 89 exhibits relatively small linearity errors even without applying both signal generation methods, so there is little difference when comparing graphs A and B. However, when comparing graphs C and D, which show linearity errors, an improvement in linearity can be observed because the error is eliminated by applying both signal generation methods.

[0474] Although several embodiments of the present invention have been described above, the present invention is not limited to the examples of embodiments described above, but includes various further variations. For example, adding a part of the circuit configuration in one embodiment described above to another embodiment, or replacing it with the circuit configuration of another embodiment, may result in yet another embodiment of the present invention.

[0475] Some signal generation circuits according to the above embodiment include a constant current supply section that supplies constant current from the positive and negative sides to the diode circuit for generating the reference voltages V1 and V2 supplied to diodes D1 and D2. At least one of the constant current supply sections may be configured as a constant current circuit, or the circuit configuration may be simplified by using a resistor with a relatively high resistance value. [Explanation of Symbols]

[0476] 1, 1A~1H…Class AB push-pull amplifier circuit, 2, 2A, 2B…Input amplifier section, 3…Output amplifier section, 4…Differential amplifier, 5, 5a, 5b…Voltage-current conversion section, 6…First output section, 7…Second output section, 8…First drive section, 9…Second drive section, 10, 10A~10H, 10J~10N, 10P~10Z, 10ZA~10ZH, 10ZJ~10ZN, 10ZP~10ZW…Signal generation circuit, 11A, 11B, 11C…Signal generation circuit, 12A, 12B, 12C…Signal generation circuit, 21~24…Current detection section, 201~208…Constant current source, 30, 30A~ 30H, 30J~30N, 30P~30Y…Voltage control section, 31, 31B~31H, 31L~31N, 31P, 31R~31T…Current supply section, 32, 32E~32H, 32L~32N, 32P, 32R~32T…Diode circuit, 33…Bias voltage supply section, 34, 34G, 34H, 34J, 34N, 34P…Voltage generation section, 35, 35S, 35T…Voltage amplification section, 41, 41A~41F…First signal output section, 410, 410B…First voltage control section, 411…First current detection section, 412, 412B…First constant current supply section, 42, 42A~4 2F...Second signal output section, 420, 420B...Second voltage control section, 421...Second current detection section, 422, 422B...Second constant current supply section, 51, 51A~51F...First signal output section, 510, 510A...First voltage supply section, 511...First current detection section, 512...First constant current supply section, 513, 513B...First diode circuit, 514...Positive voltage supply section, 52, 52A~52F...Second signal output section, 520, 520A...Second voltage supply section, 521...Second current detection section, 522...Second constant current supply section, 523, 523B...Second diode circuit, 524...Negative Side voltage supply section, 61, 61B... First signal generation section, 62, 62B... Second signal generation section, D1~D14... Diodes, Dp... Positive diode, Dn... Negative diode Dn, BF1, BF1H, BF1J, BF2, BF2G, BF2J, BF3, BF4, BF5, BF6... Buffer circuits, SA, SA23, SA24... Current sensing amplifiers, SH, SH23, SH24... Shunt resistors, U23, U24... Operational amplifiers, Ni... Current input node, Nv... Voltage input node, Nx... Current output node, N1~N10... Nodes, M1~M3... Intermediate nodes

Claims

1. A signal generation circuit that generates a first signal and a second signal corresponding to the input current, A first diode to which a first voltage is applied to the anode, A second diode to which a second voltage is applied to the cathode, A current input node is provided in the current path from the cathode of the first diode to the anode of the second diode, and into which the input current flows or flows out. A voltage control unit that controls the first voltage and the second voltage, A first current detection unit that outputs the first signal which detects the first diode current flowing through the first diode, It includes a second current detection unit that outputs the second signal which detects the second diode current flowing through the second diode, The voltage control unit, When the input current is zero, the first voltage and the second voltage are controlled so that predetermined idle currents flow as the first diode current and the second diode current, respectively. When the input current flowing from the current input node to the second diode increases, the first voltage and the second voltage are controlled such that the second diode current increases and the first diode current decreases, and the difference between the second diode current and the first diode current becomes the incoming input current. When the input current flowing from the first diode to the current input node increases, the first voltage and the second voltage are controlled such that the first diode current increases and the second diode current decreases, and the difference between the first diode current and the second diode current becomes the outflowing input current. Signal generation circuit.

2. The voltage control unit, A third diode is provided in the forward direction in the current path from the third node to the first intermediate node, A fourth diode is provided in the forward direction in the current path from the first intermediate node to the fourth node, A first resistor is provided in the current path between the third node and the fourth node, It includes a constant current supply unit that supplies a constant current flowing into the third node and a constant current flowing out from the fourth node, The voltage at the first intermediate node is maintained at the reference voltage. The first voltage generated at the third node is applied to the anode of the first diode. The second voltage generated at the fourth node is applied to the cathode of the second diode. The signal generation circuit according to claim 1.

3. The voltage control unit, A third diode is provided in the forward direction in the current path from the third node to the first intermediate node, A fourth diode is provided in the forward direction in the current path from the first intermediate node to the fourth node, A first resistor is provided in the current path between the third node and the fourth node, A bias voltage supply unit generates a bias voltage that controls the voltage of the current input node to approach a reference voltage, the bias voltage which increases when the voltage of the current input node decreases relative to the reference voltage and decreases when the voltage of the current input node increases relative to the reference voltage, and supplies the generated bias voltage to any one of the third node, the first intermediate node, and the fourth node. The system includes a constant current supply unit that supplies at least one of a constant current flowing into the third node and a constant current flowing out from the fourth node, such that current flows through the third diode and the fourth diode, respectively. The first voltage generated at the third node is applied to the anode of the first diode. The second voltage generated at the fourth node is applied to the cathode of the second diode. The signal generation circuit according to claim 1.

4. The voltage control unit maintains the voltage difference between the first voltage and the second voltage when the idle current flows through the first diode and the second diode, respectively. The signal generation circuit according to claim 1.

5. The voltage control unit, A diode circuit including one or multiple diodes connected in series in the forward direction, A constant current supply unit that supplies at least one of a constant current flowing into the anode of one end of the diode in the diode circuit and a constant current flowing out from the cathode of the other end of the diode in the diode circuit, so that a current corresponding to the idle current flows through each of the diodes in the diode circuit. The diode circuit includes a voltage generation unit that generates the first voltage and the second voltage based on the voltage generated in one or more diodes included in the diode circuit, The signal generation circuit according to claim 4.

6. The diode circuit is A fifth diode is provided in the forward direction in the current path from the fifth node to the second intermediate node, The system includes a sixth diode provided in the forward direction in the current path from the second intermediate node to the sixth node, The constant current supply unit supplies at least one of the constant current flowing into the fifth node and the constant current flowing out from the sixth node. The voltage generation unit is A first buffer circuit that receives a fifth voltage generated at the fifth node and outputs a first voltage corresponding to the fifth voltage, The system includes a second buffer circuit that receives a sixth voltage generated at the sixth node and outputs a second voltage corresponding to the sixth voltage, The signal generation circuit according to claim 5.

7. The constant current supply unit supplies a constant current flowing into the fifth node and a constant current flowing out from the sixth node, respectively. The second intermediate node is held at the reference voltage. The signal generation circuit according to claim 6.

8. The voltage control unit includes a bias voltage supply unit that generates a bias voltage that controls the voltage of the current input node to approach a reference voltage, the bias voltage which increases when the voltage of the current input node decreases relative to the reference voltage and decreases when the voltage of the current input node increases relative to the reference voltage, and supplies the generated bias voltage to the anode or cathode of one of the diodes in the diode circuit. The signal generation circuit according to claim 5.

9. The first current detection unit is, A first shunt resistor is provided in the current path between the output of the first buffer circuit and the anode of the first diode, The system includes a first current detection amplifier that amplifies the voltage generated across the first shunt resistor, The second current detection unit is, A second shunt resistor is provided in the current path between the output of the second buffer circuit and the cathode of the second diode, The system includes a second current detection amplifier that amplifies the voltage generated across the second shunt resistor, The first buffer circuit outputs to the first shunt resistor a voltage which is an amplified voltage obtained by comparing the voltage at the anode of the first diode with the fifth voltage, and which increases when the anode voltage is lower than the fifth voltage and decreases when the anode voltage is higher than the fifth voltage. The second buffer circuit outputs to the second shunt resistor a voltage which is an amplified voltage obtained by comparing the cathode voltage of the second diode with the sixth voltage, and which increases when the cathode voltage is lower than the sixth voltage and decreases when the cathode voltage is higher than the sixth voltage. The signal generation circuit according to claim 6.

10. A signal generation circuit that generates a first signal and a second signal corresponding to the input current, A first diode in which a first voltage is applied to the anode and the cathode is held at a reference voltage, A second diode in which the anode is held at the reference voltage and the second voltage is applied to the cathode, The current input node through which the input current flows in or out, A voltage control unit that controls the first voltage and the second voltage, A first current detection unit that outputs the first signal which detects the first diode current flowing through the first diode, It includes a second current detection unit that outputs the second signal which detects the second diode current flowing through the second diode, The voltage control unit, When the input current is zero, the first voltage and the second voltage are controlled so that predetermined idle currents flow as the first diode current and the second diode current, respectively. When the input current flowing in the first direction at the current input node increases, the second diode current increases and the first diode current decreases, and the first and second voltages are controlled such that the difference between the second diode current and the first diode current is a current proportional to the input current flowing in the first direction. When the input current flowing in a second direction opposite to the first direction at the current input node increases, the first diode current increases and the second diode current decreases, and the first and second voltages are controlled such that the difference between the first diode current and the second diode current is a current proportional to the input current flowing in the second direction. Signal generation circuit.

11. The voltage control unit, A seventh diode is provided in the forward direction in the current path from the seventh node to the current input node, An eighth diode is provided in the forward direction in the current path from the current input node to the eighth node, A second resistor is provided in the current path between the seventh node and the eighth node, It includes a constant current supply unit that supplies a constant current flowing into the seventh node and a constant current flowing out from the eighth node, The first voltage generated at the seventh node is applied to the anode of the first diode. The second voltage generated at the eighth node is applied to the cathode of the second diode. The signal generation circuit according to claim 10.

12. The voltage control unit, A diode circuit comprising one or a plurality of diodes connected in forward series, wherein the anode or cathode of one of the diodes is held at the reference voltage, A constant current supply unit that supplies at least one of a constant current flowing into the anode of one end of the diode in the diode circuit and a constant current flowing out from the cathode of the other end of the diode in the diode circuit, so that a current corresponding to the idle current flows through each of the diodes in the diode circuit. A voltage amplification unit that generates a first amplified voltage which is a positive voltage with respect to the reference voltage and a second amplified voltage which is a negative voltage with respect to the reference voltage by amplifying the voltage generated in one or more diodes included in the diode circuit, A first voltage divider resistor is provided in the current path between the output of the voltage amplifier that generates the first amplified voltage and the anode of the first diode, A second voltage divider resistor is provided in the current path between the anode of the first diode and the current input node, A third voltage divider resistor is provided in the current path between the output of the voltage amplifier section where the second amplified voltage is generated and the cathode of the second diode, The system includes a fourth voltage divider resistor provided in the current path between the cathode of the second diode and the current input node, The signal generation circuit according to claim 10.

13. The diode circuit is A ninth diode is provided in the forward direction in the current path from the ninth node to the third intermediate node, The system includes a tenth diode provided in the forward direction in the current path from the third intermediate node to the tenth node, The constant current supply unit supplies a constant current flowing into the 9th node and a constant current flowing out from the 10th node. The third intermediate node is held at the reference voltage, The aforementioned voltage amplification unit is The first amplified voltage is generated by amplifying the voltage generated at the ninth node. The second amplified voltage is generated by amplifying the voltage generated at the tenth node. The signal generation circuit according to claim 12.

14. The diode circuit is In the current path from the ninth node to the third intermediate node, a third resistor is provided in series with the ninth diode, The current path from the third intermediate node to the tenth node includes a fourth resistor connected in series with the tenth diode, The signal generation circuit according to claim 13.

15. The voltage control unit, A diode circuit including one or multiple diodes connected in series in the forward direction, A constant current supply unit that supplies at least one of a constant current flowing into the anode of one end of the diode in the diode circuit and a constant current flowing out from the cathode of the other end of the diode in the diode circuit, so that a current corresponding to the idle current flows through each of the diodes in the diode circuit. A voltage generation unit that generates the first voltage and the second voltage based on the voltage generated in one or more diodes included in the diode circuit, The first voltage is applied to the anode of the 11th diode, and the cathode is connected to the current input node, The second voltage is applied to the cathode of the 12th diode, and the anode is connected to the current input node. A bias voltage supply unit that generates a bias voltage that controls the voltage of the current input node to approach the reference voltage, the bias voltage which increases when the voltage of the current input node decreases relative to the reference voltage and decreases when the voltage of the current input node increases relative to the reference voltage, and supplies the generated bias voltage to the anode or cathode of one of the diodes in the diode circuit, The signal generation circuit according to claim 10.

16. The first current detection unit is, A first operational amplifier that amplifies the difference between the cathode voltage of the first diode and the reference voltage, wherein the output voltage increases when the cathode voltage of the first diode decreases relative to the reference voltage, and decreases when the cathode voltage of the first diode increases relative to the reference voltage, This includes a first negative feedback resistor provided in the current path between the cathode of the first diode and the output of the first operational amplifier, The second current detection unit is, A second operational amplifier that amplifies the difference between the voltage at the anode of the second diode and the reference voltage, wherein the output voltage increases when the voltage at the anode of the second diode decreases relative to the reference voltage, and decreases when the voltage at the anode of the second diode increases relative to the reference voltage, The system includes a second negative feedback resistor provided in the current path between the anode of the second diode and the output of the second operational amplifier, The signal generation circuit according to claim 10.

17. The voltage control unit, A positive voltage supply unit is provided in series with the third diode in the current path between the third node and the first intermediate node, The current path between the first intermediate node and the fourth node includes a negative voltage supply unit provided in series with the fourth diode, The positive voltage supply unit supplies a voltage that increases the forward voltage of the third diode. The negative voltage supply unit supplies a voltage that increases the forward voltage of the fourth diode. The signal generation circuit according to claim 2.

18. The voltage control unit, A positive voltage supply unit is provided in series with the seventh diode in the current path between the seventh node and the current input node, The current path between the current input node and the eighth node includes a negative voltage supply unit provided in series with the eighth diode, The positive voltage supply unit supplies a voltage that increases the forward voltage of the seventh diode. The negative voltage supply unit supplies a voltage that increases the forward voltage of the eighth diode. The signal generation circuit according to claim 11.

19. A signal generation circuit that generates a first signal and a second signal corresponding to the input voltage, A first signal output unit that outputs the first signal, It has a second signal output unit that outputs the second signal, The first signal output unit is, A first diode is provided in the forward direction in the current path from a first voltage node to which a first voltage is applied, to a reference voltage node held at a reference voltage, A positive first resistor is provided in series with the first diode in the current path from the first voltage node to the reference voltage node, A first voltage control unit for controlling the first voltage, The system includes a first current detection unit that outputs a first signal which detects the first diode current flowing through the first diode, The second signal output section is, A second diode is provided in the forward direction in the current path flowing from the reference voltage node to the second voltage node to which the second voltage is applied, A negative first resistor is provided in series with the second diode in the current path from the reference voltage node to the second voltage node, A second voltage control unit for controlling the second voltage, The system includes a second current detection unit that outputs a second signal which detects the second diode current flowing through the second diode, The first voltage control unit is When the input voltage is zero, the first voltage is controlled so that a predetermined idle current flows as the first diode current. When the input voltage increases in the positive direction, the first voltage is controlled so that the first diode current increases in proportion to the input voltage. When the input voltage increases in the negative direction, the first voltage is controlled so that the first diode current decreases and approaches zero. The second voltage control unit is When the input voltage is zero, the second voltage is controlled so that the idle current flows as the second diode current. When the input voltage increases in the positive direction, the second voltage is controlled so that the second diode current decreases and approaches zero. When the input voltage increases in the negative direction, the second voltage is controlled so that the second diode current increases in proportion to the input voltage. Signal generation circuit.

20. The first voltage control unit is A 13th diode is provided in the forward direction in the current path from the 13th node to the voltage input node to which the input voltage is input, It includes a first constant current supply unit that supplies a constant current flowing into the 13th node, The second voltage control unit is A 14th diode is provided in the forward direction in the current path flowing from the voltage input node to the 14th node, It includes a second constant current supply unit that supplies a constant current flowing out from the 14th node, The 13th node is connected to the first voltage node, The 14th node is connected to the second voltage node. The signal generation circuit according to claim 19.

21. The first voltage control unit is A 13th diode is provided in the forward direction in the current path flowing from the 13th node to the voltage input node, A first constant current supply unit that supplies a constant current flowing into the 13th node, The circuit includes a third buffer circuit that receives a voltage generated at the 13th node and outputs the first voltage corresponding to the input voltage, The second voltage control unit is A 14th diode is provided in the forward direction in the current path flowing from the voltage input node to the 14th node, A second constant current supply unit that supplies a constant current flowing out from the 14th node, The circuit includes a fourth buffer circuit that receives a voltage generated at the 14th node and outputs a second voltage corresponding to the input voltage, The signal generation circuit according to claim 19.

22. The positive-side first resistor is provided in the current path between the cathode of the first diode and the reference voltage node. The first current detection unit outputs the first signal corresponding to the voltage generated in the positive first resistor. The negative first resistor is provided in the current path between the reference voltage node and the anode of the second diode. The second current detection unit outputs the second signal corresponding to the voltage generated in the negative first resistor. The signal generation circuit according to claim 20 or claim 21.

23. The first voltage control unit includes a fifth resistor provided in parallel with the current path between the first voltage node and the voltage input node. The second voltage control unit includes a sixth resistor provided in parallel with the current path between the second voltage node and the voltage input node. The signal generation circuit according to claim 20.

24. The first voltage control unit includes a positive voltage supply unit provided in series with the 13th diode in the current path between the 13th node and the voltage input node. The second voltage control unit includes a negative voltage supply unit provided in series with the 14th diode in the current path between the voltage input node and the 14th node. The positive voltage supply unit supplies a voltage that increases the forward voltage of the 13th diode. The negative voltage supply unit supplies a voltage that increases the forward voltage of the 14th diode. The signal generation circuit according to claim 20 or claim 21.

25. A signal generation circuit that generates a first signal and a second signal corresponding to the input current, A first signal output unit that outputs the first signal, It has a second signal output unit that outputs the second signal, The first signal output unit is, A first diode is provided in the forward direction in the current path from a first voltage node to which a first voltage is applied, to a reference voltage node held at a reference voltage, A positive diode is provided in the forward direction in the current path from the first voltage node to the anode of the first diode, A first current input node is provided in the current path from the cathode of the positive diode to the anode of the first diode, through which the first input current flows in or out. A first current detection unit that outputs the first signal which detects the first diode current flowing through the first diode, The system includes a first voltage supply unit that supplies a first voltage to the first voltage node, which is set to allow a predetermined idle current to flow as the first diode current when the first input current is zero. The second signal output section is, A second diode is provided in the forward direction in the current path flowing from the reference voltage node to the second voltage node to which the second voltage is applied, A negative diode is provided in the forward direction in the current path from the cathode of the second diode to the second voltage node, A second current input node is provided in the current path from the cathode of the second diode to the anode of the negative diode, through which the second input current flows in or out. A second current detection unit that outputs the second signal which detects the second diode current flowing through the second diode, The system includes a second voltage supply unit that, when the second input current is zero, supplies the second voltage to the second voltage node, which is set to flow as the second diode current, such that the idle current flows through it. When the first input current flows into the first current input node, the second input current flows into the second current input node, When the first input current flows out from the first current input node, the second input current flows out from the second current input node. Signal generation circuit.

26. The first voltage supply unit is, A first diode circuit comprising one or a plurality of diodes connected in series in the forward direction, wherein current flows from the cathode of one end of the diode to the reference voltage node, and generates a voltage corresponding to the first voltage at the anode of the other end of the diode, The circuit includes a first constant current supply unit that supplies a constant current to flow into the anode of the other end diode in the first diode circuit so that a current corresponding to the idle current flows through each of the diodes in the first diode circuit, The second voltage supply unit is, A second diode circuit comprising one or a plurality of diodes connected in series in the forward direction, wherein current flows from the reference voltage node to the anode of the diode at one end, and generates a voltage corresponding to the second voltage at the cathode of the diode at the other end, The system includes a second constant current supply unit that supplies a constant current flowing out from the cathode of the other end of the diode in the second diode circuit so that a current corresponding to the idle current flows through each of the diodes in the second diode circuit, The signal generation circuit according to claim 25.

27. The first signal output unit includes a positive second resistor provided in parallel with the current path flowing from the first voltage node to the reference voltage node. The second signal output section includes a negative second resistor provided in parallel with the current path flowing from the reference voltage node to the second voltage node. The signal generation circuit according to claim 26.

28. The first voltage supply unit includes a positive third resistor provided in the current path between the anode of the other end of the diode in the first diode circuit and the positive power supply voltage, instead of the first constant current supply unit. The second voltage supply unit, in place of the second constant current supply unit, includes a negative third resistor provided in the current path between the cathode of the other end of the diode in the second diode circuit and the negative power supply voltage. The signal generation circuit according to claim 26.

29. The first signal output section includes, instead of the positive diode, a positive first resistor provided in the current path from the first voltage node to the anode of the first diode. The second signal output section includes, instead of the negative diode, a negative first resistor provided in the current path from the cathode of the second diode to the second voltage node. The signal generation circuit according to claim 26.

30. The first signal output unit includes a positive second resistor provided in parallel with the current path flowing from the first voltage node to the reference voltage node. The second signal output section includes a negative second resistor provided in parallel with the current path flowing from the reference voltage node to the second voltage node. The signal generation circuit according to claim 29.

31. The first voltage supply unit includes a fifth buffer circuit that receives the voltage generated in the first diode circuit and outputs the first voltage corresponding to the input voltage. The second voltage supply unit includes a sixth buffer circuit that receives the voltage generated in the second diode circuit and outputs the second voltage corresponding to the input voltage. The signal generation circuit according to claim 26.

32. The first signal output section includes, instead of the positive diode, a positive first resistor provided in the current path from the first voltage node to the anode of the first diode. The second signal output section includes, instead of the negative diode, a negative first resistor provided in the current path from the cathode of the second diode to the second voltage node. The signal generation circuit according to claim 31.

33. The first diode circuit includes a positive voltage supply unit provided in series with one or more diodes included in the first diode circuit. The positive voltage supply unit supplies a voltage that increases the forward voltage of each diode in the first diode circuit. The second diode circuit includes a negative voltage supply unit provided in series with one or more diodes included in the second diode circuit. The negative voltage supply unit supplies a voltage that increases the forward voltage of each diode in the second diode circuit. The signal generation circuit according to claim 26.

34. Having a first signal generation unit or a second signal generation unit, The first signal generation unit generates a first signal based on an input signal proportional to the input current, which corresponds to a target value of the sum of the first signal and the second signal, and the second signal output from the second current detection unit, and the value obtained by subtracting the second signal from the target value. The second signal generation unit generates a signal as the second signal based on the input signal and the first signal output from the first current detection unit, corresponding to a value obtained by subtracting the first signal from the target value. A signal generating circuit according to any one of claims 1 to 18.

35. The system has either a first signal generation unit instead of the first signal output unit, or a second signal generation unit instead of the second signal output unit. The first signal generation unit generates a first signal based on an input signal proportional to the input voltage, which corresponds to a target value of the sum of the first signal and the second signal, and the second signal output from the second current detection unit, and the value obtained by subtracting the second signal from the target value. The second signal generation unit generates a signal as the second signal based on the input signal and the first signal output from the first current detection unit, corresponding to a value obtained by subtracting the first signal from the target value. A signal generating circuit according to any one of claims 19 to 21.

36. The system has either a first signal generation unit instead of the first signal output unit, or a second signal generation unit instead of the second signal output unit. The first signal generation unit generates a first signal based on an input signal proportional to the first input current and the second input current, which corresponds to a target value of the sum of the first signal and the second signal, and the second signal output from the second current detection unit, and the value obtained by subtracting the second signal from the target value. The second signal generation unit generates a signal as the second signal based on the input signal and the first signal output from the first current detection unit, corresponding to a value obtained by subtracting the first signal from the target value. A signal generating circuit according to any one of claims 25 to 33.

37. A first signal generation unit generates a corrected first signal based on an input signal proportional to the input current, corresponding to a target value of the sum of the first signal and the second signal, the first signal output from the first current detection unit, and the second signal output from the second current detection unit, the first signal corresponding to the average of the value obtained by subtracting the second signal from the target value and the first signal. The system includes a second signal generation unit that generates a corrected second signal based on the input signal, the first signal output from the first current detection unit, and the second signal output from the second current detection unit, by averaging the value obtained by subtracting the first signal from the target value and the second signal. A signal generating circuit according to any one of claims 1 to 18.

38. A first signal generation unit generates a corrected first signal based on an input signal proportional to the input voltage, corresponding to a target value of the sum of the first signal and the second signal, the first signal output from the first current detection unit, and the second signal output from the second current detection unit, the first signal corresponding to the average of the value obtained by subtracting the second signal from the target value and the first signal. The system includes a second signal generation unit that generates a corrected second signal based on the input signal, the first signal output from the first current detection unit, and the second signal output from the second current detection unit, by averaging the value obtained by subtracting the first signal from the target value and the second signal. A signal generating circuit according to any one of claims 19 to 21.

39. A first signal generation unit generates a corrected first signal based on an input signal proportional to the first input current and the second input current, corresponding to a target value of the sum of the first signal and the second signal, the first signal output from the first current detection unit, and the second signal output from the second current detection unit, and the average of the value obtained by subtracting the second signal from the target value and the first signal. The system includes a second signal generation unit that generates a corrected second signal based on the input signal, the first signal output from the first current detection unit, and the second signal output from the second current detection unit, by averaging the value obtained by subtracting the first signal from the target value and the second signal. A signal generating circuit according to any one of claims 25 to 33.

40. The first current detection unit outputs a first signal indicating a current that is larger by a predetermined first offset current compared to the first diode current. The second current detection unit outputs the second signal, which indicates a current that is larger than the second diode current by a predetermined second offset current. A signal generating circuit according to any one of claims 1 to 21 or 25 to 33.

41. This is a Class AB push-pull amplifier circuit, A signal generation circuit according to any one of claims 1 to 21 or 25 to 33, A current output node into which output current flows or out, A first output unit generates a current corresponding to one of the first signal and the second signal of the signal generation circuit and discharges it from the current output node, The signal generation circuit has a second output unit that generates a current corresponding to the other of the first signal and the second signal and flows it into the current output node. Class AB push-pull amplifier circuit.

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