Semiconductor equipment

Abstract

To provide a semiconductor device that can accurately compensate for leakage current of elements that changes with temperature. [Solution] The semiconductor device 1 includes a current generation circuit 20 that generates a charging current to be supplied to a capacitor 5 connected to a connection terminal CD, and a compensation current generation circuit 50 that generates a compensation current to compensate for leakage current from an element to be compensated, one end of which is connected to a path P1 formed between the output terminal of the current generation circuit 20 and the connection terminal CD, and a current compensation circuit 30 that supplies the generated compensation current to the connection point with path P1.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] It is disclosed that a delay time is set by an externally connected capacitor by externally connecting the capacitor to an external terminal of a semiconductor device (for example, refer to Patent Document 1).

Related Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problem to be Solved by the Invention

[0004] However, in the case where a capacitor is externally connected to the external terminal of such a conventional semiconductor device and the delay time is set by the capacitor, the accuracy of the delay time setting varies depending on the operating temperature environment. This is because a temperature change causes an increase or decrease in leak current from elements including the ESD protection element connected to the charging current path, which adversely affects the charging amount of the capacitor.

[0005] The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a semiconductor device capable of accurately compensating for the leak current of an element that varies depending on the temperature environment.

Means for Solving the Problem

[0006] To solve the above-mentioned problems, a semiconductor device according to an embodiment of the present invention is characterized by comprising: a current generation circuit that generates a charging current to be supplied to a capacitor connected to a connection terminal; a compensation current generation circuit that generates a compensation current to compensate for leakage current from an element to be compensated, one end of which is connected to a path formed between the output terminal of the current generation circuit and the connection terminal; and a current compensation circuit that supplies the compensation current to the connection point with the path. [Effects of the Invention]

[0007] According to the present invention, the leakage current of an element, which changes depending on the temperature environment, can be accurately compensated. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic diagram showing an example configuration of a semiconductor device according to this embodiment. [Figure 2] This is a schematic diagram showing a first configuration example of the compensation current generation circuit of the semiconductor device according to this embodiment. [Figure 3] This is a schematic diagram showing a second configuration example of the compensation current generation circuit of the semiconductor device according to this embodiment. [Figure 4] This is a schematic diagram showing a third configuration example of the compensation current generation circuit of the semiconductor device according to this embodiment. [Figure 5] This is a schematic diagram showing a fourth configuration example of the compensation current generation circuit of the semiconductor device according to this embodiment. [Modes for carrying out the invention]

[0009] Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

[0010] Figure 1 is a schematic diagram showing an example configuration of a semiconductor device 1, which is an example of a semiconductor device according to this embodiment. Figure 2 is a schematic diagram showing the configuration of a compensation current generation circuit 50, which is a first example configuration of a compensation current generation circuit for a semiconductor device according to this embodiment.

[0011] The semiconductor device 1 includes, for example, a current generation circuit 20 that generates a charging current, and a current compensation circuit 30 that generates a compensation current, which has a compensation current generation circuit 50. The current generation circuit 20 and the current compensation circuit 30 constitute a delay circuit 10 that supplies the charging current. The semiconductor device 1 has terminals for connecting to the outside, including a VDD terminal 3, a GND terminal 4, a sense terminal SE, a reset terminal RO, and a connection terminal CD. The semiconductor device 1 also includes a voltage divider circuit 13, a reference voltage source 14, and a comparator 15 on the input terminal 11 side of the delay circuit 10, and a comparator 16, a reference voltage source 17, and an NMOS transistor 19 which is an output transistor on the output terminal 12 side of the delay circuit 10.

[0012] Terminal VDD 3 is a power supply terminal that receives the power supply voltage VDD. Terminal GND 4 is a power supply terminal that receives the ground voltage, which is an example of a power supply voltage different from the power supply voltage VDD. Connection terminal CD is grounded via capacitor 5. Sense terminal SE is connected to an externally located voltage monitoring device. Reset terminal RO is connected to a pull-up resistor (not shown in the diagram) and also to the drain of NMOS transistor 19.

[0013] The voltage divider circuit 13 is a resistor voltage divider circuit configured by connecting multiple resistors, such as two, in series, and has a first terminal connected to the sense terminal SE, a second terminal connected to the GND terminal 4, and an output terminal which is the connection point between the resistors constituting the voltage divider circuit 13 and where the divided voltage appears. The comparator 15 has an inverting input terminal (-) connected to the output terminal of the voltage divider circuit 13, a non-inverting input terminal (+) connected to the first terminal of the reference voltage source 14, and an output terminal connected to the input terminal 11 of the delay circuit 10. The second terminal of the reference voltage source 14 is connected to the GND terminal 4.

[0014] The comparator 16 has an inverting input terminal (-) connected to the output terminal 12 of the delay circuit 10, a non-inverting input terminal (+) connected to the output terminal of the reference voltage source 17, and an output terminal connected to the gate of the NMOS transistor 19. The second terminal of the reference voltage source 17 is connected to the GND terminal 4. The source and back gate of the NMOS transistor 19 are connected to the GND terminal 4.

[0015] The current generation circuit 20 includes a current source 21 which includes a first terminal connected to the VDD terminal 3, a second terminal, and a control terminal connected to the input terminal 11 of the delay circuit 10, and an NMOS transistor 22 which includes a drain connected to the second terminal of the current source 21, a gate connected to the input terminal 11, and a source and back gate connected to the GND terminal 4. Node N1, which is the connection point between the second terminal of the current source 21 and the drain of the NMOS transistor 22, corresponds to the output terminal of the current generation circuit 20.

[0016] The current compensation circuit 30 includes a compensation current generation circuit 50 that generates a compensation current to compensate for the leakage current from the ESD protection element 35 and the NMOS transistor 22, which are elements to be compensated, connected to the path P1 formed between node N1 and connection terminal CD. The compensation current generation circuit 50 has k current compensation transistors 51_1, ..., 51_k connected in parallel between a first terminal corresponding to node N2 in the current compensation circuit 30 and a second terminal connected to the GND terminal 4, for example as shown in Figures 1 and 2. Here, k is a natural number greater than or equal to 2, i.e., multiple.

[0017] The current compensation transistors 51_1, ..., 51_k are composed of transistors with the same threshold voltage and smaller area than the MOS transistors that make up the ESD protection element 35, and the overall area is smaller than that of the NMOS transistors that make up the ESD protection element 35. In addition, each drain of the current compensation transistors 51_1, ..., 51_k is connected to node N2 via k switches 52_1, ..., 52_k which act as switching elements.

[0018] The current compensation circuit 30 further includes a current mirror circuit having a PMOS transistor 31 and a PMOS transistor 32, which duplicates and folds back the compensation current passed by the compensation current generation circuit 50 at a mirror ratio of 1:n (n>1). At least one of the PMOS transistor 31 and the PMOS transistor 32 is configured to allow fine adjustment of the mirror ratio 1:n. That is, the current mirror circuit in the current compensation circuit 30 is configured with a fine adjustment range of ±α (0<α<1) based on its mirror ratio 1:n.

[0019] The sources and back gates of the PMOS transistor 31 and the PMOS transistor 32 are each connected to the VDD terminal 3. The gate and drain of the PMOS transistor 31 on the input side constituting the current mirror circuit are connected to the first end of the compensation current generation circuit 50. The connection point between the gate and drain of the PMOS transistor 31 and the compensation current generation circuit 50 (more specifically, the first end) is a node N2.

[0020] The gate of the PMOS transistor 32 on the output side constituting the current mirror circuit is connected to the gate and drain of the PMOS transistor 31. The drain of the PMOS transistor 32 is connected to a path P1. The path P1 is connected to a node N1, the drain of an NMOS transistor that is the ESD protection element 35, the output terminal 12, and the connection terminal CD.

[0021] Next, the operation of the semiconductor device 1 will be described. The semiconductor device 1 monitors the voltage of the voltage monitoring target by monitoring the voltage of the sense terminal SE connected to the voltage monitoring target. The comparator 15 compares the divided voltage of the voltage dividing circuit 13 with the reference voltage supplied from the reference voltage source 14. When the divided voltage is equal to or lower than the reference voltage supplied from the reference voltage source 14, a signal of high level (hereinafter referred to as "H level") is output, and when the divided voltage is higher than the reference voltage, a signal of low level (hereinafter referred to as "L level") is output.

[0022] The current generation circuit 20 outputs or stops outputting a charging current from node N1 depending on the signal level of the signal input to the input terminal. The current source 21 and the NMOS transistor 22 operate exclusively. Specifically, when the voltage level of the signal input to the input terminal 11 of the delay circuit 10, which corresponds to the input terminal of the current generation circuit 20, is high, the current source 21 is in an off state, stopping the supply of charging current, while the NMOS transistor 22 is in an on state. On the other hand, when the voltage level of the signal input to the input terminal 11 is low, the current source 21 is in an on state, supplying charging current from node N1 to path P1, while the NMOS transistor 22 is in an off state.

[0023] The current compensation circuit 30 compensates for the leakage current leaking from the transistor, which is connected to path P1 at one end and to the GND terminal 4 at the other end, by supplying a compensation current based on the current flowing through the compensation current generation circuit 50 to path P1. The magnitude of the compensation current is adjusted by the connection relationship between the current compensation transistors 51_1, ..., 51_k and node N2, and the Miller ratio of the current mirror circuit, which controls the magnitude of the current flowing through the compensation current generation circuit 50. In the compensation current generation circuit 50, the current flowing through the compensation current generation circuit 50, and thus the compensation current, is finely adjusted by individually switching between the closed state (on state) and the open state (off state) of the k switches 52_1, ..., 52_k. Furthermore, the compensation current is finely adjusted by fine-tuning the Miller ratio of the current mirror circuit.

[0024] Here, the leakage current flowing through the ESD protection element 35, which is the main element to be compensated, is denoted as IL35, and the currents flowing through the current compensation transistors 51_1, ..., 51_k are denoted as I11, ..., I1k, respectively. The compensation current generation circuit 50 is given by the following equation (1-1) IL35=(n±α)·(I11+…+I1k) ---(1-1) It is configured such that the following holds true. Here, n±α represents the finely adjustable Miller ratio.

[0025] When the divided voltage is less than or equal to the reference voltage supplied from the reference voltage source 14, the current source 21 turns off and the NMOS transistor 22 turns on in response to the signal from the comparator 15. The output terminal 12 of the delay circuit 10, which is at the same node as the output terminal of the current generation circuit 20, becomes the voltage of the GND terminal 4, i.e., L level. Since the voltage of the output terminal 12 supplied to the inverting input terminal (-) of the comparator 16 is lower than the reference voltage supplied from the reference voltage source 17 supplied to the non-inverting input terminal (+) of the comparator 16, the comparator 16 supplies an output signal with a signal voltage of H level to the gate of the NMOS transistor 19.

[0026] Since the NMOS transistor 19 turns on when it receives a high-level voltage at its gate, the reset terminal RO becomes the voltage at the GND terminal 4, i.e., low level. Therefore, if the divided voltage is less than or equal to the reference voltage supplied from the reference voltage source 14, no delay time is generated, and the reset signal is low level.

[0027] When the divided voltage exceeds the reference voltage supplied from the reference voltage source 14, the current source 21 turns ON and the NMOS transistor 22 turns OFF in response to a signal from the comparator 15. That is, the current generation circuit 20 starts supplying charging current and starts charging the capacitor 5 connected to connection terminal CD. In the semiconductor device 1, the charging current supplied to the capacitor 5 is a current that has been compensated by the current compensation circuit 30 for leakage current leaking from the charging path P1. As the charging of the capacitor 5 progresses, the voltage at connection terminal CD also rises.

[0028] When the voltage at connection terminal CD exceeds the reference voltage supplied from reference voltage source 17, the output signal from comparator 16 transitions from a high level to a low level, causing the NMOS transistor 19 to transition from on to off. As a result of the NMOS transistor 19 being turned off, the voltage at reset terminal RO transitions from a low level to a high level. Therefore, if the divided voltage exceeds the reference voltage supplied from reference voltage source 14, a delay time is generated, and after the delay time has elapsed, the reset signal transitions from a low level to a high level.

[0029] As described above, semiconductor device 1 has multiple transistors connected in parallel and compensation current generation circuits 50, 50A, 50B, and 50C that can switch the number of transistors connected in parallel, so that leakage current of elements that changes depending on the temperature environment can be accurately compensated. Furthermore, the current mirror circuit of the compensation current generation circuits 50, 50A, 50B, and 50C can also have its mirror ratio finely adjusted, so fine adjustments can be made to take into account, for example, the leakage current that occurs when the NMOS transistor 22 is off.

[0030] According to the semiconductor device 1, since the semiconductor device 1 is equipped with a compensation current generation circuit 50 that is smaller in area than the ESD protection element 35, the compensation current generation circuit 50 can be configured in a smaller area than conventional devices. Furthermore, the type of element to be compensated is not limited to the ESD protection element 35, but can be supplied to a variety of elements by adjusting the magnitude of the compensation current.

[0031] It should be noted that the present invention is not limited to the embodiments described above, and in practice, it can be implemented in various forms other than those described above, and various omissions, additions, substitutions, or modifications can be made without departing from the spirit of the invention. For example, the semiconductor device 1 may be equipped with compensation current generation circuits 50A, 50B, or 50C (see Figures 3 to 5 described later) instead of the compensation current generation circuit 50.

[0032] Figure 3 is a schematic diagram showing the configuration of a compensation current generation circuit 50A, which is a second configuration example of the compensation current generation circuit for the semiconductor device according to this embodiment. Figure 4 is a schematic diagram showing the configuration of a compensation current generation circuit 50B, which is a third configuration example of the compensation current generation circuit for the semiconductor device according to this embodiment. Figure 5 is a schematic diagram showing the configuration of a compensation current generation circuit 50C, which is a third configuration example of the compensation current generation circuit for the semiconductor device according to this embodiment.

[0033] The compensation current generation circuit 50A differs from the compensation current generation circuit 50 in that it has current compensation transistors 53_1, ..., 53_k instead of current compensation transistors 51_1, ..., 51_k, but otherwise it is substantially the same. The threshold voltages of the current compensation transistors 53_1, ..., 53_k are configured to be lower than the threshold voltages of the current compensation transistors 51_1, ..., 51_k, i.e., the threshold voltages of the NMOS transistors which are ESD protection elements 35.

[0034] The compensation current generation circuit 50B differs from the compensation current generation circuit 50 in that it has current compensation transistors 55_1, ..., 55_k instead of current compensation transistors 51_1, ..., 51_k, but otherwise it is substantially the same. Each of the current compensation transistors 55_1, ..., 55_k has a variable voltage source connected to its source and back gate to set a desired potential difference.

[0035] The compensation current generation circuit 50C differs from the compensation current generation circuit 50A in that it has current compensation transistors 57_1, ..., 57_k instead of current compensation transistors 53_1, ..., 53_k, but otherwise it is substantially the same. Each of the current compensation transistors 57_1, ..., 57_k has a variable voltage source connected between its source and back gate relative to the current compensation transistors 53_1, ..., 53_k. Therefore, it is possible to configure current compensation transistors 57_1, ..., 57_k with a threshold voltage even lower than that of current compensation transistors 55_1, ..., 55_k when the voltage of the variable voltage source is the same.

[0036] Furthermore, the compensation current generation circuits 50A to 50C are configured in the same way as the compensation current generation circuit 50, so that a relationship with the leakage current IL35 is established. Here, if the currents flowing through the current compensation transistors 53_1, ..., 53_k are I31, ..., I3k, respectively, then the compensation current generation circuit 50A is given by the following equation (1-2) obtained by replacing I11, ..., I1k with I31, ..., I3k in the above equation (1-1). IL35=(n±α)·(I31+…+I3k) ---(1-2) It is configured to satisfy the following condition.

[0037] The compensation current generation circuits 50B and 50C are the same as those of the compensation current generation circuit 50 or 50A. That is, if the currents flowing through the current compensation transistors 55_1, ..., 55_k are I51, ..., I5k, and the currents flowing through the current compensation transistors 57_1, ..., 57_k are I71, ..., I7k, then the compensation current generation circuits 50B and 50C are given by the following equations (1-3) and (1-4), respectively. IL35=(n±α)·(I51+…+I5k) ---(1-3) IL35=(n±α)·(I71+…+I7k) ---(1-4) It is structured in such a way that the following holds true.

[0038] In this embodiment, an example was described in which a variable voltage source is connected between the source and back gate of the current compensation transistors 55_1, ..., 55_k and 57_1, ..., 57_k, but the embodiment is not limited to this example. The variable voltage source may be a constant voltage source that supplies a constant voltage. In other words, the voltage source connected between the source and back gate of the current compensation transistors 55_1, ..., 55_k and 57_1, ..., 57_k does not have a voltage adjustment function.

[0039] Furthermore, although this embodiment describes an example in which the switching elements are switches 52_1, ..., 52_k, at least a portion of the switches 52_1, ..., 52_k may be fuses.

[0040] Furthermore, in this embodiment, the current compensation transistors 51_1, ..., 51_k, 53_1, ..., 53_k, 55_1, ..., 55_k and 57_1, ..., 57_k may have different individual drain currents, as long as the sum of their drain currents is the same. Also, the drain current ratio of current compensation transistors 51_1, 53_1, 55_1 and 57_1 and the other current compensation transistors 51_2, ..., 51_k, 53_2, ..., 53_k, 55_2, ..., 55_k and 57_2, ..., 55_k is set to a multiplier of 1:2, 2 k The current value may be configured to be adjustable in stages.

[0041] These embodiments and their variations are included within the scope and essence of the invention, as well as within the scope of the invention and its equivalents as described in the claims. [Explanation of Symbols]

[0042] 1 Semiconductor device 5 Capacitors 20 Current generation circuit 22 NMOS transistors (comparable elements) 30 Current compensation circuit 35 ESD protection elements (compensated elements) 50,50A,50B,50C compensation current generation circuit 51_1, ..., 51_k Current Compensation Transistors 52_1, ..., 52_k Switches (switching elements) 53_1, ..., 53_k Current Compensation Transistor 55_1, ..., 55_k Current Compensation Transistors 57_1, ..., 57_k Current Compensation Transistors CD connection terminal N1 is the output terminal of the current generation circuit. P1 Route

Claims

1. A current generation circuit that generates a charging current to supply to a capacitor connected to a connection terminal, A current compensation circuit has a compensation current generation circuit that generates a compensation current to compensate for leakage current from an element to be compensated, one end of which is connected to a path formed between the output terminal of the current generation circuit and the connection terminal, and supplies the compensation current to the connection point with the path, A semiconductor device characterized by comprising the following features.

2. The compensation current generation circuit has a plurality of k transistors connected in parallel between the first terminal and the second terminal. It is configured to have a smaller area than the aforementioned compensated element. The semiconductor device according to claim 1.

3. The transistor has a threshold voltage that is less than or equal to the threshold voltage of the compensated element. The semiconductor device according to claim 2.

4. The transistor has a threshold voltage lower than the threshold voltage of the compensated element. The semiconductor device according to claim 2.

5. The aforementioned transistor has a potential difference between its back gate and its source. The semiconductor device according to claim 2.

6. The semiconductor device according to claim 5, wherein the transistor has a constant voltage source including a positive electrode connected to its own back gate and a negative electrode connected to its own source.

7. The semiconductor device according to claim 5, wherein the transistor has a variable voltage source including a positive electrode connected to its own back gate and a negative electrode connected to its own source.

8. The transistor has its back gate and its source connected. The semiconductor device according to claim 2.

9. The compensation current generation circuit has a plurality of k transistors connected in parallel between the first terminal and the second terminal. The transistor includes a drain connected to the first end of the compensation current generation circuit via a switching element, a source connected to the second end of the compensation current generation circuit, a gate connected to its own source, and a back gate. At least one of the switching elements is in the closed state. The semiconductor device according to claim 1.

10. The semiconductor device according to claim 9, wherein the switching element is either a fuse or a switch.

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