Signal generating device and signal generating method

Abstract

This invention provides a signal generator and a signal generation method that enable comprehensive verification of sequence operations for objects under test that conform to PCIe Gen4 or later and USB 3.X or later standards. [Solution] The signal generator 1 comprises a display control unit 6a that selectively displays a sequence setting screen, a sequence editing screen, and a pattern editing screen on a display unit 5; a setting control unit 6b that accepts editing and setting of setting items for the PCIe Gen4 and later and USB3.X and later standards supported by each of the above screens, and stores the setting information of the setting items in a storage unit 3; and a PPG 4a that sequentially generates multiple data patterns to cause the DUT 10 to perform sequence operations according to the above standards based on the setting information.

Description

Technical Field

[0001] The present invention relates to a signal generation apparatus and a signal generation method capable of generating a signal compatible with next-generation standard tests for high-speed serial buses (High Speed Serial Bus: hereinafter also referred to as HSB) such as PCIe and USB.

Background Art

[0002] In protocols such as PCIe (registered trademark) (Peripheral Component Interconnect Express) and USB (registered trademark) (Universal Serial Bus), a sequence operation that controls a Link Training and Status State Machine (LTSSM) and switches the state of a device is essential. By sending a plurality of defined data patterns (hereinafter referred to as "sequence blocks") to the device in the correct order, the state of the device can be arbitrarily changed.

[0003] For example, PCIe has standards such as Gen1 to Gen6, and the communication speed varies in the range of 2.5GT / s to 64GT / s for each standard. All PCIe devices have backward compatibility and can switch communication speeds. State switching is also used for this communication speed switching.

[0004] For example, in PCIe, the state transition diagram of the LTSSM is as shown in Figure 6, and the states defined include L0, L0s, L1, L2, Detect, Polling, Configuration, Disabled, Hot Reset, Loopback, and Recovery.

[0005] Manufacturers of PCIe and USB devices, as well as manufacturers of their controllers, need to verify during device development testing that the device correctly transitions states upon receiving sequence blocks.

[0006] For example, in the testing of high-speed serial bus (HSB) standards such as USB and PCIe, a Bit Error Rate Test Set (BERTS) has been conventionally known (for example, Patent Document 1, etc.) that transmits a test signal of a known pattern to the device under test while it is in a signal pattern folding state (loopback) using a specific pattern, and measures the bit error rate of the input data folded back from the device under test in conjunction with the transmission of this test signal. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Patent No. 6843902 [Overview of the project] [Problems that the invention aims to solve]

[0008] By the way, in PCIe, one of the high-speed serial bus standards, the 4th generation (Gen4) has been followed by the next-generation standards, the 5th generation (Gen5) and the 6th generation (Gen6).

[0009] Specifically, for PCIe standards from the fourth generation (Gen4) onward, for example, Gen4 and Gen5 show an improvement in communication speed from 16 GT / s to 32 GT / s. Furthermore, in Gen6, the transmission signal is not represented by the common digital signals of 0 and 1, but by the PAM4 signal, which is represented by four values: 0, 1, 2, and 3, and the communication speed is 64 GT / s. In addition, PAM4-based and NRZ-based modes are defined for Scramble, and Gray-code is also required. Unless all of these functions are implemented, it will not be possible to support the next-generation standards, Gen5 and Gen6.

[0010] The conventional BERTS technology described in Patent Document 1 only supports PCIe up to PCIe Gen4, and lacks the functionality to support the next-generation standards mentioned above. While definitions for USB 3.1 and USB 3.2 have progressed, support for the even next-generation USB 3.X has not been considered. Therefore, it has been difficult to support standard testing for PCIe Gen4 and beyond, and USB 3.X and beyond, until now.

[0011] The present invention has been made to solve the above-mentioned problems and aims to provide a signal generator and a signal generation method that enable comprehensive verification of sequence operations for objects under test that have PCIe Gen4 or later and USB3.X or later standards. [Means for solving the problem]

[0012] To solve the above problems, the signal generator according to claim 1 of the present invention is a signal generator that targets an object under test having a high-speed serial bus standard equipped with a link state management mechanism, and sequentially generates and transmits a plurality of data patterns for performing a series of sequence operations that perform a desired state transition, and is characterized by comprising: a setting screen (7a) for setting the data patterns as sequence blocks for each block, a sequence editing screen (7b) for editing a plurality of setting items of the sequence block, and a pattern editing screen (7c) for editing a pattern which is one of the setting items; a setting control means (6a) for accepting editing and setting of the setting items of the sequence block by setting functions of the setting items of the standard supported by the setting screen, the sequence editing screen, and the pattern editing screen, respectively, and storing the setting information of the setting items in a storage means (3); and a pattern generator (4a) for sequentially generating the plurality of data patterns for performing the sequence operations of the standard on the object under test based on the setting information.

[0013] This configuration enables the signal generator according to claim 1 of the present invention to comprehensively verify sequence operations for objects under test that have PCIe Gen4 or later and USB 3.X or later standards.

[0014] Furthermore, the signal generator according to claim 2 of the present invention may have a configuration in which the object under test has a PCIe Gen4 or later standard as the standard for the high-speed serial bus, the display control means displays a Scramble initial value setting tool (82), a Gray-code setting tool (86), and a Scramble Mode setting tool (87) on the sequence editing screen, and the setting control means accepts the setting of the lane number that determines the initial value of scrambling using the Scramble initial value setting tool, accepts the setting to turn Gray code on or off using the Gray-code setting tool, and accepts the setting of PAM4 or NRZ mode using the Scramble Mode setting tool.

[0015] This configuration enables the signal generator according to claim 2 of the present invention to verify the operation of PCIe devices that support Gray-code and Scramble Mode, which are essential for PCIe Gen4 and later standards, and contributes to accelerating the development of PCIe devices that meet PCIe Gen4 and later standards.

[0016] Furthermore, the signal generating device according to claim 3 of the present invention may be configured such that the display control means displays a Scramble location setting tool (91, 92, 93) on the pattern editing screen for setting data locations to be scrambled, and the setting control means sets data locations to be scrambled in accordance with the setting operation of the Scramble location setting tool.

[0017] With this configuration, the signal generator according to claim 3 of the present invention can easily configure the implementation points related to Scramble, which is essential for PCIe Gen4 and later standards, and can smoothly perform operational verification of PCIe devices that meet the said standards.

[0018] Furthermore, in the signal generator according to claim 4 of the present invention, the display control means may display a communication speed setting tool (88) on the sequence editing screen that selectively sets the communication speed standards corresponding to PCIe Gen4, Gen5, and Gen6, respectively, and the setting control means may be configured to accept setting operations of the communication speed setting tool and set 16GHz, 32GHz, and 64GHz as the communication speeds corresponding to PCIe Gen4, Gen5, and Gen6, respectively.

[0019] This configuration allows the signal generator according to claim 4 of the present invention to easily support operational verification of UCIe devices assuming communication speeds of 16GHz, 32GHz, and 64GHz as defined in the PCIe Gen4, Gen5, and Gen6 standards, respectively.

[0020] To solve the above problem, a signal generation method according to claim 5 of the present invention is a signal generation method that targets a device under test conforming to a high-speed serial bus standard equipped with a link state management mechanism, and sequentially generates and transmits a plurality of data patterns for executing a series of sequence operations that perform desired state transitions, the signal generation method comprising: a display control step (S1, S3, S6) for selectively displaying a setting screen (7a) for setting the data patterns as sequence blocks on a block-by-block basis, a sequence editing screen (7b) for editing a plurality of setting items of the sequence blocks, and a pattern editing screen (7c) for editing a pattern that is one of the setting items; a setting control step (S7) for accepting editing and setting of the setting items of the sequence blocks by the setting functions of the standard setting items respectively supported by the setting screen, the sequence editing screen, and the pattern editing screen, and storing the setting information of the setting items in a storage means (3); and a step (S8) for sequentially generating the plurality of data patterns for causing the device under test to execute the sequence operations under the standard based on the setting information.

[0021] With this configuration, the signal generation method according to claim 5 of the present invention enables comprehensive verification of sequence operations targeting a device under test conforming to standards of PCIe Gen4 and later, and USB3.X and later. [Advantageous Effects of the Invention]

[0022] The present invention can provide a signal generation apparatus and a signal generation method that enable comprehensive verification of sequence operations targeting a device under test conforming to standards of PCIe Gen4 and later, and USB3.X and later. [Brief Description of the Drawings]

[0023] [Figure 1] This is a block diagram showing a schematic configuration of a signal generation apparatus according to an embodiment of the present invention. [Figure 2] This is a diagram showing an example of a sequence setting screen displayed on a display unit included in the signal generation apparatus according to the embodiment of the present invention. [Figure 3] This is a diagram showing an example of a sequence editing screen displayed on a display unit included in the signal generation apparatus according to the embodiment of the present invention. [Figure 4] This is a diagram showing an example of a pattern editing screen displayed on a display unit included in the signal generation apparatus according to the embodiment of the present invention. [Figure 5] This is a flowchart showing operation control from the setting of a sequence block to the transmission of a specific pattern by the signal generation apparatus 1 according to the embodiment of the present invention. [Figure 6] This is a diagram showing state transitions of LTSSM. [Modes for Carrying Out the Invention]

[0024] Hereinafter, modes for carrying out the present invention will be described in detail with reference to the accompanying drawings.

[0025] The signal generation apparatus and signal generation method according to the present invention connect a device having an LTSSM control function that enables transitions between states shown in FIG. 6 (for example, a USB device, a PCIe device, etc.) as a device under test (DUT), and have a signal generation function of transmitting a plurality of data patterns to the DUT in the correct order for verifying whether the DUT can normally perform state transitions in compliance with the USB and PCIe communication standards (hereinafter simply referred to as standards) of the device.

[0026] Here, the plurality of data patterns generated by the signal generation apparatus have a structure in which a series of data patterns having the order and data content corresponding to a desired state transition pattern, that is, depending on which order and which state transition is requested, are arranged in block units. Since the above series of data patterns corresponds to the flow (sequence) of state transitions, each block in which the series of data patterns is arranged is also referred to as a sequence block.

[0027] In recent years, definitions for PCIe Gen4, USB 3.1, and USB 3.2 have been established for PCIe and USB standards, respectively. In this context, the signal generator according to the present invention is equipped with a GUI (Graphical User Interface) function for setting sequence blocks that can verify state changes even for DUTs with PCIe Gen4 and later, and USB 3.2 and later standards, which were previously difficult to support.

[0028] Specifically, the signal generator and signal generation method according to the present invention have speed setting capabilities that correspond to, for example, PCIe Gen4 communication speeds of 16 GT / s, Gen5 communication speeds of 32 GT / s, and Gen6 communication speeds of 64 GT / s. Furthermore, for Gen6, in addition to NRZ, which is represented by 0s and 1s, a setting function for PAM4, which is represented by four values ​​of 0, 1, 2, and 3, is also provided. In addition, the Scramble mode can be set to PAM4-based or NRZ-based, and a Gray-code setting function is also provided.

[0029] One embodiment of the present invention will be described below. The signal generator 1 according to this embodiment generates and sends out a plurality of data patterns to cause a device under test (DUT) 10 equipped with an LTSSM to perform a series of sequence operations that result in a desired state transition. As shown in Figure 1, it is generally configured to include a setting operation unit 2, a storage unit 3, a signal transmission / reception unit 4, a display unit 5, and a control unit 6.

[0030] DUT10 can be a PCIe device or a USB device. PCIe devices are assumed to conform to PCIe Gen4 or later standards, and USB devices are assumed to conform to USB 3.1 (Gen1) or USB 3.2 (Gen2) standards (hereinafter, these may be collectively referred to as USB 3.X). The following explanation will primarily assume the use of PCIe devices conforming to Gen4 or later standards.

[0031] The setting operation unit 2 is operated by the user and consists of various soft keys, cursor keys, and arrow keys on the display screen of the display unit 5 (sequence setting screen 7a in Figure 2, sequence editing screen 7b in Figure 3, and pattern editing screen 7c in Figure 4), as well as keys, switches, and buttons provided on the main body of the device.

[0032] The setting operation unit 2 is operated when setting, editing, instructing the start and stop of transmission of a specific pattern (data pattern) to be sent to the DUT 10, and setting or editing the specific pattern.

[0033] For example, the soft keys on the setting operation unit 2 that are operated when setting a specific pattern include the "Sequence Edit" soft key 74 and the "Transmit" soft key 75 displayed on the sequence setting screen 7a in Figure 2. When the "Sequence Edit" soft key 74 is pressed on the sequence setting screen 7a in Figure 2, the display screen switches to the sequence editing screen 7b in Figure 3, for example. Also, when the "Transmit" soft key 75 on the sequence setting screen 7a is pressed, the transmission of a specific pattern to the DUT 10 based on the setting information begins.

[0034] The sequence editing screen 7b, accessed by switching from the sequence setting screen 7a, displays the following soft keys 85a, 85b, 85c, 85d, 85e, 85f, 85g, 85h, 85i, and 85j as soft keys for the setting operation unit 2 used when editing sequences: "Load", "Add", "Delete", "Copy", "Cut", "Paste", "Clear All", "OK", "Cancel", and "Save". By operating these soft keys 85a to 85j, users can select HSB standards (PCIe Gen1, 2, 3, 4, 5, 6, and USB3.1 (Gen1) or USB3.2 (Gen2)), edit blocks (#0 to #n) of a specific pattern defined by the selected standard, save the block (sequence block) setting information to the storage unit 3, and read the sequence block setting information saved in the storage unit 3.

[0035] Furthermore, in the sequence editing screen 7b, pressing the "Pattern Edit" soft key 84 switches the display screen to, for example, the pattern editing screen 7c shown in Figure 4. On the pattern editing screen 7c, the operation key group 91, 92, and 93 are displayed as soft keys for the setting operation unit 2, which are used when editing a specific pattern. By operating these operation key group 91, 92, and 93, it is possible to set, edit, and even set locations for Scramble within the pattern setting area 91b.

[0036] In the illustrated example, the soft keys on the display screen of the display unit 5 are configured as part of the setting operation unit 2, but an external input device, which is provided separately from the signal generator 1, can also be used as the setting operation unit 2.

[0037] The memory unit 3 stores various information, such as setting information for specific patterns (data patterns) set in the sequence block of the sequence setting screen 7a based on edits received via the sequence editing screen 7b and the pattern editing screen 7c (information such as the type of specific pattern defined by PCIe and USB standards, transmission order, transmission time, and number of transmissions).

[0038] The signal transmission / reception unit 4 includes a pulse pattern generator (PPG) 4a and a signal reception unit 4b, and transmits and receives signals necessary for verifying the sequence operation of the DUT 10 through control by the control unit 6 based on the operation information of the setting operation unit 2 and the stored information of the storage unit 3.

[0039] PPG4a uses the sequence editing screen 7b and the pattern editing screen 7c to sequentially generate specific patterns (multiple data patterns) for DUT10 to perform sequence operations using PCIe Gen4 or later (and USB3.X or later) communication standards, based on the sequence block setting information set in the sequence setting screen 7a, and sends them to DUT10. PPG4a constitutes the pattern generation means of the present invention.

[0040] The signal receiving unit 4b receives input data sent from the DUT 10 while the DUT 10 is transitioned to a state such as a signal pattern folding state (loopback) by a specific pattern generated in the PPG 4a, and performs signal reception processing to output to the control unit 6.

[0041] The display unit 5 is composed of, for example, a liquid crystal display mounted on the main body of the device. The display unit 5, under the control of the display control unit 6a, selectively displays on its screen a sequence setting screen 7a (see Figure 2) for setting data patterns as sequence blocks for each block, a sequence editing screen 7b (see Figure 3) for editing multiple setting items of a sequence block, and a pattern editing screen 7c (see Figure 4) for editing a pattern, which is one of the setting items of a sequence block, as well as displaying various other information.

[0042] The control unit 6 is composed of a control device such as a computer, which includes, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and an HDD (Hard Disk Drive). The control unit 6 controls the signal transmission / reception unit 4 based on the operation information of the setting operation unit 2 and the stored information of the storage unit 3, and controls each unit in order to perform state transitions of the DUT 10. It includes a display control unit 6a that controls the display unit 5 when setting or editing a specific pattern, a setting control unit 6b that controls the setting of specific patterns, etc., based on the setting operation in the setting operation unit 2, and a pattern generation control unit 6c that generates specific patterns (#0 to #n) corresponding to the sequence blocks set on the sequence setting screen 7a and controls the PPG 4a to send these specific patterns to the DUT 10 in order.

[0043] Next, the GUI functions provided in the signal generator 1 according to this embodiment will be described. The signal generator 1 according to this embodiment has a sequence setting screen 7a, a sequence editing screen 7b, and a pattern editing screen 7c, which are used when verifying the sequence operation of the DUT 10.

[0044] The sequence setting screen 7a has the function of setting the sequence block to be sent to the DUT 10. The sequence setting screen 7a has the display format shown in Figure 2, and by selecting the "Pattern" tab 71, the Test Pattern area 71a, Specification area 71b, and Sequence Block area 71c can be displayed.

[0045] In the Test Pattern area 71a, a soft key 72 for selecting the setting type is displayed, and in the Specification area 71b, a soft key 73 for selecting the standard, a soft key 74 for "Sequence Edit", and a soft key 75 for "Transmit" are displayed.

[0046] By operating soft key 72, you can set the setting type, such as "Sequence," and by operating soft key 73, you can select the desired PCIe standard (Gen1 to Gen6) (and USB3.X) for which DUT10's operation verification will be performed from the pull-down menu.

[0047] Soft key 74 for "Sequence Edit" is used when editing sequences. Soft key 75 for "Transmit" is used to instruct DUT10 to transmit a specific pattern based on the sequence block configuration information.

[0048] The sequence setting screen 7a shown in Figure 2 displays an example where "Sequence" is set as the setting type using the soft key 72, and "PCIe6" is selected as the standard for verifying the operation of the DUT10 using the soft key 73.

[0049] The sequence block area 71c is an area that displays multiple configured patterns in block units. In the sequence block area 71c, each row identified by block numbers #1 to #n represents an arbitrarily configured sequence block. Each sequence block can be configured with any pattern using the editor (pattern editing screen 7c) shown in Figure 4.

[0050] The sequence setting screen 7a also functions as an operation screen, such as instructing the output of a specific set pattern to the DUT10. By pressing the "Transmit" soft key 75 on the sequence setting screen 7a, a specific pattern is sent to the DUT10 sequentially from block number #1 to #n based on the setting information of the sequence block. At that time, if there is a setting to pause in the "Break" item of the sequence block, the sequence progress is paused while the sequence block is repeatedly sent. The sequence setting screen 7a constitutes the setting screen of the present invention.

[0051] Additionally, pressing the "Sequence Edit" soft key 74 switches to the sequence editing screen 7b shown in Figure 3, which is used for sequence editing.

[0052] The sequence editing screen 7b has the functionality of an editor for editing the sequence blocks displayed in the sequence block area 71c of the sequence settings screen 7a.

[0053] In the sequence editing screen 7b, selecting the "Scrambler" tab 81 displays the scramble settings area 81a and the sequence block area 81b, as well as the "Pattern Edit" soft key 84 used to switch to editing a specific pattern, and the soft keys 85a, 85b, 85c, 85d, 85e, 85f, 85g, 85h, 85i, and 85j for "Road," "Add," "Delete," "Copy," "Cut," "Paste," "Clear All," "OK," "Cancel," and "Save."

[0054] The scramble setting area 81a displays a soft key 82 for setting the lane number to determine the scramble seed value (initial value). The soft key 82 has a pull-down menu with options for each of the four lanes of the signal generator 1, for example, lane numbers 0 (zero), 1, 2, and 3, and the desired lane number can be set from this pull-down menu. Figure 3 shows an example of the display when lane number 0 (zero) is set to determine the initial value of the scramble.

[0055] In the sequence editing screen 7b shown in Figure 3, the initial display content of the sequence block in the sequence block area 81b is based, for example, on the preset data from the sequence setting screen 7a or the data of a specific pattern from the previous session.

[0056] In the sequence editing screen 7b, you can freely edit blocks (#0 to #n) in units of a specific pattern defined by the selected standard (e.g., PCIe Gen6) by operating the soft keys 85a, 85b, 85c, 85d, 85e, 85f, 85g, 85h, 85i, and 85j as needed, for the functions "Road", "Add", "Delete", "Copy", "Cut", "Paste", "Clear All", "OK", "Cancel", and "Save".

[0057] The items editable in each block (see Figure 3) include Pattern Type, Bitrate, Pattern, Pattern Length, Precoder, Gray code, Scramble, Num or Time [num] or [μs], Time [ns], SKP OS Insertion, SKP OS Reset, EIEOSQ (Electrical Idle Exit Ordered Set Sequence) Insertion, EIEOS Count, EIEOSQ Interval [Pattern repeats], and EIEOSQ Reset. Some of these items can be set directly by text input, while others can be selected from a pull-down menu.

[0058] The information to be configured is compatible with PCIe Gen4 and later (and USB 3.X and later) standards. For example, for pattern types, settings such as 1b1b, 8b10b, and 128b130b can be configured. For bitrate, for example, 16GHz (PCIe Gen4 compatible), 32GHz (PCIe Gen5 compatible), and 64GHz (PCIe Gen6 compatible) can be configured. The bitrate can be set by operating the soft key 88, which is displayed in association with the setting item "Bitrate" in the sequence block area 81b, and selecting the desired communication speed from its pull-down menu. The soft key 88 constitutes the communication speed setting tool of the present invention.

[0059] Regarding patterns, various patterns related to LOOPBACK and RECOVERY can be set for each standard. For Gray code, the setting can be turned ON or OFF from the pull-down menu of soft key (combo box) 86 in Figure 3. For scramble, the setting can be changed to NRZ or PAM4 from the pull-down menu of soft key (combo box) 87 in Figure 3. Soft keys 86 and 87 constitute the Gray-code setting tool and Scramble Mode setting tool of the present invention, respectively.

[0060] In the sequence editing screen 7b, pressing the "Pattern Edit" soft key 84 will switch you to the pattern editing screen 7c shown in Figure 4.

[0061] The pattern editing screen 7c is used to edit the data content corresponding to the pattern among the sequence block setting items set in the sequence block area 71c of the sequence setting screen 7a.

[0062] As shown in Figure 4, the pattern editing screen 7c has an operation key area 91a that displays operation key groups 91, 92, 93, etc., each equipped with multiple soft keys, and a pattern setting area 91b that displays a list of symbol values ​​of the pattern type associated with a sequence block.

[0063] Here, the pattern editing screen 7c accepts the setting of a specific pattern (data sequence) in the pattern setting area 91b by key operations of each soft key that makes up the operation key groups 91 and 92, or the soft keys such as the numeric keypad of the operation key group 93.

[0064] Accordingly, the pattern editing screen 7c has a function that allows you to specify a data area from an arbitrary start position to an arbitrary end position within the data array that constitutes a set specific pattern, and set that data area as the area to be scrambled. The area to be scrambled can be set in PCIe Symbol units (8 bits per Symbol in the case of 1b1b), and the pattern editing screen 7c shown in Figure 4 shows an example of the display when the areas indicated by shades of gray, i.e., symbols 1-7 and 8-15, are set as the target areas.

[0065] A "symbol" is one of the data units handled by the PCIe standard. The size of one symbol can vary depending on the encoding; it is 10 bits (8 bits of effective data) in PCIe Gen1-2's 8b10b encoding, and 8 bits in PCIe Gen3-5's 128b130b and PCIe Gen 6's 1b1b encoding.

[0066] The pattern editing screen 7c shown in Figure 4 has the functionality of an editor for configuring PCIe 1b1b. In addition to this, the pattern editing screen 7c also has similar editors for configuring PCIe 8b10b, 128b130b patterns, and USB 128b130b patterns. All of these editors have the functionality to configure the locations where scrambling will be performed.

[0067] As described above, the GUI function provided in the signal generator 1 according to this embodiment supports setting items that conform to PCIe Gen4 and later (and USB 3.X and later) standards. This setting function is realized by the display control of the display control unit 6a.

[0068] Here, we will explain in detail some typical setting items that meet the above conditions (PCIe Gen4 and later). In this embodiment, the setting items that meet the above conditions within the sequence block of the sequence setting screen 7a and the sequence editing screen 7b include the Scramble and Gray-code items.

[0069] (Scramble) Scrambling is performed to increase the data toggle rate and equalize the mark rate. The method involves taking the exclusive OR operation between the target signal and a pseudo-random bit sequence signal (PRBS) as defined in the standard. The initial value of this PRBS varies depending on the lane number. The difference between PAM4-based and NRZ-based is defined as follows in "PCI Express(r) Base Specification Revision 6.2-4.2.3.1.2 lb / lb Scrambling".

[0070] 4.2.3.1.2 1b / 1b Scrambling§ The scrambling mechanism in the 64.0 GT / s Data Rate is identical to that for the 8.0,16.0, and 32.0 GT / s Data Rates and is already covered in§Section 4.2.2.4, except for the TS0 / TS1 / TS2 / SKP Ordered Set rules defined below. §Figure 4-25 demonstrates the scrambler on the Transmitter side. All Data Stream bits as well as some Ordered Set bits are scrambled. TS1 and TS2 Ordered Sets: · Symbols 0 and 8 bypass scrambling. · Symbols 1 through 6 and Symbols 9 through 14 are scrambled. · Symbols 7 and 15 bypass scrambling if required for DC Balance, but they are scrambled if not required for DC Balance. ·TS0 Ordered Sets: · Symbols 0 and 8 bypass scrambling · Symbols 1 through 6 and Symbols 9 through l4 use NRZ-based scrambling ·NRZ-based scrambling consists of scrambling all 8 bits and then, in place of gray-coding, forcing the even bit2ito be identical to the odd bit (2i+l) [where 0<i<3]. This ensures that only voltage levels 0 and 3 are sent. · Symbols 7 and 15 bypass scrambling if required for DC Balance; else they carry even parity of Symbols 1 through 6 and Symbols 9 through 14 respectively with NRZ-scrambling · All Symbols in TS0 are NRZ-based (i.e., each UI maps to voltage levels 0 or 3,encoded as 00b or 10b). Only TS0 Ordered Set is designed to be NRZ-based in 64.0 GT / s Data Rate.

[0071] (Gray-code) The PCIe Gen6 standard specifies that gray code should be applied to Gen6 PAM4. However, it specifies that this should not be applied to the entire data area, but only to symbols that are subject to scrambling.

[0072] Gray-code is a mechanism to make the number of bits that result in an error equal to 1 when a PAM4 value has a 1-level error. The operation is simple: it swaps the 2 (10b) and 3 (11b) bits of the PAM4 symbol as follows. This makes the difference between symbols with a 1-level difference in their bit values ​​equal to 1 bit (※10b and 01b differ in both bits, but after coding, they are different from 01b and 11b, with only a 1-bit difference). Before coding: 00b, 01b, 10b, 11b After coding: 00b, 01b, 11b, 10b

[0073] Next, the operation from setting a sequence block to transmitting a specific pattern using the signal generator 1, which has the above GUI functions (sequence setting screen 7a, sequence editing screen 7b, pattern editing screen 7c), will be explained with reference to Figure 5. Note that this operation primarily assumes the selection of PCIe Gen6, but this operation is similarly compatible with PCIe Gen1-6 and USB3.X.

[0074] To set a sequence, display the sequence setting screen 7a in Figure 2 (Step S1).

[0075] Next, on the sequence setting screen 7a, use the soft key 72 to select "Sequence" as the setting type, and use the soft key 73 to select one of PCIe Gen1 to 6 as the operational verification standard from the pull-down menu (step S2).

[0076] At this time, the sequence block area 71c displays pre-configured information corresponding to the selected standard for operational verification (e.g., PCIe Gen6), such as data for a specific pattern from the previous session.

[0077] In this display state, press the "Sequence Edit" soft key 72 on the sequence setting screen 7a to switch to the sequence editing screen 7b shown in Figure 3 (step S3).

[0078] In the sequence editing screen 7b, the lane number for determining the initial value of the scramble is set using the soft key 82 in the scramble setting area 81a (step S4). Figure 3 shows an example of the display when lane number 0 is set out of four lane numbers 0 (zero), 2, 3, and 4. The soft key 82 constitutes the Scramble initial value setting tool of the present invention.

[0079] Next, on the sequence editing screen 7b, you can freely edit the specific pattern defined by the selected standard (PCIe Gen6 in this example) in block units (#0 to #n) by operating the soft keys 85a, 85b, 85c, 85d, 85e, 85f, 85g, 85h, and 85j as appropriate, using the "Add", "Delete", "Copy", "Cut", "Paste", "Clear All", "OK", and "Cancel" functions (Step S5).

[0080] Examples of specific patterns (sequence blocks) to be edited here include Gray-code and Scramble Mode, which are required in PCIe Gen4 and later standards.

[0081] Gray-code can be selected from a pull-down menu by operating the soft key 86, which is located in the sequence block area 81b and corresponds to the item "Gray-code". Specifically, the soft key 86 is used to turn Gray-code on or off.

[0082] The Scramble Mode can be set using the soft key 87 provided in the sequence block area 81b, corresponding to the item "Scramble Mode". Specifically, either PAM4 or NRZ is set using the soft key 87 (corresponding to the Scramble Mode setting tool of the present invention).

[0083] Once the sequence editing process in steps S3 to S5 above is complete, and the "Pattern Edit" soft key 84 on the sequence editing screen 7b is pressed, the screen switches to the pattern editing screen 7c (see Figure 4) (step S6).

[0084] In the pattern editing screen 7c, for example, by appropriately operating the numeric keypad (soft keys) of the operation key group 93, a specific pattern (symbol sequence) is set for each column in the pattern setting area 91b (step S6).

[0085] Furthermore, the locations where scrambling is to be performed are set by appropriately operating the various soft keys in the operation key groups 91, 92, and 93 to select the desired symbol column from the symbol columns set in the pattern setting area 91b, and then specifying the symbol column ranges corresponding to the start and end positions of the scramble (step S6). In the pattern editing screen 7c of Figure 4, an example of the display when symbols 1-7 and 8-15 of the first column are set as locations where scrambling is to be performed in the 1b1b pattern setting is shown, with the corresponding symbol columns indicated in a dark gray color. The operation key groups 91, 92, and 93 constitute the Scramble location setting tool of the present invention.

[0086] After completing pattern editing on the pattern editing screen 7c and returning to the sequence editing screen 7b (see Figure 2), the user finishes editing the block-level data of a specific pattern and presses the "Save" soft key 85j. This saves the data of the specific pattern edited on the sequence editing screen 7b and pattern editing screen 7c as setting information to the storage unit 3 (step S7).

[0087] Subsequently, to verify the operation of DUT10, press the "Transmit" soft key 75 on the sequence setting screen 7a in Figure 2. This causes the pattern generation control unit 6c of the control unit 6 to control PPG4a, which generates specific patterns (#0 to #n) corresponding to the sequence blocks set on the sequence setting screen 7a, and transmits these specific patterns to DUT10 in order (step S8).

[0088] On the other hand, when DUT10 receives a specific pattern from PPG4a, it executes a state transition operation according to the configuration information for each sequence block.

[0089] According to the editing process of specific patterns from steps S2 to S5 in Figure 5, the specific patterns that are set and sent to DUT10 will also include setting information for items that conform to PCIe Gen4 and later standards (Gray-code, Scramble Mode, Scramble initial value, etc.).

[0090] Therefore, the sequence operation of DUT10, which is executed upon receiving a specific pattern containing the above configuration information, can be used to verify whether the sequence operation is correctly performed, reflecting items that conform to PCIe Gen4 and later standards (Gray-code, Scramble Mode, Scramble initial value, etc.).

[0091] Although the above embodiment mainly describes the operation verification of PCIe devices having PCIe Gen4 or later standards, the GUI functions of this embodiment (sequence setting screen 7a, sequence editing screen 7b, pattern editing screen 7c, etc.) can also be similarly applied to the operation verification of USB devices having USB3.X or later standards.

[0092] However, the signal generator 1 according to this embodiment is specialized in the function of transmitting data patterns used for operational verification to the DUT 10, and does not have the function of receiving and analyzing signals sent out from the DUT 10 according to its state after receiving the specific pattern. To analyze signals sent out from the DUT 10 according to its state, one could, for example, connect a protocol analyzer to the DUT 10 to form a system configuration, but performing the above analysis with a protocol analyzer lacks real-time capability.

[0093] Another possible approach is to replace the signal receiving unit 4b of the signal generator 1 with an error rate measurement unit (Error Detector: ED), and configure BERTS such that the DUT 10 is switched to a feedback state by a specific pattern (test signal) sent from PPG 4a, the DUT 10 receives the signal to be measured which is looped back by the DUT 10 in response to the test signal, and the error rate is measured by the ED.

[0094] In other words, the signal generator 1 according to this embodiment supports PCIe Gen4 and later, the next-generation PCIe standard, and USB 3.X and later, the next-generation USB standard. By implementing this as a function of BERTS, it becomes possible to realize a signal generator that can perform everything from system operation verification, such as state machine operation verification, to hardware operation verification, such as error rate verification, on a single unit.

[0095] As described above, the signal generator 1 according to this embodiment targets a device under test (DUT10) equipped with an LTSSM and having PCIe Gen4 or later, and USB3.X or later standards, and sequentially generates and transmits multiple data patterns to perform a series of sequence operations that result in a desired state transition.

[0096] The signal generator 1 comprises a display control unit 6a that selectively displays a sequence setting screen 7a for setting data patterns as sequence blocks for each block, a sequence editing screen 7b for editing multiple setting items of a sequence block, and a pattern editing screen 7c for editing a pattern, which is one of the setting items; a setting control unit 6b that accepts editing and setting of the setting items of a sequence block using the setting function of the setting items of the above standard supported by the sequence setting screen 7a, sequence editing screen 7b, and pattern editing screen 7c, and stores the setting information of the setting items in the storage unit 3; and a PPG 4a) that sequentially generates multiple data patterns to cause the DUT 10 to perform sequence operations according to the above standard based on the setting information.

[0097] This configuration enables the signal generator 1 according to this embodiment to perform comprehensive verification of sequence operations targeting a DUT 10 having PCIe Gen4 or later and USB 3.X or later standards.

[0098] Furthermore, the signal generator 1 according to this embodiment has a DUT 10 that conforms to PCIe Gen4 or later standards, and the display control unit 6a displays a Scramble initial value setting tool (soft key 82), a Gray-code setting tool (soft key 86), and a Scramble Mode setting tool (soft key 87) on the sequence editing screen 7b, and the setting control unit 6b accepts the setting of the lane number that determines the initial value of scrambling using the Scramble initial value setting tool, accepts the setting to turn Gray code on or off using the Gray-code setting tool, and accepts the setting of PAM4 or NRZ mode using the Scramble Mode setting tool.

[0099] This configuration enables the signal generator 1 according to this embodiment to verify the operation of PCIe devices that support Gray-code and Scramble Mode, which are essential for PCIe Gen4 and later standards, thereby contributing to the acceleration of development of PCIe devices that conform to PCIe Gen4 and later standards.

[0100] Furthermore, in this embodiment, the signal generator 1 has a display control unit 6a that displays a Scramble location setting tool (operation key group 91, 92, 93) on the pattern editing screen 7c for setting data locations to be scrambled, and a setting control unit 6b that sets data locations to be scrambled according to the setting operation of the Scramble location setting tool.

[0101] With this configuration, the signal generator 1 according to this embodiment can easily configure the locations for Scramble, which is essential for PCIe Gen4 and later standards, and can smoothly perform operational verification of PCIe devices that comply with said standards.

[0102] Furthermore, in this embodiment, the signal generator 1 is configured such that the display control unit 6a displays a communication speed setting tool (soft key 88) on the sequence editing screen 7b for selectively setting the communication speed standards corresponding to PCIe Gen4, Gen5, and Gen6, respectively, and the setting control unit 6b accepts the setting operation of the communication speed setting tool 88 and sets 16GHz, 32GHz, and 64GHz as the communication speeds corresponding to PCIe Gen4, Gen5, and Gen6, respectively.

[0103] This configuration allows the signal generator 1 according to this embodiment to easily support operational verification of UCIe devices assuming communication speeds of 16GHz, 32GHz, and 64GHz as defined in the PCIe Gen4, Gen5, and Gen6 standards, respectively.

[0104] Furthermore, the signal generation method according to this embodiment includes a display control step (S1, S3, S6) that selectively displays a sequence setting screen 7a for setting data patterns as sequence blocks for each block, a sequence editing screen 7b for editing multiple setting items of a sequence block, and a pattern editing screen 7c for editing a pattern, which is one of the setting items; a setting control step (S7) that accepts the editing and setting of the setting items of a sequence block by setting the setting items of the above standard supported by the sequence setting screen 7a, sequence editing screen 7b, and pattern editing screen 7c, and stores the setting information of the setting items in the storage unit 3; and a PPG step (S8) that sequentially generates multiple data patterns to cause the DUT 10 to perform sequence operations according to the above standard based on the setting information.

[0105] This configuration enables comprehensive verification of sequence operations for devices under test that conform to PCIe Gen4 or later, and USB 3.X or later standards, using the signal generation method according to this embodiment.

[0106] The best mode of the signal generating device and signal generating method according to the present invention has been described above, but the present invention is not limited by this description and drawings. That is, other modes, examples, and operating techniques based on this mode, as made by those skilled in the art, are all included in the scope of the present invention. [Industrial applicability]

[0107] As described above, the present invention has the effect of enabling comprehensive verification of sequence operations for objects under test that conform to PCIe Gen4 and later standards, and USB 3.X and later standards, and is useful for signal generators and signal generation methods in general for the development of future PCIe devices and USB devices that conform to PCIe Gen4 and later standards, and USB 3.X and later standards. [Explanation of symbols]

[0108] 1. Signal Generator 2. Setting Operation Unit 3 Storage section 4. Signal transmission and reception unit 4a Pulse pattern generation unit (PPG) (Pattern generation means) 4b Signal receiving section 5 Display section 6 Control Unit 6a Display Control Unit 6b Setting Control Unit 6c Pattern generation control unit 7a Sequence settings screen (settings screen) 7b Sequence editing screen 7c Pattern Editing Screen 71 "Pattern" tab 71a Test Pattern area 71b Specification area 71c Sequence block region 72 Soft keys to select the standard 73 Soft keys to select the standard 74. Soft keys for "Sequence Edit" 75. "Transmit" soft key 76. "Manual" soft keys 81 "Scrambler" tab 81a Scramble setting area 81b Sequence block region 82 Soft Keys (Scramble Initial Settings Tool) 84. Soft keys for "Pattern Edit" 85a, 85b, 85c, 85d, 85e, 85f, 85g, 85h, 85i, 85j Soft Keys 86 Soft Keys (Gray-code setting tool) 87 Soft Keys (Scramble Mode Setting Tool) 88 Soft Keys (Communication Speed ​​Setting Tool) 91, 92, 93 Operation Key Group (Scramble Location Setting Tool) 91a Operation key area 91b Pattern setting area 10 DUT (device under test)

Claims

1. A signal generator that targets an object under test having a high-speed serial bus standard equipped with a link state management mechanism, and sequentially generates and transmits multiple data patterns to perform a series of operations that result in a desired state transition, A display control means (6a) selectively displays a setting screen (7a) for setting the data pattern as a sequence block for each block, a sequence editing screen (7b) for editing multiple setting items of the sequence block, and a pattern editing screen (7c) for editing one of the setting items, which is the pattern. The setting control means (6b) accepts the editing and setting of the setting items of the sequence block using the setting function of the setting items of the standard supported by the setting screen, the sequence editing screen, and the pattern editing screen, respectively, and stores the setting information of the setting items in the storage means (3), A pattern generating means (4a) that sequentially generates the plurality of data patterns for causing the object to be measured to perform the sequence operation according to the standard based on the setting information, A signal generating device characterized by having the following features.

2. The object under measurement has a PCIe Gen4 or later standard as the high-speed serial bus standard. The display control means displays the Scramble initial value setting tool (82), the Gray-code setting tool (86), and the Scramble Mode setting tool (87) on the sequence editing screen. The signal generator according to claim 1, characterized in that the setting control means accepts the setting of a lane number that determines the initial value of scrambling using the Scramble initial value setting tool, accepts the setting to turn Gray code on or off using the Gray-code setting tool, and accepts the setting of PAM4 or NRZ mode using the Scramble Mode setting tool.

3. The display control means displays a Scramble location setting tool (91, 92, 93) on the pattern editing screen for setting data locations where the scrambling will be performed. The signal generating device according to claim 2, characterized in that the setting control means sets data locations where scrambling is performed in accordance with the setting operation of the Scramble location setting tool.

4. The display control means displays a communication speed setting tool (88) on the sequence editing screen that selectively sets the communication speed standards corresponding to PCIe Gen4, Gen5, and Gen6, respectively. The signal generator according to claim 2, characterized in that the setting control means accepts setting operations of the communication speed setting tool and sets 16 GHz, 32 GHz, and 64 GHz as communication speeds corresponding to PCIe Gen4, Gen5, and Gen6, respectively.

5. A signal generation method for a device under test that has a high-speed serial bus standard equipped with a link state management mechanism, which generates and transmits multiple data patterns in order to perform a series of operations that result in a desired state transition, A display control step (S1, S3, S6) selectively displays a setting screen (7a) for setting the data pattern as a sequence block for each block, a sequence editing screen (7b) for editing multiple setting items of the sequence block, and a pattern editing screen (7c) for editing one of the setting items, which is the pattern. A setting control step (S7) is performed to accept the editing and setting of the setting items of the sequence block using the setting function of the setting items of the standard supported by the setting screen, the sequence editing screen, and the pattern editing screen, respectively, and to store the setting information of the setting items in the storage means (3), A PPG step (S8) in which, based on the setting information, sequentially generates the plurality of data patterns to cause the object to be measured to perform the sequence operation according to the standard, A signal generation method characterized by including [a specific component].

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