Processor

Abstract

This provides a new processor structure that maximizes the use of increasing processing power and enables efficient parallel processing. [Solution] The processor of the present invention comprises an arithmetic unit, multiple registers, an instruction control unit, a memory control unit, and an arithmetic unit control unit, and in particular improves parallel processing capability by "bundling and extending" multiple registers. Specifically, the registers are divided into bundle blocks, and instructions can be processed in parallel in each block. This makes it possible to efficiently utilize the increased number of arithmetic units. Furthermore, bundle extension is also applied to load / store instructions and arithmetic instructions, enabling parallel processing for both scalar and vector operations. It also supports the use of low-precision arithmetic units, improving efficiency in specific tasks such as AI calculations. As a result, compared to conventional scalar and vector processors, the same operations can be performed with fewer instructions, achieving improved performance, especially in tasks requiring large-scale parallel computing.

Description

Technical Field

[0001] The present invention relates to a processor.

Background Art

[0002] In processing in generative AI / LLM, 99% of operations are (large-scale) matrix multiplications, and the remaining 1% are (long) (row-direction) vector operations. In response to such circumstances, the miniaturization of process technologies has increased the number of arithmetic units that can be mounted on an LSI, and GPUs / TPUs equipped with circuits dedicated to matrix operations, such as tensor cores, for generative AI operations have emerged. For example, a TPU implementing 256×256=65,536 arithmetic units is also known.

[0003] Patent Document 1 describes a technology related to a processor suitable for processing a plurality of vector data in parallel.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Each disclosure of the above prior art documents is incorporated herein by reference. The following analysis has been made by the present inventors.

[0006] Incidentally, while using a processor equipped with dedicated matrix operation circuits can improve the performance of 99% of matrix operations in generative AI / LLM by tens of thousands to hundreds of thousands of times, the remaining 1% (row-direction) vector operations can only be improved by a few hundred times. This prevents increasing the degree of parallelism for instructions and limiting the use of a large number of arithmetic units, making vector operations a bottleneck. For this reason, processors equipped with multiple vector cores, or multiple cores like GPUs, are being used, but power consumption remains a bottleneck, and multi-core programming is difficult.

[0007] In view of the above-mentioned problems, the object of the present invention is to provide a processor that contributes to efficiently processing calculations by increasing the degree of parallelism. [Means for solving the problem]

[0008] From the perspective of the present invention, a processor is provided comprising an arithmetic unit, a plurality of registers, an instruction control unit that fetches, decodes, issues, and retires instructions from memory, a memory control unit that performs data transfer between the memory and the registers based on instructions from the instruction control unit, and an arithmetic unit control unit that performs control between the arithmetic unit and the registers based on instructions from the instruction control unit, wherein the plurality of registers are bundled and extended to enable parallel processing of instructions. [Effects of the Invention]

[0009] According to each aspect of the present invention, it is possible to provide a processor that contributes to efficiently processing calculations by increasing the degree of parallelism. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 shows a schematic configuration of a conventional scalar processor. [Figure 2] Figure 2 shows a schematic configuration of the first conventional vector processor. [Figure 3] Figure 3 shows a schematic configuration of a second conventional vector processor. [Figure 4] Figure 4 shows a schematic configuration of a third conventional vector processor. [Figure 5] Figure 5 shows a schematic configuration of a scalar processor according to the first embodiment of this disclosure. [Figure 6] Figure 6 is a diagram showing a schematic configuration of a scalar processor according to the second embodiment of this disclosure. [Figure 7] Figure 7 shows a schematic configuration of a scalar processor according to the third embodiment of this disclosure. [Figure 8] Figure 8 shows a schematic configuration of a scalar processor according to the fourth embodiment of this disclosure. [Figure 9] Figure 9 shows a schematic configuration of a vector processor according to the first embodiment of the present disclosure. [Figure 10] Figure 10 shows a schematic configuration of a vector processor according to a second embodiment of the present disclosure. [Figure 11] Figure 11 shows a schematic configuration of a vector processor according to the third embodiment of the present disclosure. [Figure 12] Figure 12 shows a schematic configuration of a vector processor according to the fourth embodiment of the present disclosure. [Figure 13] Figure 13 shows a schematic configuration of a vector processor according to the fifth embodiment of the present disclosure. [Figure 14] Figure 14 shows a schematic configuration of a vector processor according to the sixth embodiment of the present disclosure. [Modes for carrying out the invention]

[0011] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the embodiments described below. In each drawing, the same or corresponding elements are appropriately denoted by the same reference numerals. Furthermore, it should be noted that the drawings are schematic, and the dimensional relationships and ratios of each element may differ from those of reality. Even between drawings, there may be parts where the dimensional relationships and ratios differ from each other.

[0012] [Prior Art Processor] First, in order to facilitate the description of the configuration of the processor according to the embodiments of the present disclosure and the features of arithmetic processing, the configuration and arithmetic processing of a prior art processor will be described.

[0013] Figure 1 is a diagram showing a schematic configuration of a prior art scalar processor. Note that the scalar processor shown in Figure 1 is based on a RISC architecture such as RISC-V, and has a load-store architecture (register-register architecture).

[0014] The scalar processor shown in Figure 1 includes an instruction control unit, a memory control unit, scalar registers, an arithmetic unit control unit, and an arithmetic unit. The instruction control unit includes a program counter (PC), and performs fetch, decode, issue, and retire control for instructions from the memory. The memory control unit performs data transfer between the memory and the registers in accordance with an instruction from the instruction control unit. The scalar registers are a plurality of scalar registers (note that there are 4 in Figure 1, but 32 in RISC-V). The arithmetic unit control unit performs control between the arithmetic unit and the scalar registers in accordance with an instruction from the instruction control unit. The arithmetic unit generally consists of a fused multiply-add (FMA) unit and an ALU.

[0015] An example of instruction operation in a prior art scalar processor is as follows. ·Read the instruction code from the memory at the PC address in the instruction control unit (fetch) ·Instruction interpretation (decode) ·Issue instruction to memory control unit / scalar registers / arithmetic unit control unit ·Instruction completion

[0016] The instructions in the prior art scalar processor include the following. ·Control instructions (jump, conditional branch, etc.) ·Load-store instructions: memory-register transfer instructions ·Arithmetic instructions: op (add, xor, mul, etc.) -Scalar × Scalar → Scalar - Immediate price × Scalar → Scalar

[0017] (Load / Store Instructions: Memory-to-Register Transfer Instructions) ◆Load instruction (immediate value) ld Si, (Immediate) • Pseudocode Si=Mem(Immediate): Load the data specified by address Immediate (immediate value) into Si. - The instruction control unit issues the ld instruction and an immediate value to the memory control unit. - Read issued from the memory control unit to memory at an immediate address. - Transfer replies from memory to scalar registers - Writing data to scalar register Si

[0018] ◆Load instruction (scalar value) ld Si, (Sj) • Pseudocode Si=Mem(Sj): Load the data specified by address Sj into Si - The instruction control unit issues the ld instruction and Sj to the scalar register. -ld instruction and Sj value from scalar register issued to memory control unit - Read issued from the memory control unit to memory, to the Sj value address. - Transfer replies from memory to scalar registers - Writing data to scalar register Si

[0019] ◆Store command (immediate value) st Si, (Immediate) • Pseudocode Mem(Immediate)=Si: Store Si at memory address Immediate (immediate value) - The instruction control unit issues the st instruction and Si to the scalar register. The -st instruction, an immediate value, and a Si value from a scalar register are sent to the memory control unit. - The memory control unit writes data Si to the immediate address in memory.

[0020] ◆Store instruction (scalar value) st Si, (Sj) • Pseudocode Mem(Sj)=Si: Store Si at memory address (Sj) - The instruction control unit issues the st instruction and Si and Sj to the scalar registers. The -st instruction and the Si and Sj values ​​from the scalar registers are sent to the memory control unit. - The memory control unit writes data Si to the Sj address in memory.

[0021] (Scalar arithmetic instructions: op(add, xor, mul, etc.)) ◆ Arithmetic instruction (scalar × immediate value) op Si, Sj, (Immediate) • Pseudocode: Si = Sj op(add, xor, mul, etc.) (Immediate): Store the result of the operation between Sj and Immediate (immediate value) in Si. - The instruction control unit issues Sj to the scalar register. - The instruction control unit issues calculations, Sj, and immediate values ​​to the arithmetic unit control unit. - The arithmetic unit performs the operation from Sj and the immediate value. - Write calculation result to scalar register Si

[0022] ◆ Arithmetic instruction (scalar × scalar value) op Si, Sj, Sk • Pseudocode: Si = Sj op(add, xor, mul, etc.) Sk: Sj (scalar value) and the result of the operation Sk (scalar value) are stored in Si. - The instruction control unit issues Sj and Sk to the scalar registers. - The instruction control unit issues calculations, Sj, and Sk to the arithmetic unit control unit. - The arithmetic unit performs calculations from Sj and Sk. - Write calculation result to scalar register Si

[0023] As example program 1, consider the following operation. • Scalar value A × Vector value X + Vector value Y (column direction) • Multiple executions in the row direction

[0024] ◆Vector Y ← Scalar A × Vector X + Vector Y for (j=0;j <J;j++) { for (i=0;i <I;i++) { Y[i,j]=A[j]*X[i,j]+Y[i,j] } }

[0025] Executing the above calculation on a conventional scalar processor yields the following result.

[0026] s11: Length J of A s12: Starting address of A s13: Length of X s14: Start address of X s15: Starting address of Y LoopA: ld s2, (s12) # Load A[j] add s3, s13, #0 #Initialize the length of X LoopX: ld s6, (s14) # Load X[i] Calculate mul s6, s2, s6 #A[j] x X[i] ld s7, (s15) #Load Y[i] add s7, s6, s7 #Calculate A[j] x X[i] + Y[i] st s7, (s15) # Store the result in Y[i] add s14, s14, #1 #X address + 1 add s15, s15, #1 #Y address + 1 sub s3, s3, #1 #X length - 1 bnz s3, LoopX #Check completion, if not complete, go to LoopX add s12,s12,#1 #A address + 1 sub s11,s11,#1 #A length -1 bnz s11,LoopA #Check completion, if not complete, go to LoopA

[0027] The number of instructions in an example execution using a conventional scalar processor is as follows: • Number of instructions = (9 × I + 5) × J If I,J=100, the number of instructions = 90500

[0028] As program example 2, let's consider the matrix-vector product operation.

[0029] ◆Vector Z ← Matrix (M rows × K columns) X × Vector Y + Vector Z for (j=0;j <M;j++) { for (i=0;i <K;i++) { Z[j]=X[i,j]*Y[i]+Z[j] } }

[0030] Executing the above calculation on a conventional scalar processor yields the following result.

[0031] s11:M s12:K s13: Starting address of X s14: Starting address of Y s15: Starting address of Z LoopM: add s4, s14, #0 #Initialize the starting address of Y add s2, s12, #0 #Initialize Y length = K ld s8, (s15) #Load Z[j] LoopK: ld s6, (s13) # Load X[i,j] ld s7, (s4) #Load Y[i] mul s7, s6, s7 #Calculate X[i,j]*Y[i] Add s8, s7, s8 #Calculate X[i,j]*Y[i]+Z[j] add s13, s13, #1 #X address + 1 add s4, s4, #1 #Y address + 1 sub s2, s2, #1 #Y length -1 bnz s2, LoopK # Check for completion, if not complete, go to LoopK st s8, (s15) #Store the result in Z[j] add s15,s15,#1 #Z address+1 sub s11,s11,#1 #Z length -1 bnz s11,LoopM #Check completion, if not complete, go to LoopM

[0032] The number of instructions in an example execution using a conventional scalar processor is as follows: • Number of instructions = (8 × K + 7) × M If K,M=100, the number of instructions = 80700

[0033] As program example 3, let's consider the matrix multiplication operation.

[0034] ◆Matrix Z ← Matrix (M rows x K columns) X × Matrix (K rows x N columns) Y + Matrix (M rows x N columns) Z for (k = 0; k <N;k++) { for (j=0;j <M;j++) { for (i=0;i <K;i++) { Z[k,j]=X[i,j]*Y[k,i]+Z[k,j] } } }

[0035] Executing the above calculation on a conventional scalar processor yields the following result.

[0036] s10:N s11:M s12:K s13: Starting address of X s14: Starting address of Y s15: Starting address of Z LoopN: add s1, s11, #0 #Z length = M initialization LoopM: add s2, s12, #0 #Initialize Y length = K ld s8, (s15) #Load Z[k,j] LoopK: ld s6, (s13) # Load X[i,j] ld s7, (s14) #Load Y[k,i] mul s7, s6, s7 #Calculate X[i,j]*Y[k,i] add s8, s7, s8 #Calculate X[i,j]*Y[k,i]+Z[k,j] add s13, s13, #1 #X address + 1 add s14, s14, #1 #Y address + 1 sub s2, s2, #1 #Y length -1 bnz s2, LoopK # Check for completion, if not complete, go to LoopK st s8, (s15) #Store the result in Z[j] add s15,s15,#1 #Z address+1 sub s1,s1,#1 #Z length -1 bnz s1,LoopM #Check completion, if not complete, go to LoopM sub s10,s10,#1 #N-1 bnz s10, LoopM # Check completion, if not complete, proceed to LoopN

[0037] The number of instructions in an example execution using a conventional scalar processor is as follows: • Number of instructions = ((8 × K + 6) × M + 3) × N If K, M, N = 100, the number of instructions = 8,060,300

[0038] Figure 2 shows a schematic configuration of the first conventional vector processor. The scalar processor shown in Figure 2 is based on a RISC architecture such as RISC-V and has a load-store architecture (register-register architecture).

[0039] The first conventional vector processor shown in Figure 2 has a configuration in which a vector unit is added to the scalar processor shown in Figure 1, and the vector unit is provided with vector registers.

[0040] A vector register has multiple vector registers (V0, V1, ..., Vn), and in the example shown in Figure 2 there are 4, but in RISC-V there can be up to 32. Each vector register is composed of elements (Vi[0], Vi[1], ..., Vi[MAXVL-1]) with a maximum vector length (MAXVL). Note that in the example shown in Figure 2 there are 4 elements, but in RISC-V there can be up to 65,536 elements.

[0041] Vector registers, like scalar registers, are connected to the instruction control unit, memory control unit, and arithmetic unit control unit. The arithmetic unit may be shared between the scalar and vector units, or each unit may have its own arithmetic unit. Figure 2(a) shows an example configuration in which the scalar and vector units share an arithmetic unit, while Figure 2(b) shows an example configuration in which each unit has its own arithmetic unit. Note that if each unit has its own arithmetic unit, scalar and vector operations can be processed in parallel, resulting in up to twice the performance.

[0042] Conventional vector processor instructions include the following: • VL (Vector Length) setting command • Vector load / store instructions: Instructions for transferring data between memory and vector registers. • Vector operation instructions: vop (add, xor, mul, etc.) -Vector × Vector → Vector -Vector × Vector → Scalar - Vector × Scalar → Vector (Scalar → Vector (including element 0)) - Vector × Scalar → Scalar (Vector (element 0) → Scalar included)

[0043] ◆VL (Vector Length) setting command ·VL setting command setvl Si, [Sj / Immediate] Pseudocode Si=if [Sj / Immediate]≦MAXVL then [Sj / Immediate] else MAXVL Specify the AVL (Application VL) as a scalar value. If AVL ≤ MAXVL (Maximum Vector Length), write AVL to Si; otherwise, write MAXVL to Si to set VL. -If the source is Sj, read Sj from the scalar register. - In the instruction control unit, compare Sj or the immediate value with MAXVL. -Set VL and write data to scalar register Si.

[0044] ◆Vector Load / Store Instructions: Instructions for transferring data between memory and vector registers. • Vector load instruction (scalar value) vld Vi, ([Sj / immediate value / Vj[0]]),s • As a scalar value, Sj / immediate value / Vj[0] (vector register element #0) can be specified. Pseudocode for (k = 0; k <VL;k++) { Vi[k]=Mem([Sj / Immediate / Vj[0]+k*s]) } Load VL consecutive data points (each s:stride) specified by the address (scalar value / immediate value) into Vi. (1) The instruction control unit issues the vld instruction, scalar value / immediate value, VL, and stride to the memory control unit. (2) The memory control unit issues a read to memory at the address (scalar / immediate value + s*k). (3) Transfer the reply from memory to the vector register (4) Writing data to vector register Vi[k] (5) k = k + 1, k <VLなら、(2)へ

[0045] ◆Vector Load / Store Instructions: Instructions for transferring data between memory and vector registers. • Vector index loading (Gather) command: vld Vi, (Vj) Pseudocode for (k = 0; k <VL;k++) { Vi[k]=Mem(Vj[k]) } Load VL data points specified by the address (Vj: vector value) = index into Vi. (1) The instruction control unit issues the vld instruction and vectors Vj and VL to the memory control unit. (2) The memory control unit issues a read to the memory at the address (Vj[k] vector value). (3) Transfer the reply from memory to the vector register Vi (4) Writing data to vector register Vi[k] (5) k = k + 1, k <VLなら、(2)へ

[0046] ◆Vector Load / Store Instructions: Instructions for transferring data between memory and vector registers. • Vector store instruction (scalar value) vst Vi, ([Sj / immediate value / Vj[0]]),s • As a scalar value, Sj / immediate value / Vj[0] (vector register element #0) can be specified. Pseudocode for (k = 0; k <VL;k++) { Mem([Sj / Immediate / Vj[0]+k*s])=Vi[k] } VL Vi data items are stored at consecutive addresses (s:stride) specified by the address (scalar value / immediate value). (1) The instruction control unit issues the vst instruction, scalar value / immediate value, VL, and stride to the memory control unit. (2) Transfer Vi[k] from the vector register to the memory control unit. (3) The memory control unit writes Vi[k] to memory at the address (scalar / immediate value + s*k). (4) k = k + 1, k <VLなら、(2)へ

[0047] ◆Vector Load / Store Instructions: Instructions for transferring data between memory and vector registers. • Vector index store (Scater) command vst Vi, (Vj) Pseudocode for (k = 0; k <VL;k++) { Mem(Vj[k])=Vi[k] } Store VL data points Vi into the memory specified by the address (Vj: vector value) = index. (1) The instruction control unit issues the vst instruction and vectors Vj and VL to the memory control unit. (2) Transfer Vi[k] from the vector register to the memory control unit. (3) The memory control unit writes Vi[k] to memory at address (Vj[k]). (4) k = k + 1, k <VLなら、(2)へ

[0048] ◆Vector operation instructions: vop (vadd, vxor, vmul, etc.) • Vector operation instructions (vector × vector → vector): vop, Vi, Vj, Vk Pseudocode for (l=0;l <VL;l++) { Vi[l]=Vj[l] vop Vk[l] } The result of the operation between Vj and Vk for each element of the vector is stored in Vi. (1) The instruction control unit issues Vj, Vk, and VL to the vector registers. (2) The instruction control unit issues calculations and Vj and Vk to the arithmetic unit control unit. (3) The arithmetic unit performs operations from Vj[l] and Vk[l]. (4) Write the calculation result to the vector register Vi[l] (5) l = l + 1, l <VLなら、(3)へ

[0049] ◆Vector operation instructions: vop (vadd, vxor, vmul, etc.) • Vector operation instructions (vector × vector → scalar): dot (dot product) ([Si / Vi[0]]), Vj, Vk -As a scalar value, Si / Vi[0] (element #0 of vector register Vi) can be specified. Pseudocode for (l=0;l <VL;l++) { temp = Vj[l] × Vk[l] + temp } [Si|Vi[0]]=temp The inner product of vectors Vj and Vk is stored in [Si|Vi[0]]. (1) The instruction control unit issues Vj, Vk, and VL to the vector registers. (2) The instruction control unit issues calculations and Vj and Vk to the arithmetic unit control unit. (3) The arithmetic unit executes the operation Vj[l] × Vk[l] + temp (4) l = l + 1, l <VLなら、(3)へ (5) Write temporary data to [Si|Vi[0]]

[0050] ◆Vector operation instructions: vop (vadd, vxor, vmul, etc.) • Vector operation instruction (vector × scalar → vector): vop Vi, Vj, [Sk|immediate value|Vk[0]] - The scalar value is Sk / immediate value / Vk[0] (vector register element #0) Pseudocode for (l=0;l <VL;l++) { Vi[l]=Vj[l] vop [Sk|Immediate|Vk[0]] } For each element of the vector, the result of the operation between Vj and the scalar value is stored in Vi. (1) The instruction control unit issues Vj, a scalar value, and VL to the vector register. (2) The instruction control unit issues calculations, Vj, and scalar values ​​to the arithmetic unit control unit. (3) The arithmetic unit performs operations from Vj[l] and [Sk|immediate value|Vk[0]]. (4) Write the calculation result to the vector register Vi[l] (5) l = l + 1, l <VLなら、(3)へ • As a special case, - Vector → Vector (vector element transfer such as vmv, compress, etc.) - Scalar to Vector (Transfer from scalar register to vector register)

[0051] ◆Vector operation instructions: vop (vadd, vxor, vmul, etc.) • Vector operation instruction (vector × scalar → scalar): vop [Si|Vi[0]], Vj, [Sk|immediate value|Vk[0]] -Examples of operations: vmax (maximum value), vsum (sum) • As a scalar value, it is Sk / immediate value / Vk[0] (vector register element #0) Pseudocode temp=[Sk|Immediate value|Vk[0]] for (l=0;l <VL;l++) { temp=Vj[l] vop temp } [Si|Vi[0]]=temp The result of operations on each element of a scalar value and a vector is stored in a scalar. (1) The instruction control unit issues Vj, a scalar value, and VL to the vector register. (2) The instruction control unit issues calculations, Vj, and scalar values ​​to the arithmetic unit control unit. (3) The arithmetic unit performs operations on Vj[l] and temp. (4) l = l + 1, l <VLなら、(3)へ (5) Write temporary data to [Si|Vi[0]] • As a special case, - Vector to Scalar (Transfer from a vector register to a scalar register)

[0052] Figure 3 shows a schematic configuration of a second conventional vector processor. The second conventional vector processor shown in Figure 3 has a configuration in which the vector units in the vector processor shown in Figure 2 are separated into two lanes, and each vector unit is provided with vector registers that are divided into even and odd lanes.

[0053] In the second conventional vector processor shown in Figure 3, operations on vector elements are performed in parallel on each lane. Therefore, the second conventional vector processor shown in Figure 3 has up to twice the performance of the first conventional vector processor shown in Figure 2.

[0054] Figure 4 shows a schematic configuration of a third conventional vector processor. The third conventional vector processor shown in Figure 4 has a configuration in which the vector units in the vector processor shown in Figure 2 are separated into lanes of the maximum vector length, and each vector unit is provided with a vector register for one element of the vector (typical Packed SIMD).

[0055] In the third conventional vector processor shown in Figure 4, operations on vector elements are performed in parallel on each lane. Therefore, the third conventional vector processor shown in Figure 4 has performance equal to the maximum vector length (number of lanes) of the first conventional vector processor shown in Figure 2.

[0056] As example program 1, consider the following operation. • Scalar value A × Vector value X + Vector value Y (column direction) • Multiple executions in the row direction

[0057] ◆Vector Y ← Scalar A × Vector X + Vector Y for (j=0;j <J;j++) { for (i=0;i <I;i++) { Y[i,j]=A[j]*X[i,j]+Y[i,j] } }

[0058] Executing the above calculation using a conventional vector processor yields the following result.

[0059] s11: Length J of A s12: Starting address of A s13: Length of X s14: Start address of X s15: Starting address of Y LoopA: ld s2, (s12) # Load A[j] setvl s3, s13 # Set the vector length to the length of X Vld v6, (s14) #X[i] vector load vld v7, (s15) #Vector load Y[i] vmac v7, s2, v6 # Vector calculation of A[j] x X[i] + Y[i] vst v7, (s15) #Store the result in Y[i] as a vector add s12,s12,#1 #A address + 1 sub s11,s11,#1 #A length -1 bnz s11,LoopA #Check completion, if not complete, go to LoopA

[0060] The number of instructions in an example execution using a conventional vector processor is as follows: • Number of instructions = 9 × J If I,J=100, the number of instructions = 900 • Computational performance: Multiple lanes

[0061] As program example 2, let's consider the matrix-vector product operation.

[0062] ◆Vector Z ← Matrix (M rows × K columns) X × Vector Y + Vector Z for (j=0;j <M;j++) { for (i=0;i <K;i++) { Z[j]=X[i,j]*Y[i]+Z[j] } }

[0063] Executing the above calculation using a conventional vector processor yields the following result.

[0064] s11:M s12:K s13: Starting address of X s14: Starting address of Y s15: Starting address of Z LoopM: ld s8, (s15) # Load Z[j] setvl s2, s12 # Set vector length by K vld v6, (s13) #Vector load X[i,j](i) vld v7, (s14) #Vector load Y[i] vdot s8, v6, v7 #Calculate the dot product of X[i,j] and Y[i] + Z[j] st s8, (s15) #Store the result in Z[j] add s15,s15,#1 #Z address+1 sub s11,s11,#1 #Z length -1 bnz s11,LoopM #Check completion, if not complete, go to LoopM

[0065] The number of instructions in an example execution using a conventional vector processor is as follows: • Number of instructions = 9 × M If K,M=100, the number of instructions = 900. • Computational performance: Multiple lanes

[0066] As program example 3, let's consider the matrix multiplication operation.

[0067] ◆Matrix Z ← Matrix (M rows x K columns) X × Matrix (K rows x N columns) Y + Matrix (M rows x N columns) Z for (k = 0; k <N;k++) { for (j=0;j <M;j++) { for (i=0;i <K;i++) { Z[k,j]=X[i,j]*Y[k,i]+Z[k,j] } } }

[0068] Executing the above calculation using a conventional vector processor yields the following result.

[0069] s10:N s11:M s12:K s13: Starting address of X s14: Starting address of Y s15: Starting address of Z LoopN: add s1, s11, #0 #Z length = M initialization LoopM: ld s8, (s15) # Load Z[k,j] setvl s2, s12 # Set vector length by K vld v6, (s13) #Vector load X[i,j](i) vld v7, (s14) #Vector load Y[k,i] vdot s8, v6, v7 #Calculate the dot product of X[i,j] and Y[k,i] + Z[k,j] st s8, (s15) #Store the result in Z[k,j] add 15,s15,#1 #Z address+1 sub s1,s1,#1 #Z length -1 bnz s1,LoopM #Check completion, if not complete, go to LoopM sub s10,s10,#1 #N-1 bnz s10,LoopN #Check completion, if not complete, go to LoopN

[0070] The number of instructions in an example execution using a conventional vector processor is as follows: • Number of instructions = (9 × M + 3) × N If K, M, N = 100, the number of instructions = 90300. • Computational performance: Multiple lanes

[0071] [Processor of the embodiment] Figure 5 is a diagram showing the schematic configuration of a scalar processor according to the first embodiment of this disclosure. The scalar processor according to the first embodiment shown in Figure 5 is an extension of the scalar processor shown in Figure 1 by bundling scalar registers.

[0072] Bundle extension consists of a maximum number of bundles (MAXBN) of scalar registers {(S0(0), S1(0), ..., Sn(0)), (S0(1), S1(1), ..., Sn(1)), ... (S0(MAXBN-1), S1(MAXBN-1), ..., Sn(MAXBN-1))} (MAXBN=4 in Figure 5), compared to the conventional scalar registers (S0, S1, ..., Sn) (4 in Figure 5, 32 in RISC-V). Note that the conventional scalar registers (S0, S1, ..., Sn) are the same as bundle number #0 (S0(0), S1(0), ..., Sn(0)).

[0073] The scalar processor of the first embodiment shown in Figure 5 comprises an instruction control unit, a memory control unit, scalar registers, an arithmetic unit control unit, and an arithmetic unit. The instruction control unit includes a program counter (PC) and controls the fetching, decoding, issuing, and retirement of instructions from memory. The memory control unit performs data transfer between memory and registers based on instructions from the instruction control unit. The scalar registers consist of multiple scalar registers. The arithmetic unit control unit controls the relationship between the arithmetic unit and the scalar registers based on instructions from the instruction control unit. The arithmetic unit generally consists of a multiply-accumulate (FMA) and an ALU. The scalar processor of the first embodiment operates similarly to a vector processor through bundle extension of the scalar processor.

[0074] An example of instruction operation in the scalar processor of the first embodiment is as follows: • The instruction control unit reads (fetches) the instruction code from memory at the PC address. • Instruction interpretation (decoding) • Issuing instructions to the memory control unit / scalar register / arithmetic unit control unit. ·Order completed

[0075] The scalar processor of the first embodiment is provided with an instruction to set the number of bundles. • If the number of bundles is 1, it operates as before. (S0(0), S1(0), ..., Sn(0)) • If the number of bundles > 1, the following instructions are extended. - Load / Store Instructions: Memory-to-Register Transfer Instructions - Arithmetic instructions: op (add, xor, mul, etc.) *Scalar x Scalar → Scalar Extension ⇒ Scalar (bundle) x Scalar (bundle) → Scalar (bundle); (⇒ You can also add Scalar (bundle) x Scalar (bundle) → Scalar) *Immediate value × Scalar → Scalar Extension ⇒ Immediate value × Scalar (bundle) → Scalar (bundle); (⇒ You can also add Immediate value × Scalar (bundle) → Scalar)

[0076] ◆ Bundle number (number of bundles) setting command ·setbn Si, [Sj / Immediate] Pseudocode Si=if [Sj / Immediate]≦MAXBN then [Sj / Immediate] else MAXBN The number of bundles is specified as a scalar value. If the number of bundles is less than or equal to MAXBN (maximum number of bundles), the number of bundles is written to Si; otherwise, MAXBN is written to Si, and BN (number of bundles) is set. (1) If the source is Sj, read Sj(0) from the scalar register. (2) The instruction control unit compares Sj(0) or an immediate value with MAXBN. (3) Set BN and write data to scalar register Si(0)

[0077] ◆ Bundle extensions for load and store instructions: Memory-to-register transfer instructions • Load instruction (immediate value): ld Si, (Immediate) Pseudocode for (k = 0; k <BN;k++) { Si(k) = Mem([Immediate+k]) } Load BN consecutive data points specified by address Immediate (immediate value) into Si. (1) The instruction control unit issues the ld instruction, an immediate value, and BN to the memory control unit. (2) The memory control unit issues a read to memory at an address of (immediate value + k). (3) Transfer the reply from memory to a scalar register (4) Writing data to scalar register Si(k) (5) k = k + 1, k <BNなら、(2)へ Also, as with vector processors, you can specify the stride.

[0078] ◆ Bundle extensions for load and store instructions: Memory-to-register transfer instructions • Load instruction (scalar value) ld Si, (Sj) Pseudocode for (k = 0; k <BN;k++) { Si(k) = Mem([Sj(k)]) } Loads BN data points specified by address (Sj(k)) into Si(k). This is equivalent to a vector index load (Gather) instruction. (1) The instruction control unit issues the ld instruction and the scalar Sj and BN to the memory control unit. (2) The memory control unit issues a read to memory at the address (Sj(k) scalar value). (3) Transfer the reply from memory to a scalar register (4) Writing data to scalar register Si(k) (5) k = k + 1, k <BNなら、(2)へ

[0079] ◆ Bundle extensions for load and store instructions: Memory-to-register transfer instructions • Store command (immediate value): st Si, (Immediate) Pseudocode for (k = 0; k <BN;k++) { Mem([Immediate+k])=Si(k) } Store BN Si data points into consecutive addresses specified by their addresses (immediate values). (1) The instruction control unit issues the st instruction, an immediate value, and BN to the memory control unit. (2) Transfer Si(k) from the scalar register to the memory control unit. (3) The memory control unit writes Si(k) to memory at the address (immediate value + k). (4) k = k + 1, k <BNなら、(2)へ Also, as with vector processors, you can specify the stride.

[0080] ◆ Bundle extensions for load and store instructions: Memory-to-register transfer instructions • Store instruction (scalar value): ld Si, (Sj) Pseudocode for (k = 0; k <BN;k++) { Mem([Sj(k)])=Si(k) } This instruction stores BN data points Si into memory specified by the address (Sj: scalar value) = index. This is equivalent to a vector index store (Scatter) instruction. (1) The instruction control unit issues the st instruction and the scalar Sj and BN to the memory control unit. (2) Transfer Si(k) from the scalar register to the memory control unit. (3) The memory control unit writes Si(k) to the memory at the address (Sj(k)). (4) k = k + 1, k <BNなら、(2)へ

[0081] ◆ Bundle extension for scalar arithmetic instructions: op (add, xor, mul, etc.) • Arithmetic instruction (scalar × immediate value) op Si, Sj, (Immediate) Pseudocode for (k = 0; k <BN;k++) { Si(k) = Sj(k) op(add,xor,mul etc.) (Immediate) } Extend the scalar × immediate value → scalar operation to scalar operations in each bundle. ⇒ Scalar (bundle) × immediate value → Scalar (bundle) The result of the operation between Sj(k) and Immediate is stored in Si(k). (1) The instruction control unit issues Sj to the scalar register. (2) The instruction control unit issues calculations, Sj, and immediate values ​​to the arithmetic unit control unit. (3) The arithmetic unit performs the operation from Sj(k) and the immediate value. (4) Writing the calculation result to the scalar register Si(k) (5) k = k + 1, k <BNなら、(3)へ

[0082] ◆ Bundle extension for scalar arithmetic instructions: op (add, xor, mul, etc.) • Arithmetic instruction (scalar × scalar value) op Si, Sj, Sk Pseudocode for (k = 0; k <BN;k++) { Si(k) = Sj(k) op(add,xor,mul etc.) Sk(k) } Extend the scalar × scalar → scalar operation to scalar operations within each bundle. ⇒ Scalar (bundle) × Scalar (bundle) → Scalar (bundle) The result of the operation between Sj(k) (scalar value) and Sk(k) (scalar value) is stored in Si(k). (1) The instruction control unit issues Sj and Sk to the scalar registers. (2) The instruction control unit issues calculations, Sj, and Sk to the arithmetic unit control unit. (3) The arithmetic unit performs operations from Sj(k) and Sk(k). (4) Writing the calculation result to the scalar register Si(k) (5) k = k + 1, k <BNなら、(3)へ

[0083] ◆ Bundle extension for scalar arithmetic instructions: op (add, xor, mul, etc.) • Arithmetic instructions • In vector operation instructions, • Vector × Vector → Scalar -Example: Vector dot product instruction • Vector × Scalar → Vector -Examples: vector element-to-element transfer, scalar to vector (element 0) transfer Vector × Scalar → Scalar -Example: Maximum value, sum, vector (element 0) → scalar transfer Similarly, • Scalar (bundle) × Scalar (bundle) → Scalar • Scalar (bundle) × Scalar → Scalar (bundle) • Scalar (bundle) × Scalar → Scalar You may define instructions. In this case, the scalar specifies bundle number #0 (S0(0), S1(0), ..., Sn(0)).

[0084] Figure 6 shows a schematic configuration of a scalar processor according to the second embodiment of this disclosure. The scalar processor according to the second embodiment shown in Figure 6 is a bundle extension of the scalar processor shown in Figure 1, by dividing the scalar units into bundle blocks.

[0085] The scalar processor according to the second embodiment shown in Figure 6 divides the scalar bundle registers into even bundle blocks and odd bundle blocks, and each block is equipped with an arithmetic unit.

[0086] Figure 7 shows a schematic configuration of a scalar processor according to the third embodiment of this disclosure. The scalar processor according to the third embodiment shown in Figure 7 is a bundle expansion of the scalar processor shown in Figure 1, by dividing the scalar units into bundle blocks up to the maximum number of bundles.

[0087] The scalar processor according to the third embodiment shown in Figure 7 is divided into bundle blocks equal to the maximum number of bundles, so each block has only one scalar register. Furthermore, the scalar processor according to the third embodiment shown in Figure 7 has an arithmetic unit in each block. The performance is multiplied by the maximum number of bundles.

[0088] Figure 8 shows a schematic configuration of a scalar processor according to the fourth embodiment of this disclosure. The scalar processor according to the fourth embodiment shown in Figure 8 has an instruction control unit (PC) configured in each block compared to the scalar processor according to the second embodiment shown in Figure 6. Therefore, the scalar processor according to the fourth embodiment has a configuration in which scalar registers are shared in a multi-scalar core.

[0089] Each instruction control unit accesses the block's scalar registers starting from bundle number #0. In other words, instruction control unit #0 accesses bundle register S(0) of instruction control unit #i as bundle register S(i).

[0090] As example program 1, consider the following operation. • Scalar value A × Vector value X + Vector value Y (column direction) • Multiple executions in the row direction

[0091] ◆Vector Y ← Scalar A × Vector X + Vector Y for (j=0;j <J;j++) { for (i=0;i <I;i++) { Y[i,j]=A[j]*X[i,j]+Y[i,j] } }

[0092] Executing the above calculation on the scalar processor of the embodiment yields the following result.

[0093] s11: Length of A s12: Starting address of A s13: Length of X s14: Start address of X s15: Starting address of Y LoopA: ld s2, (s12) # Load A[j] setbn s3, s13 # Set the number of bundles by length X ld s6, (s14(0)) # Load X[i] for the number of bundles ld s7, (s15(0)) # Load Y[i] for the number of bundles mac s7, s2(0), s6 #Calculate A[j] x X[i] + Y[i] for each bundle. vst s7, (s15(0)) #Store the results in Y[i] for the number of bundled units setbn s3, #1 #Set bundle count to 1 add s12,s12,#1 #A address + 1 sub s11,s11,#1 #A length -1 bnz s11,LoopA #Check completion, if not complete, go to LoopA

[0094] The number of instructions in the execution example on a scalar processor of the embodiment is as follows: • Number of instructions = 10 × J If I,J=100, the number of instructions = 1000 • Computational performance: Multiple bundle blocks

[0095] As program example 2, let's consider the matrix-vector product operation.

[0096] ◆Vector Z ← Matrix (M rows × K columns) X × Vector Y + Vector Z for (j=0;j <M;j++) { for (i=0;i <K;i++) { Z[j]=X[i,j]*Y[i]+Z[j] } }

[0097] Executing the above calculation on the scalar processor of the embodiment yields the following result.

[0098] s11:M s12:K s13: Starting address of X s14: Starting address of Y s15: Starting address of Z LoopM: ld s8, (s15) # Load Z[j] setbn s2, s12 # Set the number of bundles with K ld s6, (s13(0)) #Load X[i,j] into bundles (i) ld s7, (s14(0)) # Load Y[i] for the number of bundles dot s8(0), s6, s7 #Calculate the dot product of X[i,j] and Y[i] + Z[j] setbn s2, #1 # Sets the number of bundles to 1 (scalar operation) st s8, (s15) #Store the result in Z[j] add s15,s15,#1 #Z address+1 sub s11,s11,#1 #Z length -1 bnz s11,LoopM #Check completion, if not complete, go to LoopM

[0099] The number of instructions in the execution example on a scalar processor of the embodiment is as follows: • Number of instructions = 10 × M If K,M=100, the number of instructions = 1000 • Computational performance: Multiple bundle blocks

[0100] As program example 3, let's consider the matrix multiplication operation.

[0101] ◆Matrix Z ← Matrix (M rows x K columns) X × Matrix (K rows x N columns) Y + Matrix (M rows x N columns) Z for (k = 0; k <N;k++) { for (j=0;j <M;j++) { for (i=0;i <K;i++) { Z[k,j]=X[i,j]*Y[k,i]+Z[k,j] } } }

[0102] Executing the above calculation on the scalar processor of the embodiment yields the following result.

[0103] s10:N s11:M s12:K s13: Starting address of X s14: Starting address of Y s15: Starting address of Z LoopN: add s1, s11, #0 #Z length = M initialization LoopM: ld s8, (s15) # Load Z[k,j] setbn s2, s12 # Set the number of bundles with K ld s6, (s13(0)) # Vector load of X[i,j] (i) ld s7, (s14(0)) # Vector load of Y[k,i] dot s8(0), s6, s7 #Calculate the dot product of X[i,j] and Y[k,i] + Z[k,j] setbn s2, #1 # Sets the number of bundles to 1 (scalar operation from here on) st s8, (s15) #Store the result in Z[k,j] add s15,s15,#1 #Z address+1 sub s1,s1,#1 #Z length -1 bnz s1,LoopM #Check completion, if not complete, go to LoopM sub s10,s10,#1 #N-1 bnz s10,LoopN #Check completion, if not complete, go to LoopN

[0104] The number of instructions in the execution example on a scalar processor of the embodiment is as follows: • Number of instructions = (10 × M + 3) × N If K, M, N = 100, the number of instructions = 100300 • Computational performance: Multiple bundle blocks

[0105] Figure 9 is a diagram showing the schematic configuration of a vector processor according to the first embodiment of the present disclosure. The vector processor according to the first embodiment shown in Figure 9 has a configuration that bundles and extends scalar registers and vector registers compared to the first prior art vector processor shown in Figure 2.

[0106] Register bundle extension consists of the maximum number of bundles (MAXBN) of registers {(S0(0), ..., Sn(0)), ..., (S0(MAXBD-1), ..., Sn(MAXBD-1))} and {(V0(0), ..., Vn(0)), ..., (V0(MAXBD-1), ..., Vn(MAXBD-1))} (MAXBD=4 in Figure 9) for conventional scalar registers (S0, S1, ..., Sn) and vector registers (V0, V1, ..., Vn) (4 in Figure 9, 32 in RISC-V).

[0107] Conventional scalar registers (S0, S1, ..., Sn) and vector registers (V0, V1, ..., Vn) are identical to bundle numbers #0 (S0(0), S1(0), ..., Sn(0)) and (V0(0), V1(0), ..., Vn(0)).

[0108] The vector processor of the first embodiment shown in Figure 9 comprises an instruction control unit, a memory control unit, scalar registers, vector registers, an arithmetic unit control unit, and an arithmetic unit. The instruction control unit includes a program counter (PC) and controls the fetching, decoding, issuing, and retirement of instructions from memory. The memory control unit performs data transfer between memory and registers based on instructions from the instruction control unit. The scalar registers and vector registers are multiple scalar registers. The arithmetic unit control unit performs control between the arithmetic unit and scalar registers based on instructions from the instruction control unit. The arithmetic unit generally consists of a multiply-accumulate (FMA) and an ALU.

[0109] Figure 9(a) shows an example configuration in which the scalar unit and the vector unit share an arithmetic unit, while Figure 9(b) shows an example configuration in which the scalar unit and the vector unit each have their own arithmetic units. Note that when the scalar unit and the vector unit each have their own arithmetic units, scalar and vector operations can be processed in parallel, resulting in up to twice the performance.

[0110] An example of instruction operation in the vector processor of the first embodiment is as follows: • The instruction control unit reads (fetches) the instruction code from memory at the PC address. • Instruction interpretation (decoding) • Issuing instructions to the memory control unit / scalar register / arithmetic unit control unit. ·Order completed

[0111] ◆ Added a command to set the number of bundles (bundles). • If the number of bundles is 1, it operates as before. (V0(0), V1(0), ..., Vn(0)) • If the number of bundles > 1, the following instructions are extended. • Vector instruction operation for each bundle of instructions. • Vector load / store instructions: Instructions for transferring data between memory and vector registers. ·Arithmetic instructions: vop (add, xor, mul, etc.) -Vector × Vector → Vector Extension ⇒ Vector (bundle) × Vector (bundle) → Vector (bundle) -Vector × Vector → Scalar Extension ⇒ Vector (bundle) × Vector (bundle) → Scalar (bundle) / Vector - Vector × Scalar → Vector Extension ⇒ Vector (bundle) × Scalar (bundle) / Vector → Vector (bundle) - Vector × Scalar → Scalar Extension ⇒ Vector (bundle) × Scalar (bundle) → Scalar (bundle) / Vector

[0112] ◆ Bundle size setting instruction (similar to bundle extension in scalar processors) ·setbn Si, [Sj / Immediate] Pseudocode Si=if [Sj / Immediate]≦MAXBN then [Sj / Immediate] else MAXBN Specify the number of bundles with a scalar value, and if the number of bundles ≤ MAXBN (maximum number of bundles), write the number of bundles to Si, otherwise write MAXBN to Si, to set BN (number of bundles). (1) When the source is Sj, read Sj(0) from the scalar register (2) The instruction control unit compares Sj(0) or the immediate value with MAXBN (3) Set BN, and write data to the scalar register Si(0)

[0113] FIG. 10 is a diagram illustrating a schematic configuration of a vector processor according to a second embodiment of the present disclosure. The vector processor of the second embodiment illustrated in FIG. 10 has a configuration obtained by performing bundle extension on the vector processor of the second related art illustrated in FIG. 3. Further, the vector processor of the second embodiment illustrated in FIG. 10 can also be regarded as having a configuration in which the vector unit is divided into two lanes composed of even-numbered elements and odd-numbered elements, relative to the vector processor of the first embodiment illustrated in FIG. 9. The vector processor of the second embodiment illustrated in FIG. 10 includes an arithmetic unit in each lane.

[0114] FIG. 11 is a diagram illustrating a schematic configuration of a vector processor according to a third embodiment of the present disclosure. The vector processor of the third embodiment illustrated in FIG. 11 is obtained by performing bundle extension on the vector processor of the first related art illustrated in FIG. 2 by dividing the scalar unit and the vector unit into bundle blocks.

[0115] In the vector processor according to the third embodiment illustrated in FIG. 11, the scalar bundle register and the vector register are divided into an even-numbered bundle block and an odd-numbered bundle block, and each block is provided with an arithmetic unit.

[0116] Figure 12 shows a schematic configuration of a vector processor according to the fourth embodiment of this disclosure. The vector processor of the fourth embodiment shown in Figure 12 has a configuration in which the scalar bundle registers and vector registers are divided into even bundle blocks and odd bundle blocks compared to the vector processor of the second embodiment shown in Figure 10, and it can also be seen as having a configuration in which the vector units are divided into two lanes consisting of even elements and odd elements compared to the vector processor of the third embodiment shown in Figure 11. The vector processor of the fourth embodiment can achieve parallel acceleration by lane division and parallel acceleration by block division, and has up to four times the performance of the vector processor of the first embodiment shown in Figure 9.

[0117] Figure 13 shows a schematic configuration of a vector processor according to the fifth embodiment of this disclosure. The vector processor of the fifth embodiment shown in Figure 13 has the number of lane divisions set to the maximum vector length (VLMAX) and the number of bundle block divisions set to the maximum number of bundles, compared to the vector processor of the fourth embodiment shown in Figure 12.

[0118] Figure 14 is a diagram showing the schematic configuration of a vector processor according to the sixth embodiment of this disclosure. The vector processor of the sixth embodiment shown in Figure 14 is the vector processor of the fifth embodiment shown in Figure 13, in which an instruction control unit (PC) is configured in each bundle block.

[0119] As example program 1, consider the following operation. • Scalar value A × Vector value X + Vector value Y (column direction) • Multiple executions in the row direction

[0120] ◆Vector Y ← Scalar A × Vector X + Vector Y for (j=0;j <J;j++) { for (i=0;i <I;i++) { Y[i,j]=A[j]*X[i,j]+Y[i,j] } }

[0121] Executing the above calculations on the vector processor of the embodiment yields the following result.

[0122] s11: Length of A s12: Starting address of A (number of bundles) s13: Length of X s14: Starting address of X (number of bundles) s15: Starting address of Y (number of bundles) setbn s1, s11 # Set the number of bundles by the length of A ld s2, (s12) #Load A[j] for the number of bundles setvl s3, s13 # Set the vector length to the length of X vld v6, (s14) #Vector load X[i] for bundled number of times vld v7, (s15) #Vector load Y[i] bundles by number of units vmac v7, s2, v6 # Vector calculation of A[j] x X[i] + Y[i] for bundled numbers vst v7, (s15) # Store the results in Y[i] as a vector for the number of bundled values.

[0123] The number of instructions in the execution example using the vector processor of this embodiment is as follows: • Number of instructions = 7 If I,J=100, the number of instructions = 7

[0124] As program example 2, let's consider the matrix-vector product operation.

[0125] ◆Vector Z ← Matrix (M rows × K columns) X × Vector Y + Vector Z for (j=0;j <M;j++) { for (i=0;i <K;i++) { Z[j]=X[i,j]*Y[i]+Z[j] } }

[0126] When the above operation is executed by the vector processor of the embodiment, the result is as follows.

[0127] s11:M s12:K s13:Start address of X s14:Start address of Y s15:Start address of Z setvl s2, s12 #Set vector length with K vld v7, (s14) #Vector load Y[i] setbn s1, s11 #Set bundle count with M ld s8, (s15) #Load Z[j] for the number of bundles vld v6, (s13) #Vector load X[i,j] for the number of bundles vdot s8, v6, v7(0) #Calculate inner product of X[i,j] and Y[i] plus Z[j] st s8, (s15) #Vector store the result to Y[i] for the number of bundles

[0128] The number of instructions in the execution example on the vector processor of the embodiment is as follows. ·Number of instructions=7 When K,M=100, number of instructions=7

[0129] As Program Example 3, consider a matrix-matrix product operation.

[0130] ◆Matrix Z ← Matrix (M rows × K columns) X × Matrix (K rows × N columns) Y + Matrix (M rows × N columns) Z for (k=0;k<N;k++) { for (j=0;j<M;j++) { for (i=0;i<K;i++) { Z[k,j]=X[i,j]*Y[k,i]+Z[k,j] } } }

[0131] Executing the above calculations on the vector processor of the embodiment yields the following result.

[0132] s10:N s11:M s12:K s13: Starting address of X s14: Starting address of Y s15: Starting address of Z LoopN: setvl s2, s12 # Set vector length by K vld v7, (s14) #Vector load Y[k,i] setbn s1, s11 #M to set the number of bundles ld s8, (s15) #Load Z[k,j] for the number of bundles vld v6, (s13) #Vector load X[i,j] for the number of bundles vdot s8, v6, v7(0) #Calculate the dot product of X[i,j] and Y[k,i] + Z[k,j] st s8, (s15) # Store the results in Y[k,i] as a vector for the number of bundled values add s15,s15,#K #Z address+K add s14,s14,#K #Y address+K sub s10,s10,#1 #N-1 bnz s10, LoopM # Check completion, if not complete, proceed to LoopN

[0133] The number of instructions in the execution example on a scalar processor of the embodiment is as follows: • Number of instructions = 11 × N If K, M, N = 100, the number of instructions = 1100.

[0134] The configurations and functions of the conventional scalar processor and the scalar processor of the embodiment, as well as the configurations and functions of the conventional vector processor and the vector processor of the embodiment, have been described above. The processor of the embodiment has a significantly reduced number of instructions compared to the conventional processor. The number of instructions in example programs for the processor of the embodiment and the conventional processor is summarized below.

[0135] [Table 1]

[0136] Some or all of the above embodiments may also be described as follows, but are not limited to the following: [Note 1] The arithmetic unit and, Multiple registers, The instruction control unit fetches, decodes, issues, and retires instructions from memory, A memory control unit that performs data transfer between the memory and the registers based on an instruction from the instruction control unit, A processor comprising an arithmetic unit control unit that controls the relationship between the arithmetic unit and the registers based on instructions from the instruction control unit, The aforementioned multiple registers are bundled and extended in the processor to enable parallel processing of instructions. [Note 2] The processor described in Appendix 1, wherein the aforementioned multiple registers are bundle-extended by being divided into bundle blocks. [Note 3] The processor described in Appendix 2, wherein the aforementioned multiple registers are bundle-extended by dividing them into even-bundle blocks and odd-bundle blocks. [Note 4] The processor described in Appendix 2, wherein the aforementioned multiple registers are bundle-extended by being divided into bundle blocks of the maximum number of bundles. [Note 5] The aforementioned plurality of registers are vector registers for vector operations, and the processor is described in any one of the appendices 1 to 4, which are divided into lanes with respect to the vector elements. [Note 6] The aforementioned plurality of registers are divided into lanes of the maximum vector length, as described in Appendix 5. [Note 7] A processor described in any one of the appendices 1 through 6, which implements bundle extensions for load / store instructions and arithmetic instructions. [Note 8] A processor described in any one of the appendices 1 through 7, which implements bundle extensions for arithmetic instructions on scalars and / or vectors.

[0137] Furthermore, the disclosures of the above-mentioned patent documents and other materials cited are incorporated into this document by reference. Within the framework of the full disclosure of the present invention (including the claims), further modifications and adjustments to the embodiments or examples are possible based on the fundamental technical concept. Also, within the framework of the full disclosure of the present invention, various combinations or selections (including partial deletions) of various disclosure elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible. In other words, the present invention naturally includes the full disclosure, including the claims, and various modifications and alterations that a person skilled in the art could make in accordance with the technical concept. In particular, with respect to the numerical ranges described in this document, any numerical value or sub-range included within that range should be interpreted as being specifically described, even if not otherwise stated. Furthermore, the disclosures of the above-mentioned cited documents may, if necessary, be used in part or in whole as part of the disclosure of the present invention, in accordance with the spirit of the present invention, and these may also be considered to be included in the disclosures of this application.

Claims

1. The arithmetic unit and, Multiple registers, The instruction control unit fetches, decodes, issues, and retires instructions from memory, A memory control unit that performs data transfer between the memory and the registers based on an instruction from the instruction control unit, A processor comprising an arithmetic unit control unit that controls the relationship between the arithmetic unit and the registers based on instructions from the instruction control unit, The aforementioned multiple registers are bundled and extended in the processor to enable parallel processing of instructions.

2. The processor according to claim 1, wherein the plurality of registers are bundle-extended by being divided into bundle blocks.

3. The processor according to claim 2, wherein the plurality of registers are bundle-extended by dividing them into even-bundle blocks and odd-bundle blocks.

4. The processor according to claim 2, wherein the plurality of registers are bundle-extended by being divided into bundle blocks of the maximum number of bundles.

5. The processor according to any one of claims 1 to 4, wherein the plurality of registers are vector registers for vector operations, and are divided into lanes with respect to vector elements.

6. The processor according to claim 5, wherein the plurality of registers are divided into lanes of the maximum vector length.

7. The processor according to claim 1, which implements bundle extensions for load / store instructions and arithmetic instructions.

8. The processor according to claim 1, which implements bundle extensions for arithmetic instructions on scalars and / or vectors.

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