Imaging device

Abstract

By sharing the comparison unit, it enables edge detection based on the comparison results of pixel signals, as well as illumination detection for each pixel. [Solution] The imaging device comprises a plurality of pixels that output pixel signals, a comparison unit that receives the first pixel signal read from the first pixel as an input and compares the first input with the second input, and a switching unit that switches the second input of the comparison unit between the second pixel signal read from the second pixel and a reference signal. It may also include a level setting circuit that sets the signal level of at least one of the two pixel signals by a predetermined gain.

Description

TECHNICAL FIELD

[0001] The present technology relates to an imaging apparatus. Specifically, the present technology relates to an imaging apparatus capable of edge detection and illuminance detection. BACKGROUND ART

[0002] In imaging apparatuses, edge determination of an image may be performed based on a comparison result of two pixel signals. For example, a technology is disclosed that determines the presence or absence of an edge based on a comparison result of a pair of pixel signals in which the signal level of one of the pair of pixel signals is increased or decreased by a predetermined gain (see, for example, Patent Document 1). PRIOR ART DOCUMENTS PATENT DOCUMENTS

[0003] PATENT DOCUMENT 1 International Publication No. 2021 / 090538 SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0004] However, the above-described conventional technology can perform edge detection based on the comparison result of pixel signals, but does not disclose a technology for detecting the illuminance of the pixel signals.

[0005] The present technology has been created in view of such circumstances, and an object thereof is to enable edge detection based on the comparison result of pixel signals and illuminance detection of each pixel while sharing a comparison unit. MEANS FOR SOLVING THE PROBLEMS

[0006] This technology was developed to solve the aforementioned problems, and its first aspect is an imaging device comprising: a plurality of pixels that output pixel signals; a comparison unit that receives the first pixel signal read from the first pixel as an input and compares the first input with a second input; and a switching unit that switches the second input of the comparison unit between the second pixel signal read from the second pixel and a reference signal. This allows for edge detection based on the comparison result of the pixel signals and illumination detection of each pixel, while sharing the comparison unit.

[0007] Furthermore, in the first aspect, the system may include a level setting circuit that sets the signal level of at least one of the first pixel signal and the second pixel signal by a predetermined gain. This allows for edge detection based on the comparison result of the pixel signals and illumination detection of each pixel, even if the relative magnitudes of the first and second pixel signals are unknown, while sharing the comparison unit.

[0008] Furthermore, in the first aspect, the system may include a gain switching control unit that switches the gain of the level setting circuit based on the comparison result between the first pixel signal and the reference signal. This improves the edge detection accuracy based on the comparison result of the pixel signals.

[0009] Furthermore, in the first aspect, the switching unit may include a cutoff switch for blocking the input of the second pixel signal to the second input, and a reference switch for switching the input of the reference signal to the second input. This results in the reference signal being input to the second input of the comparison unit instead of the second pixel signal.

[0010] Furthermore, in the first aspect, the reference switch may be connected to the second input side of the cutoff switch. This results in the input of the second pixel signal being cut off via the cutoff switch while the reference signal is input to the second input of the comparison unit.

[0011] Furthermore, in the first aspect, the system may include a first input capacitor connected to the first input, a second input capacitor connected to the second input, and a reference capacitor to which the reference signal is applied via the reference switch and which is connected in parallel to the second input capacitor. This enables auto-zeroing of the comparison unit while also allowing the dark level of the pixels to be reflected in the second input of the comparison unit via the reference capacitor.

[0012] Furthermore, in the first aspect, the system may include a first input capacitor connected to the first input, a second input capacitor connected to the second input, and a reference capacitor to which the reference signal is applied via the reference switch and which is connected between the second input capacitor and the cutoff switch. This enables auto-zeroing of the comparison unit while also allowing the dark level of the pixels to be reflected in the second input of the comparison unit via the reference capacitor.

[0013] Furthermore, in the first aspect, the system may include a reference signal generation unit that generates the reference signal. This results in the reference voltage being supplied from the reference signal generation unit to the comparison unit.

[0014] Furthermore, in the first aspect, the reference signal may be set to a value that allows for the determination of the saturation level of the pixel. This results in the determination of the saturation level of the pixel based on the comparison result between the second pixel signal and the reference signal.

[0015] Furthermore, in the first aspect, the reference signal may be switchable to multiple levels. This has the effect of improving the accuracy of illuminance determination based on the comparison result between the second pixel signal and the reference signal.

[0016] Furthermore, in the first aspect, the system may include a first holding unit that holds the comparison result between the first pixel signal and the second pixel signal, and a second holding unit that holds the comparison result between the first pixel signal and the reference signal. This ensures that the edge determination result and the illuminance determination result are retained even when the second input of the comparison unit is switched between the second pixel signal and the reference signal.

[0017] Furthermore, in the first aspect, a counter may be provided that performs a counting operation based on the comparison result between the first pixel signal and the reference signal. This results in the determination of the number of pixels that are equal to or greater than a predetermined signal level.

[0018] Furthermore, in the first aspect, the system may include an offset switching control unit that controls the offset during the comparison of the first pixel signal and the second pixel signal based on the comparison result between the first pixel signal and the reference signal. This results in the offset of the comparison unit during edge detection being optimized.

[0019] Furthermore, in the first aspect, the system may include an accumulation time control circuit that controls the accumulation time of the pixel based on the comparison result between the first pixel signal and the reference signal. This results in the amount of charge accumulated in the pixel being optimized according to the incident intensity.

[0020] Furthermore, in the first aspect, the accumulation time control circuit may control the accumulation time of the pixels in units of a predetermined number of frames. This eliminates the need to control the accumulation time for each pixel, while optimizing the amount of charge accumulated in the pixels according to the incident intensity.

[0021] Furthermore, in the first aspect, in controlling the accumulation time of the pixels, an edge-signal level image in which both edges and signal levels have been determined, and an edge image in which only edges have been determined, may be switched at a predetermined number of frame intervals. This eliminates the need for signal level determination for each frame, while still allowing edge determination to be performed for each frame. [Brief explanation of the drawing]

[0022] [Figure 1] This is a block diagram showing an example configuration of an imaging device according to the first embodiment. [Figure 2] This is a block diagram showing an example configuration of a solid-state imaging device according to the first embodiment. [Figure 3]This is a diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. [Figure 4] This is a cross-sectional view showing an example of a configuration of a pixel array section provided in the solid-state imaging device according to the first embodiment. [Figure 5] This is a cross-sectional view showing a modification example of the pixel array section provided in the solid-state imaging device according to the first embodiment. [Figure 6] This is a block diagram showing an example of a configuration of a signal readout circuit according to the first embodiment. [Figure 7] This is a block diagram showing an example of a configuration of a signal readout circuit according to the second embodiment. [Figure 8] This is a timing chart showing waveforms of respective sections during operation of the signal readout circuit according to the second embodiment. [Figure 9] This is a block diagram showing an example of a configuration of a signal readout circuit according to the third embodiment. [Figure 10] This is a block diagram showing an example of a configuration of a signal readout circuit according to the fourth embodiment. [Figure 11] This is a timing chart showing waveforms of respective sections during operation of the signal readout circuit according to the fourth embodiment. [Figure 12] This is a block diagram showing an example of a configuration of a signal readout circuit according to the fifth embodiment. [Figure 13] This is a block diagram showing an example of a configuration of a solid-state imaging device according to the sixth embodiment. [Figure 14] This is a block diagram showing an example of a configuration of a solid-state imaging device according to the seventh embodiment. [Figure 15] This is a block diagram showing an example of a configuration of a solid-state imaging device according to the eighth embodiment. [Figure 16] This is a block diagram showing an example of a configuration of an accumulation time control circuit according to the eighth embodiment. [Figure 17] This is a flowchart showing an accumulation time control method based on a level determination result according to the eighth embodiment. [Figure 18] This is a perspective view showing an example of a configuration of an imaging device according to the ninth embodiment. [Figure 19] This is a block diagram illustrating a schematic configuration example of a vehicle control system. [Figure 20] This is an explanatory diagram showing an example of the installation location of the imaging unit. [Modes for carrying out the invention]

[0023] The following describes the embodiments for implementing this technology. The description will proceed in the following order. 1. First Embodiment (An example that enables edge detection based on the comparison results of pixel signals and illumination detection for each pixel while sharing the comparison unit) 2. Second Embodiment (An example in which the comparison unit is shared, edge detection based on the comparison result of the pixel signals and illumination detection of each pixel are enabled, and the reference capacitance to which the reference signal is applied is connected in parallel with the input capacitance of the comparison unit) 3. Third Embodiment (An example in which the comparison unit is shared, enabling edge detection based on the comparison result of the pixel signals and illumination detection for each pixel, and connecting the reference capacitance to which the reference signal is applied between the input capacitance of the comparison unit and the cutoff switch that cuts off the input of the pixel signal) 4. A fourth embodiment (an example in which the comparison unit is shared, edge detection based on the comparison result of the pixel signals and illumination detection of each pixel are enabled, and a reference capacitor to which multiple levels of reference signals are applied is connected in parallel with the input capacitor of the comparison unit) 5. Fifth Embodiment (An example in which the comparison unit is shared, enabling edge detection based on the comparison result of the pixel signals and illumination detection for each pixel, and connecting a reference capacitance to which multiple levels of reference signals are applied between the input capacitance of the comparison unit and a cutoff switch that cuts off the input of the pixel signals) 6. Sixth Embodiment (Example of switching the gain of the pixel signal during edge detection based on the level determination result) 7. Seventh Embodiment (Example of controlling the offset when comparing the first pixel signal and the second pixel signal based on the level determination result) 8. Eighth Embodiment (Example of controlling the storage time based on the level determination result) 9. Ninth Embodiment (Example of stacked pixel arrays) 10. Examples of applications to mobile devices

[0024] <1. First Embodiment> Figure 1 is a block diagram showing an example configuration of an imaging device according to the first embodiment.

[0025] In the figure, the imaging device 100 comprises an optical system 101, a solid-state imager 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, image processing unit 104, storage unit 105, display unit 106, and operation unit 107 are connected to each other via a bus 108. The imaging device 100 may be used as a standalone unit, incorporated into a mobile terminal such as a smartphone, incorporated into an authentication device or monitoring device, or incorporated into a vehicle or drone.

[0026] The optical system 101 directs light from the subject onto the solid-state imager 102 and forms an optical image on the light-receiving surface of the solid-state imager 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0027] The solid-state imaging device 102 converts the optical image formed on the light-receiving surface into an electrical signal for each pixel, and outputs the electrical signal digitized. At this time, the solid-state imaging device 102 can detect the edges of the image based on the comparison result of two pixel signals, and can also detect the illuminance of the image based on the comparison result of the pixel signal and a reference signal. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor.

[0028] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, and imaging timing of the solid-state imaging device 102.

[0029] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and gradation conversion processing. The image processing unit 104 may also include a processor that performs processing based on software.

[0030] The storage unit 105 stores images captured by the solid-state imaging device 102, as well as imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store programs that operate the imaging device 100 based on software. The storage unit 105 may include ROM (Read Only Memory), RAM (Random Access Memory), and a memory card.

[0031] The display unit 106 displays captured images and various information to support the imaging operation. The display unit 106 may be a liquid crystal display, an organic EL (Electro-Luminescence) display, or a micro-LED display.

[0032] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0033] Depending on the configuration of the imaging device 100, some of the above-mentioned functions may be omitted, or conversely, it may have additional functions that are not disclosed.

[0034] Figure 2 is a block diagram showing an example configuration of a solid-state imaging device according to the first embodiment.

[0035] In the figure, the solid-state imaging device 102 includes a pixel array unit 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing unit 114, a horizontal scanning circuit 115, and a control circuit 116.

[0036] The pixel array section 111 comprises multiple pixels PX. The pixels PX are arranged in a matrix along the row direction (also called the horizontal direction) and the column direction (also called the vertical direction). Each pixel PX can form a source follower with the column readout circuit 113 when a signal is read out. Each pixel PX is connected to a horizontal drive line HCL for each row and to a vertical signal line VSL for each column. The horizontal drive line HCL drives each pixel PX row by row when a signal is read from each pixel PX. The vertical signal line VSL transmits the pixel signals read from the pixels PX to the column signal processing unit 114 column by column.

[0037] Each pixel PX may be a single pixel, a shared pixel with two pixels, a shared pixel with four pixels, or a shared pixel with eight pixels. Furthermore, the pixel PX may form a Bayer array or a quad-Bayer array. The light received by each pixel PX may be visible light, near-infrared (NIR), short-wavelength infrared (SWIR), ultraviolet light, or X-rays, etc.

[0038] The vertical scanning circuit 112 scans the pixels PX to be read out in the column direction. The vertical scanning circuit 112 may include a vertical register. Here, the vertical scanning circuit 112 can drive each pixel PX row by row via the horizontal drive line HCL when reading a signal from each pixel PX.

[0039] The column readout circuit 113 can configure a source follower with each pixel PX when reading a signal from each pixel PX. In this case, the column readout circuit 113 can change the potential of the vertical signal line VSL for each column based on the charge held in each pixel PX.

[0040] The column signal processing unit 114 processes the signals transmitted from each pixel PX in the column direction. At this time, the column signal processing unit 114 detects image edges based on the comparison result of two pixel signals transmitted from each pixel PX in the column direction, and also detects image illuminance based on the comparison result of the pixel signal and the reference signal REF. Here, the column signal processing unit 114 can perform edge detection based on the comparison result of the pixel signals and illuminance detection of each pixel PX while sharing the comparison unit. Furthermore, the column signal processing unit 114 can perform CDS (Correlated Double Sampling) processing based on the signals transmitted from each pixel PX in the column direction. In addition, the column signal processing unit 114 can perform AD (Analog to Digital) conversion processing based on the signals transmitted from each pixel PX in the column direction and output an imaging signal Gout. The imaging signal Gout may include an edge image and a luminance image. The luminance image may be multi-leveled in terms of the illuminance of the pixel signal. The column signal processing unit 114 includes a column ADC unit 114A.

[0041] The column ADC unit 114A can perform AD conversion processing in parallel for each column. In this case, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel PX and the reference signal REF. This AD conversion may be single-slope AD conversion.

[0042] The horizontal scanning circuit 115 scans the pixels PX to be read out in the row direction. The horizontal scanning circuit 115 may also include a horizontal register.

[0043] The control circuit 116 controls the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column reading circuit 113, and the processing timing of the column signal processing unit 114. In this case, the control circuit 116 can coordinate the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, shutter operation, and read operation are performed for each row in each frame.

[0044] Figure 3 shows an example of a pixel circuit configuration provided in a solid-state imaging device according to the first embodiment.

[0045] In the figure, pixel PX comprises a photodiode PD, a transfer transistor TG, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion transistor FD. MOS transistors can be used as the transfer transistor TG, the reset transistor 123, the amplification transistor 124, and the selection transistor 125.

[0046] The photodiode PD stores the charge converted by photoelectric conversion. The transfer transistor TG transfers the charge stored in the photodiode PD to the floating diffusion FD. The reset transistor 123 resets the floating diffusion FD. The amplification transistor 124 outputs a pixel signal based on the potential of the floating diffusion FD. The selection transistor 125 selects the output of the amplification transistor 124.

[0047] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode PD is connected to the floating diffusion FD via the transfer transistor TG. The floating diffusion FD is connected to the power supply potential VDD via the reset transistor 123. The power supply potential VDD is connected to the vertical signal line VSL via the series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0048] A transfer signal TRG is applied to the gate of the transfer transistor TG. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TRG, the reset signal RST, and the selection signal SEL can be transmitted row by row to the pixel PX via the horizontal drive line HCL shown in Figure 2.

[0049] Figure 4 is a cross-sectional view showing an example of the configuration of a pixel array section provided in a solid-state imaging device according to the first embodiment. Note that Figure 4 shows an example of a surface-illuminated solid-state imaging device. Furthermore, Figure 4 shows an example of a configuration for three pixels.

[0050] In the figure, a photodiode 232 is formed on the semiconductor substrate 231 for each pixel PX. The material of the semiconductor substrate 231 may be Si, InGaAs, or InP.

[0051] A gate electrode 214 and a wiring layer 210 are formed on the semiconductor substrate 231. The gate electrode 214 is formed on the semiconductor substrate 231 via a gate insulating film 213. A sidewall 215 is formed on the side wall of the gate electrode 214. The material of the gate electrode 214 can be, for example, polycrystalline silicon with impurities introduced. The material of the gate insulating film 213 can be, for example, a silicon oxide film. The material of the sidewall 215 can be, for example, a silicon oxide film or a silicon nitride film.

[0052] The gate electrode 214 can be used in a pixel transistor. The pixel transistor includes a transfer transistor TG, a reset transistor 123, an amplification transistor 124, and a selection transistor 125, as shown in Figure 3.

[0053] A wiring 216 is formed on the gate electrode 214. Figure 4 shows an example of a three-layer wiring. In this case, the wiring 216 is provided with an aperture OP1 that allows light to enter the photodiode 232. The gate electrode 214 and the wiring 216 are insulated via an insulating layer 217. The insulating layer 217 can be, for example, a silicon oxide film. The material of the wiring 216 can be, for example, a metal such as Al or Cu.

[0054] A color filter 218 is formed on the wiring layer 210 for each pixel PX. A microlens 219 is formed on the color filter 218 for each pixel PX. The material for the color filter 218 and microlens 219 can be, for example, a transparent resin such as acrylic or polycarbonate. Pigments may be added to the color filter 218 for coloring. The color filter 218 can be configured, for example, in a Bayer array.

[0055] Figure 5 is a cross-sectional view showing a modified example of the pixel array section provided in the solid-state imaging device according to the first embodiment. Figure 5 shows an example of a back-illuminated solid-state imaging device. Furthermore, Figure 5 shows an example configuration for three pixels.

[0056] In the figure, a photodiode 222 is formed in the semiconductor layer 221 for each pixel PX. The material of the semiconductor layer 221 may be Si, InGaAs, or InP. The semiconductor layer 221 can be formed, for example, by thinning a semiconductor substrate with the photodiode 222 formed on the front side from the back side.

[0057] A gate electrode 224 and a wiring layer 220 are formed on the semiconductor layer 221. The gate electrode 224 is formed on the semiconductor layer 221 via a gate insulating film 223. A sidewall 225 is formed on the side wall of the gate electrode 224.

[0058] The gate electrode 224 can be used in a pixel transistor. The pixel transistor includes a transfer transistor TG, a reset transistor 123, an amplification transistor 124, and a selection transistor 125, as shown in Figure 3.

[0059] A wiring 226 is formed on the gate electrode 224. Figure 5 shows an example of a three-layer wiring. The gate electrode 224 and the wiring 226 are insulated via an insulating layer 227. The semiconductor layer 221 is supported on a support substrate 230 via the insulating layer 227. The support substrate 230 may be a glass substrate, a Si substrate, or a sapphire substrate.

[0060] A color filter 228 is formed on the back side of the semiconductor layer 221 for each pixel PX. A microlens 229 is formed on the color filter 228 for each pixel PX. The color filter 228 can, for example, be configured in a Bayer array.

[0061] Figure 6 is a block diagram showing an example configuration of a signal readout circuit according to the first embodiment. In this figure, two columns of vertical signal lines VSL1 and VSL2 are shown, but there may be more vertical signal lines.

[0062] In the figure, pixels PX1 and PX2 are connected to vertical signal lines VSL1 and VSL2, respectively. Current sources GA1 and GA2 are also connected to vertical signal lines VSL1 and VSL2, respectively. Each current source GA1 and GA2 can form a source follower with each pixel PX1 and PX2. In this case, each pixel PX1 and PX2 can output a pixel signal via vertical signal lines VSL1 and VSL2, respectively. The pixel signal may include a reset level (P-phase level) and a signal level (D-phase level). The signal readout circuit includes comparators CP1 and CP2 and a switching unit KEB. Note that each comparator CP1 and CP2 is an example of a comparison unit as described in the claims.

[0063] Each comparator CP1 and CP2 detects the difference between the comparator inputs. At this time, each comparator CP1 and CP2 can detect the illuminance of each pixel PX1 and PX2 based on the comparison result between the pixel signal read from each pixel PX1 and PX2 and the reference signal REF. Furthermore, each comparator CP1 and CP2 can detect the edge between pixels PX1 and PX2 based on the comparison result of the pixel signals read from each pixel PX1 and PX2, respectively. Each comparator CP1 and CP2 is equipped with a non-inverting input and an inverting input.

[0064] Input capacitors CA1 and CA2 are connected in series to the non-inverting inputs of each comparator CP1 and CP2, respectively. Input variable capacitors CB1 and CB2 are connected in series to the inverting inputs of each comparator CP1 and CP2, respectively. Input variable capacitor CB1 sets the signal level of the inverting input of comparator CP1 by a predetermined gain. For example, input variable capacitor CB1 can reduce the gain of the signal level of the non-inverting input of comparator CP1 to less than 1. Input variable capacitor CB2 sets the signal level of the inverting input of comparator CP2 by a predetermined gain. For example, input variable capacitor CB2 can reduce the gain of the signal level of the non-inverting input of comparator CP2 to less than 1. Note that input variable capacitors CB1 and CB2 are examples of the level setting circuit described in the claims.

[0065] The non-inverting input of comparator CP1 receives the pixel signal read from pixel PX2 via input capacitor CA1. The non-inverting input of comparator CP2 receives the pixel signal read from pixel PX1 via input capacitor CA2. The inverting input of comparator CP1 receives the pixel signal from pixel PX1 switched by the switching unit KEB or the reference signal REF via input variable capacitor CB1. The inverting input of comparator CP2 receives the pixel signal from pixel PX2 switched by the switching unit KEB or the reference signal REF via input variable capacitor CB2.

[0066] The auto-zero signal AZ is input to each comparator CP1 and CP2. The auto-zero signal AZ activates auto-zero operation during the auto-zero period. In auto-zero operation, a charge that balances the non-inverting and inverting inputs of each comparator CP1 and CP2 can be accumulated in the input capacitances of each comparator CP1 and CP2, respectively.

[0067] The reference signal generator REB generates a reference signal REF. The reference signal generator REB may include a DA (Digital to Analog) converter. The reference signal REF may be switchable to multiple levels. The reference signal REF may be set to a value that allows for the determination of the saturation levels of each pixel PX1 and PX2. The reference signal REF may be a fixed value, a step wave, or a ramp wave.

[0068] The switching unit KEB switches the inverting input of comparator CP1 between the pixel signal read from pixel PX1 and the reference signal REF. The switching unit KEB also switches the inverting input of comparator CP2 between the pixel signal read from pixel PX21 and the reference signal REF. The switching unit KEB includes cutoff switches SA1 and SA2, reference switches SB1 and SB2, and reference capacitors C1 and C2.

[0069] The cutoff switch SA1 cuts off the input of the pixel signal read from pixel PX1 in relation to the inverting input of comparator CP1. The reference switch SB1 switches the input of the reference signal REF in relation to the inverting input of comparator CP1. The reference capacitor C1 is connected between the cutoff switch SA1 and the input variable capacitor CB1 when the reference signal REF is applied via the reference switch SB1.

[0070] The cutoff switch SA2 cuts off the input of the pixel signal read from pixel PX2 in relation to the inverting input of comparator CP2. The reference switch SB2 switches the input of the reference signal REF in relation to the inverting input of comparator CP2. The reference capacitor C2 receives the reference signal REF via the reference switch SB2. At this time, the reference capacitor C2 is connected between the cutoff switch SA2 and the input variable capacitor CB2.

[0071] The storage unit HA1 stores the comparison result of the comparator CP1 between the pixel signal read from pixel PX2 and the reference signal REF, based on the enable signal ENA. The storage unit HB1 stores the comparison result of the comparator CP1 between the pixel signals read from each pixel PX1 and PX2, respectively, based on the enable signal ENB. The storage unit HA2 stores the comparison result of the comparator CP2 between the pixel signal read from pixel PX1 and the reference signal REF, based on the enable signal ENA. The storage unit HB2 stores the comparison result of the comparator CP2 between the pixel signals read from each pixel PX1 and PX2, respectively, based on the enable signal ENB.

[0072] Here, when detecting the illuminance of each pixel PX1 and PX2, the respective cutoff switches SA1 and SA2 are turned off, and the respective reference switches SB1 and SB2 are turned on. At this time, the reference signal REF is input to the inverting inputs of each comparator CP1 and CP2 via the reference capacitors C1 and C2, respectively. Then, in comparator CP1, the pixel signal read from pixel PX2 is compared with the reference signal REF, and the illuminance of pixel PX2 is detected. Similarly, in comparator CP2, the pixel signal read from pixel PX1 is compared with the reference signal REF, and the illuminance of pixel PX1 is detected.

[0073] In detecting the edge between pixels PX1 and PX2, the respective cutoff switches SA1 and SA2 are turned on, and the respective reference switches SB1 and SB2 are turned off. At this time, the pixel signals read from each pixel PX2 and PX1 are input to the inverting inputs of each comparator CP1 and CP2, respectively. Then, the pixel signals read from each pixel PX1 and PX2 are compared in each comparator CP1 and CP2, and the edge between each pixel PX1 and PX2 is detected. Here, non-destructive readout can be performed for the detection of the illuminance of each pixel PX1 and PX2 and the detection of the edge between pixels PX1 and PX2, thereby improving detection accuracy.

[0074] Furthermore, when the reference switches SB1 and SB2 are turned off, the reference capacitors C1 and C2 are connected to ground potential. In this state, the reference capacitors C1 and C2 can hold the dark levels of the pixels PX1 and PX2. Then, when the reference switches SB1 and SB2 are turned on, the reference signal REF can be input to the inverting inputs of the comparators CP1 and CP2, shifted by the amount of the dark level held in the reference capacitors C1 and C2.

[0075] As described above, in the first embodiment, a switching unit KEB is provided that switches the inverting input of comparator CP1, to which the pixel signal read from pixel PX2 is input as a non-inverting input, between the pixel signal read from pixel PX1 and the reference signal REF. This makes it possible to perform edge detection based on the comparison result of the pixel signals read from each pixel PX1 and PX2, and illuminance detection of the pixel signal PX2, while sharing comparator CP1. As a result, it is possible to reduce the number of elements in the comparison circuit required for edge detection and illuminance detection, thereby achieving lower power consumption and smaller area.

[0076] <2. Second Embodiment> In the first embodiment described above, a switching unit KEB is provided that switches the inverting input of comparator CP1, to which the pixel signal read from pixel PX2 is input as a non-inverting input, between the pixel signal read from pixel PX1 and the reference signal REF. In this second embodiment, each comparator CP1 and CP2 is enabled to perform edge detection based on the comparison result of the pixel signals and illuminance detection of each pixel PX1 and PX2, and the reference capacitance to which the reference signal REF is applied is connected in parallel with the input capacitance of the comparison unit.

[0077] Figure 7 is a block diagram showing an example configuration of a signal readout circuit according to the second embodiment.

[0078] In the figure, this signal readout circuit includes input capacitors CD1, CE1, CD2, CE2 and changeover switches SC1, SD1, SC2, SD2 as input variable capacitors CB1, CB2 of the first embodiment described above. In addition, this signal readout circuit includes reference capacitors CF1, CF2 instead of reference capacitors C1, C2 of the first embodiment described above. Furthermore, this signal readout circuit includes reference switches SE1, SF1, SE2, SF2 instead of reference switches SB1, SB2 of the first embodiment described above. The other configurations of this signal readout circuit are the same as those of the signal readout circuit of the first embodiment described above.

[0079] Input capacitor CD1 is connected to the inverting input of comparator CP1. Input capacitor CE1 is connected in parallel to input capacitor CD1 at the inverting input of comparator CP1. Input capacitor CE1 is connected to ground potential via selector switch SC1. By switching selector switch SC1 on and off, the signal level at the inverting input of comparator CP1 can be set to a predetermined gain. Input capacitor CE1 is also connected between cutoff switch SA1 and input capacitor CD1 via selector switch SD1. By switching reference switch SD1 on and off, the input of the pixel signal from pixel PX1 to the inverting input of comparator CP1 can be switched.

[0080] The reference capacitor CF1 is connected in parallel with the input capacitor CD1 to the inverting input of comparator CP1. The reference capacitor CF1 is connected to ground potential via reference switch SE1. By switching reference switch SE1 on and off, the dark level can be held at the reference capacitor CF1. A reference signal REF is also applied to the reference capacitor CF1 via reference switch SF1. By switching reference switch SF1 on and off, the input of the reference signal REF to the inverting input of comparator CP1 can be switched.

[0081] Input capacitor CD2 is connected to the inverting input of comparator CP2. Input capacitor CE2 is connected in parallel to input capacitor CD2 at the inverting input of comparator CP2. Input capacitor CE2 is connected to ground potential via selector switch SC2. By switching selector switch SC2 on and off, the signal level at the inverting input of comparator CP2 can be set to a predetermined gain. Input capacitor CE2 is also connected between cutoff switch SA2 and input capacitor CD2 via selector switch SD2. By switching selector switch SD2 on and off, the input of the pixel signal from pixel PX2 to the inverting input of comparator CP2 can be switched.

[0082] The reference capacitor CF2 is connected in parallel with the input capacitor CD2 to the inverting input of comparator CP2. The reference capacitor CF2 is connected to ground potential via reference switch SE2. By switching reference switch SE2 on and off, the dark level can be held at the reference capacitor CF2. In addition, a reference signal REF is applied to the reference capacitor CF2 via reference switch SF2. By switching reference switch SF2 on and off, the input of the reference signal REF to the inverting input of comparator CP2 can be switched.

[0083] Figure 8 is a timing chart showing the waveforms of each part during operation of the signal readout circuit according to the second embodiment.

[0084] In the figure, each cutoff switch SA1 and SA2 is turned on and off based on the cutoff signal WA. Reference switches SE1 and SE2 are turned on and off based on the switching signal WE. Reference switches SF1 and SF2 are turned on and off based on the switching signal WF.

[0085] At this point, when the selection signal SEL rises (t11), the selection transistor 125 turns on, and the sources of the amplification transistors 124 for each pixel PX1 and PX2 are connected to the vertical signal lines VSL1 and VSL2, respectively. Also, the reset signal RST rises, the reset transistor 123 turns on, and the floating diffusion FD is reset. Furthermore, the auto-zero signal AZ rises, and charges that balance the non-inverting and inverting inputs of each comparator CP1 and CP2 are accumulated in the input capacitances of each comparator CP1 and CP2, respectively. In addition, the switching signal WE rises, and the reference switches SE1 and SE2 turn on. At this time, the cutoff signal WA is set to a high level, and the cutoff switches SA1 and SA2 are turned on. Also, the switching signal WF is set to a low level, and the reference switches SF1 and SF2 are turned off.

[0086] Next, when the reset signal RST falls (t12), the reset transistor 123 turns off. At this time, the potentials of each vertical signal line VSL1 and VSL2 are set to the reset levels of each pixel PX1 and PX2, respectively. At this time, the dark levels at auto-zero are held in each reference capacitor CF1 and CF2.

[0087] Next, after the auto-zero signal AZ falls (t13), the switching signal WE falls, and the reference switches SE1 and SE2 turn off.

[0088] Next, the transfer signal TRG rises (t14), and the transfer transistor TG turns on. At this time, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD. Also, the cutoff signal WA falls, and the respective cutoff switches SA1 and SA2 are turned off. Furthermore, the switching signal WF rises, and the respective reference switches SF1 and SF2 are turned on.

[0089] Next, the transfer signal TRG falls (t15), and the transfer transistor TG turns off. Also, the auto-zero mask signal AZM falls, and the outputs of each comparator CP1 and CP2 are activated. Furthermore, the enable signal ENA rises, and the outputs of each comparator CP1 and CP2 are held in the holding units HA1 and HA2. At this time, the illuminance detection period PA is set. During the illuminance detection period PA, each comparator CP1 and CP2 compares the pixel signals read from each pixel PX1 and PX2 with the reference signal REF. At this time, the inverting input potential DIA of each comparator CP1 and CP2 is set to the signal level of each pixel PX2 and PX1, respectively. The non-inverting input potential DIB of each comparator CP1 and CP2 is set to the level where the reference signal REF is shifted by the amount of the dark level held in each reference capacitor C1 and C2, respectively. This level ΔDIB can be given by the following formula. ΔDIB =(REF×CF1) / (CD1+CE1+CF1) =(REF×CF2) / (CD2+CE2+CF2) The comparison results from each comparator CP1 and CP2 are then stored in the holding units HA1 and HA2.

[0090] Next, after the illuminance detection period PA has elapsed, the cutoff signal WA rises (t16), and the cutoff switches SA1 and SA2 are turned on. Also, the switching signal WE rises, and the reference switches SE1 and SE2 are turned on. Furthermore, the switching signal WF falls, and the reference switches SF1 and SF2 are turned off. In addition, the auto-zero mask signal AZM rises, and the outputs of the comparators CP1 and CP2 are disabled. Finally, the enable signal ENA falls, and data acquisition by the holding units HA1 and HA2 is released.

[0091] Next, the auto-zero mask signal AZM falls (t17), and the outputs of comparators CP1 and CP2 are activated. The enable signal ENB rises, and the outputs of comparators CP1 and CP2 are held in the holding units HB1 and HB2. At this time, the edge detection period PB is set. During the edge detection period PB, the pixel signals read from each pixel PX1 and PX2 are compared with each other in comparators CP1 and CP2. At this time, the inverted input potential DIA of each comparator CP1 and CP2 is set to the signal level of each pixel PX2 and PX1, respectively. The non-inverted input potential DIB of each comparator CP1 and CP2 is set to the signal level of each pixel PX1 and PX2, respectively. The comparison results in each comparator CP1 and CP2 are then held in the holding units HB1 and HB2.

[0092] Next, after the edge detection period PB has elapsed, the auto-zero mask signal AZM rises (t18), and the outputs of comparators CP1 and CP2 are disabled. Also, the enable signal ENB falls, and data acquisition by the holding units HB1 and HB2 is released.

[0093] Thus, in the second embodiment described above, each comparator CP1 and CP2 enables edge detection based on the comparison result of the pixel signals and illuminance detection of each pixel PX1 and PX2, and each reference capacitor CF1 and CF2 is connected in parallel with each input capacitor CD1 and CD2. This makes it possible to improve the accuracy of edge detection and illuminance detection while reducing the number of elements in the comparison circuit required for edge detection and illuminance detection.

[0094] <3. Third Embodiment> In the second embodiment described above, each comparator CP1 and CP2 is enabled to perform edge detection based on the comparison result of the pixel signals and to detect the illuminance of each pixel PX1 and PX2, and each reference capacitor CF1 and CF2 is connected in parallel with each input capacitor CD1 and CD2. In this third embodiment, each comparator CP1 and CP2 is enabled to perform edge detection based on the comparison result of the pixel signals and to detect the illuminance of each pixel PX1 and PX2, and the reference capacitor is connected between the input capacitor and the cutoff switch.

[0095] Figure 9 is a block diagram showing an example of the configuration of a signal readout circuit according to the third embodiment.

[0096] In the figure, this signal readout circuit includes reference capacitors CX1 and CX2 instead of reference capacitors CF1 and CF2 in the second embodiment described above. Furthermore, this signal readout circuit includes reference switches SX1, SY1, SX2, and SY2 instead of reference switches SE1, SF1, SE2, and SF2 in the second embodiment described above. The other configurations of this signal readout circuit are the same as those of the signal readout circuit in the second embodiment described above. Also, the timing chart showing the waveforms of each part during operation of this signal readout circuit is the same as the timing chart in Figure 8.

[0097] The reference capacitance CX1 is connected between the input capacitance CD1 and the cutoff switch SA1. The reference capacitance CX1 is connected to ground potential via the reference switch SX1. By switching the reference switch SX1 on and off, the dark level can be held at the reference capacitance CX1. In addition, the reference signal REF is applied to the reference capacitance CX1 via the reference switch SY1. By switching the reference switch SY1 on and off, the input of the reference signal REF can be switched relative to the inverting input of the comparator CP1.

[0098] The reference capacitance CX2 is connected between the input capacitance CD2 and the cutoff switch SA2. The reference capacitance CX2 is connected to ground potential via the reference switch SX2. By switching the reference switch SX2 on and off, the dark level can be held at the reference capacitance CX2. In addition, the reference signal REF is applied to the reference capacitance CX2 via the reference switch SY2. By switching the reference switch SY2 on and off, the input of the reference signal REF can be switched relative to the inverting input of the comparator CP2.

[0099] Thus, in the third embodiment described above, each comparator CP1 and CP2 enables edge detection based on the comparison result of the pixel signals and illuminance detection of each pixel PX1 and PX2, and each reference capacitor CX1 and CX2 is connected between each input capacitor CD1 and CD2 and each cutoff switch SA1 and SA2, respectively. This makes it possible to improve the accuracy of edge detection and illuminance detection while reducing the number of elements in the comparison circuit required for edge detection and illuminance detection.

[0100] <4. Fourth Embodiment> In the second embodiment described above, each comparator CP1 and CP2 is enabled to perform edge detection based on the comparison result of the pixel signals and to detect the illuminance of each pixel PX1 and PX2, and each reference capacitor CF1 and CF2 is connected in parallel with each input capacitor CD1 and CD2. In this fourth embodiment, each comparator CP1 and CP2 is enabled to perform edge detection based on the comparison result of the pixel signals and to detect the illuminance of each pixel PX1 and PX2, and the level of the reference signal applied to the reference capacitor connected in parallel with the input capacitor is switchable.

[0101] Figure 10 is a block diagram showing an example configuration of a signal readout circuit according to the fourth embodiment. In this figure, an example is shown in which the level of the reference signal REF can be switched in four stages, but the level of the reference signal REF may be switched to any two or more arbitrary levels. Also, in this figure, an example of switching the level of the reference signal REF of comparator CP1 of the second embodiment described above is shown, but the same can be applied to switching the level of the reference signal REF of comparator CP2. Furthermore, in this figure, an example is shown in which the input variable capacitor CB1 of the first embodiment described above is used to set the signal level of the inverting input of comparator CP1 with a predetermined gain.

[0102] In the figure, this signal readout circuit includes reference switches S11 to S14 instead of reference switches SE1 and SF1 in the second embodiment described above. The other configurations of this signal readout circuit are the same as those of the signal readout circuit in the second embodiment described above.

[0103] Each reference switch S11 to S14 switches the input voltages V11 to V14 to the reference capacitance CF1, respectively. When any one of the reference switches S11 to S14 is ON, all other reference switches S11 to S14 are OFF. Each voltage V11 to V14 can be set to a different value from one another.

[0104] Figure 11 is a timing chart showing the waveforms of each part during operation of the signal readout circuit according to the fourth embodiment.

[0105] In the figure, when each reference switch S11 to S14 is turned on, the voltages V11 to V14 applied to the inverting input of comparator CP1 rise. When each reference switch S11 to S14 is turned off, the voltages V11 to V14 applied to the inverting input of comparator CP1 fall. The waveforms other than the voltages V11 to V14 during the operation of this signal readout circuit are the same as the waveforms of each part during the operation of the signal readout circuit in the second embodiment described above.

[0106] Here, from time t11 to t14, voltage V11 is set to a high level, and voltages V12 to V14 are set to low levels. Then, after voltage V11 falls, voltage V12 rises.

[0107] Next, during the illuminance detection period PA, voltage V12 falls while voltage V13 rises. Subsequently, voltage V13 falls while voltage V14 rises. At this time, the level of the reference signal REF changes in a stepwise manner. Then, in comparator CP1, the pixel signal read from pixel PX2 is compared with the stepwise changing reference signal REF. At this time, the inverting input potential DIA of comparator CP1 is set to the signal level of pixel PX2. The non-inverting input potential DIB of comparator CP1 is set to a level where the reference signal REF is shifted by the amount of the dark level held in the reference capacitor C1. The comparison result in comparator CP1 is then held in the holding unit HA1. At this time, the holding unit HA1 can hold the comparison result in comparator CP1 for each level of the stepwise changing reference signal REF.

[0108] Thus, in the fourth embodiment described above, the comparator CP1 enables edge detection based on the comparison result of the pixel signals and illuminance detection of the pixel PX2, and also allows switching of the level of the reference signal REF applied to the reference capacitor CF1 connected in parallel with the input variable capacitor CB1. This makes it possible to improve the accuracy of edge detection and illuminance detection while reducing the number of elements in the comparison circuit required for edge detection and illuminance detection, and also improve the resolution of illuminance detection.

[0109] <5. Fifth Embodiment> In the third embodiment described above, each comparator CP1 and CP2 is enabled to perform edge detection based on the comparison result of the pixel signals and to detect the illuminance of each pixel PX1 and PX2, and each reference capacitor CX1 and CX2 is connected between each input capacitor CD1 and CD2 and each cutoff switch SA1 and SA2, respectively. In this fifth embodiment, each comparator CP1 and CP2 is enabled to perform edge detection based on the comparison result of the pixel signals and to detect the illuminance of each pixel PX1 and PX2, and the level of the reference signal applied to the reference capacitor connected between the input capacitor and the cutoff switch is switchable.

[0110] Figure 12 is a block diagram showing an example configuration of a signal readout circuit according to the fifth embodiment. In this figure, an example is shown in which the level of the reference signal REF can be switched in four stages, but the level of the reference signal REF may be switched to any two or more arbitrary levels. Also, in this figure, an example of switching the level of the reference signal REF of comparator CP1 of the third embodiment described above is shown, but the same can be applied to switching the level of the reference signal REF of comparator CP2. Furthermore, in this figure, an example is shown in which the input variable capacitor CB1 of the first embodiment described above is used to set the signal level of the inverting input of comparator CP1 with a predetermined gain.

[0111] In the figure, this signal readout circuit includes reference switches S21 to S24 instead of reference switches SX1 and SY1 in the third embodiment described above. The other configurations of this signal readout circuit are the same as those of the signal readout circuit in the third embodiment described above. Furthermore, the timing chart showing the waveforms of each part during the operation of this signal readout circuit is the same as the timing chart in Figure 11.

[0112] Each of the reference switches S21 to S24 switches the input voltages V11 to V14 to the reference capacitance CX1, respectively. When any one of the reference switches S21 to S24 is ON, all the other reference switches S21 to S24 are OFF.

[0113] Thus, in the fifth embodiment described above, the comparator CP1 enables edge detection based on the comparison result of the pixel signals and illuminance detection of the pixel PX1, and also allows switching of the level of the reference signal REF applied to the reference capacitor CX1 connected between the input variable capacitor CB1 and the cutoff switch SA1. This makes it possible to improve the accuracy of edge detection and illuminance detection while reducing the number of elements in the comparison circuit required for edge detection and illuminance detection, and also improve the resolution of illuminance detection.

[0114] <6. Sixth Embodiment> In the first embodiment described above, a switching unit KEB is provided that switches the inverting input of comparator CP1, to which the pixel signal read from pixel PX2 is input as a non-inverting input, between the pixel signal read from pixel PX1 and the reference signal REF. In this sixth embodiment, the gain of the pixel signal during edge detection is switched based on the level determination result of the pixel signals read from each pixel PX1 and PX2.

[0115] Figure 13 is a block diagram showing an example configuration of a solid-state imaging device according to the sixth embodiment.

[0116] In the figure, this solid-state imaging device has a gain switching control unit GK added to the solid-state imaging device of the second embodiment described above. In addition, this signal readout circuit is equipped with input variable capacitors CG1 and CG2 instead of input capacitors CE1 and CE2 of the second embodiment described above. The other configurations of this solid-state imaging device are the same as those of the solid-state imaging device of the second embodiment described above.

[0117] The variable input capacitor CG1 is connected in parallel with the input capacitor CD1 to the inverting input of comparator CP1. The variable input capacitor CG1 is connected to ground potential via selector switch SC1. Furthermore, the variable input capacitor CG1 is connected between the cutoff switch SA1 and the input capacitor CD1 via selector switch SD1. By changing the capacitance value of the variable input capacitor CG1, the signal level at the inverting input of comparator CP1 can be set to a predetermined gain.

[0118] The variable input capacitor CG2 is connected in parallel with the input capacitor CD2 to the inverting input of comparator CP2. The variable input capacitor CG2 is connected to ground potential via selector switch SC2. Furthermore, the variable input capacitor CG2 is connected between the cutoff switch SA2 and the input capacitor CD2 via selector switch SD2. By changing the capacitance value of the variable input capacitor CG2, the signal level at the inverting input of comparator CP2 can be set to a predetermined gain.

[0119] The gain switching control unit GK switches the gain of the signal level at the inverting input of each comparator CP1 and CP2 based on the comparison result between the pixel signal read from each pixel PX1 and PX2 and the reference signal REF. At this time, the gain switching control unit GK can switch the selector switches SC1, SD1, SC2, and SD2 based on the output of each comparator CP1 and CP2 when comparing the pixel signal read from each pixel PX1 and PX2 with the reference signal REF. By switching the selector switches SC1, SD1, SC2, and SD2, the signal level at the inverting input of each comparator CP1 and CP2 can be set to a predetermined gain. For example, when the level of the pixel signal read from each pixel PX1 and PX2 is high, the gain of the signal level at the inverting input of each comparator CP1 and CP2 can be decreased. On the other hand, when the level of the pixel signal read from each pixel PX1 and PX2 is low, the gain of the signal level at the inverting input of each comparator CP1 and CP2 can be increased. Furthermore, the gain switching control unit GK can be shared by multiple columns.

[0120] Thus, in the sixth embodiment described above, the gain of the pixel signal during edge detection is switched based on the level determination result of the pixel signal read from each pixel PX1 and PX2. This makes it possible to improve the accuracy of edge detection while reducing the number of elements in the comparison circuit required for edge detection and illuminance detection.

[0121] In the sixth embodiment, an example was shown in which the gain switching control unit GK is applied to the configuration of the second embodiment described above. However, the gain switching control unit GK may also be applied to any of the configurations of the third to fifth embodiments described above.

[0122] <7. Seventh Embodiment> In the sixth embodiment described above, the gain of the pixel signal during edge detection was switched based on the level determination result of the pixel signal read from each pixel PX1 and PX2. In this seventh embodiment, the offset during comparison of the pixel signals read from each pixel PX1 and PX2 is switched based on the level determination result of the pixel signal read from each pixel PX1 and PX2.

[0123] Figure 14 is a block diagram showing an example configuration of a solid-state imaging device according to the seventh embodiment.

[0124] In the figure, this solid-state imaging device includes an offset switching control unit FK instead of the gain switching control unit GK of the sixth embodiment described above. Furthermore, this signal readout circuit uses reference signals REF1 and REF2 instead of the reference signal REF of the sixth embodiment described above. Also, this signal readout circuit has reference switches SG1 and SG2 added to the signal readout circuit of the sixth embodiment described above. The other configurations of this solid-state imaging device are the same as those of the solid-state imaging device of the sixth embodiment described above.

[0125] Each reference signal REF1 and REF2 can set the offset when comparing the pixel signals read from each pixel PX1 and PX2. The levels of each reference signal REF1 and REF2 can be made different from each other.

[0126] Reference signal REF1 is applied to reference capacitor CF1 via reference switch SF1. Reference signal REF2 is also applied to reference capacitor CF1 via reference switch SG1. Reference signal REF1 is applied to reference capacitor CF2 via reference switch SF2. Reference signal REF2 is also applied to reference capacitor CF2 via reference switch SG2.

[0127] The offset switching control unit FK switches the offset during the comparison of the pixel signals read from each pixel PX1 and PX2 based on the comparison result between the pixel signals read from each pixel PX1 and PX2 and the reference signals REF1 and REF2. At this time, the offset switching circuit FK can switch each reference switch SF1, SF2, SG1, and SG2 based on the output of each comparator CP1 and CP2 during the comparison of the pixel signals read from each pixel PX1 and PX2 and the reference signals REF1 and REF2. By switching each reference switch SF1, SF2, SG1, and SG2, the offset during the comparison of the pixel signals read from each pixel PX1 and PX2 can be switched. At this time, the offset set based on the reference signal REF1 can be superimposed on the inverting inputs of each comparator CP1 and CP2 via each reference capacitor CF1 and CF2. Also, the offset set based on the reference signal REF2 can be superimposed on the inverting inputs of each comparator CP1 and CP2 via each reference capacitor CG1 and CG2. For example, when the level of the pixel signal read from each pixel PX1 and PX2 is high, the offset switching control unit FK can increase the signal level offset of the inverting input of each comparator CP1 and CP2. On the other hand, when the level of the pixel signal read from each pixel PX1 and PX2 is low, the offset switching control unit FK can decrease the signal level offset of the inverting input of each comparator CP1 and CP2. Note that the offset switching control unit FK can be shared by multiple columns.

[0128] Thus, in the seventh embodiment described above, the offset during comparison of the pixel signals read from each pixel PX1 and PX2 is switched based on the level determination result of the pixel signals read from each pixel PX1 and PX2. This makes it possible to improve the accuracy of edge detection while reducing the number of elements in the comparison circuit required for edge detection and illuminance detection.

[0129] In the seventh embodiment, an example was shown in which the offset switching control unit FK is applied to the configuration of the second embodiment described above. However, the offset switching control unit FK may also be applied to any of the configurations of the third to sixth embodiments described above.

[0130] <8. Eighth Embodiment> In the first embodiment described above, a switching unit KEB is provided that switches the inverting input of comparator CP1, to which the pixel signal read from pixel PX2 is input as a non-inverting input, between the pixel signal read from pixel PX1 and the reference signal REF. In this seventh embodiment, the storage time of each pixel PX1 and PX2 is controlled based on the level determination result of the pixel signals read from each pixel PX1 and PX2.

[0131] Figure 15 is a block diagram showing an example configuration of a solid-state imaging device according to the eighth embodiment.

[0132] In the figure, this solid-state imaging device is modified from the solid-state imaging device of the second embodiment described above by adding a counter CK and an accumulation time control circuit AK. The other configurations of this solid-state imaging device are the same as those of the solid-state imaging device of the second embodiment described above.

[0133] The counter CK performs a counting operation based on the inversion timing of the outputs of each comparator CP1 and CP2, and outputs the count value CNT to the storage time control circuit AK. At this time, the count value CNT can represent the illuminance of each pixel PX1 and PX2.

[0134] The storage time control circuit AK controls the storage time of each pixel PX1 and PX2 based on the level determination result of the pixel signal read from each pixel PX1 and PX2. Here, the storage time control circuit AK can output storage time data CIT to the vertical scanning circuit 112 based on the count value CNT from the counter CK. The storage time control circuit AK may also control the storage time of each pixel PX1 and PX2 in units of a predetermined number of frames. In this case, the vertical scanning circuit 112 drives each pixel PX1 and PX2 based on the storage time data CIT and controls the storage time of each pixel PX1 and PX2.

[0135] Figure 16 is a block diagram showing an example configuration of the storage time control circuit according to the eighth embodiment.

[0136] In the figure, the storage time control circuit AK includes a short storage table 801, a long storage table 802, and a selector 803.

[0137] The short-storage table 801 stores data specifying a shorter storage time. The long-storage table 802 stores data specifying a longer storage time. The selector 803 switches between outputting data stored in the short-storage table 801 or the long-storage table 802 based on the count value CNT obtained by the counter CK.

[0138] Figure 17 is a flowchart showing the storage time control method based on the level determination result according to the eighth embodiment. In this figure, an example is shown in which the storage time of each pixel PX1 and PX2 is controlled on a frame-by-frame basis. Furthermore, the storage time control method based on the level determination result of the pixel signal read from each pixel PX1 and PX2 may be applied to any of the solid-state imaging devices of the first to seventh embodiments described above.

[0139] In the figure, the solid-state imaging device increments the image frame number by 1 (S101). The initial value of the image frame number can be set to 0.

[0140] Next, the solid-state imaging device determines whether the frame number is a multiple of 10 (S102). If the frame number is not a multiple of 10, it acquires the edge image in which the edge has been determined (S103) and proceeds to S108. Any of the methods described in the first to seventh embodiments above may be applied to acquire the edge image.

[0141] On the other hand, if the frame number is a multiple of 10, the solid-state imaging device acquires an edge-signal level image in which the edges and signal levels have been determined (S104). Any of the methods described in the first to seventh embodiments above may be applied to acquire the edge-signal level image.

[0142] Next, the solid-state imaging device performs region designation (S105). In this region designation, the range of pixels PX in the pixel array section 111 can be specified.

[0143] Next, the solid-state imaging device acquires the count value until the comparison result with the threshold of the signal level within the specified area is reversed (S106).

[0144] Next, the solid-state imaging device determines whether the count value is within the specified range (S107). If the count value is not within the specified range, it controls the storage time for each pixel PX1 and PX2 (S109) and returns to S104.

[0145] Next, the solid-state imaging device determines whether the frame number is the last frame number (S108). If the frame number is the last frame number, the process is terminated.

[0146] On the other hand, if the solid-state imaging device does not have the last frame number, it returns to S101 and repeats the process from S102 to S109.

[0147] Note that while Figure 17 shows an example of switching between edge signal level images and edge images in units of 10 frames, the switching can be done in units of other numbers of frames. Also, while Figure 17 shows an example of switching between edge signal level images and edge images in units of a predetermined number of frames, the edge signal level image can be acquired continuously.

[0148] Thus, in the eighth embodiment described above, the storage time of each pixel PX1 and PX2 is controlled based on the level determination result of the pixel signal read from each pixel PX1 and PX2. This makes it possible to optimize the amount of charge stored in each pixel PX1 and PX2 according to the incident intensity, thereby improving edge detection accuracy. Furthermore, by switching between the edge / signal level image and the edge image in units of a predetermined number of frames, it is possible to perform edge determination for each frame without needing signal level determination for each frame, thereby improving the frame rate.

[0149] <9. The ninth embodiment> In the first embodiment described above, a switching unit KEB is provided that switches the inverting input of a comparator CP1, to which the pixel signal read from pixel PX2 is input as a non-inverting input, between the pixel signal read from pixel PX1 and a reference signal REF. In this ninth embodiment, substrates on which a solid-state imaging device is formed, each having a pixel array section in which pixels PX are arranged in a matrix, are stacked.

[0150] Figure 18 is a perspective view showing an example of the configuration of an imaging device according to the ninth embodiment.

[0151] In figure a, the solid-state imaging device 901 comprises a support substrate 911 and a semiconductor substrate 912. The semiconductor substrate 912 is laminated on the support substrate 911. A pixel array section 913 and peripheral circuits 914 are formed on the semiconductor substrate 912. A column readout circuit 915 and a column ADC 916 are formed on the peripheral circuits 914. The column readout circuit 915 and the column ADC 916 may be formed on both sides of the pixel array section 913 in the column direction.

[0152] In the pixel array section 913, pixels PX are arranged in a matrix along the row direction and the column direction. The column readout circuit 915 can use any of the configurations of the first to eighth embodiments described above. The column ADC 916 can perform AD conversion on a column-by-column basis on the signals read out via the column readout circuit 915. In this case, the solid-state imaging device 901 can be configured as a back-illuminated image sensor.

[0153] In figure b, the solid-state imaging device 902 comprises semiconductor substrates 921 and 922. The semiconductor substrate 922 is stacked on the semiconductor substrate 921. A pixel array section 923 is formed on the semiconductor substrate 922. A peripheral circuit 924 is formed on the semiconductor substrate 922. A column readout circuit 925 and a column ADC 926 are formed on the peripheral circuit 924. The column readout circuit 925 can be configured in any of the first to eighth embodiments described above. The column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction. In this case, the solid-state imaging device 902 can be configured as a back-illuminated image sensor.

[0154] Thus, in the ninth embodiment described above, the substrates on which each solid-state imaging device 901 and 902 is formed are stacked. This makes it possible to thin the semiconductor substrates 912 and 922 on which each pixel array section 913 and 923 is formed, while supporting each pixel array section 913 and 923, thereby forming a back-illuminated image sensor.

[0155] <10. Examples of applications to mobile devices> The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0156] Figure 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0157] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 19, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0158] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0159] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0160] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0161] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0162] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0163] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0164] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0165] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0166] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example in Figure 19, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0167] Figure 20 shows an example of the installation position of the imaging unit 12031.

[0168] In Figure 20, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0169] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0170] Figure 20 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0171] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0172] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0173] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0174] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0175] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 12031 of the configuration described above. Specifically, for example, each imaging device of the above embodiment can be applied to the imaging unit 12031. By applying the technology described herein to the vehicle control system 12000, it is possible to detect image edges and illumination while suppressing increases in the size and power consumption of the imaging unit 12031.

[0176] The embodiments described above are merely examples for realizing the present technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of the present technology bearing the same name. However, the present technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology. Furthermore, the effects described herein are merely examples and are not limiting, and other effects may also exist.

[0177] Furthermore, this technology can also be configured as follows. (1) Multiple pixels that output pixel signals, The first pixel signal read from the first pixel is input to the first input, and a comparison unit compares the first input with the second input. A switching unit that switches the second input of the comparison unit between the second pixel signal read from the second pixel and the reference signal. An imaging device equipped with the following features. (2) A level setting circuit that sets the signal level of at least one of the first pixel signal and the second pixel signal by a predetermined gain. The imaging apparatus according to claim 1, comprising: The imaging apparatus according to (1) above, comprising: (3) A gain switching control unit that switches the gain of the level setting circuit based on the comparison result between the first pixel signal and the reference signal. The imaging apparatus according to (2) above, comprising: (4) The switching unit is A cutoff switch for blocking the input of the second pixel signal to the second input, A reference switch that switches the input of the reference signal to the second input, An imaging device according to any one of (1) to (3) above, comprising: (5) The reference switch is connected to the second input side of the cutoff switch. The imaging apparatus according to (3) above, comprising: (6) A first input capacitor connected to the first input, The second input capacitance connected to the aforementioned second input, The reference signal is applied via the reference switch, and the reference capacitor connected in parallel to the second input capacitor is The imaging apparatus according to (4) above, comprising: (7) A first input capacitor connected to the first input, The second input capacitance connected to the aforementioned second input, The reference signal is applied via the reference switch, and the reference capacitor connected between the second input capacitor and the cutoff switch is The imaging apparatus according to (4) above, comprising: (8) Reference signal generation unit that generates the reference signal The imaging apparatus according to (4) above, comprising: (9) The reference signal is set to a value that allows for the determination of the saturation level of the pixel. The imaging device described in any of (1) to (8) above. (10) The reference signal is switchable to multiple levels. The imaging device described in any of (1) to (9) above. (11) A first holding unit that holds the comparison result of the first pixel signal and the second pixel signal, A second holding unit that holds the comparison result between the first pixel signal and the reference signal, An imaging device according to any one of (1) to (10) above, comprising: (12) A counter that performs a counting operation based on the comparison result between the first pixel signal and the reference signal. An imaging device according to any one of (1) to (11) above, comprising: (13) Offset switching control unit that controls the offset when comparing the first pixel signal and the second pixel signal based on the comparison result of the first pixel signal and the reference signal. An imaging device according to any one of (1) to (12) above, comprising: (14) Storage time control circuit that controls the storage time of the pixel based on the comparison result of the first pixel signal and the reference signal. An imaging device according to any one of (1) to (13) above, comprising: (15) The storage time control circuit controls the storage time of the pixels in units of a predetermined number of frames. The imaging device described in (14) above. (16) In controlling the accumulation time of the pixels, an edge-signal level image in which both the edge and signal level have been determined and an edge image in which only the edge has been determined are switched at predetermined frame intervals. The imaging device described in (15) above. [Explanation of Symbols]

[0178] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image Processing Unit 105 Storage section 106 Display section 107 Operation section 108 Bus 111 Pixel Array Section 112 Vertical scanning circuit 113 Column Readout Circuit 114 Column Signal Processing Unit 114A Column ADC section 115 Horizontal scanning circuit 116 Control circuits PX pixels HCL Horizontal Drive Line VSL vertical signal line PD photodiode FD Floating Diffusion TG Transfer Transistor 123 Reset Transistor 124 Amplifying Transistors 125 Selective Transistors KEB switching unit SA1, SA2 shutoff switches SB1, SB2 Reference Switch C1, C2 reference capacity CP1, CP2 comparators HA1, HA2, HB1, HB2 holding part

Claims

1. Multiple pixels that output pixel signals, The first pixel signal read from the first pixel is input to the first input, and a comparison unit compares the first input with the second input. A switching unit that switches the second input of the comparison unit between the second pixel signal read from the second pixel and the reference signal. An imaging device equipped with the following features.

2. A level setting circuit that sets the signal level of at least one of the first pixel signal and the second pixel signal by a predetermined gain. The imaging apparatus according to claim 1, comprising:

3. A gain switching control unit switches the gain of the level setting circuit based on the comparison result between the first pixel signal and the reference signal. The imaging device according to claim 2, comprising:

4. The aforementioned switching unit is A cutoff switch for blocking the input of the second pixel signal to the second input, A reference switch that switches the input of the reference signal to the second input, The imaging apparatus according to claim 1, comprising:

5. The reference switch is connected to the second input side of the cutoff switch. The imaging device according to claim 3, comprising:

6. A first input capacitor connected to the first input, The second input capacitance connected to the second input, The reference signal is applied via the reference switch, and the reference capacitor connected in parallel to the second input capacitor is The imaging device according to claim 4, comprising:

7. A first input capacitor connected to the first input, The second input capacitance connected to the second input, The reference signal is applied via the reference switch, and the reference capacitor connected between the second input capacitor and the cutoff switch is The imaging device according to claim 4, comprising:

8. Reference signal generation unit that generates the aforementioned reference signal The imaging device according to claim 4, comprising:

9. The reference signal is set to a value that allows for the determination of the pixel's saturation level. The imaging apparatus according to claim 1.

10. The aforementioned reference signal is switchable to multiple levels. The imaging apparatus according to claim 1.

11. A first holding unit that holds the comparison result between the first pixel signal and the second pixel signal, A second holding unit that holds the comparison result between the first pixel signal and the reference signal, The imaging apparatus according to claim 1, comprising:

12. A counter that performs a counting operation based on the comparison result between the first pixel signal and the reference signal. The imaging apparatus according to claim 1, comprising:

13. An offset switching control unit controls the offset during the comparison of the first pixel signal and the second pixel signal based on the comparison result of the first pixel signal and the reference signal. The imaging apparatus according to claim 1, comprising:

14. An accumulation time control circuit controls the accumulation time of the pixel based on the comparison result between the first pixel signal and the reference signal. The imaging apparatus according to claim 1, comprising:

15. The storage time control circuit controls the storage time of the pixels in units of a predetermined number of frames. The imaging apparatus according to claim 14.

16. In controlling the accumulation time of the aforementioned pixels, an edge / signal level image in which both edges and signal levels have been determined, and an edge image in which only edges have been determined, are switched at predetermined frame intervals. The imaging apparatus according to claim 15.

Images