Nitride semiconductor devices

Abstract

We provide nitride semiconductor devices with high voltage resistance. [Solution] The nitride semiconductor device 1 comprises a substrate 10, an n-type semiconductor layer 12 provided above the substrate 10, a p-type semiconductor layer 14 provided above the n-type semiconductor layer 12, a buffer layer 16 provided above the p-type semiconductor layer 14, a channel layer 18 provided above the buffer layer 16, a barrier layer 20 provided above the channel layer 18, a gate electrode 30 provided above the barrier layer 20, a source electrode 32 and a drain electrode 34 provided above the buffer layer 16 and electrically connected to the channel layer 18, a p-type contact layer 26 provided in contact with the inner surface of a first opening 24 that penetrates the barrier layer 20, the channel layer 18 and the buffer layer 16 and reaches the p-type semiconductor layer 14, an ohmic electrode 36 provided in contact with the contact layer 26 and electrically connected to the source electrode 32, and a lower electrode 38 provided below the substrate 10.

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, a diode, and a transistor. In the semiconductor device disclosed in Patent Document 1, the cathode of the diode is formed on the first surface side of the semiconductor substrate, and the anode is formed on the second surface side. Further, the transistor is formed on the first surface with a buffer layer interposed therebetween.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the conventional semiconductor device described above, a leakage current may flow between the source electrode and the drain electrode via the interface between the buffer layer and the channel layer. This leads to the problem of insufficient withstand voltage.

[0005] Accordingly, the present disclosure provides a nitride semiconductor device with high withstand voltage.

Means for Solving the Problems

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes: a substrate; an n-type first semiconductor layer provided above the substrate; a p-type second semiconductor layer provided above the first semiconductor layer; a first nitride semiconductor layer provided above the second semiconductor layer; a second nitride semiconductor layer provided above the first nitride semiconductor layer; a third nitride semiconductor layer provided above the second nitride semiconductor layer and having a larger band gap than the second nitride semiconductor layer; a gate electrode provided above the third nitride semiconductor layer; a source electrode and a drain electrode provided above the first nitride semiconductor layer and electrically connected to the second nitride semiconductor layer; a p-type contact layer provided in contact with the inner surface of a first opening that penetrates the third nitride semiconductor layer, the second nitride semiconductor layer, and the first nitride semiconductor layer to reach the second semiconductor layer; an ohmic electrode provided in contact with the contact layer and electrically connected to the source electrode; and a lower electrode provided below the substrate.

Effects of the Invention

[0007] According to the present disclosure, a nitride semiconductor device with high withstand voltage can be provided.

Brief Description of the Drawings

[0008] [Figure 1] FIG. 1 is a cross-sectional view of the nitride semiconductor device according to Embodiment 1. [Figure 2] FIG. 2 is a plan view of the nitride semiconductor device according to Embodiment 1. [Figure 3] FIG. 3 is a cross-sectional view of a nitride semiconductor device according to a modification of Embodiment 1. [Figure 4] FIG. 4 is a cross-sectional view in an outer peripheral region of the nitride semiconductor device according to the modification of Embodiment 1. [Figure 5] FIG. 5 is a plan view showing a mounting layout of the nitride semiconductor device according to Embodiment 1. [Figure 6] FIG. 6 is a cross-sectional view of the nitride semiconductor device according to Embodiment 2. [Figure 7]Figure 7 is a cross-sectional view of a nitride semiconductor device according to Embodiment 3. [Figure 8] Figure 8 is a cross-sectional view of a nitride semiconductor device according to a modified example of Embodiment 3. [Figure 9] Figure 9 is a cross-sectional view of a nitride semiconductor device according to Embodiment 4. [Modes for carrying out the invention]

[0009] (Summary of this disclosure) A nitride semiconductor device according to a first aspect of the present disclosure comprises a substrate, an n-type first semiconductor layer provided above the substrate, a p-type second semiconductor layer provided above the first semiconductor layer, a first nitride semiconductor layer provided above the second semiconductor layer, a second nitride semiconductor layer provided above the first nitride semiconductor layer, a third nitride semiconductor layer provided above the second nitride semiconductor layer and having a larger band gap than the second nitride semiconductor layer, a gate electrode provided above the third nitride semiconductor layer, a source electrode and a drain electrode provided above the first nitride semiconductor layer and electrically connected to the second nitride semiconductor layer, a p-type contact layer provided in contact with the inner surface of a first opening that penetrates the third nitride semiconductor layer, the second nitride semiconductor layer and the first nitride semiconductor layer and reaches the second semiconductor layer, an ohmic electrode provided in contact with the contact layer and electrically connected to the source electrode, and a lower electrode provided below the substrate.

[0010] As a result, a depletion layer extends from the p-type contact layer near the interface between the second nitride semiconductor layer and the first nitride semiconductor layer, thereby reducing leakage current across the interface. This enables the realization of nitride semiconductor devices with high breakdown voltage. Furthermore, since the n-type first semiconductor layer and the p-type second semiconductor layer constitute a vertical pn diode, the breakdown voltage can be further increased. In addition, since an ohmic electrode is connected to the pn diode via the contact layer, good ohmic contact can be obtained.

[0011] A nitride semiconductor device according to a second aspect of the present disclosure is a nitride semiconductor device according to a first aspect, wherein the second nitride semiconductor layer is divided into an active region and an inactive region in a plan view of the substrate, the gate electrode, the source electrode and the drain electrode are provided in the active region in a plan view of the substrate, and the first opening penetrates the inactive region.

[0012] As a result, two-dimensional electron gas (2DEG) is not generated in the inert region, reducing the 2DEG region connected to the source electrode. Therefore, parasitic capacitance between the gate and source can be reduced. In addition, the inert region can be effectively utilized in the formation of the pn diode, thus reducing the chip area.

[0013] A nitride semiconductor device according to a third aspect of this disclosure is a nitride semiconductor device according to a second aspect, comprising a threshold adjustment layer provided between the third nitride semiconductor layer and the gate electrode.

[0014] This allows the transistor threshold to be adjusted.

[0015] A nitride semiconductor device according to a fourth aspect of this disclosure is a nitride semiconductor device according to a third aspect, wherein the threshold adjustment layer is a p-type semiconductor layer.

[0016] This allows the potential at the conduction band edge of the channel located below the threshold adjustment layer to be increased, thereby raising the threshold. For example, it can be easily implemented as a normally-off transistor.

[0017] A nitride semiconductor device according to a fifth aspect of this disclosure is a nitride semiconductor device according to a third or fourth aspect, wherein the main component of the threshold adjustment layer is the same as the main component of the contact layer.

[0018] This allows the threshold adjustment layer and the contact layer to be formed in the same process.

[0019] A nitride semiconductor device according to a sixth aspect of this disclosure is a nitride semiconductor device according to any one of the third to fifth aspects, wherein the contact layer mainly comprises a p-type nitride semiconductor.

[0020] This allows the contact layer to be formed by methods such as epitaxial growth, similar to other nitride semiconductor layers.

[0021] A nitride semiconductor device according to the seventh aspect of this disclosure is a nitride semiconductor device according to any one of the third to fifth aspects, wherein the contact layer mainly comprises a p-type oxide semiconductor.

[0022] This allows oxide semiconductor films to be formed with good coverage using methods such as sputtering or atomic layer deposition (ALD).

[0023] A nitride semiconductor device according to the eighth aspect of this disclosure is a nitride semiconductor device according to any one of the third to seventh aspects, wherein the threshold adjustment layer is provided so as to cover a recess provided in the third nitride semiconductor layer.

[0024] This allows the transistor threshold to be adjusted by adjusting the depth of the recess. Furthermore, since the portion of the third nitride semiconductor layer other than the recess does not substantially affect the threshold, the concentration of 2DEG can be increased by making the non-recessed portion thicker. A higher concentration of 2DEG reduces the on-resistance.

[0025] A nitride semiconductor device according to the ninth aspect of this disclosure is a nitride semiconductor device according to any one of the first to eighth aspects, wherein the ohmic electrode is in contact with the first semiconductor layer through a second opening that penetrates the contact layer and the second semiconductor layer at the bottom surface of the first opening and reaches the first semiconductor layer.

[0026] This makes it possible to realize an MPS (Merged PiN Schottky) diode that combines the advantages of both pn diodes and Schottky barrier diodes. For example, it can achieve high voltage resistance and low operating voltage.

[0027] A nitride semiconductor device according to a tenth aspect of the present disclosure is a nitride semiconductor device according to any one of the second to eighth aspects, wherein, in a plan view of the substrate, a third opening is provided in the outer peripheral region surrounding the active region and the inactive region, which penetrates the third nitride semiconductor layer, the second nitride semiconductor layer, the first nitride semiconductor layer, and the second semiconductor layer and reaches the first semiconductor layer.

[0028] This allows for the electrical isolation of the device through the third aperture.

[0029] A nitride semiconductor device according to an eleventh aspect of this disclosure is a nitride semiconductor device according to a tenth aspect, comprising an insulating film that contacts and covers the inner surface of the third opening.

[0030] As a result, the insulating film covers the third opening, thereby reducing the leakage current in the outer region.

[0031] A nitride semiconductor device according to a twelfth aspect of this disclosure is a nitride semiconductor device according to an eleventh aspect, wherein the insulating film includes at least one of O and N and Si.

[0032] This allows for the formation of a good insulating film.

[0033] A nitride semiconductor device according to a thirteenth aspect of this disclosure is a nitride semiconductor device according to an eleventh aspect, wherein the insulating film includes at least one of O and N and Al.

[0034] This allows for the formation of a good insulating film.

[0035] A nitride semiconductor device according to a fourteenth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to thirteenth aspects, comprising a source electrode and a source pad electrically connected to the source electrode, provided above the ohmic electrode so as to cover the first opening.

[0036] This allows for the formation of a pn diode by effectively utilizing the area below the source pad, thereby reducing the chip area.

[0037] A nitride semiconductor device according to a 15th aspect of the present disclosure is a nitride semiconductor device according to any one of the 1st to 14th aspects, comprising a first graphene layer that contacts and covers the upper surface of the second semiconductor layer, and the first opening further penetrates the first graphene layer.

[0038] This allows the heat generated by the transistor to be efficiently dissipated through the graphene layer.

[0039] A nitride semiconductor device according to the sixteenth aspect of this disclosure is a nitride semiconductor device according to the fifteenth aspect, wherein the substrate, the first semiconductor layer, and the second semiconductor layer all contain SiC as the main component.

[0040] This allows the heat generated by the transistor to be efficiently dissipated through the substrate and semiconductor layer, which mainly contain SiC.

[0041] A nitride semiconductor device according to the 17th aspect of this disclosure is a nitride semiconductor device according to any one of the 1st to 16th aspects, wherein the substrate, the first semiconductor layer, and the second semiconductor layer all contain a nitride semiconductor as a main component.

[0042] This reduces the likelihood of lattice mismatch and improves the film quality of the nitride semiconductor layer. Consequently, leakage currents mediated by crystal defects and interface states can be reduced, and the breakdown voltage of nitride semiconductor devices can be increased.

[0043] The embodiments will be described in detail below with reference to the drawings.

[0044] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, any components in the following embodiments that are not described in an independent claim will be described as optional components.

[0045] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale may not necessarily match in each figure. Also, in each figure, substantially identical components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0046] Furthermore, in this specification, terms indicating relationships between elements such as parallel and orthogonal, terms indicating the shape of elements such as rectangles, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent.

[0047] Furthermore, in this specification, the "thickness direction" of the substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layer and is also referred to as the "vertical direction." In addition, the direction parallel to the main surface of the substrate may be referred to as the "horizontal direction." A "vertical" semiconductor device means a device in which the main path of the drain current is in the vertical direction, that is, a device in which the drain current passes through the substrate in the vertical direction. A "horizontal" semiconductor device means a device in which the main path of the drain current is in the horizontal direction, that is, a device in which the drain current does not pass through the substrate.

[0048] Furthermore, the side of the substrate on which the heterostructure generating 2DEG is provided is considered the "upper" or "upper side," and the opposite side is considered the "lower" or "lower side." In this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather are used as terms defined by the relative positional relationship based on the stacking order in the stacked configuration. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close contact with each other and are in touch.

[0049] Furthermore, in this specification, unless otherwise specified, "plan view" refers to a view of the semiconductor device substrate from a direction perpendicular to the main surface, that is, a view of the main surface of the substrate from the front.

[0050] Furthermore, in this specification, "A and B overlap in a plan view" means that at least a part of A and at least a part of B overlap. That is, this includes cases where only a part of A and only a part of B overlap, where all of A overlaps with B, where all of B overlaps with A, where A and B completely overlap each other, and so on.

[0051] Furthermore, n-type and p-type represent the conductivity types of semiconductors, and they are conductivity types with opposite polarities. + The "type" indicates a state in which a high concentration of n-type dopant is added to the semiconductor, also known as heavy doping. - The term "type" refers to a state in which a low concentration of n-type dopant is added to a semiconductor, also known as light doping. + Type and n - All of these types are examples of n types, and they may be referred to simply as n types without distinction. Also, p types, p + type and p - The same applies to the dopants. For n-type dopants in nitride semiconductors, Si and Ge are used. For p-type dopants in nitride semiconductors, Mg and Be are used.

[0052] Further, in the present specification, the term "main component" means the component having the highest content ratio among all components constituting a member. For example, a component with a content ratio of 50% or more is the main component. The component may be a material, an element, a compound, or the like.

[0053] Further, in the present specification, AlGaN refers to the ternary mixed crystal Al x Ga 1-x N (0<x<1). Hereinafter, multi-component mixed crystals are abbreviated by the sequence of their respective constituent element symbols, such as AlInN, GaInN, and the like. For example, Al which is an example of a nitride semiconductor x Ga 1-x-y In y N (0<x<1, 0<y<1, and 0<x+y<1) is abbreviated as AlGaInN. x, 1-x-y, and y represent the composition ratios of Al, Ga, and In, respectively.

[0054] Further, in the present specification, ordinal numbers such as "first" and "second" do not indicate the number or order of constituent elements unless otherwise specified, and are used for the purpose of avoiding confusion and distinguishing constituent elements of the same type.

[0055] (Embodiment 1) [Configuration] First, the configuration of the semiconductor device according to Embodiment 1 will be described with reference to FIG. 1 and FIG. 2.

[0056] FIG. 1 is a cross-sectional view of the nitride semiconductor device 1 according to the present embodiment. FIG. 2 is a plan view of the nitride semiconductor device 1 according to the present embodiment. FIG. 1 shows a cross section obtained by combining the cross section taken along line IA-IA and the cross section taken along line IB-IB shown in FIG. 2.

[0057] Note that in FIG. 1, each constituent element such as a semiconductor layer, an insulating layer, and an electrode included in the nitride semiconductor device 1 is hatched with oblique lines representing a cross section. Note that the oblique hatching representing the cross section is omitted for the channel layer 18. The same applies to other cross-sectional views from FIG. 3 onwards.

[0058] The nitride semiconductor device 1 shown in Figure 1 is a normally-off type lateral transistor. That is, the threshold voltage of the nitride semiconductor device 1 is greater than 0V. In the nitride semiconductor device 1, for example, the source electrode 32 is grounded and a positive potential is applied to the drain electrode 34. When a potential below the threshold voltage, such as 0V or a negative potential, is applied to the gate electrode 30, the nitride semiconductor device 1 becomes non-conductive, i.e., off, and no current flows between the source electrode 32 and the drain electrode 34. When a positive potential exceeding the threshold voltage is applied to the gate electrode 30, the nitride semiconductor device 1 becomes conductive, i.e., on, and current flows from the drain electrode 34 towards the source electrode 32. The current that flows from the drain electrode 34 towards the source electrode 32 when the device is on is also called the drain current. The drain current flows in a direction parallel to the main surface of the substrate 10, i.e., in the lateral direction.

[0059] As shown in Figure 2, the nitride semiconductor device 1 can be divided into a device region 2, an element isolation region 3, and an outer peripheral region 4 in a plan view. Note that the outer peripheral region 4 is not required.

[0060] Device region 2 is the area enclosed by the dotted rectangle shown in Figure 2. Device region 2 is the main region of the nitride semiconductor device 101 and is also called the operating region or active region. Device region 2 is provided with a gate electrode 30, a source electrode 32, and a drain electrode 34. Specifically, multiple source electrodes 32 and multiple drain electrodes 34 are arranged alternately in device region 2, with a gate electrode 30 in between. When the device region 2 is ON, 2DEG19 is generated and a drain current flows.

[0061] The element isolation region 3 is the region other than the device region 2, and is also called the peripheral region, inactive region, or pad region. In a plan view of the substrate 10, the element isolation region 3 is provided in an annular shape surrounding the rectangular device region 2. The element isolation region 3 is provided with gate wiring 50, gate pad 51, source pad 53, and drain pad 55. In addition, multiple source wirings 52 and multiple drain wirings 54 are provided so as to extend from the element isolation region 3 toward the device region 2.

[0062] The outer peripheral region 4 is the region that surrounds the device region 2 and the element isolation region 3 in a plan view. For example, as shown in Figure 2, the outer peripheral region 4 is provided in a ring shape along the outer edge of the substrate 10. The outer peripheral region 4 is also called the termination region. Note that multiple devices can be formed on a single substrate 10. In this case, the outer peripheral region 4 is provided to isolate the devices and does not necessarily have to be along the outer edge of the substrate 10.

[0063] The nitride semiconductor device 1 according to this embodiment is a nitride semiconductor device in which the semiconductor layer including the channel mainly contains nitride semiconductor. Specifically, each of the n-type semiconductor layer 12, p-type semiconductor layer 14, buffer layer 16, channel layer 18, barrier layer 20, threshold adjustment layer 22, and contact layer 26 mainly contains nitride semiconductor.

[0064] Nitride semiconductor device 1 is a device having an AlGaN / GaN heterostructure. Due to spontaneous polarization and piezoelectric polarization occurring on the (0001) plane of GaN, a high concentration of 2DEG19 is generated near the heterointerface. Therefore, even when undoped, 1 × 10¹⁶ 2DEG19 is generated near the heterointerface. 13 cm -2 The above sheet carrier concentrations can be obtained. Nitride semiconductor device 1 is a high electron mobility transistor (HEMT) containing 2DEG19 as the channel.

[0065] As shown in Figure 1, the nitride semiconductor device 1 comprises a substrate 10, an n-type semiconductor layer 12, a p-type semiconductor layer 14, a buffer layer 16, a channel layer 18, a barrier layer 20, a threshold adjustment layer 22, a contact layer 26, a gate electrode 30, a source electrode 32, a drain electrode 34, an ohmic electrode 36, a lower electrode 38, and an insulating film 40. A first opening 24 is provided in the element isolation region 3 of the nitride semiconductor device 1. As shown in Figure 2, the nitride semiconductor device 1 also comprises a gate wiring 50, a source wiring 52, a drain wiring 54, a gate pad 51, a source pad 53, and a drain pad 55.

[0066] The substrate 10 is a nitride semiconductor substrate mainly composed of nitride semiconductors such as GaN. For example, the substrate 10 has a thickness of 300 μm and a carrier concentration of 5 × 10¹⁶ 18 cm -3 n + The substrate mainly contains GaN of type [type]. The planar shape of the substrate 10 is, for example, rectangular, but is not limited to this.

[0067] The substrate 10 may be a semiconductor substrate such as a silicon (Si) substrate or a zinc oxide (ZnO) substrate. Alternatively, the substrate 10 may be a conductive substrate such as a graphite substrate containing graphene.

[0068] The n-type semiconductor layer 12 is an example of an n-type first semiconductor layer and is provided above the substrate 10. The n-type semiconductor layer 12 mainly contains a nitride semiconductor. The n-type semiconductor layer 12 is a nitride semiconductor layer containing at least one of In, Al, and Ga. The n-type semiconductor layer 12 is, for example, an n-type semiconductor layer with a thickness of 8 μm. - This film mainly contains n-type GaN. The n-type semiconductor layer 12 contains, for example, Si as an n-type dopant (also called n-type impurity). The donor concentration of the n-type semiconductor layer 12 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 1 x 10 17 cm -3 The following is an example: 1 × 10 16 cm-3 Furthermore, the carbon concentration (C concentration) of the n-type semiconductor layer 12 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 5 x 10 16 cm -3 The following describes the n-type semiconductor layer 12, which is provided in contact with the upper surface (main surface) of the substrate 10.

[0069] The p-type semiconductor layer 14 is an example of a second p-type semiconductor layer and is provided above the n-type semiconductor layer 12. The p-type semiconductor layer 14 mainly contains a nitride semiconductor. The p-type semiconductor layer 14 is a nitride semiconductor layer containing at least one of In, Al, and Ga. For example, the p-type semiconductor layer 14 has a thickness of 400 nm and a carrier concentration of 1 × 10⁻¹⁶ 17 cm -3 This film mainly contains p-type GaN. The p-type semiconductor layer 14 contains, for example, Mg as a p-type dopant (also called a p-type impurity). The concentration of p-type impurities in the p-type semiconductor layer 14 is, for example, 5 × 10⁻⁶. 18 cm -3 The above 2 x 10 19 cm -3 The following applies: The p-type semiconductor layer 14 is provided in contact with the upper surface of the n-type semiconductor layer 12.

[0070] The buffer layer 16 is an example of a first nitride semiconductor layer and is provided above the p-type semiconductor layer 14. Specifically, the buffer layer 16 is provided in contact with the upper surface of the p-type semiconductor layer 14. The buffer layer 16 has, for example, a stacked structure of multiple nitride semiconductor layers. Each of the multiple nitride semiconductor layers mainly contains an i-type nitride semiconductor such as GaN, AlGaN, or AlN. The buffer layer 16 is provided to increase the breakdown voltage between the drain electrode 34 provided above and the p-type semiconductor layer 14. For example, the thickness of the buffer layer 16 is 4 μm or more and 12 μm or less. The buffer layer 16 may be made highly resistive by adding, for example, carbon. The carbon concentration of the buffer layer 16 is higher than the carbon concentration of the n-type semiconductor layer 12, for example, 5 × 10⁻¹⁶. 17 cm -3 The above 5 x 10 18 cm-3 The following applies:

[0071] The channel layer 18 is an example of a second nitride semiconductor layer and is provided above the buffer layer 16. Specifically, the channel layer 18 is provided in contact with the upper surface of the buffer layer 16. The channel layer 18 is a nitride semiconductor layer containing at least one of In, Al, and Ga. For example, the channel layer 18 mainly contains undoped GaN. A portion of the channel layer 18 may be made n-type by adding impurities such as Si. The thickness of the channel layer 18 is, for example, 150 nm, but is not particularly limited.

[0072] The channel layer 18 is a layer containing the channel of the nitride semiconductor device 1, and is the layer through which drain current flows when the nitride semiconductor device 1 is turned on. The channel layer 18 is sometimes also called the electron transport layer. Specifically, 2DEG19 is generated within the channel layer 18 near the interface with the barrier layer 20. 2DEG19 extends parallel to the main surface of the substrate 10 along the interface between the channel layer 18 and the barrier layer 20.

[0073] The barrier layer 20 is an example of a third nitride semiconductor layer and is provided above the channel layer 18. Specifically, the barrier layer 20 is provided in contact with the upper surface of the channel layer 18. The barrier layer 20 is a nitride semiconductor layer containing at least one of In, Al, and Ga. For example, the barrier layer 20 is a layer mainly composed of undoped AlGaN. The barrier layer 20 has a larger band gap than the channel layer 18. Therefore, an AlGaN / GaN heterointerface is formed between the barrier layer 20 and the channel layer 18. The barrier layer 20 supplies electrons to the channel (i.e., 2DEG19) formed in the channel layer 18. The barrier layer 20 is sometimes called an electron supply layer.

[0074] In this embodiment, the barrier layer 20 is provided with a recess 21. The recess 21 is a recess that extends from the upper surface of the barrier layer 20 toward the substrate 10. In the portion where the recess 21 is provided, the thickness of the barrier layer 20 is reduced. As the thickness of the barrier layer 20 is reduced, the polarization is weakened, making it less likely for 2DEG19 to occur directly below the recess 21. Therefore, the threshold of the transistor can be adjusted by adjusting the depth of the recess 21. For example, when the gate-source voltage is 0V, it is possible to prevent 2DEG19 from occurring directly below the recess 21, making it easy to achieve normally-off operation of the transistor. The thickness of the portion of the barrier layer 20 where the recess 21 is provided is, for example, 15nm to 25nm. The thickness of the portion where the recess 21 is provided is the distance between the bottom surface of the recess 21 and the lower surface of the barrier layer 20.

[0075] Since the threshold can be adjusted in the portion where the recess portion 21 is provided, it becomes possible to increase the thickness of the barrier layer 20 in the portion where the recess portion 21 is not provided. As the thickness of the barrier layer 20 increases, the concentration of 2DEG19 increases, which reduces the on-resistance. In this way, by providing the recess portion 21, it is possible to achieve both normally-off operation of the transistor and reduction of on-resistance. Note that the recess portion 21 does not necessarily have to be provided, and the thickness of the barrier layer 20 may be constant.

[0076] The threshold adjustment layer 22 is provided between the barrier layer 20 and the gate electrode 30. Specifically, the threshold adjustment layer 22 is provided in contact with the upper surface of the barrier layer 20 and the lower surface of the gate electrode 30, respectively. The threshold adjustment layer 22 contacts and covers at least a portion of the bottom surface of the recess portion 21. In this embodiment, the threshold adjustment layer 22 is provided so as to cover the recess portion 21. For example, the threshold adjustment layer 22 contacts and covers the bottom surface and side surface of the recess portion 21 and the portion of the upper surface of the barrier layer 20 near the upper end of the side surface of the recess portion 21. The threshold adjustment layer 22 is provided between the source electrode 32 and the drain electrode 34, spaced apart from each of them.

[0077] The threshold adjustment layer 22 is a p-type semiconductor layer. Specifically, the threshold adjustment layer 22 is a p-type nitride semiconductor layer containing at least one of In, Al, and Ga. For example, the threshold adjustment layer 22 is a layer mainly composed of p-type GaN. In this embodiment, the main component of the threshold adjustment layer 22 is the same as the main component of the contact layer 26. For example, Mg is added to the threshold adjustment layer 22 as a p-type impurity. For example, the threshold adjustment layer 22 has a thickness of 200 nm and a carrier concentration of 1 × 10⁻¹⁶. 19 cm -3 This is a film made of p-type GaN. Note that the thickness of the threshold adjustment layer 22 and the carrier concentration are merely examples and can be changed as appropriate.

[0078] The presence of the threshold adjustment layer 22 raises the potential at the conduction band edge of the channel. This reduces the carrier concentration directly below the threshold adjustment layer 22, allowing the transistor's threshold to be shifted to the positive side. As a result, normally-off operation of the transistor can be easily achieved.

[0079] The first opening 24 is an opening that penetrates the barrier layer 20, the channel layer 18, and the buffer layer 16 to reach the p-type semiconductor layer 14. The bottom surface 24a of the first opening 24 is part of the p-type semiconductor layer 14. The bottom surface 24a is flush with the interface between the buffer layer 16 and the p-type semiconductor layer 14, but may be located below this interface. The bottom surface 24a is, for example, parallel to the main surface of the substrate 10.

[0080] In this embodiment, the first opening 24 is formed such that its opening area increases as it moves away from the substrate. Specifically, the side surface 24b of the first opening 24 is inclined at an angle. The inclination angle of the side surface 24b is not particularly limited and may be 90°. That is, the side surface 24b may be perpendicular to the bottom surface 24a.

[0081] The contact layer 26 is provided in contact with the inner surface of the first opening 24. Specifically, the contact layer 26 contacts and covers the bottom surface 24a and the side surface 24b of the first opening 24. The contact layer 26 covers the side surface 24b from the lower end to the upper end, but it may cover only a part of the side surface 24b. For example, the contact layer 26 may cover only the portion of the side surface 24b in which the buffer layer 16 is exposed, and not cover the portion of the channel layer 18 and barrier layer 20 that is exposed. Alternatively, the contact layer 26 may cover only the portion of the side surface 24b in which the buffer layer 16 and channel layer 18 are exposed, and not cover the portion of the barrier layer 20 that is exposed. Furthermore, a part of the contact layer 26 may cover a part of the upper surface of the barrier layer 20 outside the first opening 24. The thickness of the contact layer 26 is uniform, but is not limited to this.

[0082] In this embodiment, the contact layer 26 mainly comprises a p-type nitride semiconductor. The contact layer 26 contains at least one of In, Al, and Ga. For example, the contact layer 26 is a layer mainly comprising p-type GaN. For example, the main components of the contact layer 26 are the same as the main components of the threshold adjustment layer 22. The contact layer 26 can be formed in the same process as the threshold adjustment layer 22.

[0083] The gate electrode 30 is located above the barrier layer 20. In this embodiment, the gate electrode 30 is located above the threshold adjustment layer 22. Specifically, the gate electrode 30 is in contact with the upper surface of the threshold adjustment layer 22 and is electrically connected to the threshold adjustment layer 22.

[0084] The gate electrode 30 is formed using a conductive material such as a metal. For example, the gate electrode 30 can be made of a material that is ohmic connected to a p-type nitride semiconductor such as p-type GaN. For example, Pd, Ni, WSi, Pt, Au, etc. can be used as the gate electrode 30. The gate electrode 30 is a single layer or multilayer film formed using a single metal or an alloy of two or more metals.

[0085] The source electrode 32 and drain electrode 34 are located above the buffer layer 16 and are electrically connected to the channel layer 18. Specifically, the source electrode 32 and drain electrode 34 are located in contact with the upper surface of the barrier layer 20. The source electrode 32 and drain electrode 34 are spaced apart from the gate electrode 30 and the threshold adjustment layer 22, respectively, with the gate electrode 30 and the threshold adjustment layer 22 sandwiched between them.

[0086] The source electrode 32 and the drain electrode 34 are each formed using a conductive material such as a metal. For example, the source electrode 32 and the drain electrode 34 can each be made of a material that is ohmic connected to an n-type nitride semiconductor such as n-type GaN. The source electrode 32 and the drain electrode 34 are single-layer or multilayer films formed using a single metal or an alloy of two or more metals. For example, Ti, Al, Mo, Hf, etc. can be used as the source electrode 32 and the drain electrode 34. The source electrode 32 and the drain electrode 34 have, for example, the same composition. The source electrode 32 and the drain electrode 34 can be formed in the same process.

[0087] The ohmic electrode 36 is provided in contact with the contact layer 26 and is electrically connected to the source electrode 32. The ohmic electrode 36 is formed with a uniform thickness along the upper surface of the contact layer 26, but is not limited to this. The ohmic electrode 36 may be provided so as to contact only the portion of the contact layer 26 that is along the bottom surface 24a of the first opening 24. Alternatively, the ohmic electrode 36 may be provided so as to fill the inside of the first opening 24, or it may cover a portion of the upper surface of the barrier layer 20 outside the first opening 24.

[0088] The ohmic electrode 36 is formed using a conductive material such as a metal. For example, the ohmic electrode 36 can be made of a material that is ohmic-connected to a p-type nitride semiconductor such as p-type GaN. For example, Pd, Ni, WSi, Pt, Au, etc. can be used as the ohmic electrode 36. The ohmic electrode 36 is a single layer or multilayer film formed using a single metal or an alloy of two or more metals. The ohmic electrode 36 may have the same composition as the gate electrode 30. In this case, the ohmic electrode 36 and the gate electrode 30 can be formed in the same process.

[0089] The lower electrode 38 is an electrode located on the underside of the substrate 10. The lower electrode 38 is also called the back electrode. Specifically, the lower electrode 38 is located in contact with the underside of the substrate 10 and is electrically connected to the drain electrode 34.

[0090] The lower electrode 38 is formed using a conductive material such as a metal. For example, the lower electrode 38 can be made of a material that is ohmic connected to an n-type nitride semiconductor such as n-type GaN. The lower electrode 38 is a single layer or multilayer film formed using a single metal or an alloy of two or more metals. For example, Ti, Al, Mo, Hf, etc. can be used as the lower electrode 38.

[0091] The insulating film 40 is provided above the gate electrode 30, source electrode 32, and drain electrode 34. Specifically, the insulating film 40 is provided so as to cover the barrier layer 20, gate electrode 30, source electrode 32, and drain electrode 34. The insulating film 40 contains at least one of O and N, and Si. Alternatively, the insulating film 40 may contain at least one of O and N, and Al. The insulating film 40 has a laminated structure of multiple insulating films. The multiple insulating films are, for example, insulating films such as SiN, SiO2, SiON, and Al2O3. The insulating film 40 may also have a single-layer structure of one insulating film.

[0092] As shown in Figure 1, a source wire 52 and a drain wire 54 are provided above the insulating film 40. Although not shown in Figure 1, a source pad 53 and a drain pad 55, as shown in Figure 2, are also provided above the insulating film 40. The insulating film 40 is provided with through holes for electrically connecting the source wire 52 and the source electrode 32, and through holes for electrically connecting the drain wire 54 and the drain electrode 34. In the example shown in Figure 2, the gate electrode 30 is located on the same layer as the gate wire 50 and the gate pad 51, but this is not the only option. The gate wire 50 and the gate pad 51 may be provided above the insulating film 40.

[0093] The gate wiring 50, the multiple source wirings 52 and the multiple drain wirings 54, as well as the gate pad 51, source pad 53 and drain pad 55, are all provided above the barrier layer 20. The gate wiring 50 and the multiple source wirings 52 are provided at different heights, with a portion of the insulating film 40 between them to prevent contact between them. The height refers to the distance from the main surface of the substrate 10. For example, the gate wiring 50 is provided so as to extend inside the insulating film 40 in a direction parallel to the main surface of the substrate 10. The multiple source wirings 52 and the multiple drain wirings 54 are provided on the upper surface of the insulating film 40.

[0094] In this embodiment, there is a one-to-one correspondence between the source wiring 52 and the source electrode 32. The source wiring 52 is located above the corresponding source electrode 32 in the device region 2. The source wiring 52 is electrically connected to the source pad 53 and the corresponding source electrode 32.

[0095] Furthermore, the drain wiring 54 and the drain electrode 34 correspond one-to-one. The drain wiring 54 is located above the corresponding drain electrode 34 in the device region 2. The drain wiring 54 is electrically connected to the drain pad 55 and the corresponding drain electrode 34.

[0096] The gate pad 51, source pad 53, and drain pad 55 are all provided on the insulating film 40, with their respective upper surfaces exposed. The gate pad 51 and gate wiring 50 are provided at the same height, but may be electrically connected by conductive vias or the like provided in the insulating film 40. The same applies to the source pad 53 and source wiring 52, and the drain pad 55 and drain wiring 54.

[0097] Furthermore, as shown in Figures 1 and 2, a portion of the source wiring 52 extends beyond the gate electrode 30 to the drain electrode 34. The portion of the source wiring 52 located between the gate electrode 30 and the drain electrode 34 in a plan view of the substrate 10 is the source field plate 52A. The source field plate 52A can alleviate electric field concentration between the gate and drain.

[0098] Furthermore, the source pad 53 is provided so as to cover the source via hole 60. The source via hole 60 is a through-hole penetrating the insulating film 40 and includes a first opening 24 penetrating the barrier layer 20, the channel layer 18, and the buffer layer 16. For example, as shown in Figure 1, the source pad 53 is provided along the inner surface of the source via hole 60 and is in contact with the ohmic electrode 36 within the first opening 24. The source pad 53 may completely fill the first opening 24 or completely fill the source via hole 60. In other words, the upper surface of the source pad 53 may be flattened.

[0099] The gate wiring 50, multiple source wirings 52 and multiple drain wirings 54, as well as the gate pad 51, source pad 53 and drain pad 55, are all formed using a metallic material. Suitable metallic materials for the pads and wiring include metals with low resistivity and high thermal conductivity, such as Au or Cu. The pads and wiring are single-layer metal films made of one type of metal or an alloy of two or more types of metals, but they may also be laminated films of multiple metal films with different compositions.

[0100] In addition, in the element isolation region 3, a portion of the channel layer 18 may be made highly resistive. Figure 3 is a cross-sectional view of a nitride semiconductor device 101 according to a modified example of Embodiment 1.

[0101] In the nitride semiconductor device 101 shown in Figure 3, a high-resistance region 70 is provided spanning the channel layer 18 and the barrier layer 20. The high-resistance region 70 includes the entire barrier layer 20 in the device isolation region 3 and the upper part of the channel layer 18. The high-resistance region 70 may also include the entire channel layer 18 in the device isolation region 3. In the nitride semiconductor device 101 according to this modified example, the first opening 24 penetrates the high-resistance region 70.

[0102] The high-resistance region 70 is formed by implanting B or Fe into the channel layer 18 and the barrier layer 20 by ion implantation. As a result, 2DEG19 does not occur in the high-resistance region 70. The high-resistance region 70 is an inactivated region of the channel layer 18 and can also be called an inactive region. The channel layer 18 can be divided into an active region located in the device region 2 and an inactive region located in the element isolation region 3. The high-resistance region 70 is a region of the channel layer 18 with higher resistance than the active region.

[0103] Thus, since 2DEG19 does not occur in the inert region of the channel layer 18, the region of 2DEG19 connected to the source electrode 32 becomes smaller. Therefore, the parasitic capacitance between the gate and source can be reduced. In addition, the inert region can be effectively utilized for the formation of the pn diode, which will be explained below, so the chip area can be reduced.

[0104] [Main characteristic configuration] In the nitride semiconductor device 1 according to this embodiment, a vertical pn diode is formed, comprising a p-type semiconductor layer 14, an n-type semiconductor layer 12, and an n-type substrate 10. The pn diode is also called a body diode. The ohmic electrode 36 is the anode electrode of the body diode and is electrically connected to the source electrode 32. The lower electrode 38 is the cathode electrode of the body diode and is electrically connected to the drain electrode 34.

[0105] The body diode is connected between the source electrode 32 and the drain electrode 34 of the transistor. When the transistor is turned on, the drain electrode 34 is at a higher potential than the source electrode 32, so a reverse bias is applied to the body diode. Therefore, if the avalanche breakdown voltage of the body diode is low, current can flow through the body diode when an overvoltage is applied between the drain electrode 34 and the source electrode 32. In other words, the overvoltage can be absorbed by the body diode, and the destruction of the transistor can be suppressed.

[0106] Specifically, the avalanche breakdown voltage of the body diode is designed to be lower than the longitudinal breakdown voltage between the p-type semiconductor layer 14 electrically connected to the source electrode 32 and the drain electrode 34. Furthermore, the avalanche breakdown voltage of the body diode is designed to be lower than the lateral breakdown voltage between the gate electrode 30 and the drain electrode 34. This allows the body diode to absorb overvoltages, thereby suppressing transistor failure. Note that the longitudinal breakdown voltage may be lower than or equal to the lateral breakdown voltage.

[0107] A first opening 24, a contact layer 26, and an ohmic electrode 36 are provided to electrically connect the p-type semiconductor layer 14 of the body diode, which is provided to absorb overvoltage, to the source electrode 32. The end of the interface between the buffer layer 16 and the channel layer 18 is exposed on the side surface 24b of the first opening 24. The interface between the buffer layer 16 and the channel layer 18 can become a path for leakage current flowing between the source electrode 32 and the drain electrode 34. Specifically, leakage current can flow from the source electrode 32 through the source wiring 52, source pad 53, and ohmic electrode 36 to the interface between the buffer layer 16 and the channel layer 18, and then between the source electrode 34 and the drain electrode 34.

[0108] In contrast, in this embodiment, a contact layer 26 is provided so as to cover the end of the interface between the buffer layer 16 and the channel layer 18 that is exposed on the side surface 24b of the first opening 24. As a result, the depletion layer extends from the side surface 24b to include the vicinity of the interface between the buffer layer 16 and the channel layer 18. Therefore, the contact resistance between the ohmic electrode 36 and the interface between the buffer layer 16 and the channel layer 18 can be increased. Consequently, leakage current from the source electrode 32 through the ohmic electrode 36 can be suppressed, and the breakdown voltage of the nitride semiconductor device 1 can be increased.

[0109] Furthermore, the contact layer 26 covers the upper surface of the p-type semiconductor layer 14 by contacting it at the bottom surface 24a of the first opening 24, so the ohmic electrode 36 and the p-type semiconductor layer 14 are not in direct contact. Since etching damage remains at the bottom surface 24a of the first opening 24 when the first opening 24 is formed, the contact resistance would be high if the ohmic electrode 36 and the p-type semiconductor layer 14 were in contact. In contrast, by bringing the ohmic electrode 36 into contact with the contact layer 26, good contact can be achieved. This makes it possible to reduce the resistance of the body diode.

[0110] Furthermore, in this embodiment, an opening and an insulating film are provided to suppress leakage current in the outer peripheral region 4 of the nitride semiconductor device 1. The specific configuration of the outer peripheral region 4 will be described below using a cross-sectional view of a nitride semiconductor device 101 in which a high-resistance region 70 is provided. Figure 4 is a cross-sectional view of the outer peripheral region 4 of a nitride semiconductor device 101 according to a modified example of this embodiment. Note that a similar structure can be provided even in the case of a nitride semiconductor device 1 in which the high-resistance region 70 is not provided. Figure 4 corresponds to the cross-section along line IV-IV shown in Figure 2.

[0111] As shown in Figure 4, a third opening 62 is provided in the outer peripheral region 4. For this reason, the outer peripheral region 4 is sometimes referred to as the mesa separation region.

[0112] The third opening 62 penetrates the barrier layer 20, the channel layer 18, the buffer layer 16, and the p-type semiconductor layer 14 to reach the n-type semiconductor layer 12. The bottom surface 62a of the third opening 62 is part of the n-type semiconductor layer 12. The bottom surface 62a is located below the interface between the p-type semiconductor layer 14 and the n-type semiconductor layer 12, but may be flush with the interface. The bottom surface 62a is, for example, parallel to the main surface of the substrate 10. In this embodiment, the side surface 62b of the third opening 62 is inclined at an angle. The inclination angle of the side surface 62b is not particularly limited and may be 90°. That is, the side surface 62b may be perpendicular to the bottom surface 62a.

[0113] Furthermore, the nitride semiconductor device 101 includes an insulating film 42. The insulating film 42 contacts and covers the inner surface of the third opening 62. Specifically, the insulating film 42 contacts and covers the bottom surface 62a and the side surface 62b of the third opening 62.

[0114] The insulating film 42 comprises at least one of O and N, and Si. Alternatively, the insulating film 42 may comprise at least one of O and N, and Al. For example, the insulating film 42 is an insulating film such as SiN, SiO2, SiON, or Al2O3. The insulating film 42 may have a single-layer structure or a multilayer structure.

[0115] The insulating film 42 is formed, for example, by a spin coating method. In the spin coating method, a liquid insulating film material is applied to a wafer, the material is spread across the entire wafer by rotating it, and then it is baked. By removing water and organic components through baking, the insulating film 42 is formed.

[0116] Compared to general film deposition methods such as plasma CVD and sputtering, the spin coating method can suppress process damage during film deposition at the pn junction interface on the side surface 62b of the third aperture 62. Therefore, it is possible to suppress the increase in leakage current during the off state and improve the off-state characteristics.

[0117] Figure 4 shows an example where the thickness of the insulating film 42 is uniform, but the thickness of the insulating film 42 may vary depending on the location. The insulating film 42 formed using the spin coating method may not be formed uniformly. Specifically, it may be formed thicker in lower areas such as inside the third opening 62, and thinner and with a smoother shape in higher areas such as on the barrier layer 20. In addition to the spin coating method, the insulating film 42 may also be formed by other deposition methods such as thermal CVD, ALD, or remote plasma CVD, in which the plasma does not come into contact with the substrate.

[0118] The insulating film 42 may also be provided within the device region 2. Specifically, the insulating film 40 shown in Figures 1 and 3 may have a layered structure, and one of the multiple insulating films included in the insulating film 40 may be the insulating film 42. Alternatively, the insulating film 42 may be the same as the insulating film 40.

[0119] Furthermore, a gentler slope of the side surface 62b improves the coverage of the insulating film 42. This suppresses leakage current in the outer peripheral region 4. Conversely, if the slope of the side surface 62b is steeper, the area of ​​the outer peripheral region 4 in plan view can be reduced. This enables miniaturization of the nitride semiconductor device 101. The slope of the side surface 62b may be adjusted according to the requirements for suppressing leakage current and miniaturization.

[0120] Here, we will describe specific implementation examples of the nitride semiconductor device 1 or 101. Figure 5 is a diagram showing the implementation layout of the nitride semiconductor device 1 according to this embodiment.

[0121] The nitride semiconductor device 1 or 101 is bonded to the die frame 85 using solder material or the like. This electrically connects the lower electrode 38 of the nitride semiconductor device 1 or 101 to the die frame 85.

[0122] Furthermore, as shown in Figure 5, wires 90 are connected to the gate pad 51, source pad 53, and drain pad 55, respectively. Wires 90 are conductive metal wires such as Au, Al, and Cu. Wires 90 are also called bonding wires. The multiple wires 90 specifically include wires 90g, 90sf, 90ss, and 90d.

[0123] Specifically, the gate pad 51 is connected to the gate terminal 80 via wire 90g. The source pad 53 is connected to the source force terminal 82 via multiple wires 90sf and to the source sense terminal 83 via wire 90ss. The drain pad 55 is connected to the drain terminal 84 via multiple wires 90d. The number of wires 90 connecting each pad to each terminal is not particularly limited.

[0124] The gate terminal 80, source force terminal 82, and drain terminal 84 are terminals for receiving power from an external source to supply power to the gate electrode 30, source electrode 32, and drain electrode 34, respectively. The source sense terminal 83 is a terminal for detecting the source potential. The source sense terminal 83 is optional. The layout and shape of each terminal are not particularly limited. Since the die frame 85 and the drain terminal 84 are electrically connected, the drain electrode 34 and the lower electrode 38 can be electrically connected.

[0125] (Embodiment 2) Next, Embodiment 2 will be described.

[0126] Embodiment 2 differs from Embodiment 1 primarily in that the body diode is an MPS diode. The following explanation will focus on the differences from Embodiment 1, omitting or simplifying the explanation of the commonalities.

[0127] Figure 6 is a cross-sectional view of the nitride semiconductor device 201 according to this embodiment. Figure 6 corresponds to the cross-section along the IB-IB line in Figure 2. The cross-sectional configurations of the device region 2 and the outer peripheral region 4 of the nitride semiconductor device 201 according to this embodiment are the same as the cross-sectional configurations of the nitride semiconductor device 1 or 101 shown in Figure 1 or Figure 3.

[0128] As shown in Figure 6, the nitride semiconductor device 201 differs from the nitride semiconductor device 101 shown in Figure 3 in that it has an ohmic electrode 236 instead of an ohmic electrode 36. The ohmic electrode 236 is in contact with the n-type semiconductor layer 12 through a second opening 260.

[0129] The second opening 260 penetrates the contact layer 26 and the p-type semiconductor layer 14 at the bottom surface 24a of the first opening 24 and reaches the n-type semiconductor layer 12. The bottom surface of the second opening 260 is part of the n-type semiconductor layer 12. The second opening 260 is formed by partially and continuously etching away the contact layer 26 and the p-type semiconductor layer 14 within the first opening 24 after the contact layer 26 has been formed. At this time, the surface layer of the n-type semiconductor layer 12 may be removed. In this case, the bottom surface of the second opening 260 will be below the interface between the p-type semiconductor layer 14 and the n-type semiconductor layer 12.

[0130] In this embodiment, the ohmic electrode 236 contacts both the p-type semiconductor layer 14 and the n-type semiconductor layer 12. Specifically, the ohmic electrode 236 is ohmic-connected to the p-type semiconductor layer 14 and functions as the anode electrode of a pn diode composed of the p-type semiconductor layer 14 and the n-type semiconductor layer 12. The ohmic electrode 236 is also Schottky-connected to the n-type semiconductor layer 12, forming a Schottky barrier diode (SBD). In other words, in this embodiment, an MPS diode including a pn diode and an SBD is provided as the body diode. This makes it possible to achieve high breakdown voltage and low operating voltage.

[0131] In the example shown in Figure 6, there are three second openings 260, but the design is not limited to this. The number and size of the second openings 260 are not particularly limited, nor is the size of the contact area between the ohmic electrode 236 and the n-type semiconductor layer 12.

[0132] Furthermore, while a high-resistance region 70 is provided in the element isolation region 3 of the nitride semiconductor device 201, this is not limited to that. In the nitride semiconductor device 201, similar to the nitride semiconductor device 1, a high-resistance region 70 is not required.

[0133] (Embodiment 3) Next, Embodiment 3 will be described.

[0134] Embodiment 3 differs from Embodiment 1 mainly in that the contact layer contains an oxide semiconductor as its main component. Below, we will focus on explaining the differences from Embodiment 1, and omit or simplify the explanation of the common points.

[0135] Figure 7 is a cross-sectional view of the nitride semiconductor device 301 according to this embodiment. Similar to Figures 1 and 3, Figure 7 is a cross-sectional view that combines the cross-section along the IA-IA line and the cross-section along the IB-IB line in Figure 2. The cross-sectional configuration of the outer peripheral region 4 of the nitride semiconductor device 301 according to this embodiment is the same as the cross-sectional configuration of the nitride semiconductor device 1 or 101 shown in Figure 1 or Figure 3.

[0136] As shown in Figure 7, the nitride semiconductor device 301 differs from the nitride semiconductor device 101 shown in Figure 3 in that it has a contact layer 326 instead of a contact layer 26. The contact layer 326 mainly contains a p-type oxide semiconductor. For example, the contact layer 326 is a layer mainly containing NiO or Ga2O3.

[0137] The contact layer 326, which mainly contains a p-type oxide semiconductor, can be formed with good coverage by sputtering or ALD. This suppresses the increase in resistance and leakage current. In the case of the contact layer 326, which mainly contains a p-type oxide semiconductor, a depletion layer spreads near the interface between the buffer layer 16 and the channel layer 18, similar to the first embodiment, so that the leakage current between the source electrode 32 and the drain electrode 34 can be suppressed.

[0138] In the nitride semiconductor device 301, the main components of the contact layer 326 and the threshold adjustment layer 22 are different, so the contact layer 326 and the threshold adjustment layer 22 must be formed in different processes. Alternatively, the threshold adjustment layer 22 may contain a p-type oxide semiconductor as its main component, similar to the contact layer 326.

[0139] Figure 8 is a cross-sectional view of a nitride semiconductor device 302 according to a modified example of this embodiment. Similar to Figure 7, Figure 8 corresponds to a cross-sectional view combining the cross-section along the IA-IA line and the cross-section along the IB-IB line in Figure 2. The cross-sectional configuration of the outer peripheral region 4 of the nitride semiconductor device 302 according to this modified example is the same as the cross-sectional configuration of nitride semiconductor device 1 or 101 shown in Figure 1 or Figure 3.

[0140] As shown in Figure 8, the nitride semiconductor device 302 differs from the nitride semiconductor device 301 shown in Figure 7 in that it has a threshold adjustment layer 322 instead of a threshold adjustment layer 22. The threshold adjustment layer 322 mainly contains a p-type oxide semiconductor. Specifically, the main component of the threshold adjustment layer 322 is the same as the main component of the contact layer 326. This allows the threshold adjustment layer 322 and the contact layer 326 to be formed in the same process.

[0141] In nitride semiconductor devices 301 and 302, a high-resistance region 70 is provided in the element isolation region 3, but this is not limited to nitride semiconductor devices 301 and 302. Similar to nitride semiconductor device 1, a high-resistance region 70 is not required in nitride semiconductor devices 301 and 302. Furthermore, nitride semiconductor devices 301 and 302 may be equipped with an MPS diode as a body diode, as shown in Figure 6. That is, a second opening 260 may be provided on the bottom surface 24a of the first opening 24.

[0142] (Embodiment 4) Next, Embodiment 4 will be described.

[0143] Embodiment 4 differs from Embodiment 1 mainly in that the substrate, n-type semiconductor layer, and p-type semiconductor layer all contain SiC as the main component. Below, we will focus on explaining the differences from Embodiment 1, and omit or simplify the explanation of the common points.

[0144] Figure 9 is a cross-sectional view of the nitride semiconductor device 401 according to this embodiment. Similar to Figures 1 and 3, Figure 9 corresponds to a cross-sectional view combining the cross-section along the IA-IA line and the cross-section along the IB-IB line in Figure 2. The cross-sectional configuration of the outer peripheral region 4 of the nitride semiconductor device 401 according to this embodiment is the same as the cross-sectional configuration of the nitride semiconductor device 1 or 101 shown in Figure 1 or Figure 3.

[0145] As shown in Figure 9, the nitride semiconductor device 401 differs from the nitride semiconductor device 101 shown in Figure 3 in that it includes a substrate 410, an n-type semiconductor layer 412, and a p-type semiconductor layer 414 instead of the substrate 10, n-type semiconductor layer 12, and p-type semiconductor layer 14. Furthermore, the nitride semiconductor device 401 includes graphene layers 415 and 452.

[0146] The substrate 410 is a SiC substrate containing SiC as its main component. For example, the substrate 410 has a thickness of 100 μm n + This substrate mainly contains type 10 SiC. The donor concentration of substrate 410 is, for example, 1 × 10 17 cm -3 The above 1 x 10 19 cm -3 The following applies: SiC can be 4H-SiC, 6H-SiC, or 3C-SiC, etc.

[0147] The n-type semiconductor layer 412 is an example of a first semiconductor layer mainly composed of n-type SiC, and is provided above the substrate 410. The n-type semiconductor layer 412 is, for example, an n-type semiconductor layer with a thickness of 7 μm. - This film mainly contains n-type SiC. The n-type semiconductor layer 412 contains an n-type dopant, such as N or P. The donor concentration of the n-type semiconductor layer 412 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 1 x 10 17 cm -3 The following is an example: 1 × 10 16 cm -3 The n-type semiconductor layer 412 is provided, for example, in contact with the upper surface (main surface) of the substrate 410.

[0148] The p-type semiconductor layer 414 is an example of a second semiconductor layer mainly composed of p-type SiC, and is provided above the n-type semiconductor layer 412. The p-type semiconductor layer 414 has, for example, a thickness of 400 nm and a carrier concentration of 1 × 10⁻¹⁶ 17 cm -3This film mainly contains p-type SiC. The p-type semiconductor layer 414 contains p-type dopants, such as Al and B. The concentration of p-type impurities in the p-type semiconductor layer 414 is, for example, 5 × 10⁻⁶. 18 cm -3 The above 2 x 10 19 cm -3 The following is the case: The p-type semiconductor layer 414 is provided in contact with the upper surface of the n-type semiconductor layer 412.

[0149] The graphene layer 415 is an example of a first graphene layer, and it contacts and covers the upper surface of the p-type semiconductor layer 414. The graphene layer 415 is, for example, an epitaxial graphene layer formed by epitaxial growth. As shown in Figure 9, the graphene layer 415 is not provided on the bottom surface 24a of the first opening 24. That is, the first opening 24 penetrates not only the barrier layer 20, the channel layer 18, and the buffer layer 16, but also the graphene layer 415.

[0150] The graphene layer 452 is an example of a second graphene layer and is provided on the source wiring 52, source pad 53, and drain wiring 54. Although not shown in Figure 9, the graphene layer 452 may also be provided on the drain pad 55, gate pad 51, and gate wiring 50. The graphene layer 452 is also called a graphene cap layer.

[0151] Graphene layers 415 and 452, as well as SiC, have higher thermal conductivity than nitride semiconductors. Therefore, the heat generated in the transistor can be dissipated efficiently.

[0152] In the nitride semiconductor device 401, a high-resistance region 70 is provided in the element isolation region 3, but this is not limited to this. In the nitride semiconductor device 401, the high-resistance region 70 is not required, similar to the nitride semiconductor device 1. In addition, the nitride semiconductor device 401 may be equipped with an MPS diode as shown in Figure 6 as the body diode. That is, a second opening 260 may be provided on the bottom surface 24a of the first opening 24. Furthermore, the nitride semiconductor device 401 may be equipped with a contact layer 326 mainly composed of a p-type oxide semiconductor instead of the contact layer 26. In addition, the nitride semiconductor device 401 may be equipped with a threshold adjustment layer 322 mainly composed of a p-type oxide semiconductor instead of the threshold adjustment layer 22.

[0153] (Other embodiments) Although nitride semiconductor devices according to one or more embodiments have been described above based on embodiments, this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to these embodiments that a person skilled in the art could conceive, as well as forms constructed by combining components from different embodiments, are also included within the scope of this disclosure.

[0154] For example, in the above embodiment, the source electrode 32 and the drain electrode 34 are provided on the upper surface of the barrier layer 20, but this is not limited to this. At least one of the source electrode 32 and the drain electrode 34 may be provided in contact with the 2DEG 19. For example, source openings and drain openings may be provided that penetrate the barrier layer 20 and reach the channel layer 18. The bottom surfaces of the source opening and the drain opening are located below the interface between the barrier layer 20 and the channel layer 18. This allows the 2DEG 19 to be exposed on the sides of the source opening and the drain opening. By forming the source electrode 32 in the source opening and the drain electrode 34 in the drain opening, the 2DEG 19 can be brought into contact with the source electrode 32 and the drain electrode 34. This reduces the on-resistance.

[0155] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or equivalents thereof. [Industrial applicability]

[0156] The nitride semiconductor devices relating to this disclosure are useful, for example, as power devices used in power supply circuits, inverter circuits, and the like for electrical equipment. [Explanation of Symbols]

[0157] 1, 101, 201, 301, 302, 401 Nitride Semiconductor Devices 2 Device Areas 3-element isolation region 4 Outer area 10,410 boards 12,412 n-type semiconductor layer 14,414 p-type semiconductor layer 16 Buffer Layers 18 channel layers 19 2DEG 20 Barrier layer 21 Recessed section 22,322 threshold adjustment layer 24 First opening 24a, 62a Bottom 24b, 62b side 26, 326 contact layers 30 Postal Codes 32 Source electrodes 34 Drain electrode 36,236 ohmic electrodes 38 Lower electrode 40, 42 Insulating film 50 gate wiring 51 Gate Pad 52 Source Wiring 52A Source Field Plate 53 Sourcepad 54 Drain wiring 55 Drain Pad 60 Source Beer Hall 62 Third opening 70 High resistance region 80 Gate terminals 82 Source Force Terminal 83 Source Sense Terminal 84 Drain terminal 85 Die Frame 90, 90d, 90g, 90sf, 90ss wire 260 Second opening 415, 452 Graphene layer

Claims

1. circuit board and An n-type first semiconductor layer provided above the substrate, A p-type second semiconductor layer is provided above the first semiconductor layer, A first nitride semiconductor layer provided above the second semiconductor layer, A second nitride semiconductor layer is provided above the first nitride semiconductor layer, A third nitride semiconductor layer is provided above the second nitride semiconductor layer and has a larger band gap than the second nitride semiconductor layer, A gate electrode provided above the third nitride semiconductor layer, A source electrode and a drain electrode are provided above the first nitride semiconductor layer and electrically connected to the second nitride semiconductor layer, A p-type contact layer is provided in contact with the inner surface of a first opening that penetrates the third nitride semiconductor layer, the second nitride semiconductor layer, and the first nitride semiconductor layer and reaches the second semiconductor layer, An ohmic electrode provided in contact with the contact layer and electrically connected to the source electrode, The substrate comprises a lower electrode provided below the substrate, Nitride semiconductor devices.

2. The second nitride semiconductor layer is divided into an active region and an inactive region in a plan view of the substrate. The gate electrode, the source electrode, and the drain electrode are provided within the active region in a plan view of the substrate. The first opening penetrates the inert region. The nitride semiconductor device according to claim 1.

3. The device comprises a threshold adjustment layer provided between the third nitride semiconductor layer and the gate electrode. The nitride semiconductor device according to claim 2.

4. The threshold adjustment layer is a p-type semiconductor layer. The nitride semiconductor device according to claim 3.

5. The main component of the threshold adjustment layer is the same as the main component of the contact layer. The nitride semiconductor device according to claim 4.

6. The contact layer mainly comprises a p-type nitride semiconductor. A nitride semiconductor device according to any one of claims 3 to 5.

7. The contact layer mainly comprises a p-type oxide semiconductor. A nitride semiconductor device according to any one of claims 3 to 5.

8. The threshold adjustment layer is provided so as to cover the recess portion provided in the third nitride semiconductor layer. A nitride semiconductor device according to any one of claims 3 to 5.

9. The ohmic electrode is in contact with the first semiconductor layer through a second opening that penetrates the contact layer and the second semiconductor layer at the bottom surface of the first opening and reaches the first semiconductor layer. A nitride semiconductor device according to any one of claims 1 to 5.

10. In a plan view of the substrate, the outer peripheral region surrounding the active region and the inactive region is provided with a third opening that penetrates the third nitride semiconductor layer, the second nitride semiconductor layer, the first nitride semiconductor layer, and the second semiconductor layer and reaches the first semiconductor layer. A nitride semiconductor device according to any one of claims 2 to 5.

11. The third opening is provided with an insulating film that contacts and covers the inner surface, The nitride semiconductor device according to claim 10.

12. The insulating film comprises at least one of O and N, and Si. The nitride semiconductor device according to claim 11.

13. The insulating film comprises at least one of O and N, and Al. The nitride semiconductor device according to claim 11.

14. The source pad is provided above the ohmic electrode so as to cover the first opening and is electrically connected to the source electrode and the ohmic electrode. A nitride semiconductor device according to any one of claims 1 to 5.

15. The second semiconductor layer comprises a first graphene layer that contacts and covers the upper surface of the second semiconductor layer, The first opening further penetrates the first graphene layer. A nitride semiconductor device according to any one of claims 1 to 5.

16. The substrate, the first semiconductor layer, and the second semiconductor layer all contain SiC as the main component. The nitride semiconductor device according to claim 15.

17. The substrate, the first semiconductor layer, and the second semiconductor layer all contain nitride semiconductors as their main component. A nitride semiconductor device according to any one of claims 1 to 5.

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