Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present invention provides a semiconductor device comprising a silicide layer provided above a silicon layer in a contact hole, and a method for manufacturing a semiconductor device. [Solution] A semiconductor device comprising an interlayer insulating film 38 provided above a silicon layer 110, an intervening layer 66 provided above the interlayer insulating film, a barrier metal layer 60 provided above the intervening layer, a front-side metal layer 53 provided above the barrier metal layer, and a silicide layer 63 provided above the silicon layer in a contact hole 54, wherein the manufacturing method includes the steps of providing an interlayer insulating film above the silicon layer, providing an intervening layer above the interlayer insulating film, providing a barrier metal layer above the intervening layer, providing a silicide layer above the silicon layer in a contact hole provided in the interlayer insulating film, and providing a front-side metal layer above the barrier metal layer.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 describes a semiconductor device comprising a "first alloy layer," an "oxide layer," a "barrier metal layer," and a "plug layer." [Prior art document] [Patent] [Patent Document 1] International Publication No. 2024 / 014401 [Patent Document 2] International Publication No. 2024 / 014402 [Patent Document 3] International Publication No. 2024 / 171683 [Patent Document 4] Patent No. 7420270 [Patent Document 5] Japanese Unexamined Patent Publication No. 2021-168418 [Patent Document 6] Japanese Unexamined Patent Publication No. 2024-084054 [Patent Document 7] Japanese Unexamined Patent Publication No. 2024-101464 [Overview of the project]

[0003] In a first embodiment of the present invention, a semiconductor device is provided comprising: a silicon layer; an interlayer insulating film of silicate glass having a contact hole and provided above the silicon layer; an intervening layer provided above the interlayer insulating film; a barrier metal layer provided above the intervening layer; a front-side metal layer provided above the barrier metal layer; and a silicide layer provided above the silicon layer in the contact hole.

[0004] In the semiconductor device described above, the thickness of the intervening layer may be thinner than the thickness of the interlayer insulating film.

[0005] In any of the above semiconductor devices, the thickness of the intervening layer above the interlayer insulating film may be 3 nm or more and 20 nm or less.

[0006] In any of the semiconductor devices described above, the barrier metal layer may be in contact with the silicide layer.

[0007] In any of the above semiconductor devices, the fluorine concentration of the intervening layer may be lower than the fluorine concentration on the upper surface of the interlayer insulating film.

[0008] In any of the semiconductor devices described above, the interlayer insulating film may include a first insulating layer provided above the silicon layer and a second insulating layer provided above the first insulating layer and having a higher fluorine concentration than the first insulating layer.

[0009] In any of the semiconductor devices described above, the intervening layer may be in contact with the second insulating layer.

[0010] In any of the semiconductor devices described above, the barrier metal layer may include a first barrier metal portion provided above the intervening layer and a second barrier metal portion provided above the first barrier metal portion.

[0011] In any of the semiconductor devices described above, the first barrier metal portion and the second barrier metal portion may be provided above the interlayer insulating film and on the sidewall of the contact hole. The first barrier metal portion may be in contact with the sidewall of the contact hole.

[0012] In any of the semiconductor devices described above, the intervening layer, the first barrier metal portion, and the second barrier metal portion may be provided above the interlayer insulating film and on the side walls of the contact holes.

[0013] In any of the above semiconductor devices, the intervening layer may contain titanium nitride.

[0014] In any of the above-described semiconductor devices, the first barrier metal portion may contain titanium. The second barrier metal portion may contain titanium nitride.

[0015] In any of the semiconductor devices described above, the second barrier metal portion may contain titanium nitride that is denser than the intervening layer.

[0016] In any of the semiconductor devices described above, the intervening layer may include a silicon oxide film.

[0017] In any of the semiconductor devices described above, the first barrier metal portion may contain titanium. The second barrier metal portion may contain titanium nitride.

[0018] In a second aspect of the present invention, there is provided a semiconductor device comprising: a base layer; an interlayer insulating film having a contact hole and provided above the base layer; an intervening layer provided above the interlayer insulating film; a barrier metal layer provided above the intervening layer; a front-side metal layer provided above the barrier metal layer; and an alloy layer provided above the base layer in the contact hole.

[0019] In a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of: providing a silicate glass interlayer insulating film above a silicon layer; providing an intervening layer above the interlayer insulating film; providing a barrier metal layer above the intervening layer; providing a silicide layer above the silicon layer in a contact hole formed in the interlayer insulating film; and providing a front-side metal layer above the barrier metal layer.

[0020] The method for manufacturing a semiconductor device described above may include a step of forming the contact hole in the interlayer insulating film after the step of providing the interlayer insulating film and before the step of providing the intervening layer.

[0021] In any of the methods for manufacturing a semiconductor device described above, a step of implanting halide ions into the bottom of the contact hole may be included after the step of forming the contact hole and before the step of providing the intervening layer.

[0022] The method for manufacturing a semiconductor device according to any one of the above may comprise, after the step of providing the intervening layer and before the step of providing the barrier metal layer, a step of providing the contact hole in the interlayer insulating film.

[0023] The method for manufacturing a semiconductor device according to any one of the above may comprise, after the step of providing the contact hole and before the step of providing the barrier metal layer, a step of implanting halide ions into the bottom of the contact hole.

[0024] The method for manufacturing a semiconductor device according to any one of the above may comprise, before the step of implanting halide ions into the bottom of the contact hole, a step of providing a resist above the intervening layer.

[0025] In the method for manufacturing a semiconductor device according to any one of the above, the step of providing the interlayer insulating film may include a step of providing a first insulating layer above the silicon layer, and a step of providing a second insulating layer above the first insulating layer.

[0026] In the method for manufacturing a semiconductor device according to any one of the above, the step of providing the barrier metal layer is may include a step of providing a first barrier metal portion above the intervening layer, and a step of providing a second barrier metal portion above the first barrier metal portion.

[0027] The method for manufacturing a semiconductor device according to any one of the above may comprise, after the step of providing the intervening layer and before the step of providing the first barrier metal portion, an annealing step, and after the step of providing the second barrier metal portion and before the step of providing the front surface side metal layer, a sintering step.

[0028] The method for manufacturing a semiconductor device according to any one of the above may comprise no annealing step after the step of providing the intervening layer and before the step of providing the first barrier metal portion, and comprise a sintering step after the step of providing the second barrier metal portion and before the step of providing the front surface side metal layer.

[0029] In any of the above-described methods for manufacturing a semiconductor device, the step of providing the intervening layer may include the step of providing the intervening layer containing titanium nitride.

[0030] In any of the above methods for manufacturing a semiconductor device, the step of providing the first barrier metal portion may include the step of providing the first barrier metal portion containing titanium. The step of providing the second barrier metal portion may include the step of providing the second barrier metal portion containing titanium nitride.

[0031] In any of the above methods for manufacturing a semiconductor device, the step of providing the intervening layer may include the step of providing the intervening layer which includes a silicon oxide film.

[0032] In any of the above methods for manufacturing a semiconductor device, the step of providing the first barrier metal portion may include the step of providing the first barrier metal portion containing titanium. The step of providing the second barrier metal portion may include the step of providing the second barrier metal portion containing titanium nitride.

[0033] A fourth aspect of the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: providing an interlayer insulating film above a base layer; providing an intervening layer above the interlayer insulating film; providing a barrier metal layer above the intervening layer; providing an alloy layer above the base layer in a contact hole provided in the interlayer insulating film; and providing a front-side metal layer above the barrier metal layer.

[0034] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0035] [Figure 1A] An example of a top view of the semiconductor device 100 is shown. [Figure 1B] An example of a cross-section from a-a' in Figure 1A is shown. [Figure 1C]An example of a b-b' section in Figure 1A is shown. [Figure 2A] A modified top view of the semiconductor device 100 is shown. [Figure 2B] A modified top view of the semiconductor device 100 is shown. [Figure 2C] An example of a c-c' section in Figure 2B is shown. [Figure 2D] An example of a d-d' section in Figure 2B is shown. [Figure 3A] This is an enlarged cross-sectional view of semiconductor device 100. [Figure 3B] This is an enlarged cross-sectional view of semiconductor device 100. [Figure 4A] This is an enlarged cross-sectional view of semiconductor device 100. [Figure 4B] This is an enlarged cross-sectional view of semiconductor device 100. [Figure 5A] This is an enlarged cross-sectional view of semiconductor device 100. [Figure 5B] This is an enlarged cross-sectional view of semiconductor device 100. [Figure 6] An example of the e-e' section in Figure 1A or Figure 2B is shown. [Figure 7] An example of the f-f' section in Figure 1A or Figure 2B is shown. [Figure 8] An example of a top view of a semiconductor device 100 equipped with a temperature sensing unit 180 is shown. [Figure 9] This is an example of an enlarged cross-sectional view of the temperature sensing unit 180. [Figure 10A] An example of a g-g' cross section is shown in Figure 8. [Figure 10B] An example of a g-g' cross section is shown in Figure 8. [Figure 10C] An example of a g-g' cross section is shown in Figure 8. [Figure 11A] This is a flowchart showing an example of the manufacturing process for semiconductor device 100. [Figure 11B] An example of the manufacturing process for semiconductor device 100 is shown. [Figure 12A] This is a flowchart showing an example of the manufacturing process for semiconductor device 100. [Figure 12B] An example of the manufacturing process for semiconductor device 100 is shown. [Modes for carrying out the invention]

[0036] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0037] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0038] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0039] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0040] In this specification, when P+ type or N+ type is used, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is used, it means that the doping concentration is lower than that of P type or N type.

[0041] Figure 1A shows an example of a top view of a semiconductor device 100. In this example, the semiconductor device 100 is a semiconductor chip equipped with a transistor section 70. The semiconductor device 100 is not limited to a transistor, as long as it is a semiconductor element having a MOS gate structure on a semiconductor substrate 10.

[0042] The transistor section 70 is the region obtained by projecting the collector region 22, which is provided on the back side of the semiconductor substrate 10, onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT. In this example, the transistor section 70 is an IGBT. However, the transistor section 70 may also be other transistors such as a MOSFET.

[0043] In this figure, the region around the active part of the semiconductor device 100 is shown, and other regions are omitted. For example, an edge termination structure may be provided in the negative region in the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure has, for example, a guard ring, a field plate, a resurf, or a structure combining these. In this example, for convenience, the negative edge in the Y-axis direction is described, but the same applies to other edges of the semiconductor device 100.

[0044] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, a diamond substrate, or any other substrate. In this example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 is an example of a silicon layer 110, which will be described later. The silicon layer 110 is an example of a base layer. In this specification, when simply referred to as a "top view," it means viewing from the top side of the semiconductor substrate 10. The semiconductor substrate 10 has a front surface 21 and a back surface 23, as described later.

[0045] The semiconductor device 100 in this example comprises a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 also includes an emitter electrode 52 and a gate metal layer 50 located above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and gate metal layer 50 are examples of the front-side metal layer 53, which will be described later. The gate trench 40 is an example of the MOS gate structure of the semiconductor device 100. While the semiconductor device 100 in this example is a transistor with a MOS gate structure, it may also be a diode with a MOS gate structure.

[0046] The emitter electrode 52 is located above the gate trench 40, dummy trench 30, emitter region 12, base region 14, contact region 15, and well region 17. The gate metal layer 50 is located above the connection portion 25 and the well region 17.

[0047] The emitter electrode 52 and the gate metal layer 50 are formed from a metal-containing material. At least a portion of the emitter electrode 52 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 are provided separated from each other.

[0048] The emitter electrode 52 and gate metal layer 50 are provided above the semiconductor substrate 10, with an interlayer insulating film 38 in between. The interlayer insulating film 38 is omitted in Figure 1A. A barrier metal layer 60 and an intervening layer 66, described later, are provided between the emitter electrode 52 and gate metal layer 50 and the interlayer insulating film 38. The barrier metal layer 60 and the intervening layer 66 are omitted in Figure 1A. Contact holes 54, 55, and 56 are provided through the interlayer insulating film 38.

[0049] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive part within the transistor section 70 via the connection section 25. A plug layer made of tungsten or the like may be formed inside the contact hole 55. The plug layer will be described later.

[0050] The contact hole 56 connects the emitter electrode 52 to the dummy conductive part in the dummy trench 30. A plug layer made of tungsten or the like may be formed inside the contact hole 56.

[0051] The connection portion 25 is connected to the front-side metal layer 53, such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. In this example, the connection portion 25 may be provided extending in the X-axis direction and electrically connected to the gate conductive portion. The connection portion 25 may also be provided between the emitter electrode 52 and the dummy conductive portion. In this example, the connection portion 25 is not provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0052] The gate trench portion 40 is an example of a plurality of trench portions extending in a predetermined stretching direction on the front surface 21 side of the semiconductor substrate 10. The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 may have two extended portions 41 that extend along a stretching direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connecting portion 43 that connects the two extended portions 41.

[0053] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extended portions 41 of the gate trench portion 40, electric field concentration at the ends of the extended portions 41 can be mitigated. In the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be electrically connected to the gate conductive portion via the connection portion 25.

[0054] The dummy trench section 30 is an example of a plurality of trench sections extending in a predetermined stretching direction on the front surface 21 side of the semiconductor substrate 10. The dummy trench section 30 is a trench section electrically connected to the emitter electrode 52. The dummy trench section 30, like the gate trench section 40, is arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). In this example, the dummy trench section 30 has an I-shape on the front surface 21 of the semiconductor substrate 10, but like the gate trench section 40, it may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench section 30 may have two extended portions extending along the stretching direction and a connecting portion connecting the two extended portions.

[0055] The transistor section 70 in this example has a structure in which two gate trench sections 40 and two dummy trench sections 30 are arranged in a repeating pattern. That is, the transistor section 70 in this example has gate trench sections 40 and dummy trench sections 30 in a 1:1 ratio. For example, the transistor section 70 has one dummy trench section 30 between two extended sections 41.

[0056] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 may be greater than the ratio of the dummy trench portion 30, and vice versa. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 2:3 or 2:4. Furthermore, the transistor portion 70 may have all trenches as gate trench portions 40 and not have dummy trench portions 30.

[0057] The well region 17 is a second conductivity type region located on the front surface 21 side of the semiconductor substrate 10, closer to the drift region 18, which will be described later. The well region 17 is an example of a well region located on the periphery side of the active portion 120. The active portion 120 will be described later. The well region 17 is, for example, of the P+ type. The well region 17 is formed in a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. A portion of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17. The bottom of the extending end of the gate trench portion 40 and the dummy trench portion 30 may be covered by the well region 17.

[0058] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided by extending in the stretching direction.

[0059] The mesa portion 71 is a mesa portion provided adjacent to the trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is the part of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be the portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. The extended portion of each trench portion may be considered as one trench portion. That is, the region sandwiched between two extended portions may be considered as the mesa portion.

[0060] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are provided alternately in the stretching direction.

[0061] The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, P-type. The base region 14 may be provided at both ends of the mesa portion 71 in the Y-axis direction on the front surface 21 of the semiconductor substrate 10. Note that Figure 1A shows only one end of the base region 14 in the Y-axis direction.

[0062] The emitter region 12 is a first conductivity type region with a higher doping concentration than the drift region 18. In this example, the emitter region 12 is N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may extend in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0063] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0064] The contact region 15 is located above the base region 14 and is a region of a second conductivity type with a higher doping concentration than the base region 14. In this example, the contact region 15 is of type P+. In this example, the contact region 15 is located on the front surface 21 of the mesa portion 71. The contact region 15 may be located in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. In this example, the contact region 15 is in contact with both the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also located below the contact hole 54.

[0065] Figure 1B shows an example of the a-a' cross-section in Figure 1A. The a-a' cross-section is the XZ plane passing through the emitter region 12 in the transistor section 70. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an intervening layer 66, a barrier metal layer 60, a plug layer 64, an emitter electrode 52, and a collector electrode 24 in the a-a' cross-section. The collector electrode 24 is an example of a back-side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0066] The drift region 18 is a region of a first conductivity type provided on the semiconductor substrate 10. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining on the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0067] The buffer region 20 is a first-conductivity region located on the back surface 23 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the buffer region 20 is N-type. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may function as a field stop layer to prevent the depletion layer extending from the underside of the base region 14 from reaching the collector region 22 of the second-conductivity region. The buffer region 20 may be omitted.

[0068] The collector region 22 is located below the buffer region 20 in the transistor section 70. The collector region 22 has a second conductivity type. In this example, the collector region 22 is of type P+.

[0069] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as metal. The material of the collector electrode 24 may be the same as or different from the material of the emitter electrode 52.

[0070] The base region 14 is a second conductivity type region located above the drift region 18. The base region 14 is located in contact with the gate trench portion 40. The base region 14 may be located in contact with the dummy trench portion 30.

[0071] The emitter region 12 is provided above the base region 14. The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0072] The storage region 16 is a first conductivity type region located on the front surface 21 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the storage region 16 is N-type. However, the storage region 16 does not necessarily have to be provided.

[0073] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration in the accumulation region 16 is higher than the doping concentration in the drift region 18. The ion implantation dose in the accumulation region 16 is 1.0E+12cm -2 The above is 1.0E+13cm -2 The following may be the case. Also, the ion implantation dose for the accumulation region 16 is 3.0E+12cm². -2 The above is for 6.0E+12cm. -2 The following is also possible: By providing a storage region 16, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced.

[0074] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, and storage region 16 is provided, each trench penetrates these regions as well, reaching the drift region 18. The statement that a trench penetrates a doping region is not limited to cases where the doping region is formed before the trenches are formed. Cases where doping regions are formed between the trenches after the trenches have been formed are also included in cases where the trenches penetrate a doping region.

[0075] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. In other examples, the gate insulating film 42 may be formed by depositing an insulating material such as an oxide film. The gate conductive portion 44 is formed inside the gate trench, on the inside of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. In this example, the gate conductive portion 44 is of the N+ type. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38.

[0076] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces an adjacent base region 14 on the mesa portion 71 side, with the gate insulating film 42 in between. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is created on the surface layer of the interface in contact with the gate trench within the base region 14.

[0077] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 may be covered with an interlayer insulating film 38 on the front surface 21.

[0078] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. In this example, the bottom surface of the contact hole 54 is not located below the front surface 21 of the semiconductor substrate 10 provided below the interlayer insulating film 38, but in other examples, the bottom surface of the contact hole 54 may be located below the front surface 21 of the semiconductor substrate 10 provided below the interlayer insulating film 38. Similarly, contact holes 55 and 56 may be provided through the interlayer insulating film 38, and the bottom surfaces of contact holes 55 and 56 may be located below the upper surfaces of the connection portion 25 and dummy conductive portion 34 provided below the interlayer insulating film 38. The thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited to this.

[0079] The interlayer insulating film 38 may be a silicon oxide film. The interlayer insulating film 38 may be a BPSG (Boro-phospho Silicate Glass) film, a BSG (borosilicate glass) film, or a PSG (Phosphosilicate glass) film. The interlayer insulating film 38 may contain a high-temperature silicon oxide (HTO) film or a low-temperature silicon oxide (LTO) film. Details of the composition of the interlayer insulating film 38 will be described later.

[0080] The intervening layer 66 is provided above the interlayer insulating film 38. The intervening layer 66 may be provided on the side wall of the contact hole 54. However, the intervening layer 66 may be provided only above the interlayer insulating film 38. Further details of the intervening layer 66 will be described later.

[0081] The barrier metal layer 60 is provided above the intervening layer 66. The barrier metal layer 60 may contain a predetermined conductive metal. The barrier metal layer 60 may be provided on the sidewall of the contact hole 54. Further details of the barrier metal layer 60 will be described later.

[0082] The plug layer 64 is provided inside the contact hole 54, on the inside of the barrier metal layer 60. The plug layer 64 is a conductive material that fills the inside of the contact hole 54. The plug layer 64 may be made of a different material from the emitter electrode 52. For example, the material of the plug layer 64 is tungsten.

[0083] The back-side lifetime control region 151 may be provided in the transistor section 70. However, the back-side lifetime control region 151 may be omitted. The back-side lifetime control region 151 is a region in which a lifetime killer is intentionally formed by injecting impurities into the semiconductor substrate 10. In one example, the back-side lifetime control region 151 is formed by injecting helium into the semiconductor substrate 10. The back-side lifetime control region 151 may also be formed by injecting protons. By providing the back-side lifetime control region 151, the turn-off time can be reduced and the tail current suppressed, thereby reducing losses during switching.

[0084] Lifetime killers are carrier recombination centers. Lifetime killers may be lattice defects. For example, lifetime killers may be vacancies, double vacancies, composite defects between these and elements constituting the semiconductor substrate 10, or dislocations. Lifetime killers may also be noble gas elements such as helium and neon, or metallic elements such as platinum. Electron beams or protons may be used to form lattice defects.

[0085] The lifetime killer concentration is the concentration of carrier recombination centers. The lifetime killer concentration may also be the concentration of lattice defects. For example, the lifetime killer concentration may be the concentration of vacancies such as vacancies and double vacancies, the concentration of composite defects between these vacancies and the elements constituting the semiconductor substrate 10, or the concentration of dislocations. Furthermore, the lifetime killer concentration may also be the chemical concentration of noble gas elements such as helium and neon, or the chemical concentration of metallic elements such as platinum.

[0086] The back-side lifetime control region 151 is located on the back surface 23 side of the center of the semiconductor substrate 10 in the depth direction. In this example, the back-side lifetime control region 151 is located in the buffer region 20. In this example, the back-side lifetime control region 151 is located across the entire surface of the semiconductor substrate 10 in the XY plane and can be formed without using a mask. The back-side lifetime control region 151 may also be located on a portion of the semiconductor substrate 10 in the XY plane. The dose of impurities for forming the back-side lifetime control region 151 is 0.5E+10cm². -2 The above is 1.0E+14cm -2 Even if the following applies, 5.0E+10cm -2 The above is 1.0E+13cm -2 The following is also acceptable.

[0087] The rear-side lifetime control region 151 may be formed by injection from the rear surface 23 side. This makes it easier to avoid affecting the front surface 21 side of the semiconductor device 100. For example, the rear-side lifetime control region 151 is formed by irradiating with helium or protons from the rear surface 23 side. Here, whether the rear-side lifetime control region 151 is formed by injection from the front surface 21 side or the rear surface 23 side can be determined by obtaining the state of the front surface 21 side by the SR method or by measuring the leakage current.

[0088] Figure 1C shows an example of a b-b' cross section in Figure 1A. The b-b' cross section is the XZ plane passing through the contact region 15 in the mesa portion 71. Similar to the a-a' cross section, the semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, an intervening layer 66, a barrier metal layer 60, a plug layer 64, an emitter electrode 52, and a collector electrode 24 in the b-b' cross section.

[0089] The contact area 15 is provided above the base area 14. The contact area 15 is provided between the base area 14 and the front surface 21. The contact area 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. In this example, the contact area 15 is in contact with both the dummy trench portion 30 and the gate trench portion 40.

[0090] The plug region 19 is a region of second conductivity type with a higher doping concentration than the contact region 15. The plug region 19 is, for example, of type P++. In this example, the plug region 19 is located on the front surface 21. The plug region 19 is located above the contact region 15 in the b-b' cross section. In this example, the plug region 19 is in contact with the contact region 15. The plug region 19 is located in the mesa portion 71 in the b-b' cross section, but not in the mesa portion 71 in the a-a' cross section. That is, the plug region 19 may be provided discretely in the extension direction on the front surface 21. In other examples, the plug region 19 may not be located over the entire area above the contact region 15 in the mesa portion 71, but may be located in a portion of the area above the emitter region 12 in the mesa portion 71.

[0091] Figure 2A shows a modified top view of the semiconductor device 100. In this example, only some components of the semiconductor device 100 are shown, and some components have been omitted.

[0092] The semiconductor substrate 10 has edges 102 when viewed from above. In this example, the semiconductor substrate 10 has two pairs of edges 102 that face each other when viewed from above. In this example, the X axis and Y axis are parallel to one of the edges 102.

[0093] The semiconductor substrate 10 is provided with an active section 120. The active section 120 is a region where the main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode 52 is provided above the active section 120, but it is omitted in this figure.

[0094] The active section 120 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a freewheeling diode (FWD). In the example shown in Figure 2A, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the front surface 21 of the semiconductor substrate 10. In other examples, the active section 120 may be provided with only one of the transistor section 70 and the diode section 80.

[0095] In this example, the region where the transistor section 70 is located is denoted by the symbol "I", and the region where the diode section 80 is located is denoted by the symbol "F". The transistor section 70 and the diode section 80 may each have a longitudinal length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0096] The diode portion 80 is the region obtained by projecting the cathode region 82, which is provided on the back surface 23 of the semiconductor substrate 10, onto the upper surface of the semiconductor substrate 10. The cathode region 82 will be described later. On the back surface 23 of the semiconductor substrate 10, a P+ type collector region 22 may be provided in the region other than the cathode region 82. In this specification, an extended region 85, which is an extension of the diode portion 80 in the Y-axis direction to the gate wiring described later, may also be included in the diode portion 80. A collector region 22 may be provided on the back surface 23 of the extended region 85.

[0097] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad and a cathode pad. Each pad is located near the edge 102. The vicinity of the edge 102 refers to the area between the edge 102 and the emitter electrode 52 in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0098] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the gate conductive portion 44 of the gate trench portion 40 of the active portion 120. The semiconductor device 100 is provided with gate wiring that connects the gate pad 112 and the gate trench portion 40. In Figure 2A, the gate wiring is hatched with diagonal lines.

[0099] The gate wiring in this example has an outer perimeter gate wiring 130 and an inter-active-part gate wiring 131. The gate wiring may be constructed by combining either the gate metal layer 50 or the connection part 25, or both, as appropriate. The outer perimeter gate wiring 130 and the inter-active-part gate wiring 131 may have the same configuration or different configurations. The outer perimeter gate wiring 130 is positioned between the active part 120 and the edge 102 of the semiconductor substrate 10 in a top view. In this example, the outer perimeter gate wiring 130 surrounds the active part 120 in a top view. The area surrounded by the outer perimeter gate wiring 130 in a top view may be considered the active part 120. The outer perimeter gate wiring 130 is also connected to the gate pad 112. The outer perimeter gate wiring 130 is positioned above the semiconductor substrate 10. The outer perimeter gate wiring 130 may be composed of a gate metal layer 50 and a connection part 25.

[0100] The inter-active-part gate wiring 131 is provided between multiple active parts 120. In Figure 2A, two active parts 120 are arranged side by side in the Y-axis direction. By providing the inter-active-part gate wiring 131 between multiple active parts 120 inside the semiconductor substrate 10, variations in the wiring length from the gate pad 112 can be reduced for each region of the semiconductor substrate 10.

[0101] The inter-active-part gate wiring 131 is connected to the gate trench portion of the active part 120. The inter-active-part gate wiring 131 is located above the semiconductor substrate 10. In this example, the inter-active-part gate wiring 131 is composed of a gate metal layer 50 and a connecting portion 25. The gate metal layer 50 may be a metal layer containing aluminum or the like.

[0102] The inter-active-part gate wiring 131 may be connected to the outer peripheral gate wiring 130. In this example, the inter-active-part gate wiring 131 extends in the X-axis direction, crossing the active part 120 from one outer peripheral gate wiring 130 to the other outer peripheral gate wiring 130, approximately in the center in the Y-axis direction. When the active part 120 is divided by the inter-active-part gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X-axis direction in each divided region.

[0103] The edge termination structure 140 is provided on the front surface 21 of the semiconductor substrate 10. In a top view, the edge termination structure 140 is provided between the active portion 120 and the edge 102. In this example, the edge termination structure 140 is positioned between the outer peripheral gate wiring 130 and the edge 102. The edge termination structure 140 mitigates electric field concentration on the front surface 21 side of the semiconductor substrate 10. The edge termination structure 140 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 120.

[0104] Figure 2B shows a modified top view of the semiconductor device 100. The semiconductor device 100 in this example includes a transistor section 70 and a diode section 80. This figure is an enlarged top view of region A in Figure 2A.

[0105] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17, all located inside the front surface 21 of the semiconductor substrate 10. The gate trench 40 and the dummy trench 30 are examples of trenches.

[0106] The dummy trench portion 30 in this example may have a U-shape on the front surface 21 of the semiconductor substrate 10, similar to the gate trench portion 40. That is, the dummy trench portion 30 may have two extended portions 31 extending along the stretching direction and a connecting portion 33 connecting the two extended portions 31.

[0107] The semiconductor device 100 in this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other. The transistor section 70 in this example includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80. However, the semiconductor device 100 does not necessarily have to include the boundary section 90.

[0108] The boundary portion 90 is provided in the transistor portion 70 and is adjacent to the diode portion 80. The boundary portion 90 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the boundary portion 90 does not have an emitter region 12. In this example, the trench portion of the boundary portion 90 is a dummy trench portion 30. In this example, the boundary portion 90 is arranged such that both ends in the X-axis direction are dummy trench portions 30.

[0109] The contact holes 54 are located above the base region 14 in the diode section 80. The contact holes 54 are located above the contact region 15 in the boundary section 90. None of the contact holes 54 are located above the well regions 17 located at both ends in the Y-axis direction.

[0110] The mesa portion 91 is provided at the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the mesa portion 91 has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0111] The mesa portion 81 is provided in the diode portion 80 in the region sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10. In this example, the mesa portion 81 has a well region 17 on the negative side in the Y-axis direction.

[0112] The emitter region 12 is provided in the mesa portion 71, but it does not need to be provided in the mesa portions 81 and 91. The contact region 15 is provided in the mesa portions 71 and 91, but it does not need to be provided in the mesa portion 81.

[0113] Figure 2C shows an example of the c-c' cross section in Figure 2B. The c-c' cross section is the XZ plane passing through the emitter region 12 in the transistor section 70. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an intervening layer 66, a barrier metal layer 60, a plug layer 64, an emitter electrode 52, and a collector electrode 24 in the c-c' cross section. The semiconductor device 100 in this example includes a back-side lifetime control region 151 and a front-side lifetime control region 152. However, the semiconductor device 100 does not have to include either the back-side lifetime control region 151 or the front-side lifetime control region 152. The semiconductor device 100 in this example has a collector region 22 and a cathode region 82 on the back side 23 of the buffer region 20.

[0114] The contact area 15 is located above the base area 14 in the mesa portion 91. The contact area 15 is located in contact with the dummy trench portion 30 in the mesa portion 91. In other cross-sections, the contact area 15 may be located on the front surface 21 of the mesa portion 71. The plug area 19 is located above the contact area 15 in the mesa portion 91 and above the base area 14 in the mesa portion 81.

[0115] The storage region 16 is provided in the transistor section 70 and the diode section 80. In this example, the storage region 16 is provided across the entire surface of the transistor section 70 and the diode section 80. However, the storage region 16 does not necessarily have to be provided in the diode section 80.

[0116] The cathode region 82 is located below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. In other words, the collector region 22 is located below the boundary 90 in this example.

[0117] The rear-side lifetime control region 151 is provided in both the transistor section 70 and the diode section 80. This allows the semiconductor device 100 in this example to accelerate recovery in the diode section 80 and further improve switching losses. The rear-side lifetime control region 151 may be formed in the same manner as the rear-side lifetime control region 151 in other embodiments.

[0118] The front-side lifetime control region 152 is provided on the front surface 21 side of the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the front-side lifetime control region 152 is provided in the drift region 18. The front-side lifetime control region 152 is provided in both the transistor section 70 and the diode section 80. The front-side lifetime control region 152 is provided in the diode section 80 and the boundary section 90, and may not be provided in part of the transistor section 70. In other examples, the front-side lifetime control region 152 may be provided in the entire area of ​​the transistor section 70 and the diode section 80, or in the entire area or part of either, and may also be provided in the area surrounding the active section 120 such as the edge termination structure section 140. The front-side lifetime control region 152 can reduce reverse recovery loss by suppressing hole injection from the diode section 80 and the transistor section 70.

[0119] The front-side lifetime control region 152 may be formed by any method among the methods for forming the back-side lifetime control region 151. The elements and dose amounts used to form the back-side lifetime control region 151 and the front-side lifetime control region 152 may be the same or different.

[0120] The front-side lifetime control region 152 is provided extending from the diode portion 80 to the transistor portion 70. The front-side lifetime control region 152 may be formed by irradiation from the front surface 21 of the semiconductor substrate 10. The front-side lifetime control region 152 may also be formed by irradiation from the back surface 23 of the semiconductor substrate 10. In this example, the front-side lifetime control region 152 is provided below the gate trench portion 40. When particle beams or the like used to form the front-side lifetime control region 152 pass through the MOS gate structure of the semiconductor device 100, defects may occur at the interface between the gate oxide film and the semiconductor substrate.

[0121] The semiconductor device 100 may be a power semiconductor device for controlling power, etc. The semiconductor device 100 in this example has a vertical semiconductor structure with a back-side metal layer on the back surface 23 side of the semiconductor substrate 10. However, the semiconductor device 100 may also have a horizontal semiconductor structure without a metal layer on the back surface 23 side.

[0122] In this example, the semiconductor device 100 is described using a trench gate RC-IGBT as an example. However, the semiconductor device 100 may be a planar gate semiconductor device or another semiconductor device such as a diode. The semiconductor device 100 may include an N-channel MOSFET or a P-channel MOSFET.

[0123] Figure 2D shows an example of the d-d' cross section in Figure 2B. The d-d' cross section is the XZ plane passing through the contact region 15 in the mesa portion 71. Similar to the c-c' cross section, the semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, an intervening layer 66, a barrier metal layer 60, a plug layer 64, an emitter electrode 52, and a collector electrode 24 in the d-d' cross section.

[0124] The mesa portion 71 has a base region 14, a contact region 15, a storage region 16, and a plug region 19. The mesa portion 91 has a base region 14, a contact region 15, a storage region 16, and a plug region 19. The mesa portion 81 has a base region 14, a storage region 16, and a plug region 19, similar to the c-c' section. The plug region 19 may be provided continuously in the stretching direction on the front surface 21 of the mesa portions 81 and 91. In other examples, the plug region 19 may be provided discretely in the stretching direction or the arrangement direction on the front surface 21 of the mesa portions 81 and 91.

[0125] Figure 3A is an enlarged cross-sectional view of the semiconductor device 100. In this example, an enlarged cross-sectional view near the contact hole 54 is shown. The cross-section in this example is an XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The semiconductor substrate 10 is an example of a silicon layer 110. The emitter electrode 52 is an example of a front-side metal layer 53. The semiconductor device 100 comprises a semiconductor substrate 10, an interlayer insulating film 38, an intervening layer 66, a barrier metal layer 60, an emitter electrode 52, and a silicide layer 63. The semiconductor device 100 may also include a plug layer 64.

[0126] Figure 3B is an enlarged cross-sectional view of the semiconductor device 100. The cross-section in this example differs from that of Figure 3A in that it passes through the contact region 15 on the front surface 21. The semiconductor device 100 comprises a semiconductor substrate 10, an interlayer insulating film 38, an intervening layer 66, a barrier metal layer 60, an emitter electrode 52, and a silicide layer 63. The semiconductor device 100 may also include a plug region 19 and a plug layer 64. That is, the region below the contact hole 54 of the semiconductor substrate 10, which is an example of a silicon layer 110, may be of the second conductivity type as in this example, or of the first conductivity type as in the example of Figure 3A. The case where the region below the contact hole 54 of the semiconductor substrate 10 is the base region 14 may be the same as the case where it is the contact region 15. The following describes in detail an example of connecting a semiconductor substrate 10, which is an example of a silicon layer 110, and an emitter electrode 52, which is an example of a front-side metal layer 53, with a contact hole 54, with reference to Figures 3A and 3B.

[0127] In this specification, the structure near the contact hole may be described using the contact hole 54, but the same structure may be applied to other contact holes such as contact hole 55 and contact hole 56. That is, the intervening layer 66, barrier metal layer 60, silicide layer 63, plug layer 64, and plug region 19 may be provided in other contact holes such as contact hole 55 and contact hole 56. Similarly, the intervening layer 66, barrier metal layer 60, silicide layer 63, plug layer 64, and plug region 19 may be provided in contact hole 58, which will be described later.

[0128] The interlayer insulating film 38 has contact holes 54 and is provided above the silicon layer 110. In this example, the interlayer insulating film 38 is provided above the semiconductor substrate 10, which is an example of the silicon layer 110. The interlayer insulating film 38 contains silicate glass. The interlayer insulating film 38 may contain a BPSG film, a BSG film, or a PSG film.

[0129] Interlayer insulating film 38 may include a first insulating layer 382 and a second insulating layer 384. The first insulating layer 382 may be provided above the silicon layer 110. The first insulating layer 382 in the present example is provided above the semiconductor substrate 10, which is an example of the silicon layer 110. The second insulating layer 384 may be provided above the first insulating layer 382.

[0130] The first insulating layer 382 is, by way of example, a silicon oxide film. The first insulating layer 382 may be an HTO film or an LTO film. In another example, the first insulating layer 382 may be formed by thermally oxidizing the semiconductor substrate 10, the gate conductive portion 44, the dummy conductive portion 34, or the like. The second insulating layer 384 is, by way of example, silicate glass. The second insulating layer 384 may be a BPSG film, a BSG film, or a PSG film.

[0131] The second insulating layer 384 may have a higher fluorine concentration or boron concentration than the first insulating layer 382. For example, fluoride ions may be implanted into the bottom of the contact hole 54 to form the plug region 19. By way of example, the fluoride ions are boron fluoride ions (BF2 + ). In this case, fluoride ions irradiated from above the semiconductor substrate 10 are also implanted into the second insulating layer 384, and the fluorine concentration in the second insulating layer 384 may become higher than that in the first insulating layer 382. Note that the impurity ions implanted into the bottom of the contact hole are not limited to fluoride ions. The impurity ions implanted into the bottom of the contact hole may be, for example, boron ions (B + ). In addition, the second insulating layer 384 may be a silicate glass containing boron and made of a material different from that of the first insulating layer 382. Through the above, the second insulating layer 384 may have a higher boron concentration than the first insulating layer 382.

[0132] The intervening layer 66 is provided above the interlayer insulating film 38. The intervening layer 66 may be in contact with the second insulating layer 384. The thickness of the intervening layer 66 may be thinner than the thickness of the interlayer insulating film 38. The thickness of the intervening layer 66 above the interlayer insulating film 38 may be 3 nm or more and 20 nm or less, more preferably 5 nm or more and 10 nm or less.

[0133] The fluorine or boron concentration in the interlayer 66 may be lower than the fluorine or boron concentration on the upper surface of the interlayer insulating film 38. As described above, when impurity ions such as fluoride ions or boron ions are implanted into the bottom of the contact hole 54 to form the plug region 19, the fluorine or boron concentration on the upper surface of the interlayer insulating film 38 may become higher. The fluorine or boron concentration in the interlayer 66 may be lower than the fluorine or boron concentration on the upper surface of the interlayer insulating film 38, which has become higher due to the implantation of impurity ions.

[0134] The intervening layer 66 may contain titanium nitride. It may also be formed from the same material as the second barrier metal portion 62, which will be described later. For example, the intervening layer 66 is formed by sputtering titanium nitride above the interlayer insulating film 38.

[0135] The intervening layer 66 may contain a silicon oxide film. The intervening layer 66 may contain an LTO film or an HTO film. For example, the intervening layer 66 is formed by depositing an LTO film or an HTO film on top of the interlayer insulating film 38. As another example, the intervening layer 66 may contain a TEOS (Tetra Eth Oxy Silane) film. For example, the intervening layer 66 is formed by depositing a TEOS film on top of the interlayer insulating film 38 using plasma CVD.

[0136] The intervening layer 66 may be made of a material other than titanium nitride or silicon oxide film. For example, the intervening layer 66 may contain silicon nitride or titanium oxide.

[0137] The barrier metal layer 60 is provided above the intervening layer 66. The barrier metal layer 60 may contain a predetermined conductive metal. For example, the barrier metal layer 60 may contain at least one of titanium, cobalt, nickel, tantalum, magnesium, vanadium, lanthanum, palladium, or zirconium. The barrier metal layer 60 may contain a metal that reacts with the underlying layer to form an alloy layer. In this example, the barrier metal layer 60 may contain a metal that reacts with silicon to form a silicide. The barrier metal layer 60 in this example has a first barrier metal portion 61 and a second barrier metal portion 62.

[0138] The first barrier metal portion 61 is provided above the intervening layer 66. The first barrier metal portion 61 contains a predetermined conductive metal. The first barrier metal portion 61 may contain a predetermined conductive metal monolayer film. For example, the first barrier metal portion 61 contains titanium. For example, the first barrier metal portion 61 is formed by sputtering titanium above the intervening layer 66.

[0139] The second barrier metal portion 62 is provided above the first barrier metal portion 61. The second barrier metal portion 62 contains a predetermined conductive material. The second barrier metal portion 62 may contain a predetermined conductive metal oxide film. For example, the second barrier metal portion 62 contains titanium nitride. For example, the second barrier metal portion 62 is formed by sputtering titanium nitride above the first barrier metal portion 61.

[0140] For example, the barrier metal layer 60 is formed by sputtering titanium above the intervening layer 66, sputtering titanium nitride above the titanium, and then performing sintering. In the sintering process, at least a portion of the titanium may be nitrided to become titanium nitride. That is, the second barrier metal portion 62 may contain titanium nitride formed by sputtering, may contain titanium nitride formed by sintering, or may contain both titanium nitride formed by sputtering and titanium nitride formed by sintering.

[0141] Titanium nitride formed by sintering is denser than titanium nitride formed by sputtering. As described above, the intervening layer 66 may contain titanium nitride formed by sputtering. In this case, the second barrier metal portion 62 may contain titanium nitride that is denser than the intervening layer 66.

[0142] The intervening layer 66, the first barrier metal portion 61, and the second barrier metal portion 62 may be provided above the interlayer insulating film 38 and on the side walls of the contact hole 54. For example, the intervening layer 66, the first barrier metal portion 61, and the second barrier metal portion 62 are formed after the contact hole 54 is formed in the interlayer insulating film 38. In this way, the intervening layer 66, the first barrier metal portion 61, and the second barrier metal portion 62 may be provided on the side walls of the contact hole 54. However, the formation order of the contact hole 54, the intervening layer 66, the first barrier metal portion 61, and the second barrier metal portion 62 is not limited to this. Details of the manufacturing method of the semiconductor device 100 will be described later.

[0143] The plug layer 64 may be provided in contact with the second barrier metal portion 62 in the contact hole 54. Alternatively, the plug layer 64 may be provided outside the contact hole 54, above the interlayer insulating film 38, in contact with the second barrier metal portion 62. The plug layer 64 may be omitted, and the emitter electrode 52 may be filled inside the contact hole 54.

[0144] The front-side metal layer 53 is provided above the barrier metal layer 60. In this example, the emitter electrode 52, which is an example of the front-side metal layer 53, is provided above the barrier metal layer 60. The emitter electrode 52 may be provided above the second barrier metal portion 62. The emitter electrode 52 may be provided above the plug layer 64.

[0145] In the semiconductor device 100 of this example, a barrier metal layer 60 is provided between the interlayer insulating film 38 and the front-side metal layer 53. This suppresses ion intrusion from the front-side metal layer 53 or the package material during mounting and its reach to the gate insulating film 42, thereby preventing a decrease in the threshold voltage of the semiconductor device 100.

[0146] The silicide layer 63 is provided above the silicon layer 110 in the contact hole 54. The silicide layer 63 is an example of an alloy layer provided above the underlying layer. In this example, the silicide layer 63 is provided above the semiconductor substrate 10, which is an example of the silicon layer 110. The silicide layer 63 may be provided on the semiconductor substrate 10. For example, the silicide layer 63 is formed when the material of the barrier metal layer 60 deposited at the bottom of the contact hole 54 during the barrier metal layer 60 formation process reacts with the silicon of the semiconductor substrate 10 during the sintering process to form silicide. In this case, the silicide layer 63 may be formed to a depth deeper than the surface 21. Thus, the barrier metal layer 60 may contain a metal that reacts with silicon to form silicide.

[0147] If the intervening layer 66 contains titanium nitride, the silicide layer 63 may be formed by the material of the intervening layer 66 reacting with the silicon of the semiconductor substrate 10 during the sintering process to form a silicide. If the intervening layer 66 contains a silicon oxide film, the silicide layer 63 may be formed by the material of the barrier metal layer 60 deposited at the bottom of the contact hole 54 during the barrier metal layer 60 formation process reacting with the silicon of the intervening layer 66 during the sintering process to form a silicide. In other words, the silicide layer 63 may contain reaction products between the barrier metal layer 60 and the semiconductor substrate 10, reaction products between the barrier metal layer 60 and the intervening layer 66, and reaction products between the intervening layer 66 and the semiconductor substrate 10.

[0148] The barrier metal layer 60 may be in contact with the silicide layer 63. In this example, the barrier metal layer 60 is in contact with the silicide layer 63 at the bottom of the contact hole 54. The second barrier metal portion 62 may be in contact with the silicide layer 63. In other examples, the first barrier metal portion 61 may remain between the silicide layer 63 and the second barrier metal portion 62. As described above, the silicide layer 63 may be formed by the silicideization of the material of the barrier metal layer 60. This allows the barrier metal layer 60 to be in contact with the silicide layer 63.

[0149] The plug region 19 may be provided on the surface of the silicon layer 110 below the silicide layer 63. This makes it possible to reduce the contact resistance between the silicide layer 63 and P-type regions such as the contact region 15, as shown in the example in Figure 3B.

[0150] When the first barrier metal portion is provided in contact with the interlayer insulating film, poor adhesion between the first barrier metal portion and the interlayer insulating film may occur, potentially leading to delamination due to stress from wire bonding or other factors. For example, if the first barrier metal portion contains a metal that reacts with silicon to form a silicide, and the interlayer insulating film contains silicate glass, adhesion between the first barrier metal portion and the interlayer insulating film may be poor. Furthermore, if a plug region is formed to reduce contact resistance between the silicide layer and the silicon layer, and the fluorine or boron concentration of the interlayer insulating film is high due to the implantation of impurity ions to form the plug region, adhesion may be particularly poor.

[0151] In the semiconductor device 100 of this example, an intervening layer 66 is provided above the interlayer insulating film 38, and a barrier metal layer 60 is provided above the intervening layer 66. That is, the intervening layer 66 is provided between the barrier metal layer 60 and the interlayer insulating film 38. This improves the adhesion between layers and prevents delamination. Therefore, the semiconductor device 100 of this example can prevent delamination by suppressing ion intrusion from the front metal layer 53 or the package material during mounting and its reach to the gate insulating film 42, thanks to the barrier metal layer 60.

[0152] Furthermore, in the semiconductor device 100 of this example, since an intervening layer 66 is provided between the barrier metal layer 60 and the interlayer insulating film 38, even when the fluorine concentration or boron concentration of the interlayer insulating film 38 is high, the adhesion between layers is improved and delamination can be prevented. Therefore, the semiconductor device 100 of this example can prevent delamination while reducing the contact resistance between the silicide layer 63 and the silicon layer 110.

[0153] In addition, the first barrier metal portion may be removed to prevent a decrease in adhesion. In the semiconductor device 100 of this example, an intervening layer 66 is provided between the barrier metal layer 60 and the interlayer insulating film 38, so the adhesion between layers can be improved and delamination can be prevented with a simpler process than removing the first barrier metal portion.

[0154] For example, if the intervening layer 66 contains titanium nitride, the first barrier metal portion 61 contains titanium, and the second barrier metal portion 62 contains titanium nitride, the adhesion between the intervening layer 66 containing titanium nitride and the interlayer insulating film 38 containing silicate glass, and the adhesion between the intervening layer 66 containing titanium nitride and the first barrier metal portion 61 containing titanium, are higher than the adhesion between the first barrier metal portion 61 containing titanium and the interlayer insulating film 38 containing silicate glass. Therefore, interlayer adhesion is improved, and delamination can be prevented.

[0155] As another example, when the intervening layer 66 contains a silicon oxide film, the first barrier metal portion 61 contains titanium, and the second barrier metal portion 62 contains titanium nitride, the adhesion between the intervening layer 66 containing the silicon oxide film and the interlayer insulating film 38 containing silicate glass, and the adhesion between the intervening layer 66 containing the silicon oxide film and the first barrier metal portion 61 containing titanium, are higher than the adhesion between the first barrier metal portion 61 containing titanium and the interlayer insulating film 38 containing silicate glass. Therefore, interlayer adhesion is improved, and delamination can be prevented.

[0156] As described above, the thickness of the intervening layer 66 above the interlayer insulating film 38 may be 3 nm or more and 20 nm or less. If the thickness of the intervening layer 66 above the interlayer insulating film 38 is less than 3 nm, it may be difficult to form a thin intervening layer 66, or improved interlayer adhesion may not be achieved. Therefore, the thickness of the intervening layer 66 above the interlayer insulating film 38 may be 3 nm or more.

[0157] Figure 4A is an enlarged cross-sectional view of the semiconductor device 100. The cross-section in this example is the XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example differs from the embodiment in Figure 3A in that it includes an intervening layer 66 between the silicide layer 63 and the silicon layer 110. In this example, the differences from the embodiment in Figure 3A will be explained in detail, and other aspects may be the same as those of the embodiment in Figure 3A.

[0158] The intervening layer 66 in this example contains a silicon oxide film. The intervening layer 66 may also contain titanium nitride. At least a portion of the intervening layer 66 may remain unused in the sintering process for silicide formation of the barrier metal layer 60. In this case, the silicide layer 63 may be provided above the silicon layer 110 via the intervening layer 66. Even if a very thin layer of the intervening layer 66 remains at the bottom of the contact hole 54, it will not lead to a significant increase in resistance between the plug layer 64 and the silicon layer 110, so the intervening layer 66 may remain at the bottom of the contact hole 54. The remaining intervening layer 66 may be located below the silicide layer 63 or inside the silicide layer 63.

[0159] As described above, the thickness of the intervening layer 66 above the interlayer insulating film 38 may be 3 nm or more and 20 nm or less. If the thickness of the intervening layer 66 above the interlayer insulating film 38 is increased, the thickness of the intervening layer 66 remaining at the bottom of the contact hole 54 will also increase. For example, if the thickness of the intervening layer 66 above the interlayer insulating film 38 is greater than 20 nm, the increased thickness of the intervening layer 66 remaining at the bottom of the contact hole 54 may lead to an increase in resistance between the plug layer 64 and the silicon layer 110. Therefore, the thickness of the intervening layer 66 above the interlayer insulating film 38 may be 20 nm or less. Furthermore, when forming the intervening layer 66 such that the thickness of the intervening layer 66 above the intervening insulating film 38 differs from the thickness of the intervening layer 66 inside the contact hole 54, for example, if the intervening layer 66 inside the contact hole 54 is thinned or removed during manufacturing, the thickness of the intervening layer 66 above the intervening insulating film 38 is not limited to 20 nm or less, but may be thicker, even in the embodiments shown in Figures 3A, 3B, or 4A.

[0160] Figure 4B is an enlarged cross-sectional view of the semiconductor device 100. The cross-section in this example differs from that of Figure 4A in that it passes through the contact area 15 on the front surface 21. Otherwise, it may be the same as the example in Figure 4A.

[0161] Figure 5A is an enlarged view of the cross-section of the semiconductor device 100. The cross-section in this example is the XZ cross-section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example differs from the embodiment in Figure 3A in that the intervening layer 66 is not provided on the side wall of the contact hole 54. In this example, the differences from the embodiment in Figure 3A will be explained in particular, and other aspects may be the same as those of the embodiment in Figure 3A.

[0162] The first barrier metal portion 61 and the second barrier metal portion 62 may be provided above the interlayer insulating film 38 and on the side walls of the contact holes 54. The first barrier metal portion 61 may be in contact with the side walls of the contact holes 54.

[0163] For example, the contact hole 54 is formed after the interlayer 66 is formed above the interlayer insulating film 38. Subsequently, the first barrier metal portion 61 and the second barrier metal portion 62 may be formed. In this way, the interlayer 66 is not provided on the side wall of the contact hole 54, and the first barrier metal portion 61 and the second barrier metal portion 62 are provided on the side wall of the contact hole 54. Therefore, the first barrier metal portion 61 may be in contact with the side wall of the contact hole 54. However, the formation order of the contact hole 54, the interlayer 66, the first barrier metal portion 61 and the second barrier metal portion 62 is not limited to this. Details of the manufacturing method of the semiconductor device 100 will be described later.

[0164] In the semiconductor device 100 of this example, an intervening layer 66 is provided above the interlayer insulating film 38, and a barrier metal layer 60 is provided above the intervening layer 66. That is, the intervening layer 66 is provided between the barrier metal layer 60 and the interlayer insulating film 38. This improves the adhesion between layers and prevents delamination. Therefore, the semiconductor device 100 of this example can prevent delamination by suppressing ion intrusion from the front metal layer 53 or the package material during mounting and its reach to the gate insulating film 42, thanks to the barrier metal layer 60.

[0165] Delamination due to low adhesion between the first barrier metal portion and the interlayer insulating film is largely due to the upper surface of the interlayer insulating film. Therefore, in the semiconductor device 100 of this example, even if an intervening layer 66 is not provided on the side wall of the contact hole 54, an intervening layer 66 is provided between the barrier metal layer 60 and the interlayer insulating film 38 above the interlayer insulating film 38, thereby improving interlayer adhesion and preventing delamination.

[0166] The thickness of the intervening layer 66 above the interlayer insulating film 38 may be 3 nm or more. In this example, the thickness of the intervening layer 66 above the interlayer insulating film 38 may be 20 nm or less, 100 nm or less, or 200 nm or less. In this example, since the intervening layer 66 is not formed inside the contact hole, increasing the thickness of the intervening layer 66 above the interlayer insulating film 38 does not lead to an increase in resistance between the plug layer 64 and the silicon layer 110 at the bottom of the contact hole.

[0167] Figure 5B is an enlarged view of the cross-section of the semiconductor device 100. The cross-section in this example differs from that of Figure 5A in that it passes through the contact area 15 on the front surface 21. Otherwise, it may be the same as the example in Figure 5A.

[0168] Figure 6 shows an example of the e-e' cross section in Figure 1A or Figure 2B. The e-e' cross section is the YZ plane passing through the inter-active gate wiring 131. In this example, the inter-active gate wiring 131 includes a gate metal layer 50 and a connecting portion 25. The gate metal layer 50 is an example of the front-side metal layer 53. The connecting portion 25 is an example of the silicon layer 110. In this example, the silicon layer 110 includes polysilicon. A coating layer 68 such as polyimide may be provided above the inter-active gate wiring 131.

[0169] The connection portion 25 may be provided above the semiconductor substrate 10 via an insulating layer 26. The insulating layer 26 may be formed simultaneously with the gate insulating film 42 and the dummy insulating film 32. The connection portion 25 is electrically connected to the gate conductive portion 44. In this example, the cross-section of the active portion gate wiring 131 has been described, but the outer peripheral gate wiring 130 may also be provided with a gate metal layer 50 and a connection portion 25 in the same manner.

[0170] The gate metal layer 50 is provided above the semiconductor substrate 10. A portion of the front-side metal layer 53 may overlap with the silicon layer 110 in the depth direction of the semiconductor substrate 10. In this example, the gate metal layer 50 is electrically connected to the connection portion 25 via a contact hole 55 provided above the connection portion 25. The gate metal layer 50 may be formed from the same material as the emitter electrode 52, or it may be made from a different material.

[0171] The configuration between the interlayer insulating film 38 and the front-side metal layer 53, and the vicinity of the contact hole 55, may be the same as in the embodiments of the interlayer insulating film 38 and the front-side metal layer 53, and the contact hole 54, as described in Figures 3A to 5B. That is, the semiconductor device 100 comprises an intervening layer 66 provided above the interlayer insulating film 38, a barrier metal layer 60 provided above the intervening layer 66, and a silicide layer 63 provided above the silicon layer 110. The contact hole 55 may also be provided similarly for the outer periphery gate wiring 130. As described above, even in areas above which wire bonding is not directly performed, or in areas separated from the MOS gate structure, the interlayer insulating film 38 and the surface metal layer 53, as well as the upper part near the contact hole, may be provided with an intervening layer 66 above the interlayer insulating film 38, a barrier metal layer 60 above the intervening layer 66, and a silicide layer 63 above the silicon layer 110.

[0172] In Figure 6, no intervening layer 66 is provided on the upper surface of the interlayer insulating film 38 that is not covered by the gate metal layer 50 and the barrier metal layer 60. If the intervening layer 66 is a conductive material such as titanium nitride, the intervening layer 66 is not provided on the upper surface of the interlayer insulating film 38 between the gate metal layer 50 and the other front-side metal layers 53. As a result, each of the front-side metal layers is electrically isolated from each other. On the other hand, if the intervening layer 66 is an insulating material such as a silicon oxide film, the intervening layer 66 may be provided continuously on the upper surface of the interlayer insulating film 38 to below the emitter electrode 52 or other metal layers outside the range of Figure 6. In this case as well, the gate metal layer 50 and the other front-side metal layers 53 such as the emitter electrode 52 are electrically isolated.

[0173] Figure 7 shows an example of the f-f' cross section in Figure 1A or Figure 2B. The f-f' cross section is the XZ plane passing through the dummy trench section 30.

[0174] The silicon layer 110 may be provided in the semiconductor substrate 10. The dummy conductive portion 34 in this example is an example of a silicon layer 110 provided in the semiconductor substrate 10. A contact hole 56 may be provided above the dummy conductive portion 34. The contact hole 56 functions as a contact hole for connecting the emitter electrode 52 and the dummy conductive portion 34. The emitter electrode 52 is an example of a front-side metal layer 53.

[0175] The configuration between the interlayer insulating film 38 and the front-side metal layer 53, and the vicinity of the contact hole 56, may be the same as the embodiment of the interlayer insulating film 38 and the front-side metal layer 53, and the contact hole 54, as described in Figures 3A to 5B. That is, the semiconductor device 100 comprises an intervening layer 66 provided above the interlayer insulating film 38, a barrier metal layer 60 provided above the intervening layer 66, and a silicide layer 63 provided above the silicon layer 110.

[0176] In Figures 1A, 2B, 6, and 7, the gate conductive part 44 and the gate metal layer 50 are connected via the connection part 25 and the contact hole 55, and the dummy conductive part 34 and the emitter electrode 52 are connected via the contact hole 56. The gate conductive part 44 and the gate metal layer 50 may be connected via the contact hole 55 without using the connection part 25, and the dummy conductive part 34 and the emitter electrode 52 may be connected via the connection part 25 and the contact hole 56.

[0177] Figure 8 shows an example of a top view of a semiconductor device 100 equipped with a temperature sensing unit 180. The semiconductor device 100 in this example includes a gate pad 112, a sense electrode 114, an anode pad 116, and a cathode pad 118.

[0178] The front-side metal layer 53 may include an emitter electrode 52, a gate pad 112, a sense electrode 114, an anode pad 116, and a cathode pad 118, which are partially exposed from the coating layer 68. The front-side metal layer 53 may be electrically connected to a conductive member such as a lead frame. The front-side metal layer 53 may be electrically connected to an external electrode of the semiconductor device 100 by wire bonding or the like. The front-side metal layer 53 may also include wiring such as a gate metal layer 50 covered by the coating layer 68. The number and position of the front-side metal layer 53 are not limited to this example.

[0179] The sense electrode 114 is electrically connected to a current sense unit 115 located below the sense electrode 114. The sense electrode 114 detects the current flowing through the current sense unit 115. The current sense unit 115 detects the current flowing through the transistor unit 70. The current sense unit 115 has a structure corresponding to the transistor unit 70, and simulates the operation of the transistor unit 70 by flowing a current proportional to the current flowing through the transistor unit 70. By using the current sense unit 115, the current flowing through the transistor unit 70 can be monitored. The configuration of the interlayer insulating film 38 of the current sense unit 115 between the sense electrode 114 and the gate metal layer 50, as well as the configuration of the interlayer insulating film 38 of the transistor unit 70 between the emitter electrode 52 and the gate metal layer 50, as well as the configuration of the contact hole.

[0180] The temperature sensing unit 180 is located on or inside the semiconductor substrate 10. In this example, the temperature sensing unit 180 is located on a well region 17 between the transistor sections 70 in the central part of the semiconductor device 100. The temperature sensing unit 180 detects the temperature of the active section 120. The temperature sensing unit 180 may have a diode formed of single-crystal or polycrystalline silicon. The temperature sensing unit 180 is used to detect the temperature of the semiconductor device 100 and protect the semiconductor chip from overheating. The temperature sensing unit 180 is connected to a constant current source. When the temperature of the semiconductor device 100 changes, the forward voltage of the current flowing through the temperature sensing unit 180 changes. The semiconductor device 100 can detect the temperature based on the change in the forward voltage of the temperature sensing unit 180. The temperature sensing unit 180 has a longitudinal direction in the Y-axis direction and a short direction in the X-axis direction, but is not limited to this.

[0181] The anode pad 116 is electrically connected to the anode region of the temperature sensing unit 180. The anode pad 116 is electrically connected to the anode region of the temperature sensing unit 180 by anode wiring 117.

[0182] The cathode pad 118 is electrically connected to the cathode region of the temperature sensing unit 180 by cathode wiring 119.

[0183] Figure 9 is an example of an enlarged cross-sectional view of the temperature sensing unit 180. In this example, the temperature sensing unit 180 includes a cathode electrode 186, an anode electrode 187, a cathode region 181, and an anode region 182. The cathode electrode 186 and anode electrode 187 are examples of the front-side metal layer 53. The cathode region 181 and anode region 182 are examples of the silicon layer 110. A coating layer 68, such as polyimide, may be provided above the temperature sensing unit 180.

[0184] The temperature sensing unit 180 has a diode provided on the semiconductor substrate 10. The temperature sensing unit 180 detects the temperature of the semiconductor device 100 by utilizing the fact that the current-voltage characteristics of the diode change according to temperature. The temperature sensing unit 180 is positioned above the semiconductor substrate 10 via an insulating film 184. The insulating film 184 may be a deposited film such as an HTO film, or a film obtained by thermal oxidation of the semiconductor substrate 10, etc. The temperature sensing unit 180 may be provided above the well region 17.

[0185] The cathode region 181 and the anode region 182 constitute a PN diode. For example, the cathode region 181 is formed of an N-type semiconductor and functions as the cathode of the PN diode. The anode region 182 is formed of a P-type semiconductor and functions as the anode of the PN diode. The cathode region 181 and the anode region 182 are provided on an insulating film 184. The material of the cathode region 181 and the anode region 182 may be polysilicon.

[0186] The cathode electrode 186 is electrically connected to the cathode region 181 via a contact hole 58. The cathode electrode 186 may be made of the same material as the emitter electrode 52. The cathode electrode 186 is electrically connected to the cathode pad 118 by cathode wiring 119.

[0187] The anode electrode 187 is electrically connected to the anode region 182 via a contact hole 58. A plug region 19 may be formed at the bottom of the contact hole 58 above the anode region 182. The anode electrode 187 may be made of the same material as the emitter electrode 52. The anode electrode 187 is electrically connected to the anode pad 116 by anode wiring 117.

[0188] The interlayer insulating film 38 is provided on the upper surfaces of the cathode region 181 and the anode region 182. Contact holes 58 may be formed in the interlayer insulating film 38 of the temperature sensing portion 180.

[0189] Below the temperature sensing portion 180, element regions such as the transistor portion 70 and the diode portion 80 may be provided. In this example, the temperature sensing portion 180 is surrounded by the transistor portion 70. However, the temperature sensing portion 180 may be surrounded by the diode portion 80, or it may be located in a region away from the active portion 120, or near the edge termination structure portion 140. In this example, a collector region 22 is provided below the temperature sensing portion 180, but a high-density region such as the collector region 22 does not necessarily have to be formed below the temperature sensing portion 180.

[0190] The configuration between the interlayer insulating film 38 and the front-side metal layer 53, and the vicinity of the contact hole 58, may be the same as the embodiment of the interlayer insulating film 38 and the front-side metal layer 53, and the contact hole 54, as described in Figures 3A to 5B. That is, the semiconductor device 100 comprises an intervening layer 66 provided above the interlayer insulating film 38, a barrier metal layer 60 provided above the intervening layer 66, and a silicide layer 63 provided above the silicon layer 110.

[0191] Figure 10A shows an example of the g-g' cross-section in Figure 8. The g-g' cross-section is the XZ plane passing through the gate pad 112. In this example, the semiconductor device 100 has a semiconductor substrate 10, a connecting portion 25, an interlayer insulating film 38, an intervening layer 66, a barrier metal layer 60, a plug layer 64, and a gate pad 112 in the g-g' cross-section. The connecting portion 25 is an example of a silicon layer 110. The gate pad 112 is an example of a front-side metal layer 53.

[0192] A coating layer 68, such as polyimide, may be provided on a portion of the upper part of the gate pad 112. The portion of the upper surface of the gate pad 112 that is exposed and not covered by the coating layer 68 is defined as the opening region 164.

[0193] The connection portion 25 may be provided above the semiconductor substrate 10 via an insulating layer 26. The connection portion 25 may be directly connected to the gate conductive portion 44 extending to the active portion 120 outside the range shown in Figure 10A, in which case the connection portion 25 and the insulating layer 26 may be formed simultaneously with the gate conductive portion 44 and the gate insulating film 42. Alternatively, the connection portion 25 may not be directly connected to the gate conductive portion 44 extending to the active portion 120, in which case the connection portion 25 and the insulating layer 26 may be formed simultaneously with the gate conductive portion 44 and the gate insulating film 42 or separately.

[0194] The gate pad 112 is provided above the semiconductor substrate 10. The gate pad 112 may be provided overlapping with the connection portion 25 in the depth direction of the semiconductor substrate 10. In this example, the gate pad 112 is electrically connected to the connection portion 25 via a contact hole 55 provided above the connection portion 25. The gate pad 112 may be formed of the same material as the emitter electrode 52, or it may be made of a different material. The gate pad 112 may extend outside the opening region 164 and function as the gate metal layer 50 of the active portion gate wiring 131 or the outer peripheral gate wiring 130.

[0195] The configuration between the interlayer insulating film 38 and the front-side metal layer 53, and the vicinity of the contact hole 55, may be the same as the embodiment of the interlayer insulating film 38 and the front-side metal layer 53, and the contact hole 54, as described in Figures 3A to 5B. That is, the semiconductor device 100 comprises an intervening layer 66 provided above the interlayer insulating film 38, a barrier metal layer 60 provided above the intervening layer 66, and a silicide layer 63 provided above the silicon layer 110.

[0196] Figure 10B shows an example of the g-g' cross section in Figure 8. The semiconductor device 100 in this example differs from the embodiment in Figure 10A in that it has a gate trench portion 40 below the opening region 164 of the gate pad 112. In this example, the differences from the embodiment in Figure 10A will be explained in detail, and other aspects may be the same as those of the embodiment in Figure 10A.

[0197] The gate trench portion 40 in the area overlapping with the gate pad 112 is provided in the well region 17. The diffusion depth of the well region 17 is greater than the depth of the gate trench portion 40. In this example, the entire gate trench portion 40 in the area overlapping with the gate pad 112 is provided in the well region 17 when viewed from above. This makes it possible to mitigate electric field concentration at the bottom of each gate trench portion 40.

[0198] In this example, the gate pad 112 is electrically connected to the gate conductive portion 44 via a contact hole 55 provided above the gate conductive portion 44. The gate conductive portion 44 is an example of a silicon layer 110. In this example, the gate trench portion 40 may or may not extend to the active portion 120.

[0199] Figure 10C shows an example of the g-g' cross section in Figure 8. The semiconductor device 100 in this example differs from the embodiment in Figure 10A in that the contact hole 55 is not provided over the entire area below the opening region 164 of the gate pad 112. Otherwise, it may be the same as the embodiment in Figure 10A.

[0200] In this example, the connection portion 25 and insulating layer 26 are not provided in the entire area below the gate pad 112. In other examples, the connection portion 25 and insulating layer 26 may be provided between the interlayer insulating film 38 and the semiconductor substrate 10 in part or all of the area below the gate pad 112. The configuration between the interlayer insulating film 38 and the front-side metal layer 53 may be the same as the embodiment between the interlayer insulating film 38 and the front-side metal layer 53 described in Figures 3A to 5B. That is, the semiconductor device 100 includes an intervening layer 66 provided above the interlayer insulating film 38 and a barrier metal layer 60 provided above the intervening layer 66.

[0201] In Figures 10A to 10C, the lower part of the coating layer 68 is described as being the same as the lower part of the opening region 164, but they may have different structures. That is, for example, the structure below the coating layer 68 may be the structure shown in Figure 10A, and the structure below the opening region 164 may be the structure shown in Figure 10C. Also, in Figures 10A to 10C, the gate pad 112 is described as an example, but the configuration between the interlayer insulating film 38 and the surface metal layer 53, and the vicinity of the contact hole may also be applied below other pads that do not have an element below them. In this example, the same may be applied to the region of the sense electrode 114 that does not have the current sensing portion 115 below it, the anode pad 116, and the cathode pad 118.

[0202] In the above description, an example was given in which the intervening layer 66 and barrier metal layer 60 are provided over the entire surface above the interlayer insulating film 38. However, the area over which the intervening layer 66 and barrier metal layer 60 are provided above the interlayer insulating film 38 is not limited to this. For example, in order to suppress fluctuations in characteristics such as a decrease in the threshold voltage of the semiconductor device 100, there may be a mixture of areas over the interlayer insulating film 38 where the barrier metal layer 60 is provided and areas where the barrier metal layer 60 is not provided. In this case, the intervening layer 66 does not need to be provided in the areas where the barrier metal layer 60 is not provided. Also, in areas where the influence of stress due to wire bonding is small, the intervening layer 66 does not need to be provided.

[0203] Figure 11A is a flowchart showing an example of the manufacturing process for a semiconductor device 100. The manufacturing process in this example is an example of a method for manufacturing the components near the contact holes. That is, the manufacturing process for the semiconductor device 100 may include other steps not shown in this flowchart, such as a step of forming the base region 14, emitter region 12, and contact region 15, etc., by ion implantation into the semiconductor substrate 10. The contact holes may be contact holes 54, 55, 56, or 58.

[0204] In step S100, an interlayer insulating film 38 of silicate glass is provided above the silicon layer 110. Step S100 for providing the interlayer insulating film 38 may include step S102 for providing a first insulating layer 382 above the silicon layer 110, and step S104 for providing a second insulating layer 384 above the first insulating layer 382. The first insulating layer 382 may be a silicon oxide film, an HTO film, or an LTO film. The second insulating layer 384 may be silicate glass, a BPSG film, a BSG film, or a PSG film.

[0205] In step S110, contact holes are provided in the interlayer insulating film 38. The contact holes may be provided by etching the interlayer insulating film 38. In step S110, contact holes such as contact holes 54, 55, 56, and 58 may be formed in the interlayer insulating film 38. The manufacturing process of the semiconductor device 100 in this example may include step S110, in which contact holes are provided in the interlayer insulating film 38, after step S100, in which the intervening layer 66 is provided, and before step S140. Therefore, the manufacturing process of the semiconductor device 100 in this example may be the manufacturing process of the semiconductor device 100 as shown in Figures 3A to 4B.

[0206] In step S120, a resist 192 is provided. In step S130, impurity ions 190 are injected into the bottom of the contact holes in the openings of the resist 192. The manufacturing process of the semiconductor device 100 in this example may include step S130, in which impurity ions 190 are injected into the bottom of the contact holes, after step S110 in which contact holes are provided and before step S140 in which the intervening layer 66 is provided. The impurity ions 190 may include halide ions. As an example, the halide ions are fluoride ions, more specifically, boron fluoride ions. The injection of impurity ions 190 may later form a plug region 19. The bottom of the contact holes where a plug region 19 is not formed may be covered with resist 192. Note that the ions injected into the bottom of the contact holes are not limited to halide ions. The ions injected into the bottom of the contact holes may be, for example, boron ions.

[0207] The impurity ions 190 may be implanted from above the semiconductor substrate 10. The resist 192 may cover part or all of the interlayer insulating film 38. If the interlayer insulating film 38 is not covered by the resist 192, the impurity ions 190 may also be implanted into the interlayer insulating film 38, which may increase the halogen or boron concentration on the upper surface of the interlayer insulating film, or the halogen or boron concentration in the second insulating layer 384. Step S120 may be omitted if the electrical connection between the N-type impurity region and the front-side metal layer 53 is not hindered even if the impurity ions 190 are implanted across the entire bottom of the contact hole. For example, step S120 may be omitted if the bottom of the contact hole is located below the lower surface of the interlayer insulating film 38, or if the concentration of the N-type impurity region is sufficiently high. The resist 192 is removed after the implantation of impurity ions 190 in step S130 and before the formation of the intervening layer 66 in step S140.

[0208] In step S140, an intervening layer 66 is provided above the interlayer insulating film 38. Step S140 of providing the intervening layer 66 may include the step of providing an intervening layer 66 containing titanium nitride. Step S140 of providing the intervening layer 66 may include the step of providing an intervening layer 66 containing a silicon oxide film.

[0209] If step S140 for providing the intervening layer 66 includes providing an intervening layer 66 containing titanium nitride, the intervening layer 66 may be formed by sputtering titanium nitride above the interlayer insulating film 38. If step S140 for providing the intervening layer 66 includes providing an intervening layer 66 containing a silicon oxide film, the intervening layer 66 may be formed by depositing an LTO film or an HTO film above the interlayer insulating film 38, or by depositing a TEOS film above the interlayer insulating film 38 using plasma CVD.

[0210] In step S150, annealing is performed. Through the annealing process, a plug region 19 may be formed in the area where impurity ions 190 are implanted at the bottom of the contact hole, and in the area where the impurities have diffused.

[0211] In step S160, a barrier metal layer 60 is provided above the intervening layer 66. Step S160 for providing the barrier metal layer 60 may include step S162 for providing a first barrier metal portion 61 above the intervening layer 66, and step S164 for providing a second barrier metal portion 62 above the first barrier metal portion 61. Step S162 for providing the first barrier metal portion 61 may include the step of providing a first barrier metal portion 61 containing titanium. For example, step S162 for providing the first barrier metal portion 61 may include the step of sputtering titanium. Step S164 for providing the second barrier metal portion 62 may include the step of providing a second barrier metal portion 62 containing titanium nitride. For example, step S164 for providing the second barrier metal portion 62 may include the step of sputtering titanium nitride.

[0212] In step S170, sintering is performed. During the sintering process, at least a portion of the titanium may be nitrided to become titanium nitride. That is, step S170, in which sintering is performed, may be part of step S160, in which the barrier metal layer 60 is provided, and may be part of step S164, in which the second barrier metal portion 62 is provided. For example, the combination of the step of sputtering titanium and the step of sintering S170 may be part of step S164, in which the second barrier metal portion 62 is provided.

[0213] In step S180, a silicide layer 63 is provided above the silicon layer 110 in a contact hole provided in the interlayer insulating film 38. Step S180, in which the silicide layer 63 is provided, may be part of step S170, which is sintering. That is, the silicide layer 63 may be formed when the material of the barrier metal layer 60 deposited at the bottom of the contact hole reacts with the silicon of the silicon layer 110 during the sintering process to form a silicide. In this case, the silicide layer 63 may be formed to a position deeper than the surface 21. The silicide layer 63 may contain reaction products between the barrier metal layer 60 and the silicon layer 110 during the sintering process, reaction products between the barrier metal layer 60 and the intervening layer 66 during the sintering process, and reaction products between the intervening layer 66 and the silicon layer 110 during the sintering process.

[0214] In step S190, a front-side metal layer 53 is provided above the barrier metal layer 60. The manufacturing process of the semiconductor device 100 may include a step of providing a plug layer 64 before step S180, in which the front-side metal layer 53 is provided. For example, tungsten may be formed by CVD to fill the inside of the contact holes, and the unwanted tungsten film outside the contact holes may be removed by etch-back. The formed front-side metal layer 53 is patterned, and the barrier metal layer 60 may also be patterned at the same time. If the intervening layer 66 is made of a conductive material such as titanium nitride, it is patterned in the same way as the front-side metal layer 53 and the barrier metal layer 60, and the intervening layer 66 is not left on the upper surface of the interlayer insulating film 38 between each of the front-side metal layers 53. If the intervening layer 66 is made of an insulating material such as a silicon oxide film, the intervening layer 66 is not patterned and may be left on the upper surface of the interlayer insulating film 38 between each of the front-side metal layers 53.

[0215] The manufacturing process for the semiconductor device 100 in this example includes an annealing step S150 after the step S140 of providing the intervening layer 66 and before the step S162 of providing the first barrier metal portion 61, and a sintering step S170 after the step S164 of providing the second barrier metal portion 62 and before the step S190 of providing the front-side metal layer 53. The annealing step S150 may be omitted. That is, the manufacturing process for the semiconductor device 100 may include a sintering step S170 after the step S140 of providing the intervening layer 66 and before the step S162 of providing the first barrier metal portion 61, without annealing, and after the step S164 of providing the second barrier metal portion 62 and before the step of providing the front-side metal layer 53. In this case, in the sintering step S170, a plug region 19 may be formed in the region where impurity ions 190 are implanted at the bottom of the contact hole. Furthermore, the annealing step S150 may be performed before the step S140 in which the intervening layer 66 is provided. In this order, the intervening layer 66 will not be overheated even if the annealing to form the plug region 19 is to be performed at a high temperature. Also, if the step S140 in which the intervening layer 66 is provided involves heating, the plug region 19 may be formed in the region at the bottom of the contact hole in which impurity ions 190 have been implanted.

[0216] After step S140, which involves providing the intervening layer 66, and before step S160, which involves providing the barrier metal layer 60, a step may be provided to etch and remove or thin the intervening layer 66 at the bottom of the contact hole. By including a step to etch the intervening layer 66, the thickness of the intervening layer 66 at the bottom of the contact hole and the intervening layer 66 above the interlayer insulating film 38 can be finely varied. This eliminates problems such as the intervening layer 66 being too thick at the bottom of the contact hole, hindering the formation of the silicide layer 63, or the intervening layer 66 itself having high electrical resistance, or the intervening layer 66 being too thin above the interlayer insulating film 38, resulting in insufficient improvement of adhesion with the barrier metal layer 60. When the intervening layer 66 on the side of the contact hole is removed, the completed contact hole may have the structure shown in Figure 5A or Figure 5B.

[0217] Figure 11B shows an example of the manufacturing process for semiconductor device 100. This example of the manufacturing process corresponds to the flowchart in Figure 11A.

[0218] In step S100, an interlayer insulating film 38 of silicate glass is provided above the silicon layer 110. In step S110, a contact hole is provided in the interlayer insulating film 38. In step S120, a resist 192 is provided. In step S130, impurity ions 190 are injected into the bottom of the contact hole opening in the resist 192. When impurity ions 190 are injected from above the semiconductor substrate 10, impurity ions 190 are also injected into the second insulating layer 384, which is not covered by the resist 192 and whose upper surface is exposed, which may result in an increase in the halogen concentration or boron concentration in the second insulating layer 384.

[0219] In step S140, an intervening layer 66 is provided above the interlayer insulating film 38. In this example, since a contact hole is formed in step S110, the intervening layer 66 is also formed at the bottom and side walls of the contact hole. In step S150, annealing is performed. Through the annealing process, a plug region 19 is formed at the bottom of the contact hole in the region where ions were implanted and in the region where impurities were diffused.

[0220] In step S160, a barrier metal layer 60 is provided above the intervening layer 66. In this example, since a contact hole is formed in step S110, the first barrier metal portion 61 and the second barrier metal portion 62 are also formed at the bottom and side walls of the contact hole.

[0221] In step S170, sintering is performed, and in step S180, a silicide layer 63 is formed above the silicon layer 110 in the contact hole provided in the interlayer insulating film 38. The intervening layer 66 and the first barrier metal portion 61 formed at the bottom of the contact hole contribute to silicide formation in steps S170 and S180, and the silicide layer 63 is formed. At this time, the silicide layer 63 may be formed to a position deeper than the surface 21. As shown in the examples in Figures 4A and 4B, at least a portion of the intervening layer 66 may remain without contributing to silicide formation.

[0222] In step S190, a front-side metal layer 53 is provided above the barrier metal layer 60. A plug layer 64 may be provided before step S190.

[0223] Figure 12A is a flowchart showing an example of the manufacturing process for semiconductor device 100. The manufacturing process for semiconductor device 100 in this example differs from the embodiment in Figure 11A in that the order of the steps for providing the intervening layer 66 and providing the contact holes is different. In this example, the differences from the embodiment in Figure 11A will be explained in detail, and other aspects may be the same as those in the embodiment in Figure 11A.

[0224] In step S200, an interlayer insulating film 38 of silicate glass is provided above the silicon layer 110. The details of steps S200, S202, and S204 may be the same as those of steps S100, S102, and S104 in Figure 11A.

[0225] In step S210, an intervening layer 66 is provided above the interlayer insulating film 38. The details of the method for providing the intervening layer 66 may be the same as in step S140 of Figure 11A.

[0226] In step S220, contact holes are provided in the interlayer insulating film 38. The contact holes may be provided by etching the intervening layer 66 and the interlayer insulating film 38. In step S220, contact holes such as contact holes 54, 55, 56, and 58 may be formed in the interlayer insulating film 38. The manufacturing process of the semiconductor device 100 in this example may include step S220, in which contact holes are provided in the interlayer insulating film 38, after step S210, in which the intervening layer 66 is provided, and before step S260, in which the barrier metal layer 60 is provided. Therefore, the manufacturing process of the semiconductor device 100 in this example may be the manufacturing process of the semiconductor device 100 shown in Figures 5A and 5B.

[0227] In step S230, a resist 192 is provided. The resist 192 may cover part or all of the upper part of the intervening layer 66. In step S240, impurity ions 190 are injected into the bottom of the contact holes in the openings of the resist 192. That is, the manufacturing process of the semiconductor device 100 in this example may include a step S240 in which impurity ions 190 are injected into the bottom of the contact holes after step S220 in which contact holes are provided and before step S260 in which the barrier metal layer 60 is provided, and a step S230 in which a resist 192 is provided above the intervening layer 66 before step S240 in which impurity ions 190 are injected into the bottom of the contact holes.

[0228] By providing the resist 192 before implanting the impurity ions 190, it is possible to prevent the impurity ions 190 from being implanted into the bottom of the contact hole where the plug region 19 is not provided. In this case, by covering the intervening layer 66 with the resist 192, it is possible to prevent the halogen concentration or boron concentration in the intervening layer 66 and the interlayer insulating film 38 below it from becoming high. However, step S230 of providing the resist 192 may be omitted. Also, if the concentration of the impurity ions 190 to be implanted is low, the resist 192 does not need to be provided above the intervening layer 66. The resist 192 is removed after the implantation of the impurity ions 190 in step S240.

[0229] In step S250, annealing is performed. The annealing process may form plug regions 19 in the areas where impurity ions 190 are implanted at the bottom of the contact hole, and in the areas where the impurities have diffused. However, as explained in relation to Figure 11A, the annealing step S250 may be omitted. In this case, the plug regions 19 may be formed in the sintering step S270 described later.

[0230] In step S260, a barrier metal layer 60 is provided above the intervening layer 66. In step S270, sintering is performed. In step S280, a silicide layer 63 is provided above the silicon layer 110 in the contact hole provided in the interlayer insulating film 38. In step S290, a front-side metal layer 53 is provided above the barrier metal layer 60. The details of steps S260 to S290 may be the same as steps S160 to S190 in Figure 11A.

[0231] Figure 12B shows an example of the manufacturing process for semiconductor device 100. This example of the manufacturing process corresponds to the flowchart in Figure 12A.

[0232] In step S200, an interlayer insulating film 38 of silicate glass is provided above the silicon layer 110, and in step S210, an interlayer layer 66 is provided above the interlayer insulating film 38.

[0233] In step S220, a contact hole is provided in the interlayer insulating film 38; in step S230, a resist 192 is provided; and in step S240, impurity ions 190 are injected into the bottom of the contact hole opening in the resist 192. The resist 192 may also cover the top of the interlayer 66. In the manufacturing process of the semiconductor device 100 in this example, the contact hole is provided after the interlayer 66 is provided, so the interlayer 66 is not formed on the bottom and side walls of the contact hole. Furthermore, by providing the resist 192 before injecting the impurity ions 190, a plug region 19 can be selectively formed at the bottom of the contact hole, and by having the resist 192 also cover the top of the interlayer 66, it is possible to prevent the halogen concentration or boron concentration in the interlayer 66 and the interlayer insulating film 38 below it from becoming high.

[0234] In step S250, annealing is performed. Through the annealing process, a plug region 19 is formed in the area where ions are implanted and in the area where impurities are diffused at the bottom of the contact hole.

[0235] In step S260, a barrier metal layer 60 is provided above the intervening layer 66. In this example, since a contact hole is formed in step S220, the first barrier metal portion 61 and the second barrier metal portion 62 are also formed at the bottom and side walls of the contact hole.

[0236] In step S270, sintering is performed, and in step S280, a silicide layer 63 is formed above the silicon layer 110 in the contact holes provided in the interlayer insulating film 38. The first barrier metal portion 61 formed at the bottom of the contact hole contributes to silicide formation in steps S270 and S280, and the silicide layer 63 is formed. At this time, the silicide layer 63 may be formed to a position deeper than the surface 21.

[0237] In step S290, a front-side metal layer 53 is provided above the barrier metal layer 60. A plug layer 64 may be provided before step S280.

[0238] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0239] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0240] 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 17...Well region, 18...Drift region, 19...Plug region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 26...Insulating layer, 30...Dummy trench portion, 31...Extended portion, 32...Dummy insulating film, 33...Connection portion, 34...Dummy conductive portion, 38... Interlayer insulating film, 40...Gate trench section, 41...Stretched section, 42...Gate insulating film, 43...Connection section, 44...Gate conductive section, 50...Gate metal layer, 52...Emitter electrode, 53...Front side metal layer, 54...Contact hole, 55...Contact hole, 56...Contact hole, 58...Contact hole, 60...Barrier metal layer, 61...First barrier metal section, 62...Second barrier metal section, 63...Silicide layer, 64...Plug layer, 66... ...Interfacing layer, 68...Coating layer, 70...Transistor section, 71...Mesa section, 80...Diode section, 81...Mesa section, 82...Cathode region, 85...Extension region, 90...Boundary section, 91...Mesa section, 100...Semiconductor device, 102...Edge, 110...Silicon layer, 112...Gate pad, 114...Sense electrode, 115...Current sense section, 116...Anode pad, 117...Anode wiring, 118...Cathode pad, 119...Cathode wiring, 120 ...Active section, 130...Outer periphery gate wiring, 131...Gate wiring between active sections, 140...Edge termination structure, 151...Lifetime control region on the back side, 152...Lifetime control region on the front side, 164...Opening region, 180...Temperature sensing section, 181...Cathode region, 182...Anode region, 184...Insulating film, 186...Cathode electrode, 187...Anode electrode, 190...Impure ions, 192...Resist, 382...First insulating layer, 384...Second insulating layer

Claims

1. Silicon layer and Having a contact hole, an interlayer insulating film of silicate glass provided above the silicon layer, An intervening layer provided above the interlayer insulating film, A barrier metal layer provided above the aforementioned intervening layer, A front-side metal layer provided above the barrier metal layer, In the aforementioned contact hole, a silicide layer is provided above the silicon layer, Equipped with Semiconductor equipment.

2. The thickness of the intervening layer is thinner than the thickness of the interlayer insulating film. The semiconductor device according to claim 1.

3. The thickness of the intervening layer above the interlayer insulating film is 3 nm or more and 20 nm or less. The semiconductor device according to claim 1.

4. The barrier metal layer is in contact with the silicide layer. The semiconductor device according to claim 1.

5. The fluorine concentration of the intervening layer is lower than the fluorine concentration on the upper surface of the interlayer insulating film. The semiconductor device according to any one of claims 1 to 4.

6. The interlayer insulating film is A first insulating layer provided above the silicon layer, A second insulating layer is provided above the first insulating layer and has a higher fluorine concentration than the first insulating layer, has The semiconductor device according to any one of claims 1 to 4.

7. The intervening layer is in contact with the second insulating layer. The semiconductor device according to claim 6.

8. The barrier metal layer is A first barrier metal portion provided above the intervening layer, A second barrier metal portion is provided above the first barrier metal portion, has The semiconductor device according to any one of claims 1 to 4.

9. The first barrier metal portion and the second barrier metal portion are provided above the interlayer insulating film and on the side walls of the contact holes, The first barrier metal portion is in contact with the side wall of the contact hole. The semiconductor device according to claim 8.

10. The intervening layer, the first barrier metal portion, and the second barrier metal portion are provided above the interlayer insulating film and on the side walls of the contact holes. The semiconductor device according to claim 8.

11. The intervening layer contains titanium nitride. The semiconductor device according to claim 8.

12. The first barrier metal portion contains titanium, The second barrier metal portion contains titanium nitride. The semiconductor device according to claim 11.

13. The second barrier metal portion contains titanium nitride that is denser than the intervening layer. The semiconductor device according to claim 12.

14. The intervening layer includes a silicon oxide film. The semiconductor device according to claim 8.

15. The first barrier metal portion contains titanium, The second barrier metal portion contains titanium nitride. The semiconductor device according to claim 14.

16. Substrate and Having a contact hole, an interlayer insulating film is provided above the underlying layer, An intervening layer provided above the interlayer insulating film, A barrier metal layer provided above the aforementioned intervening layer, A front-side metal layer provided above the barrier metal layer, In the aforementioned contact hole, an alloy layer is provided above the underlying layer, Equipped with Semiconductor equipment.

17. The steps include: providing an interlayer insulating film of silicate glass above the silicon layer; The step of providing an intervening layer above the interlayer insulating film, The step of providing a barrier metal layer above the intervening layer, In the contact hole provided in the interlayer insulating film, the step of providing a silicide layer above the silicon layer, The step of providing a front-side metal layer above the barrier metal layer, Equipped with A method for manufacturing a semiconductor device.

18. After the step of providing the interlayer insulating film, and before the step of providing the intervening layer, the interlayer insulating film is provided with a step of providing the contact holes. The method for manufacturing a semiconductor device according to claim 17.

19. After the step of creating the contact hole, and before the step of creating the intervening layer, the procedure includes a step of implanting halide ions into the bottom of the contact hole. The method for manufacturing a semiconductor device according to claim 18.

20. After the step of providing the intervening layer, and before the step of providing the barrier metal layer, the procedure includes providing the contact holes in the interlayer insulating film. The method for manufacturing a semiconductor device according to claim 17.

21. After the step of creating the contact holes and before the step of creating the barrier metal layer, the procedure includes a step of implanting halide ions into the bottom of the contact holes. A method for manufacturing a semiconductor device according to claim 20.

22. The step of providing a resist above the intervening layer is provided before the step of implanting halide ions into the bottom of the contact hole. The method for manufacturing a semiconductor device according to claim 21.

23. The step of providing the interlayer insulating film is, The steps include providing a first insulating layer above the silicon layer, The step of providing a second insulating layer above the first insulating layer, has A method for manufacturing a semiconductor device according to any one of claims 17 to 22.

24. The step of providing the barrier metal layer is, The step of providing a first barrier metal portion above the intervening layer, The step of providing a second barrier metal portion above the first barrier metal portion, has A method for manufacturing a semiconductor device according to any one of claims 17 to 22.

25. After the step of providing the intervening layer, and before the step of providing the first barrier metal portion, there is a step of annealing, After the step of providing the second barrier metal portion, and before the step of providing the front side metal layer, there is a sintering step, Equipped with The method for manufacturing a semiconductor device according to claim 24.

26. After the step of providing the intervening layer, and before the step of providing the first barrier metal portion, the process includes a step of not annealing, and after the step of providing the second barrier metal portion, and before the step of providing the front side metal layer, the process includes a step of sintering. The method for manufacturing a semiconductor device according to claim 24.

27. The step of providing the intervening layer includes the step of providing the intervening layer containing titanium nitride. The method for manufacturing a semiconductor device according to claim 24.

28. The step of providing the first barrier metal portion includes the step of providing the first barrier metal portion containing titanium, The step of providing the second barrier metal portion includes the step of providing the second barrier metal portion containing titanium nitride. The method for manufacturing a semiconductor device according to claim 27.

29. The step of providing the intervening layer includes the step of providing the intervening layer which includes a silicon oxide film. The method for manufacturing a semiconductor device according to claim 24.

30. The step of providing the first barrier metal portion includes the step of providing the first barrier metal portion containing titanium, The step of providing the second barrier metal portion includes the step of providing the second barrier metal portion containing titanium nitride. The method for manufacturing a semiconductor device according to claim 29.

31. The step of providing an interlayer insulating film above the underlying layer, The step of providing an intervening layer above the interlayer insulating film, The step of providing a barrier metal layer above the intervening layer, In the contact hole provided in the interlayer insulating film, the step of providing an alloy layer above the underlying layer, The step of providing a front-side metal layer above the barrier metal layer, Equipped with A method for manufacturing a semiconductor device.

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