Charge / discharge control circuit, charge / discharge control method, and battery device

Abstract

To provide a charge / discharge control circuit, a charge / discharge control method, and a battery device that suppress malfunctions that occur when a switch element controlling the charging or discharging of a secondary battery is turned on or off, compared to conventional technology. [Solution] A charge / discharge control circuit for preventing malfunctions when switching a switch element that controls the charging and discharging of a secondary battery is turned on or off includes: an abnormality detection circuit that detects an abnormal state in which charging or discharging is prohibited and generates an abnormality detection signal, and stops generating the abnormality detection signal when it detects that the abnormal state has been resolved; a control circuit that generates a switch control signal of a first or second value to turn the switch element on or off based on the abnormality detection signal; and a state transition detection circuit that generates a first timing request signal based on a change in the value of the switch control signal and stops generating the first timing request signal after a predetermined first period from the generation of the first timing request signal. The control circuit holds the switch control signal at the value at the time the first timing request signal was generated when the first timing request signal is generated.

Description

Technical Field

[0001] The present disclosure relates to a charge-discharge control circuit, a charge-discharge control method, and a battery device that control charge and discharge of a battery such as a secondary battery, for example.

Background Art

[0002] In general, a battery device for a secondary battery includes a secondary battery, a charge-discharge control circuit so-called a protection circuit, an external positive terminal used for charging and discharging the secondary battery, an external negative terminal, a charge control transistor that controls charging of the secondary battery, and a discharge control transistor that controls discharging of the secondary battery. The charge-discharge control circuit includes an external negative voltage input terminal having an external negative voltage corresponding to the voltage of the external negative terminal. The charge-discharge control circuit is configured to detect various states using fluctuations in the external negative voltage, and malfunctions occur due to unintended fluctuations in the external negative voltage. In order to suppress such malfunctions, for example, Patent Document 1 discloses a technology related to a charge-discharge control circuit that can detect that a charger is connected even when a charger with a voltage lower than a predetermined value is connected in a state where the charge-discharge control circuit of the battery device turns off the discharge control transistor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The conventional charge-discharge control circuit may erroneously detect an abnormality of the battery device due to the operation of a switch element that controls charging or discharging of the secondary battery, leading to a malfunction of the protection function for the secondary battery.

[0005] The purpose of this disclosure is to provide a charge / discharge control circuit, a charge / discharge control method, and a battery device that suppress malfunctions that occur when a switch element controlling the charging or discharging of a secondary battery is turned on or off, compared to the prior art. [Means for solving the problem]

[0006] A charge / discharge control circuit according to one aspect of the present disclosure is a charge / discharge control circuit for preventing malfunctions when a switch element that controls the charging or discharging of a secondary battery is turned on or off, and comprises: an abnormality detection circuit that detects a charge prohibition abnormal state or a discharge prohibition abnormal state and generates an abnormality detection signal, and detects the resolution of the charge prohibition abnormal state or the discharge prohibition abnormal state and stops generating the abnormality detection signal; a control circuit that generates a switch control signal having a first value for turning off the switch element or a switch control signal having a second value for turning on the switch element based on the abnormality detection signal; and a state transition detection circuit that generates a first timing request signal based on a change in the value of the switch control signal and stops generating the first timing request signal after a predetermined first period from the generation of the first timing request signal, wherein the control circuit holds the switch control signal at the value at the time the first timing request signal was generated when the first timing request signal is generated. [Effects of the Invention]

[0007] According to this disclosure, it is possible to provide a charge / discharge control circuit, a charge / discharge control method, and a battery device that suppress malfunctions that occur when a switch element controlling the charging or discharging of a secondary battery is turned on or off, compared to the prior art. [Brief explanation of the drawing]

[0008] [Figure 1] A schematic diagram of the battery device according to Embodiment 1. [Figure 2] A schematic diagram of the time measurement circuit according to Embodiment 1. [Figure 3] A schematic diagram of the frequency divider circuit according to Embodiment 1. [Figure 4] A timing chart showing an example of the operation of the oscillator circuit and frequency divider circuit according to Embodiment 1. [Figure 5] A schematic diagram showing an example of a time setting method for the time setting circuit according to Embodiment 1. [Figure 6] A schematic diagram of the state transition detection circuit according to Embodiment 1. [Figure 7] A schematic diagram of the discharge control driver and charge control driver according to Embodiment 1. [Figure 8] A flowchart showing an example of the operation of the charge / discharge control circuit according to Embodiment 1. [Figure 9] A timing chart showing an example of the operation of the charge / discharge control circuit according to Embodiment 1. [Figure 10] A timing chart showing an example of the operation of a charge / discharge control circuit related to a comparative example. [Figure 11] This is a schematic diagram of a battery device according to Embodiment 2. [Figure 12] A schematic diagram of the time measurement circuit according to Embodiment 2. [Figure 13] A schematic diagram of the state transition detection circuit according to Embodiment 2. [Figure 14] A timing chart showing an example of the operation of the charge / discharge control circuit according to Embodiment 2. [Figure 15] A schematic diagram of a modified time measurement circuit. [Figure 16] A schematic diagram of a modified battery device. [Modes for carrying out the invention]

[0009] The embodiments of this disclosure will be described below with reference to the drawings. However, the configurations described below are merely examples of this disclosure, and this disclosure is not limited to the embodiments described below. The technology in this disclosure is not limited thereto, and various modifications, substitutions, additions, and omissions are possible in other embodiments as long as they do not depart from the technical idea of ​​this disclosure, depending on the design, etc.

[0010] The present disclosure has been fully described in connection with preferred embodiments with reference to the accompanying drawings, but various variations and modifications will be apparent to those skilled in the art. It is to be understood that such variations and modifications are included therein insofar as they do not depart from the scope of the present disclosure as defined by the appended claims.

[0011] In the present disclosure, when describing a comparative example, a modified example, or a plurality of embodiments, differences from Embodiment 1 will be mainly explained. In this case, in the comparative example, modified example, or other embodiments, components that are identical or equivalent to those in Embodiment 1 will be described with the same reference numerals. Further, in the comparative example, modified example, or other embodiments, descriptions overlapping with those of Embodiment 1 may be omitted. Features described in the modified examples or embodiments may be combined with each other as long as no contradiction arises.

[0012] In general, a battery device for a secondary battery includes a secondary battery, a charge / discharge control circuit having a protection function for protecting the secondary battery during, for example, charging or discharging, a discharge control transistor that controls discharging of the secondary battery, and a charge control transistor that controls charging of the secondary battery. The battery device further includes an external positive terminal and an external negative terminal used for charging and discharging the secondary battery. The charge / discharge control circuit includes an external negative voltage input terminal having an external negative voltage corresponding to the voltage of the external negative terminal. The charge / discharge control circuit is configured to monitor the state of the secondary battery, generate control signals for switching on and off each of the discharge control transistor and the charge control transistor, and output the control signals to the discharge control driver and the charge control driver, thereby controlling charging and discharging of the secondary battery. The charge / discharge control circuit is configured to detect various states using fluctuations in the external negative voltage. Therefore, if unintended fluctuations in the external negative voltage occur, a malfunction of the charge / discharge control circuit may occur. In addition to fluctuations in the external negative voltage, a malfunction of the charge / discharge control circuit may occur due to erroneous detection of an abnormal state. If such a malfunction occurs when an abnormal state arises, the protection function that should inherently operate in the abnormal state will not operate, and the battery device may be damaged.

[0013] A charge-discharge control circuit according to the present disclosure is a charge-discharge control circuit that prevents malfunction of a switch element for controlling charging or discharging of a secondary battery when the switch element is turned on or off. The charge-discharge control circuit includes an abnormality detection circuit that detects an abnormality and generates an abnormality detection signal, a control circuit that generates a switch control signal for controlling the switch element related to charging or discharging of the secondary battery, and a state transition detection circuit that detects a change in the value of the switch control signal. The abnormality detection circuit detects a charging prohibition abnormal state or a discharging prohibition abnormal state to generate the abnormality detection signal, and detects cancellation of the charging prohibition abnormal state or the discharging prohibition abnormal state to stop generating the abnormality detection signal. The control circuit generates the switch control signal having a first value for turning off the switch element or the switch control signal having a second value for turning on the switch element based on the abnormality detection signal. The state transition detection circuit generates a first timing request signal based on a change in the value of the switch control signal, and stops generating the first timing request signal after a predetermined first period from the generation. The control circuit holds the switch control signal at the value at the time of generation of the first timing request signal while the first timing request signal is being generated. With such a configuration, even if, for example, the abnormality detection circuit erroneously detects the charging prohibition abnormal state or the discharging prohibition abnormal state based on a change in the value of the switch control signal and generates the abnormality detection signal, the control circuit does not change the value of the switch control signal based on the abnormality detection signal. Therefore, the charge-discharge control circuit according to the present disclosure can suppress malfunction that occurs when the switch element for controlling charging or discharging of the secondary battery is turned on or off. In addition, in the charge-discharge control circuit according to the present disclosure, the control circuit can preset the first period during which the value of the switch control signal is not changed based on the abnormality detection signal. Therefore, according to the charge-discharge control circuit of the present disclosure, the time required to prohibit the fluctuation of the value of the switch control signal can be set in consideration of the component configuration of the device to which the charge-discharge control circuit is attached and the parameters of the circuit elements, so that the battery device can be protected more appropriately than in the prior art.

[0014] (Embodiment 1) A battery device 1 according to Embodiment 1 of the present disclosure will be described with reference to Figure 1. Figure 1 is a schematic diagram of the battery device 1 according to Embodiment 1 of the present disclosure.

[0015] The battery device 1 comprises a charge / discharge control circuit 10, a secondary battery 11, a discharge control transistor 12, a charge control transistor 13, and external positive terminal T21 and external negative terminal T22 to which the load 2 is connected. The battery device 1 also comprises resistors 14 to 16. In Embodiment 1, the discharge control transistor 12 and the charge control transistor 13 are N-type MOS transistors. The discharge control transistor 12 and the charge control transistor 13 are examples of switch elements. The discharge control transistor 12 is an example of a second switch element, and the charge control transistor 13 is an example of a first switch element. The discharge control transistor 12 and the charge control transistor 13 may be other switch elements such as bipolar transistors such as IGBTs (Insulated Gate Bipolar Transistors). Similarly, each MOS transistor described later may be another switch element such as a bipolar transistor.

[0016] The external positive terminal T21 is connected to the external negative terminal T22 via load 2. Load 2 includes at least one of a resistive load and a capacitive load. A resistive load refers to a battery-powered device, such as a CPU or motor. A capacitive load refers to the capacitance of a capacitor, or the total capacitance of all parasitic capacitances such as wiring. Load 2 may include a charger for charging a secondary battery.

[0017] The charge / discharge control circuit 10 includes a control circuit 20, an overcharge detection circuit 21, a short-circuit detection circuit 22, a time measurement circuit 23, AND circuits 24 and 25, a state transition detection circuit 26, a discharge control driver 27, a charge control driver 28, and a charger connection detection circuit 29. The charge / discharge control circuit 10 also includes a positive power terminal T11, a negative power terminal T12, a discharge control terminal T13, a charge control terminal T14, an external negative voltage input terminal T15, and a current detection terminal T16.

[0018] The source of the discharge control transistor 12 is connected to the negative terminal of the secondary battery 11 and grounded. The drain of the discharge control transistor 12 is connected to the drain of the charge control transistor 13. The gate of the discharge control transistor 12 is connected to the discharge control driver 27 via the discharge control terminal T13. The discharge control voltage DO is input to the gate from the discharge control driver 27. The source of the charge control transistor 13 is connected to the external negative terminal T22 via the resistor 15. The gate of the charge control transistor 13 is connected to the charge control driver 28 via the charge control terminal T14. The charge control voltage CO is input to the gate from the charge control driver 28. The discharge control transistor 12 has a parasitic diode D1, and the charge control transistor 13 has a parasitic diode D2. The discharge control transistor 12 is switched on and off by the discharge control voltage DO input to its gate from the discharge control driver 27. The charge control transistor 13 is switched on and off by the charge control voltage CO input to its gate from the charge control driver 28.

[0019] The positive power terminal T11 is connected to the positive terminal of the secondary battery 11 and the external positive terminal T21. The negative power terminal T12 is connected to the negative terminal of the secondary battery 11. The external negative voltage input terminal T15 is connected to the external negative terminal T22 and one end of the resistor 15 via a resistor 14. The external negative voltage input terminal T15 has an external negative voltage VM corresponding to the voltage of the external negative terminal T22. The current detection terminal T16 is connected to the other end of the resistor 15 via a resistor 16. The negative power supply voltage VSS of the negative power terminal T12 is input to each circuit of the charge / discharge control circuit 10, but is omitted in the block diagrams from Figure 1 onward, except for some circuits. The external negative voltage input terminal T15 is an example of an external voltage detection terminal.

[0020] The charge / discharge control circuit 10 has one or more protection modes that control the discharge control transistor 12 or the charge control transistor 13 to a predetermined state based on an abnormality detection signal from an abnormality detection circuit such as an overcharge detection circuit 21 or a short-circuit detection circuit 22. The charge / discharge control circuit 10 switches to a mode different from the normal mode, for example, from the normal mode to a predetermined protection mode, based on an abnormality detection signal having a high level. In this way, the charge / discharge control circuit 10 according to Embodiment 1 can perform at least protection against overcharging and protection against short circuits as protection against abnormalities. The charge / discharge control circuit 10 also switches from a predetermined protection mode to, for example, the normal mode, based on an abnormality detection signal having a low level. Furthermore, the charge / discharge control circuit 10 switches from a predetermined protection mode to, for example, the normal mode, based on a detection signal relating to a recovery condition from a predetermined protection mode, such as a charger connection detection signal Scrd having a high level, which will be described later. The detection signal relating to the recovery condition is generated, for example, based on a comparison between an external negative electrode voltage VM and a predetermined threshold in a predetermined detection circuit. Thus, the charge / discharge control circuit 10 according to Embodiment 1 can recover from protection against overcharging and short circuits based on a predetermined signal.

[0021] The control circuit 20 generates a discharge control signal Sdc and a charge control signal Scc to control the discharge control transistor 12 and the charge control transistor 13, respectively, to a predetermined state, based on an abnormality detection signal from an abnormality detection circuit such as an overcharge detection circuit 21 or a short-circuit detection circuit 22. The control circuit 20 is composed of predetermined circuit elements and logic circuits. The control circuit 20 may be configured to include an arithmetic circuit such as a CPU and a memory device which is a storage medium for storing arithmetic programs and data.

[0022] For example, the charge / discharge control circuit 10 transitions from, for example, normal mode to overcharge protection mode after a predetermined delay time T1 based on an overcharge detection signal Socd having a high level. The control circuit 20 generates a low-level charge control signal Scc based on the high-level overcharge detection signal Socd from the overcharge detection circuit 21 and outputs it to the charge control driver 28 and the state transition detection circuit 26. The charge control driver 28 turns off the charge control transistor 13 based on the charge control signal Scc. The control circuit 20 then controls the charge control signal Scc to keep the charge control transistor 13 off during overcharge protection mode. The charge / discharge control circuit 10 transitions from, for example, overcharge protection mode to, for example, normal mode after a predetermined delay time based on an overcharge detection signal Socd having a low level. The control circuit 20 generates a high-level charge control signal Scc based on the low-level overcharge detection signal Socd from the overcharge detection circuit 21 and turns on the charge control transistor 13 via the charge control driver 28, and controls the charge control signal Scc to keep the charge control transistor 13 on during normal mode.

[0023] Thus, when the conditions for returning from a predetermined protection mode are met, the charge / discharge control circuit 10 releases the protection mode and transitions to another mode, such as the normal mode. The delay time T1 may be the same as the delay time when returning from the overcharge protection mode, or it may be different from the other. The charge control signal Scc is an example of a switch control signal. The low level of the charge control signal Scc is an example of the first value. The high level of the charge control signal Scc is an example of the second value. The delay time T1 is an example of the second period. The delay time when returning from the overcharge protection mode is an example of the third period.

[0024] For example, the charge / discharge control circuit 10 transitions from, for example, normal mode to short-circuit protection mode after a predetermined delay time T3 based on a high-level short-circuit detection signal Ssd. The control circuit 20 generates a low-level discharge control signal Sdc based on the high-level short-circuit detection signal Ssd from the short-circuit detection circuit 22 and outputs it to the discharge control driver 27. The discharge control driver 27 turns off the discharge control transistor 12 based on the discharge control signal Sdc. The control circuit 20 then controls the discharge control signal Sdc to keep the discharge control transistor 12 off during short-circuit protection mode. The charge / discharge control circuit 10 transitions from, for example, short-circuit protection mode to, for example, normal mode after a predetermined delay time based on a high-level charger connection detection signal Scrd. The control circuit 20 generates a high-level discharge control signal Sdc based on the high-level charger connection detection signal Scrd from the charger connection detection circuit 29, turns on the discharge control transistor 12 via the discharge control driver 27, and controls the discharge control signal Sdc to keep the discharge control transistor 12 on during normal mode.

[0025] The delay time T3 may be the same as the delay time when recovering from short-circuit protection mode, or it may be different from the delay time. Delay time T3 is an example of the fourth period. The delay time when recovering from short-circuit protection mode based on the charger connection detection signal Scod is an example of the fifth period. The discharge control signal Sdc is an example of a switch control signal. A low level of the discharge control signal Sdc is an example of the first value. A high level of the discharge control signal Sdc is an example of the second value.

[0026] Furthermore, when the control circuit 20 receives an abnormality detection signal with a high level, it generates a protection delay time measurement request Spdm with a high level and outputs it to the time measurement circuit 23, AND circuit 24, and AND circuit 25. The control circuit 20 receives a delay time elapsed signal with a high level after a predetermined delay time from the generation of the aforementioned signal. The charge / discharge control circuit 10 switches, for example, from normal mode to a predetermined protection mode based on the delay time elapsed signal with a high level. The delay time elapsed signal includes, for example, the overcharge delay time elapsed signal Socdp and the short-circuit delay time elapsed signal Ssdp, which will be described later. For example, if a short-circuit delay time elapsed signal Ssdp with a high level is generated while a protection delay time measurement request Spdm with a high level is being generated based on the generation of a short-circuit detection signal Ssd, the charge / discharge control circuit 10 switches from normal mode to short-circuit protection mode. For example, if a high-level overcharge delay time elapsed signal Socdp occurs while a high-level protection delay time measurement request Spdm is being generated based on the generation of an overcharge detection signal Socd, the charge / discharge control circuit 10 switches from normal mode to overcharge protection mode. The control circuit 20 generates a low-level protection delay time measurement request Spdm based on a high-level short-circuit delay time elapsed signal Ssdp or an overcharge delay time elapsed signal Socdp.

[0027] The protection delay time measurement request (Spdm) is an example of the second to fifth timing request signals. The control circuit 20 generating a protection delay time measurement request (Spdm) with a high level is an example of the control circuit 20 generating the second timing request signal. The control circuit 20 generating a protection delay time measurement request (Spdm) with a low level is an example of the control circuit 20 ceasing to generate the second timing request signal.

[0028] When the control circuit 20 receives a charge control transition time measurement request (Sctm) having a high level, as described later, the charge / discharge control circuit 10 transitions from an arbitrary operating mode to a charge control transition mode. In the charge control transition mode, the control circuit 20 operates in such a way that it does not change the levels of the charge control signal (Scc) and the discharge control signal (Sdc) even when it receives an abnormality detection signal. For example, in the charge control transition mode, the control circuit 20 prohibits the generation of a protection delay time measurement request (Spdm) having a high level. When the control circuit 20 receives a charge control transition time measurement request (Sctm) having a low level, the charge / discharge control circuit 10 transitions from the charge control transition mode to an arbitrary operating mode. For example, the control circuit 20 releases the prohibition on the generation of a protection delay time measurement request (Spdm) having a high level.

[0029] The overcharge detection circuit 21 receives the positive power supply voltage VDD at the positive power supply terminal T11 and the negative power supply voltage VSS at the negative power supply terminal T12. The overcharge detection circuit 21 generates an overcharge detection signal Socd based on the voltage difference between the positive power supply voltage VDD and the negative power supply voltage VSS and outputs it to the control circuit 20. When the overcharge detection circuit 21 detects that the voltage difference is greater than or equal to a predetermined overcharge detection voltage, it generates an overcharge detection signal Socd with a high level. When the overcharge detection circuit 21 detects that the voltage difference is less than a predetermined overcharge recovery voltage, it generates an overcharge detection signal Socd with a low level. The overcharge detection voltage may be, for example, 4.5V. The delay time T1 may be, for example, 1 second.

[0030] The overcharge detection circuit 21 is an example of an abnormality detection circuit. The overcharge detection signal Socd is an example of an abnormality detection signal and a charging abnormality detection signal. The condition that the difference voltage between the positive electrode power supply voltage VDD and the negative electrode power supply voltage VSS is greater than or equal to a predetermined overcharge detection voltage is an example of a charging prohibition abnormal state. The condition that the difference voltage is less than a predetermined overcharge recovery voltage is an example of the resolution of the charging prohibition abnormal state. The overcharge detection circuit 21 generating an overcharge detection signal Socd with a high level is an example of the overcharge detection circuit 21 generating an abnormality detection signal. The overcharge detection circuit 21 generating an overcharge detection signal Socd with a low level is an example of the overcharge detection circuit 21 stopping the generation of an abnormality detection signal.

[0031] The short-circuit detection circuit 22 receives the external negative voltage VM at the external negative voltage input terminal T15 and the current detection voltage CS at the current detection terminal T16. The short-circuit detection circuit 22 generates a short-circuit detection signal Ssd based on the difference voltage between the external negative voltage VM and the current detection voltage CS and outputs it to the control circuit 20. The short-circuit detection circuit 22 may be configured to detect abnormal conditions for a short circuit based on other voltages, such as generating a short-circuit detection signal Ssd based on the difference voltage between the external negative voltage VM and the negative power supply voltage VSS. When the short-circuit detection circuit 22 detects that the difference voltage is greater than or equal to a predetermined short-circuit detection voltage, it generates a short-circuit detection signal Ssd with a high level. When the short-circuit detection circuit 22 detects that the difference voltage is less than a predetermined short-circuit recovery voltage, it generates a short-circuit detection signal Ssd with a low level. The short-circuit detection voltage may be, for example, 20mV. The delay time T3 may be, for example, 0.25ms.

[0032] The short-circuit detection circuit 22 is an example of an abnormality detection circuit. The short-circuit detection signal Ssd is an example of an abnormality detection signal and a discharge abnormality detection signal. The condition that the difference voltage between the external negative electrode voltage VM and the current detection voltage CS is greater than or equal to a predetermined short-circuit detection voltage is an example of a discharge prohibition abnormal condition. The short-circuit detection circuit 22 generating a short-circuit detection signal Ssd with a high level is an example of the short-circuit detection circuit 22 generating an abnormality detection signal.

[0033] The charger connection detection circuit 29 receives an external negative voltage VM. The charger connection detection circuit 29 compares the external negative voltage VM with a predetermined charger connection detection threshold voltage. When the charger connection detection circuit 29 detects that the external negative voltage VM has been pulled down to a voltage lower than the charger connection detection threshold voltage due to the connection of the charger, it generates a charger connection detection signal Scd, for example, having a high level, after a predetermined delay time from the detection and outputs it to the control circuit 20. Generating such a high-level charger connection detection signal Scd is one example of the charger connection detection circuit 29 generating a charger connection detection signal.

[0034] The time measurement circuit 23 generates an overcharge delay time elapsed signal Socdp, a short-circuit delay time elapsed signal Ssdp, and a charge control transition time elapsed signal Sctp, each having a predetermined level, and outputs them to AND circuits 24, 25, and 26, respectively. Based on a protection delay time measurement request Spdm or a charge control transition time measurement request Sctm having a high level, the time measurement circuit 23 measures a predetermined period and generates the time elapsed signals Socdp, Ssdp, and Sctp having a high level. Based on a protection delay time measurement request Spdm and a charge control transition time measurement request Sctm having a low level, the time measurement circuit 23 generates the time elapsed signals Socdp, Ssdp, and Sctp having a low level. Based on a protection delay time measurement request Spdm and a charge control transition time measurement request Sctm having a low level, the time measurement circuit 23 resets the timing.

[0035] The overcharge delay time elapsed signal Socdp is an example of a second period elapsed signal. The charge control transition time elapsed signal Sctp is an example of a first period elapsed signal. The time measurement circuit 23 generating an overcharge delay time elapsed signal Socdp or a short-circuit delay time elapsed signal Ssdp having a high level is an example of the time measurement circuit 23 generating a second period elapsed signal. The time measurement circuit 23 generating an overcharge delay time elapsed signal Socdp or a short-circuit delay time elapsed signal Ssdp having a low level is an example of the time measurement circuit 23 stopping the generation of a second period elapsed signal. The time measurement circuit 23 generating a charge control transition time elapsed signal Sctp having a high level is an example of the time measurement circuit 23 generating a first period elapsed signal. The time measurement circuit 23 generating a charge control transition time elapsed signal Sctp having a low level is an example of the time measurement circuit 23 stopping the generation of a first period elapsed signal.

[0036] Figure 2 is a schematic diagram of the time measurement circuit 23 according to Embodiment 1. The time measurement circuit 23 according to Embodiment 1 comprises an OR circuit 231, an oscillator circuit 232, a frequency divider circuit 233, and a time setting circuit 234.

[0037] The OAR circuit 231 generates an oscillation instruction signal Soi having a predetermined level based on the input protection delay time measurement request Spdm and charge control transition time measurement request Sctm, and outputs it to the oscillation circuit 232 and frequency divider circuit 233. The OAR circuit 231 generates an oscillation instruction signal Soi having a high level if at least one of the protection delay time measurement request Spdm and charge control transition time measurement request Sctm has a high level. The OAR circuit 231 generates an oscillation instruction signal Soi having a low level if both the protection delay time measurement request Spdm and charge control transition time measurement request Sctm have low levels.

[0038] The oscillator circuit 232 generates a clock signal Scl based on the input oscillation instruction signal Soi and outputs it to the frequency divider circuit 233. When the oscillator circuit 232 receives an oscillation instruction signal Soi with a high level, it starts oscillating and switches the clock signal Scl between a high level and a low level at a predetermined period Tcl, such as 0.5ms. When the oscillator circuit 232 receives an oscillation instruction signal Soi with a low level, it stops oscillating and generates a clock signal Scl with a low level.

[0039] The frequency divider circuit 233 generates a divided signal Sdiv based on the input clock signal Scl and outputs it to the time setting circuit 234. When the frequency divider circuit 233 receives the oscillating clock signal Scl, it sets the period Tcl of the clock signal Scl to 2 n-1 The frequency divider circuit 233 generates n divided signals Sdiv, each divided by a factor of two. n is a natural number. The n divided signals Sdiv include divided signals Sdiv1, Sdiv2, ..., Sdivn. In this specification, the n divided signals Sdiv1, Sdiv2, ..., Sdivn are also referred to as divided signals Sdiv as appropriate. The frequency divider circuit 233 divides each divided signal Sdivn (n is a natural number) by the period Tcl of the clock signal Scl. n-1 The signal switches between high and low levels at twice the frequency. Additionally, the frequency divider circuit 233 is initialized when it receives an oscillation instruction signal Soi with a low level, and generates a frequency divider signal Sdiv with a low level.

[0040] Figure 3 is a schematic diagram of a frequency divider circuit 233 according to Embodiment 1. As shown in Figure 3, the frequency divider circuit 233 comprises a plurality of toggle flip-flop (TFF) circuits 2331 to 2333 and a plurality of buffer circuits 2334 to 2337. The frequency divider circuit 233 shown in Figure 3 is an example for the case where n=4. n is not limited to 4, and any number such as 5, 10, 20 can be set. The clock signal Scl from the oscillator circuit 232 is input to terminal CLK of TFF circuit 2331. Terminal Q of TFF circuit 2331 is connected to terminal CLK of TFF circuit 2332. Terminal Q of TFF circuit 2332 is connected to terminal CLK of TFF circuit 2333. The signal obtained by inverting the level of the oscillation instruction signal Soi from the OR circuit 231 is input to terminal R of each TFF circuit 2331 to 2333. When each TFF circuit 2331 to 2333 receives an oscillation instruction signal Soi with a low level, it resets the level of the signal generated from terminal Q to a predetermined level, such as a low level.

[0041] Buffer circuits 2334 to 2337 buffer the input signal and generate a signal with a similar level to the input signal. Buffer circuit 2334 receives the clock signal Scl from the oscillator circuit 232 and generates a divided signal Sdiv1 with a similar level to the clock signal Scl. Buffer circuit 2335 receives the signal from terminal Q of the TFF circuit 2331 and generates a divided signal Sdiv2 with a similar level to the input signal. Buffer circuit 2336 receives the signal from terminal Q of the TFF circuit 2332 and generates a divided signal Sdiv3 with a similar level to the input signal. Buffer circuit 2337 receives the signal from terminal Q of the TFF circuit 2333 and generates a divided signal Sdiv4 with a similar level to the input signal.

[0042] Figure 4 is a timing chart showing an example of the operation of the oscillator circuit 232 and frequency divider circuit 233 according to Embodiment 1. The horizontal axis of Figure 4 represents time. The vertical axis of Figure 4 represents the level of the oscillation instruction signal Soi, the level of the clock signal Scl, and the levels of each frequency divider signal Sdiv1 to Sdiv4, respectively. Sdiv represents the value when the frequency divider signal Sdiv, which is represented by each frequency divider signal Sdiv1 to Sdiv4, is represented by 4 bits. The elapsed time shows an example of the elapsed time [ms] represented by Sdiv.

[0043] Until the oscillator circuit 232 receives an oscillation instruction signal Soi with a high level, the frequency divider circuit 233 generates frequency divider signals Sdiv1 to Sdiv4 with low levels. At time t10, when the Ore circuit 231 generates an oscillation instruction signal Soi with a high level, the oscillator circuit 232 switches the clock signal Scl between high and low levels at a predetermined period Tcl based on the oscillation instruction signal Soi with a high level. At time t11, when the clock signal Scl with a high level is received, the buffer circuit 2334 generates a frequency divider signal Sdiv1 with a high level. At time t12, when the clock signal Scl changes from high level to low level, the buffer circuit 2334 generates a frequency divider signal Sdiv1 with a low level. The TFF circuit 2331 generates a signal with a high level from terminal Q, and the buffer circuit 2335 generates a frequency divider signal Sdiv2 with a high level.

[0044] At time t13, when the clock signal Scl changes from a high level to a low level, buffer circuit 2334 generates a divided signal Sdiv1 with a low level. TFF circuit 2331 generates a signal with a low level from terminal Q, and buffer circuit 2335 generates a divided signal Sdiv2 with a low level. TFF circuit 2332 generates a signal with a high level from terminal Q, and buffer circuit 2336 generates a divided signal Sdiv3 with a high level.

[0045] At time t14, when the clock signal Scl changes from a high level to a low level, buffer circuit 2334 generates a divided signal Sdiv1 with a low level. TFF circuit 2331 generates a signal with a low level from terminal Q, and buffer circuit 2335 generates a divided signal Sdiv2 with a low level. TFF circuit 2332 generates a signal with a low level from terminal Q, and buffer circuit 2336 generates a divided signal Sdiv3 with a low level. TFF circuit 2333 generates a signal with a high level from terminal Q, and buffer circuit 2337 generates a divided signal Sdiv4 with a high level. In this way, the divided circuit 233 generates divided signals Sdiv1 to Sdiv4 with predetermined levels based on the oscillation of the clock signal Scl.

[0046] In Embodiment 1, the frequency divide signal Sdiv is a signal that can be represented by 4 bits. In Figure 4, the frequency divide signal Sdiv is represented by 1 when each of the frequency divide signals Sdiv1 to Sdiv4 has a high level, and by 0 when each of the frequency divide signals Sdiv1 to Sdiv4 has a low level. At time t11, the frequency divide signal Sdiv1 has a high level, and the other signals have low levels. Therefore, the frequency divide signal Sdiv is represented by "0001", indicating that 0.25 ms has elapsed. At time t12, the frequency divide signal Sdiv2 has a high level, and the other signals have low levels. Therefore, the frequency divide signal Sdiv is represented by "0010", indicating that 0.5 ms has elapsed. If the frequency divider signals Sdiv1 and Sdiv2 are at a high level and the other signals are at a low level, the frequency divider signal Sdiv is represented as "0011", indicating that 0.75 ms has elapsed. In this way, the frequency divider signal Sdiv can indicate a predetermined elapsed time since the occurrence of a protection delay time measurement request Spdm or a charge control transition time measurement request Sctm, which are at a high level, based on the frequency divider signals Sdiv1 to Sdiv4, which are at a high level.

[0047] The time setting circuit 234 shown in Figure 2 generates high-level time-elapsed signals Socdp, Ssdp, and Sctp by timing a predetermined period based on the frequency division signal Sdiv. The time setting circuit 234 is configured so that a predetermined period for each time-elapsed signal can be arbitrarily set by a circuit signal switching device such as a laser trimmer. For example, the time setting circuit 234 may be configured to include multiple trimming fuses. By cutting all but one of these fuses with a laser trimmer, the time setting circuit 234 can generate and output a predetermined signal when an arbitrarily set period has elapsed. The time setting circuit 234 is not limited to this configuration, and for example, the predetermined period may be set by switching the connections of metal wiring in the manufacturing process of the time setting circuit 234.

[0048] Figure 5 is a schematic diagram showing an example of a time setting method for the time setting circuit 234 according to Embodiment 1. Figure 5 shows a first setting circuit 234A, which is a part of the time setting circuit 234. The first setting circuit 234A is a circuit for measuring the delay time T3 related to the short-circuit delay time elapsed signal Ssdp. The first setting circuit 234A comprises terminals Td1 to Td3, a plurality of fuses 2341 to 2343, and an AND circuit 2344. Fuse 2341 has one end connected to terminal Td1 and the other end connected to terminal Td3. Fuse 2342 has one end connected to terminal Td2 and the other end connected to terminal Td3. Fuse 2343 has one end connected to the output terminal of the AND circuit 2344 and the other end connected to terminal Td3. The AND circuit 2344 has a first input terminal connected to terminal Td1, a second input terminal connected to terminal Td2, and an output terminal that generates a signal having a predetermined level based on the input signal.

[0049] A frequency divider signal Sdiv1 is input to terminal Td1. A frequency divider signal Sdiv2 is input to terminal Td2. Terminal Td3 generates a short-circuit delay time elapsed signal Ssdp with a predetermined level. The AND circuit 2344 generates a signal with the level of the logical AND of frequency divider signals Sdiv1 and Sdiv2 and outputs it to fuse 2343.

[0050] In the first setting circuit 234A, two of the three fuses 2341 to 2343 are blown by the laser trimming device 50. The first setting circuit 234A generates a short-circuit delay time elapsed signal Ssdp from the frequency divider signal Sdiv input to the remaining fuse. For example, when fuses 2342 and 2343 are blown, the delay time T3 is set to the period from when a protection delay time measurement request Spdm or a charge control transition time measurement request Sctm with a high level is input until the frequency divider signal Sdiv1 with a high level is generated, i.e., 0.25 ms. The first setting circuit 234A generates a short-circuit delay time elapsed signal Ssdp with a high level 0.25 ms after the protection delay time measurement request Spdm or a charge control transition time measurement request Sctm with a high level is input. For example, when fuses 2341 and 2343 are blown, the delay time T3 is set to 0.5 ms. For example, when fuses 2341 and 2342 are blown, the delay time T3 is set to 0.75 ms. In this way, the time setting circuit 234 can generate a signal with a high level for each elapsed time signal after a predetermined period of time from the input of the protection delay time measurement request Spdm or the charge control transition time measurement request Sctm.

[0051] The time setting circuit 234 further includes a second setting circuit for the overcharge delay time elapsed signal Socdp and a third setting circuit for the charge control transition time elapsed signal Sctp. The second and third setting circuits may each have a different configuration from the first setting circuit 234A. For example, the second setting circuit may include six fuses and three AND circuits and be configured to measure the delay time T1 based on the frequency divider signals Sdiv1 to Sdiv3. Similarly, the third setting circuit may be configured to measure a predetermined period T2 using multiple fuses and multiple AND circuits. Thus, the time setting circuit 234 includes multiple circuits for measuring predetermined periods, and each of the multiple predetermined periods can be measured using each circuit. Therefore, the delay time T1, the predetermined period T2, and the delay time T3 can even be measured by the same time measurement circuit 23 that generates different overcharge delay time elapsed signals Socdp, charge control transition time elapsed signal Sctp, and short-circuit delay time elapsed signal Ssdp.

[0052] The AND gate 24 shown in Figure 1 generates an overcharge delay time measurement stop request Socms, which has a logical AND level between the protection delay time measurement request Spdm and the overcharge delay time elapsed signal Socdp, and outputs it to the control circuit 20. Specifically, the AND gate 24 generates an overcharge delay time measurement stop request Socms with a high level when it receives a protection delay time measurement request Spdm with a high level and an overcharge delay time elapsed signal Socdp with a high level. Otherwise, the AND gate 24 generates an overcharge delay time measurement stop request Socms with a low level. The control circuit 20 may be configured to operate based on the protection delay time measurement request Spdm and the overcharge delay time elapsed signal Socdp, without going through the AND gate 24. Other AND gates may be configured similarly.

[0053] The AND circuit 25 generates a short-circuit delay time measurement stop request Ssms, which has a logical AND level of the protection delay time measurement request Spdm and the short-circuit delay time elapsed signal Ssdp, and outputs it to the control circuit 20. Specifically, the AND circuit 25 generates a short-circuit delay time measurement stop request Ssms with a high level when it receives a protection delay time measurement request Spdm with a high level and a short-circuit delay time elapsed signal Ssdp with a high level. Otherwise, the AND circuit 25 generates a short-circuit delay time measurement stop request Ssms with a low level. The control circuit 20 may be configured to receive the protection delay time measurement request Spdm and the short-circuit delay time elapsed signal Ssdp without going through the AND circuit 25 and operate based on those signals.

[0054] The state transition detection circuit 26 detects state transitions of the charge control transistor 13 based on the charge control signal Scc. For example, the state transition detection circuit 26 can detect when the charge control transistor 13 transitions from the off state to the on state based on a high-level charge control signal Scc. The state transition detection circuit 26 can also detect when the charge control transistor 13 transitions from the on state to the off state based on a low-level charge control signal Scc.

[0055] The state transition detection circuit 26 generates a charge control transition time measurement request Sctm based on the charge control signal Scc and outputs it to the control circuit 20 and the time measurement circuit 23. The state transition detection circuit 26 generates a high-level charge control transition time measurement request Sctm based on a change in the level of the charge control signal Scc. After a predetermined period T2 following the generation of the high-level charge control transition time measurement request Sctm, the state transition detection circuit 26 generates a low-level charge control transition time measurement request Sctm. Specifically, after the generation of the high-level charge control transition time measurement request Sctm, the state transition detection circuit 26 generates a low-level charge control transition time measurement request Sctm upon receiving a high-level charge control transition time elapsed signal Sctp. The predetermined period T2 may be, for example, 1 ms. The predetermined period T2 is an example of the first period and the sixth period.

[0056] The charge control transition time measurement request (Sctm) is an example of a first timing request signal. The state transition detection circuit 26 generating a charge control transition time measurement request (Sctm) with a high level is an example of the state transition detection circuit 26 generating a first timing request signal. The state transition detection circuit 26 generating a charge control transition time measurement request (Sctm) with a low level is an example of the state transition detection circuit 26 stopping the generation of the first timing request signal.

[0057] Figure 6 is a schematic diagram of the state transition detection circuit 26 according to Embodiment 1. The state transition detection circuit 26 comprises flip-flop (FF) circuits 261 and 262 and an OR circuit 263. FF circuits 261 and 262 each generate signals based on the charging control signal Scc and the charging control transition time elapsed signal Sctp, and output them to the OR circuit 263.

[0058] FF circuit 261 includes a terminal CLK to which a charging control signal Scc is input, a terminal R to which a charging control transition time elapsed signal Sctp is input, and a terminal Q that generates a signal having a predetermined level based on the input signal. FF circuit 262 includes a terminal CLK to which the inverted value of the charging control signal Scc is input, a terminal R to which a charging control transition time elapsed signal Sctp is input, and a terminal Q that generates a signal having a predetermined level based on the input signal. When the charging control signal Scc changes from a low level to a high level, FF circuit 261 latches and generates a signal having a high level from terminal Q. When the charging control signal Scc changes from a high level to a low level, FF circuit 262 latches and generates a signal having a high level from terminal Q. When FF circuit 261 and FF circuit 262 receive the charging control transition time elapsed signal Sctp having a high level, they release the latch and generate a signal having a low level from terminal Q.

[0059] The OR circuit 263 generates a charge control transition time measurement request Sctm having a level of logical OR of the signal from FF circuit 261 and the signal from FF circuit 262. In other words, the OR circuit 263 generates a charge control transition time measurement request Sctm with a high level if at least one of the signals from FF circuit 261 and the signals from FF circuit 262 has a high level. The OR circuit 263 generates a charge control transition time measurement request Sctm with a low level if both the signals from FF circuit 261 and the signals from FF circuit 262 have a low level.

[0060] The discharge control driver 27 shown in Figure 1 is configured to receive the negative electrode power supply voltage VSS and the discharge control signal Sdc from the control circuit 20. The discharge control driver 27 generates a discharge control voltage DO and outputs it to the gate of the discharge control transistor 12. The discharge control driver 27 controls the discharge control voltage DO based on the discharge control signal Sdc to switch the discharge control transistor 12 on and off. For example, when the discharge control driver 27 receives a high-level discharge control signal Sdc, it generates a high-level discharge control voltage DO to turn on the discharge control transistor 12. When the discharge control driver 27 receives a low-level discharge control signal Sdc, it generates a low-level discharge control voltage DO to turn off the discharge control transistor 12.

[0061] The charge control driver 28 is configured to receive an external negative voltage VM and a charge control signal Scc from the control circuit 20. The charge control driver 28 generates a charge control voltage CO and outputs it to the gate of the charge control transistor 13. The charge control driver 28 controls the charge control voltage CO based on the charge control signal Scc to switch the charge control transistor 13 on and off. For example, when the charge control driver 28 receives a high-level charge control signal Scc, it generates a charge control voltage CO with a high level to turn on the charge control transistor 13. When the charge control driver 28 receives a low-level charge control signal Scc, it generates a charge control voltage CO with a low level to turn off the charge control transistor 13.

[0062] Figure 7 is a schematic diagram of a discharge control driver 27 and a charge control driver 28 according to Embodiment 1. The discharge control driver 27 comprises a P-type MOS transistor 271, an N-type MOS transistor 272, and an inverter 273. A positive power supply voltage VDD is applied to the source of the P-type MOS transistor 271. The gate of the P-type MOS transistor 271 is connected to the gate of the N-type MOS transistor 272. The drain of the P-type MOS transistor 271 is connected to the drain of the N-type MOS transistor 272. The source of the N-type MOS transistor 272 is connected to a negative power supply terminal T12 having a negative power supply voltage VSS. The connection point between the drain of the P-type MOS transistor 271 and the drain of the N-type MOS transistor 272 is connected to the gate of the discharge control transistor 12. The input terminal of the inverter 273 receives a discharge control signal Sdc. The output terminal of the inverter 273 is connected to the connection point between the gate of the P-type MOS transistor 271 and the gate of the N-type MOS transistor 272.

[0063] The inverter 273 generates a signal with a level that is the inverted level of the received discharge control signal Sdc and outputs it to the gates of the P-type MOS transistor 271 and the N-type MOS transistor 272. When a high-level discharge control signal Sdc is input to the discharge control driver 27, the P-type MOS transistor 271 is turned on. As a result, the discharge control driver 27 generates a high-level discharge control voltage DO based on the positive power supply voltage VDD and turns on the discharge control transistor 12. When a low-level discharge control signal Sdc is input to the discharge control driver 27, the N-type MOS transistor 272 is turned on. As a result, the discharge control driver 27 generates a low-level discharge control voltage DO based on the negative power supply voltage VSS and turns off the discharge control transistor 12.

[0064] The charge control driver 28 comprises a P-type MOS transistor 281, an N-type MOS transistor 282, and an inverter 283. A positive power supply voltage VDD is applied to the source of the P-type MOS transistor 281. The gate of the P-type MOS transistor 281 is connected to the gate of the N-type MOS transistor 282. The drain of the P-type MOS transistor 281 is connected to the drain of the N-type MOS transistor 282. The source of the N-type MOS transistor 282 is connected to an external negative voltage input terminal T15 having an external negative voltage VM. The connection point between the drain of the P-type MOS transistor 281 and the drain of the N-type MOS transistor 282 is connected to the gate of the charge control transistor 13. The input terminal of the inverter 283 receives a charge control signal Scc. The output terminal of the inverter 283 is connected to the connection point between the gate of the P-type MOS transistor 281 and the gate of the N-type MOS transistor 282.

[0065] The inverter 283 generates a signal with a level that is the inverted level of the received charge control signal Scc and outputs it to the gates of the P-type MOS transistor 281 and the N-type MOS transistor 282. When a high-level charge control signal Scc is input to the charge control driver 28, the P-type MOS transistor 281 is turned on. As a result, the charge control driver 28 generates a high-level charge control voltage CO based on the positive electrode power supply voltage VDD and turns on the charge control transistor 13. When a low-level charge control signal Scc is input to the charge control driver 28, the N-type MOS transistor 282 is turned on. As a result, the charge control driver 28 generates a low-level charge control voltage CO based on the external negative electrode voltage VM and turns off the charge control transistor 13.

[0066] When a low-level charge control voltage CO is generated, the charge control transistor 13 is turned off by the extraction of the charge stored in its gate. For example, this charge moves to the source of the charge control transistor 13 via the N-type MOS transistor 282, resistor 14, and resistor 15, causing a current Ig to flow. As a result, a predetermined potential difference based on this current Ig is generated across resistor 14, causing the external negative electrode voltage VM to rise above the current detection voltage CS.

[0067] It takes a predetermined period Toff to extract the charge stored in the gate of the charge control transistor 13. The predetermined period Toff may be the time required to extract most of the charge. For example, if the gate capacitance of the charge control transistor 13 is 10 nF and the resistance of the current path is 10 kΩ, the time constant is, for example, 100 μs. In this case, the predetermined period Toff is, for example, about 300 μs.

[0068] If an abnormal condition caused by an increase in the external negative electrode voltage VM due to current Ig is detected between the generation of a low-level charge control signal Scc and the elapsed of a predetermined period Toff, the predetermined abnormal condition may be falsely detected. In recent years, in order to suppress heat generation during charging and discharging, it has been required to lower the on-resistance of the discharge control transistor 12 and the charge control transistor 13 and the resistance of the shunt resistor 15. Increasing the element size of each transistor 12 and 13 to lower the on-resistance increases the gate capacitance, so the predetermined period Toff becomes longer compared to transistors with smaller element sizes. Therefore, the period during which malfunctions occur due to false detection may become longer. Also, if the resistance value of the shunt resistor 15 is reduced, the potential difference across the shunt resistor 15 due to current becomes smaller, so it is necessary to detect the short-circuit current or charge / discharge overcurrent at a smaller voltage. Therefore, false detection may occur for a longer period compared to circuits with a large shunt resistor value.

[0069] The charge / discharge control circuit 10 according to this disclosure is configured not to accept abnormality detection signals for a predetermined period following a change in the charge control signal Scc, in order to prevent malfunctions caused by false detection of a predetermined abnormal state resulting from a change in the charge control signal Scc. With this configuration, even if a predetermined abnormal state caused by a change in the charge control signal Scc is falsely detected, the charge control signal Scc will not be controlled based on the false detection. Therefore, it is possible to prevent malfunctions caused by such false detections.

[0070] The charge / discharge control circuit 10 according to Embodiment 1 has a plurality of operating modes that hold at least one of the discharge control transistor 12 and the charge control transistor 13 in a predetermined state. The predetermined state includes an on state and an off state. The plurality of operating modes include a normal mode, an overcharge protection mode, a short-circuit protection mode, and a charge control transition mode. The charge / discharge control circuit 10 is configured to operate in one of the plurality of operating modes. When a charge prohibition abnormal state or a discharge prohibition abnormal state is detected, the charge / discharge control circuit 10 operates in a predetermined protection mode. The protection modes include an overcharge protection mode and a short-circuit protection mode. When the charge / discharge control circuit 10 is detected to have resolved the charge prohibition abnormal state or the discharge prohibition abnormal state, it may be configured to operate, for example, in a normal mode. While operating in some protection modes, the charge / discharge control circuit 10 may be configured to transition from a predetermined protection mode to a normal mode based on a signal from a circuit different from the abnormality detection circuit, rather than on the resolution of the charge prohibition abnormal state or the discharge prohibition abnormal state. For example, the charge / discharge control circuit 10 is configured to transition from short-circuit protection mode to normal mode when it receives a charger connection detection signal Scrd having a high level from the charger connection detection circuit 29 while operating in short-circuit protection mode. For example, when the control circuit 20 receives a charger connection detection signal Scrd having a high level while operating in short-circuit protection mode, it generates a protection delay time measurement request Spdm having a high level. The protection delay time measurement request Spdm from the control circuit 20 may also be output to the time measurement circuit 23, AND circuits 24, 25, and an AND circuit not shown. When the control circuit 20 receives a predetermined delay time measurement stop request having a high level from the AND circuit, the charge / discharge control circuit 10 switches from short-circuit protection mode to normal mode. The AND circuit generates the predetermined delay time measurement stop request as, for example, the logical AND of the protection delay time measurement request Spdm and a predetermined delay time elapsed signal from the time measurement signal 23. The time measurement signal 23 may be configured to generate a predetermined delay time elapsed signal having a high level after a predetermined delay time has elapsed, for example, from the occurrence of a protection delay time measurement request Spdm having a high level.Thus, the charge / discharge control circuit 10 may be configured such that the transition from normal mode to a predetermined protection mode and the transition from the predetermined protection mode to normal mode occur based on signals from different detection circuits. The charge / discharge control circuit 10 operates in a predetermined transition mode when the level of the charge control signal Scc changes. The transition modes include charge control transition modes.

[0071] The normal mode is an operating mode that is executed, for example, when the conditions for transitioning to a predetermined protection mode are not met. In the normal mode, the charge / discharge control circuit 10 operates to keep the discharge control transistor 12 and the charge control transistor 13 in the ON state. Therefore, in the normal mode, the control circuit 20 generates a discharge control signal Sdc and a charge control signal Scc, both of which are high levels.

[0072] The overcharge protection mode is an operating mode that is executed when overcharging of the secondary battery 11 is detected. When the overcharge detection circuit 21 detects a predetermined charging prohibition abnormal state based on the positive electrode power supply voltage VDD and the negative electrode power supply voltage VSS, the charge / discharge control circuit 10 transitions, for example, from normal mode to overcharge protection mode. In overcharge protection mode, the charge / discharge control circuit 10 operates to keep the discharge control transistor 12 in the ON state and to keep the charge control transistor 13 in the OFF state in order to prohibit charging. Therefore, in overcharge protection mode, the control circuit 20 generates a discharge control signal Sdc with a high level and a charge control signal Scc with a low level.

[0073] The short-circuit protection mode is an operating mode that is executed when an overcurrent is detected in the discharge path of the secondary battery 11. The discharge path may be a closed circuit, for example, where current flows from the positive electrode of the secondary battery 11 through the load 2 to the negative electrode of the secondary battery 11. When the short-circuit detection circuit 22 detects a discharge prohibition abnormal condition based on the external negative electrode voltage VM and the current detection voltage CS, the charge / discharge control circuit 10 transitions, for example, from the normal mode to the discharge protection mode. In the discharge protection mode, the charge / discharge control circuit 10 operates to keep the discharge control transistor 12 in the off state and the charge control transistor 13 in the on state in order to prohibit discharge. Therefore, in the short-circuit protection mode, the control circuit 20 generates a discharge control signal Sdc with a low level and a charge control signal Scc with a high level.

[0074] The charge control transition mode is an operating mode that is executed when the level of the charge control signal Scc generated by the control circuit 20 changes. In the charge control transition mode, the charge / discharge control circuit 10 operates to maintain the levels of the discharge control signal Sdc and the charge control signal Scc when transitioning from any operating mode to the charge control transition mode. For example, the charge / discharge control circuit 10 transitions from the normal mode to the charge control transition mode when the discharge control signal Sdc is at a high level and the charge control signal Scc changes from a high level to a low level. When the charge / discharge control circuit 10 is operating in the charge control transition mode, it operates to maintain the discharge control signal Sdc at a high level and the charge control signal Scc at a low level, even if an abnormal detection signal with a high level is generated. After a predetermined period, such as a predetermined period T2, has elapsed since operating in the charge control transition mode, the charge / discharge control circuit 10 transitions from the charge control transition mode to another operating mode.

[0075] Next, the operation of the charge / discharge control circuit 10 according to Embodiment 1 will be described. Figure 8 is a flowchart showing an example of the operation of the charge / discharge control circuit 10 according to Embodiment 1.

[0076] The charge / discharge control circuit 10 first operates in normal mode, and the control circuit 20 generates a high-level charge control signal Scc. The charge / discharge control circuit 10 determines whether or not a high-level overcharge detection signal Socd has been input (S10) via the control circuit 20. If the charge / discharge control circuit 10 has not received a high-level overcharge detection signal Socd (S10: No), it executes step S10 again.

[0077] When an overcharge detection signal Socd having a high level is input to the charge / discharge control circuit 10 (S10: Yes), the control circuit 20 determines whether a predetermined delay time T1 has elapsed since the input of the overcharge detection signal Socd having a high level (S11). The control circuit 20 can determine whether a predetermined delay time T1 has elapsed based, for example, on the overcharge delay time elapsed signal Socdp from the time measurement circuit 23.

[0078] If the charge / discharge control circuit 10 has not received a high-level overcharge detection signal Socd for a predetermined delay time T1 (S11: No), it executes step S10 again. If the predetermined delay time T1 has elapsed (S11: Yes), the charge / discharge control circuit 10 transitions, for example, from normal mode to overcharge protection mode (S12). By operating in this manner, the charge / discharge control circuit 10 can determine whether a predetermined delay time T1 has elapsed since the input of the high-level overcharge detection signal Socd. When the charge / discharge control circuit 10 transitions to overcharge protection mode, the control circuit 20 generates a low-level charge control signal Scc, which turns off the charge control transistor 13 via the charge control driver 28.

[0079] Next, the charge / discharge control circuit 10 generates a low-level charge control signal Scc via the control circuit 20 (S13). When the level of the charge control signal Scc changes, the charge / discharge control circuit 10 generates a high-level charge control transition time measurement request Sctm via the state transition detection circuit 26 (S14). As a result, the charge / discharge control circuit 10 transitions from the overcharge protection mode to the charge control transition mode (S15). The charge / discharge control circuit 10 maintains the state of each transistor 12 and 13 in the overcharge protection mode. That is, the charge / discharge control circuit 10 keeps the discharge control transistor 12 in the ON state and keeps the charge control transistor 13 in the OFF state.

[0080] The charge / discharge control circuit 10 determines whether the charge control transition time measurement request (Sctm) has stopped, as determined by the control circuit 20 (S16). The charge / discharge control circuit 10 may determine that the charge control transition time measurement request (Sctm) has stopped, for example, when the charge control transition time measurement request (Sctm) changes from a high level to a low level. If the charge control transition time measurement request (Sctm) has not stopped (S16: No), the charge / discharge control circuit 10 executes step S16 again. If the charge control transition time measurement request (Sctm) has stopped (S16: Yes), the charge / discharge control circuit 10 transitions from the charge control transition mode to the overcharge protection mode (S17). While operating in the charge control transition mode, the charge / discharge control circuit 10 does not accept abnormal detection signals such as short-circuit detection signals and does not transition to a predetermined protection mode based on such abnormal detection signals.

[0081] Then, for example, the charge / discharge control circuit 10 determines whether or not a short-circuit detection signal SSD having a high level has been input by the control circuit 20 (S18). If the charge / discharge control circuit 10 has not received a short-circuit detection signal SSD having a high level (S18: No), it executes step S18 again.

[0082] When a short-circuit detection signal SSD having a high level is input to the charge / discharge control circuit 10 (S18: Yes), the control circuit 20 determines whether a predetermined delay time T3 has elapsed since the input of the short-circuit detection signal SSD having a high level (S19). The control circuit 20 can determine whether a predetermined delay time T3 has elapsed based, for example, on the short-circuit delay time elapsed signal SSDp from the time measurement circuit 23.

[0083] If the charge / discharge control circuit 10 has not received a high-level short-circuit detection signal SSD, a predetermined delay time T3 has not elapsed (S19: No), it executes step S18 again. If the predetermined delay time T3 has elapsed (S19: Yes), the charge / discharge control circuit 10 transitions, for example, from overcharge protection mode to short-circuit protection mode (S20). By operating in this manner, the charge / discharge control circuit 10 can determine whether a predetermined delay time T3 has elapsed since the input of the short-circuit detection signal SSD. When the charge / discharge control circuit 10 transitions to short-circuit protection mode, the control circuit 20 generates a low-level discharge control signal Sdc, which turns off the discharge control transistor 12 via the discharge control driver 27. In this way, after transitioning from the charge control transition mode to another mode, the charge / discharge control circuit 10 can receive an abnormality detection signal, such as a short-circuit detection signal, and transition to a predetermined protection mode after a predetermined delay time based on the abnormality detection signal has elapsed.

[0084] Figure 9 is a timing chart showing an example of the operation of the charge / discharge control circuit 10 according to Embodiment 1. The example shown in Figure 9 is a timing chart relating to the overcharge protection mode. The horizontal axis of Figure 9 represents time. The vertical axes of Figure 9 represent the level of the overcharge detection signal Socd, the level of the protection delay time measurement request Spdm, the level of the overcharge delay time elapsed signal Socdp, the state of the overcharge protection mode, the level of the charge control signal Scc, the level of the charge control transition time measurement request Sctm, the level of the charge control transition time elapsed signal Sctp, the charge control voltage CO, the external negative electrode voltage VM, the level of the short-circuit detection signal Ssd, the state of the short-circuit protection mode, and the state of the time measurement circuit 23. In Figure 9 and Figures 10 and 14 described later, the waveforms of predetermined protection modes such as the overcharge protection mode are shown as ON when the conditions for operating in the protection mode are met, and as OFF when the conditions for canceling operation in the protection mode are met.

[0085] In the timing chart shown in Figure 9, the charge / discharge control circuit 10 operates in normal mode before time point t1. At time point t1, when the overcharge detection circuit 21 generates an overcharge detection signal Socd with a high level, the control circuit 20 generates a protection delay time measurement request Spdm with a high level. When the time measurement circuit 23 receives the protection delay time measurement request Spdm with a high level, at time point t2, a predetermined delay time T1 related to overcharge protection from the generation of the protection delay time measurement request Spdm with a high level, it generates an overcharge delay time elapsed signal Socdp with a high level. When the control circuit 20 receives an overcharge delay time measurement stop request Socms with a high level from the AND circuit 24, it generates a protection delay time measurement request Spdm with a low level. The charge / discharge control circuit 10 also transitions from normal mode to overcharge protection mode.

[0086] In overcharge protection mode, the control circuit 20 generates a low-level charge control signal Scc to turn off the charge control transistor 13. The state transition detection circuit 26 latches in response to the change in the charge control signal Scc from high to low level and generates a high-level charge control transition time measurement request Sctm. Based on the generation of the high-level charge control transition time measurement request Sctm, the charge / discharge control circuit 10 transitions from overcharge protection mode to charge control transition mode. Also, when the charge control driver 28 receives a low-level charge control signal Scc, it reduces the charge control voltage CO to, for example, the external negative electrode voltage VM to turn off the charge control transistor 13. The charge control voltage CO corresponds to the gate voltage of the charge control transistor 13. When the gate voltage is reduced, as shown in Figure 7, the external negative electrode voltage VM rises due to the current based on the release of charge stored in the gate of the charge control transistor 13.

[0087] When the voltage difference between the external negative electrode voltage VM and the current detection voltage CS exceeds a predetermined threshold voltage, the short-circuit detection circuit 22 generates a high-level short-circuit detection signal Ssd at time t3, after a predetermined time, due to a false detection of a discharge prohibition abnormal state. However, because the charge / discharge control circuit 10 is operating in charge control transition mode, the control circuit 20 does not accept the high-level short-circuit detection signal Ssd. For example, even if the control circuit 20 receives a high-level short-circuit detection signal Ssd, it does not generate a high-level protection delay time measurement request Spdm. Thus, even if the short-circuit detection circuit 22 generates a high-level short-circuit detection signal Ssd due to a false detection, the control circuit 20 does not accept the high-level short-circuit detection signal Ssd, and therefore does not generate a high-level protection delay time measurement request Spdm. The control circuit 20 prohibits the generation of a high-level protection delay time measurement request Spdm until a predetermined period T2 has elapsed from the generation of a high-level charge control transition time measurement request Sctm. As a result, when a charge control transition time measurement request Sctm with a high level is generated, the control circuit 20 maintains the level of the charge control signal Scc at the level at the time the charge control transition time measurement request Sctm with a high level was generated.

[0088] From time t3 onward, the charge control voltage CO gradually decreases due to charge release. At time t4, after a predetermined period Toff from time t3, when the charge control voltage CO falls below the threshold voltage Vthc of the charge control transistor 13, the charge control transistor 13 turns off. With the charge control transistor 13 turned off, the external negative electrode voltage VM is pulled down by the charger voltage of the charger connected as load 2. As a result, the short-circuit detection circuit 22 generates a short-circuit detection signal Ssd with a low level. Thus, even if a false detection of a short circuit occurs during the charge control transition mode, the charge / discharge control circuit 10 does not transition to short-circuit protection mode.

[0089] Furthermore, when the time measurement circuit 23 receives a charge control transition time measurement request Sctm with a high level at time t2, it generates a charge control transition time elapsed signal Sctp with a high level at time t5, a predetermined period T2 after the generation of the charge control transition time measurement request Sctm. When the state transition detection circuit 26 receives the charge control transition time elapsed signal Sctp with a high level, it releases its latch and generates a charge control transition time measurement request Sctm with a low level. As a result, the charge / discharge control circuit 10 transitions from the charge control transition mode to the overcharge protection mode. Therefore, the control circuit 20 receives protection detection signals such as the short-circuit detection signal Ssd from time t5 onward. In other words, the control circuit 20 releases the prohibition on the generation of a protection delay time measurement request Spdm with a high level.

[0090] As shown in Figure 9, the time measurement circuit 23 stops timing before time t1. At time t1, the time measurement circuit 23 measures the delay time T1 related to overcharging until time t2. At time t2, the time measurement circuit 23 resets the timing state and measures a predetermined period T2 related to charging until time t5. The time measurement circuit 23 stops timing from time t5 onward.

[0091] Thus, even if a short circuit is falsely detected when the charge control transistor 13 is turned off due to the detection of an abnormal condition related to overcharging, the charge / discharge control circuit 10 can turn off the charge control transistor 13 without transitioning to short-circuit protection mode. Therefore, the charge / discharge control circuit 10 can appropriately turn off the charge control transistor 13 when overcharging occurs and protect the battery device 1.

[0092] Figure 10 is a timing chart showing an example of the operation of a charge / discharge control circuit according to a comparative example. Compared to the charge / discharge control circuit 10 according to Embodiment 1, this charge / discharge control circuit does not include a state transition detection circuit 26 and AND circuits 24-25. The example shown in Figure 10 shows a timing chart related to the overcharge protection mode. The horizontal axis of Figure 10 represents time. The vertical axes of Figure 10 represent the level of the overcharge detection signal Socd, the level of the overcharge delay time elapsed signal Socdp, the state of the overcharge protection mode, the level of the charge control signal Scc, the level of the discharge control signal Sdc, the charge control voltage CO, the external negative electrode voltage VM, the level of the short-circuit detection signal Ssd, the level of the protection delay time measurement request Spdm, the level of the short-circuit delay time elapsed signal Ssdp, the state of the short-circuit protection mode, and the state of the time measurement circuit 23.

[0093] Between time points t1 and t2, the charge / discharge control circuit of the comparative example operates in the same manner as the charge / discharge control circuit 10. At time point t2, if the voltage difference between the external negative electrode voltage VM and the current detection voltage CS exceeds a predetermined threshold voltage, the short-circuit detection circuit generates a high-level short-circuit detection signal Ssd at time point t3, after a predetermined time, due to a false detection of an abnormal discharge prohibition state. When the control circuit of the comparative example receives the high-level short-circuit detection signal Ssd, it generates a high-level protection delay time measurement request Spdm.

[0094] In this comparative example, the predetermined period Toff is longer than the predetermined short-circuit protection delay time T3. When the time measurement circuit receives a protection delay time measurement request Spdm with a high level, it generates a short-circuit delay time elapsed signal Ssdp with a high level from time t3 to time t6, which is after the delay time T3. Based on the generation of the short-circuit delay time elapsed signal Ssdp with a high level, the control circuit generates a protection delay time measurement request Spdm with a low level. In addition, the charge / discharge control circuit transitions from overcharge protection mode to short-circuit protection mode.

[0095] Therefore, the control circuit generates a high-level charge control signal Scc and a low-level discharge control signal Sdc. Since the charge control signal Scc changes to a high level before the predetermined period Toff has elapsed, the charge control transistor 13 remains in the ON state. Thus, even if the charge / discharge control circuit of the comparative example detects an abnormality related to overcharging, it may not be able to switch from the overcharge protection mode to the short-circuit protection mode and turn off the charge control transistor 13. Consequently, the charge / discharge control circuit of the comparative example may not be able to properly protect the secondary battery because, due to unintended mode transitions, it may allow charging and prohibit discharge even when charging should be prohibited.

[0096] The charge / discharge control circuit 10 according to this disclosure, upon detecting a change in the level of the charge control signal Scc, does not transition from the protection mode at the time of the change to another protection mode for a predetermined period T2 from the time of the detection. Therefore, the control circuit 20 does not accept abnormal detection signals such as the short-circuit detection signal SSD. For example, even if a short-circuit detection signal SSD with a high level occurs, it does not request measurement of the delay time T3 to transition to the short-circuit detection mode. Therefore, the charge / discharge control circuit 10 according to this disclosure can prevent unintended mode transitions due to a transient rise in the external negative electrode voltage VM caused by the turning off of the charge control transistor 13. Accordingly, the charge / discharge control circuit 10 according to this disclosure can protect the battery device 1 by preventing malfunction of the charge / discharge control circuit 10 caused by an increase in the external negative electrode voltage VM.

[0097] (Embodiment 2) Referring to Figure 11, an overview of the battery device 1a according to Embodiment 2 of this disclosure will be described. Figure 11 is a schematic diagram of the battery device 1a according to Embodiment 2 of this disclosure. The battery device 1a includes a charge / discharge control circuit 10a instead of the charge / discharge control circuit 10 in Embodiment 1. The charge / discharge control circuit 10a includes a control circuit 20a, an over-discharge detection circuit 30, a short-circuit detection circuit 22a, a time measurement circuit 23a, and a state transition detection circuit 26a instead of the control circuit 20, an overcharge detection circuit 21, a short-circuit detection circuit 22, a time measurement circuit 23, and a state transition detection circuit 26. Furthermore, the charge / discharge control circuit 10a includes AND circuits 31 and 32 instead of the AND circuit 24.

[0098] The charge / discharge control circuit 10a has one or more protection modes that control the discharge control transistor 12 or the charge control transistor 13 to a predetermined state based on an abnormality detection signal from an abnormality detection circuit such as the over-discharge detection circuit 30 or the short-circuit detection circuit 22a.

[0099] For example, the charge / discharge control circuit 10a transitions from, for example, normal mode to over-discharge protection mode after a predetermined delay time based on the over-discharge detection signal Sodd which has a high level. The control circuit 20a generates a discharge control signal Sdc which has a low level based on the over-discharge detection signal Sodd which has a high level from the over-discharge detection circuit 30 and outputs it to the discharge control driver 27 and the state transition detection circuit 26a. The discharge control driver 27 turns off the discharge control transistor 12 based on the discharge control signal Sdc which has a low level. The control circuit 20a then controls the discharge control signal Sdc so that the discharge control transistor 12 remains off during over-discharge protection mode. The charge / discharge control circuit 10a transitions from, for example, normal mode after a predetermined delay time T4 based on the over-discharge detection signal Sodd which has a low level. The control circuit 20a generates a high-level discharge control signal Sdc based on a low-level over-discharge detection signal Sodd from the over-discharge detection circuit 30, turning on the discharge control transistor 12 via the discharge control driver 27, and controls the discharge control signal Sdc to keep the discharge control transistor 12 turned on during normal mode. The delay time when transitioning to the over-discharge protection mode may be the same as the delay time T4 when returning from the over-discharge protection mode, or they may be different. The delay time when transitioning to the protection mode for a discharge prohibition abnormal condition is an example of the fourth period. The delay time when returning from the protection mode for a discharge prohibition abnormal condition, such as the delay time T4, is an example of the fifth period.

[0100] When control circuit 20a receives an abnormality detection signal with a high level, it generates a protection delay time measurement request Spdm with a high level and outputs it to time measurement circuit 23a, AND circuit 25, AND circuit 31, and AND circuit 32. Similarly, when control circuit 20a receives a charger connection detection signal Scrd with a high level, it generates a protection delay time measurement request Spdm with a high level and outputs it to time measurement circuit 23a, AND circuit 25, AND circuit 31, and AND circuit 32. After a predetermined delay time from the generation of the above, control circuit 20a receives a delay time elapsed signal with a high level. Based on the delay time elapsed signal with a high level, the charge / discharge control circuit 10a switches, for example, from normal mode to a predetermined protection mode. The delay time elapsed signal includes, for example, a short-circuit delay time elapsed signal Ssdp, an over-discharge detection delay time elapsed signal Sodddp and an over-discharge recovery delay time elapsed signal Sodrdp, which will be described later. For example, if a high-level over-discharge recovery delay time elapsed signal Sodrdp occurs while a high-level protection delay time measurement request Spdm is being generated based on the cessation of the generation of the over-discharge detection signal Sodd, the charge / discharge control circuit 10a switches from the over-discharge protection mode to the normal mode. For example, if a high-level over-discharge recovery delay time elapsed signal Sodrdp occurs while operating in the short-circuit protection mode, while a high-level protection delay time measurement request Spdm is being generated based on the generation of a high-level charger connection detection signal Scrd, the charge / discharge control circuit 10a switches from the short-circuit protection mode to the normal mode. The control circuit 20a generates a low-level protection delay time measurement request Spdm based on a high-level short-circuit delay time elapsed signal Ssdp, an over-discharge detection delay time elapsed signal Sodddp, or an over-discharge recovery delay time elapsed signal Sodrdp. In this embodiment, the charge / discharge control circuit 20a is configured to measure the delay time related to recovery from the short-circuit protection mode using the over-discharge recovery delay time elapsed signal Sodrdp, but the charge / discharge control circuit 20a is not limited to this configuration. For example, the charge / discharge control circuit 20a may further include an AND circuit that generates a logical AND of the protection delay time measurement request Spdm and the short-circuit recovery delay time elapsed signal from the time measurement circuit 23a and outputs it to the control circuit 20a.For example, by configuring the time measurement circuit 23a to generate a short-circuit recovery delay time elapsed signal having a high level after a delay time for recovery from short-circuit protection mode, the charge / discharge control circuit 20a may be configured such that the delay time T4 for recovery from over-discharge mode is different from the delay time for recovery from short-circuit protection mode.

[0101] When the control circuit 20a receives a control transition time measurement request Stm having a high level, as described later, based on a change in the discharge control signal Sdc, the charge / discharge control circuit 10a transitions from an arbitrary operating mode to a discharge control transition mode. In the discharge control transition mode, the control circuit 20a operates in such a way that it does not change the levels of the charge control signal Scc and the discharge control signal Sdc even when it receives an abnormality detection signal. When the control circuit 20a receives a control transition time measurement request Stm having a low level, the charge / discharge control circuit 10a transitions from the discharge control transition mode to an arbitrary operating mode. For example, the control circuit 20a releases the prohibition on the generation of a protection delay time measurement request Spdm having a high level.

[0102] The over-discharge detection circuit 30 receives the positive power supply voltage VDD and the negative power supply voltage VSS. Based on the voltage difference between the positive power supply voltage VDD and the negative power supply voltage VSS, the over-discharge detection circuit 30 generates an over-discharge detection signal Sodd and outputs it to the control circuit 20a. When the over-discharge detection circuit 30 detects that the voltage difference is less than a predetermined over-discharge detection voltage, it generates an over-discharge detection signal Sodd with a high level. When the over-discharge detection circuit 30 detects that the voltage difference is equal to or greater than the over-discharge recovery voltage, it generates an over-discharge detection signal Sodd with a low level. The over-discharge detection voltage may be, for example, 2.6V. The over-discharge recovery voltage may be, for example, 2.6V.

[0103] The over-discharge detection circuit 30 is an example of an abnormality detection circuit. The over-discharge detection signal Sodd is an example of an abnormality detection signal and a discharge abnormality detection signal. When the difference voltage between the positive electrode power supply voltage VDD and the negative electrode power supply voltage VSS is less than a predetermined over-discharge detection voltage, this is an example of a discharge prohibition abnormal state. When the difference voltage is greater than or equal to a predetermined over-discharge recovery voltage, this is an example of the discharge prohibition abnormal state being resolved. When the over-discharge detection circuit 30 generates an over-discharge detection signal Sodd with a high level, this is an example of the over-discharge detection circuit 30 generating an abnormality detection signal. When the over-discharge detection circuit 30 generates an over-discharge detection signal Sodd with a low level, this is an example of the over-discharge detection circuit 30 stopping the generation of an abnormality detection signal.

[0104] The short-circuit detection circuit 22a receives the external negative voltage VM and the negative power supply voltage VSS. Based on the voltage difference between the external negative voltage VM and the negative power supply voltage VSS, the short-circuit detection circuit 22a generates a short-circuit detection signal Ssd and outputs it to the control circuit 20a. When the short-circuit detection circuit 22a detects that the voltage difference is greater than or equal to a predetermined short-circuit detection voltage, it generates a short-circuit detection signal Ssd with a high level. When the short-circuit detection circuit 22a detects that the voltage difference is less than the short-circuit recovery voltage, it generates a short-circuit detection signal Ssd with a low level. The short-circuit detection voltage may be, for example, 1V.

[0105] The time measurement circuit 23a generates an over-discharge detection delay time elapsed signal Sodddp having a predetermined level and outputs it to the AND circuit 31. The time measurement circuit 23a generates an over-discharge recovery delay time elapsed signal Sodrdp having a predetermined level and outputs it to the AND circuit 32. The time measurement circuit 23a generates a charge control transition time elapsed signal Sctp or a discharge control transition time elapsed signal Sdtp having a predetermined level and outputs it to the state transition detection circuit 26a. Based on a protection delay time measurement request Spdm having a high level or a control transition time measurement request Stm described later, the time measurement circuit 23a measures a predetermined period and generates high-level time elapsed signals Ssdp, Sctp, Sdtp, Sodddp, and Sodrdp. Based on a protection delay time measurement request Spdm and a control transition time measurement request Stm having low levels, the time measurement circuit 23a generates low-level time elapsed signals Ssdp, Sctp, Sdtp, Sodddp, and Sodrdp. The time measurement circuit 23a resets the timing based on a protection delay time measurement request Spdm and a control transition time measurement request Stm, both of which have low levels.

[0106] Figure 12 is a schematic diagram of the time measurement circuit 23a according to Embodiment 2. The time measurement circuit 23a according to Embodiment 2 comprises an OR circuit 231a, an oscillator circuit 232, a frequency divider circuit 233, and a time setting circuit 234a.

[0107] The OAR circuit 231a generates an oscillation instruction signal Soi having a predetermined level based on the input protection delay time measurement request Spdm and control transition time measurement request Stm, and outputs it to the oscillation circuit 232 and frequency divider circuit 233. The OAR circuit 231a generates an oscillation instruction signal Soi having a high level if at least one of the protection delay time measurement request Spdm and control transition time measurement request Stm has a high level. The OAR circuit 231 generates an oscillation instruction signal Soi having a low level if both the protection delay time measurement request Spdm and control transition time measurement request Stm have low levels.

[0108] The time setting circuit 234a measures a predetermined delay time based on the frequency division signal Sdiv and generates high-level time-elapsed signals Ssdp, Sctp, Sdtp, Sodddp, and Sodrdp.

[0109] The AND circuit 31 shown in Figure 11 generates an over-discharge detection delay time measurement stop request Soddms, which has a logical AND level between the protection delay time measurement request Spdm and the over-discharge detection delay time elapsed signal Sodddp, and outputs it to the control circuit 20a.

[0110] The AND circuit 32 generates an over-discharge recovery delay time measurement stop request Sodrms, which has a logical AND level between the protection delay time measurement request Spdm and the over-discharge recovery delay time elapsed signal Sodrdp, and outputs it to the control circuit 20a.

[0111] The state transition detection circuit 26a generates a control transition time measurement request Stm based on the charge control signal Scc or the discharge control signal Sdc and outputs it to the control circuit 20a and the time measurement circuit 23a. When the level of the charge control signal Scc changes, the state transition detection circuit 26a generates a control transition time measurement request Stm with a high level. After a predetermined period T2 has elapsed, the state transition detection circuit 26a generates a control transition time measurement request Stm with a low level. Furthermore, when the level of the discharge control signal Sdc changes, the state transition detection circuit 26a generates a control transition time measurement request Stm with a high level. After a predetermined period T5 has elapsed, the state transition detection circuit 26a generates a control transition time measurement request Stm with a low level. Specifically, when the state transition detection circuit 26a receives a charge control transition time elapsed signal Sctp or a discharge control transition time elapsed signal Sdtp with a high level, it generates a control transition time measurement request Stm with a low level. The control transition time measurement request Stm is an example of a first timing request signal. The discharge control transition time elapsed signal Sdtp is an example of a first period elapsed signal. The predetermined period T5 may be the same as the predetermined period T2, or they may be different from each other. The predetermined period T5 is an example of the first period and the seventh period.

[0112] Figure 13 is a schematic diagram of a state transition detection circuit 26a according to Embodiment 2. The state transition detection circuit 26a further comprises FF circuits 264 and 265 and OR circuits 266 and 267 in addition to the state transition detection circuit 26. FF circuits 264 and 265 each generate signals based on the discharge control signal Sdc and the discharge control transition time elapsed signal Sdtp, and output them to the OR circuit 266. The OR circuit 267 generates a control transition time measurement request Stm based on the signals from the OR circuit 263 and the OR circuit 266.

[0113] FF circuit 264 includes a terminal CLK to which the discharge control signal Sdc is input, a terminal R to which the discharge control transition time elapsed signal Sdtp is input, and a terminal Q that generates a signal having a predetermined level based on the input signal. FF circuit 265 includes a terminal CLK to which the inverted value of the discharge control signal Sdc is input, a terminal R to which the discharge control transition time elapsed signal Sdtp is input, and a terminal Q that generates a signal having a predetermined level based on the input signal. FF circuit 264 operates similarly to FF circuit 261 based on the discharge control signal Sdc and the discharge control transition time elapsed signal Sdtp. FF circuit 265 operates similarly to FF circuit 262 based on the discharge control signal Sdc and the discharge control transition time elapsed signal Sdtp.

[0114] The OR circuit 266 generates a discharge control transition time measurement request Sdtm having the level of the logical OR of the signal from FF circuit 264 and the signal from FF circuit 265.

[0115] The OAR circuit 267 generates a control transition time measurement request Stm, which has a level of logical OR between the charge control transition time measurement request Sctm from the OAR circuit 263 and the discharge control transition time measurement request Sdtm from the OAR circuit 266.

[0116] In the charge / discharge control circuit 10a according to Embodiment 2, the plurality of operating modes further include an over-discharge protection mode and a discharge control transition mode. The protection mode further includes an over-discharge protection mode. The charge / discharge control circuit 10a operates in a predetermined transition mode when at least one of the levels of the discharge control signal Sdc and the charge control signal Scc changes. The transition mode further includes a discharge control transition mode.

[0117] The over-discharge protection mode is an operating mode that is executed when over-discharge of the secondary battery 11 is detected. When the over-discharge detection circuit 30 detects a predetermined discharge prohibition abnormal state based on the positive electrode power supply voltage VDD and the negative electrode power supply voltage VSS, the charge / discharge control circuit 10a transitions, for example, from the normal mode to the over-discharge protection mode. In the over-discharge protection mode, the charge / discharge control circuit 10a operates to keep the discharge control transistor 12 in the off state and the charge control transistor 13 in the on state in order to prohibit discharge. Therefore, in the over-discharge protection mode, the control circuit 20a generates a discharge control signal Sdc with a low level and a charge control signal Scc with a high level.

[0118] The discharge control transition mode is an operating mode that is executed when the level of the discharge control signal Sdc generated by the control circuit 20a changes. The charge / discharge control circuit 10a operates in the discharge control transition mode in the same way as in the charge control transition mode. After a predetermined period, such as a predetermined period T5, has elapsed since operating in the discharge control transition mode, the charge / discharge control circuit 10a transitions from the discharge control transition mode to another operating mode.

[0119] Figure 14 is a timing chart showing an example of the operation of the charge / discharge control circuit 10a according to Embodiment 2. The example shown in Figure 14 is a timing chart relating to the over-discharge protection mode. The horizontal axis of Figure 14 represents time. The vertical axes of Figure 14 represent the level of the over-discharge detection signal Sodd, the level of the protection delay time measurement request Spdm, the level of the over-discharge detection delay time elapsed signal Sodrdp, the state of the over-discharge protection mode, and the level of the discharge control signal Sdc, respectively. The vertical axes of Figure 14 also represent the level of the control transition time measurement request Stm, the level of the discharge control transition time elapsed signal Sdtp, the discharge control voltage DO, the external negative electrode voltage VM, the level of the short-circuit detection signal Ssd, the state of the short-circuit protection mode, and the state of the time measurement circuit 23a, respectively.

[0120] In the timing chart shown in Figure 14, the charge / discharge control circuit 10a operates in over-discharge protection mode before time t21. At time t21, when the over-discharge detection circuit 30 detects the resolution of an abnormal condition related to over-discharge and generates an over-discharge detection signal Sodd with a low level, the control circuit 20a generates a protection delay time measurement request Spdm with a high level. The over-discharge detection circuit 30 may also generate a protection delay time measurement request Spdm with a high level, for example, when the positive electrode power supply voltage VDD becomes higher than the over-discharge recovery voltage. When the time measurement circuit 23a receives a protection delay time measurement request Spdm with a high level, it generates an over-discharge recovery delay time elapsed signal Sodrdp with a high level at time t22, after a predetermined delay time T4 related to the recovery of over-discharge protection. When the control circuit 20a receives an over-discharge recovery delay time measurement stop request Sodrms with a high level from the AND circuit 32, it generates a protection delay time measurement request Spdm with a low level. Furthermore, the charge / discharge control circuit 10a transitions from over-discharge protection mode to normal mode.

[0121] When transitioning from over-discharge protection mode to normal mode, the control circuit 20a generates a discharge control signal Sdc with a high level to turn on the discharge control transistor 12. The state transition detection circuit 26a latches in response to the change in the discharge control signal Sdc from a low level to a high level and generates a control transition time measurement request Stm with a high level. Also, when the discharge control driver 27 receives the discharge control signal Sdc with a high level, it raises the discharge control voltage DO to, for example, the positive electrode power supply voltage VDD to turn on the discharge control transistor 12.

[0122] During the period from time t22 to time t23, the discharge control transistor 12 is in the off state because the discharge control voltage DO has not yet risen sufficiently. Therefore, during this period, the external negative voltage VM is held in a pulled-up state by the load 2, and the short-circuit detection circuit 22a generates a high-level short-circuit detection signal Ssd at time t22 due to a false detection of a discharge prohibition abnormal state. However, since the charge / discharge control circuit 10a is operating in discharge control transition mode, the control circuit 20a does not accept the high-level short-circuit detection signal Ssd. In this way, the control circuit 20a prohibits the generation of a high-level protection delay time measurement request Spdm until a predetermined period T5 has elapsed from the generation of a high-level control transition time measurement request Stm.

[0123] At time t23, after a predetermined period Ton from time t22, if the discharge control voltage DO rises above the threshold voltage Vthd of the discharge control transistor, the discharge control transistor 12 turns on. As a result, the external negative electrode voltage VM is pulled down to the negative electrode power supply voltage VSS. The predetermined period Ton may be, for example, the period from when the P-type MOS transistor 271 of the discharge control driver 27 turns on until the discharge control transistor 12 turns on. Due to the decrease in the external negative electrode voltage VM, the short-circuit detection circuit 22a stops the false detection and generates a short-circuit detection signal Ssd with a low level. In this way, even if a false detection of a short circuit occurs during the discharge control transition mode, the charge / discharge control circuit 10a does not transition to the short-circuit protection mode.

[0124] Furthermore, when the time measurement circuit 23a receives a control transition time measurement request Stm with a high level at time t22, it generates a discharge control transition time elapsed signal Sdtp with a high level at time t24, a predetermined period T5 related to discharge from the generation of the discharge control transition time measurement request Sdtm. When the state transition detection circuit 26a receives the discharge control transition time elapsed signal Sdtp with a high level, it releases its latch and generates a control transition time measurement request Stm with a low level. As a result, the charge / discharge control circuit 10a transitions from the discharge control transition mode to the normal mode. Therefore, from time t24 onward, the control circuit 20a receives protection detection signals such as the short-circuit detection signal Ssd. In other words, the control circuit 20a releases the prohibition on the generation of the protection delay time measurement request Spdm with a high level.

[0125] As shown in Figure 14, the time measurement circuit 23a stops timing before time t21. At time t21, the time measurement circuit 23a measures a delay time T4 related to over-discharge recovery until time t22. At time t22, the time measurement circuit 23a resets the timing state and measures a predetermined period T5 related to discharge until time t24. The time measurement circuit 23a stops timing from time t24 onward.

[0126] Thus, even if a short circuit is erroneously detected when the discharge control transistor 12 is turned on due to the detection of recovery from an abnormal state related to over-discharge, the charge / discharge control circuit 10a can turn on the discharge control transistor 12 without transitioning to short-circuit protection mode. Therefore, the charge / discharge control circuit 10a can appropriately turn on the discharge control transistor 12 when recovering from the over-discharge protection mode to prevent malfunction.

[0127] (modified version) In the above-described embodiment 2, the time measurement circuit 23a generates a predetermined time-elapsed signal having a high level using the oscillator circuit 232, frequency divider circuit 233, and time setting circuit 234a. However, the time measurement circuit 23a may be configured to generate the time-elapsed signal using other configurations.

[0128] Figure 15 is a schematic diagram of a modified time measurement circuit 23b. The time measurement circuit 23b includes a buffer circuit 231b, a time setting circuit 234b, an RC delay circuit 235, and an RC delay circuit 236 instead of the OR circuit 231a and time setting circuit 234b in the time measurement circuit 23a. The time measurement circuit 23b measures time using a circuit equivalent to that of the time measurement circuit 23a based on a high-level protection delay time measurement request Spdm.

[0129] The modified state transition detection circuit does not include the OR circuit 267 in the state transition detection circuit 26a, and generates a high-level charge control transition time measurement request Sctm based on the change in the charge control signal Scc. The modified state transition detection circuit also generates a high-level discharge control transition time measurement request Sdtm based on the change in the discharge control signal Sdc. The time measurement circuit 23b inputs the high-level charge control transition time measurement request Sctm to the RC delay circuit 235 and generates a charge control transition time elapsed signal Sctp after a predetermined period T2. The time measurement circuit 23b inputs the high-level discharge control transition time measurement request Sdtm to the RC delay circuit 236 and generates a discharge control transition time elapsed signal Sdtp after a predetermined period T5.

[0130] The charge-discharge control circuits 10 and 10a according to the above-described embodiments 1 and 2 include a discharge control transistor 12 and a charge control transistor 13 in a low-side configuration. That is, the charge-discharge control circuits 10 and 10a have a configuration in which the discharge control transistor 12 and the charge control transistor 13 are connected in series between the negative electrode of the secondary battery 11 (i.e., the negative electrode power terminal T12) and the external negative electrode terminal T22. However, the charge-discharge control circuits according to this disclosure are not limited to this configuration. The charge-discharge control circuit may also have a high-side configuration in which the discharge control transistor 12 and the charge control transistor 13 are connected in series between the positive electrode of the secondary battery 11 (i.e., the positive electrode power terminal T11) and the external positive electrode terminal T21.

[0131] Figure 16 is a schematic diagram of a modified battery device 1b. Battery device 1b includes a charge / discharge control circuit 10b and resistors 17-19 instead of the charge / discharge control circuit 10 and resistors 14-16 in battery device 1 according to Embodiment 1. Charge / discharge control circuit 10b includes an external positive voltage input terminal T17 for monitoring the external positive voltage VP of the external positive terminal T21, instead of the external negative voltage input terminal T15 in charge / discharge control circuit 10. Also, as described above, in battery device 1b, the discharge control transistor 12 and the charge control transistor 13 are connected between the positive power supply terminal T11 and the external positive terminal T21. The source of the discharge control transistor 12 is connected to the external positive terminal T21 via a resistor 18.

[0132] The external positive voltage input terminal T17 is connected to the external positive terminal T21 and one end of the resistor 18 via resistor 17. The current detection terminal T16 is connected to the other end of resistor 18 via resistor 19. The external positive voltage input terminal T17 is an example of an external voltage detection terminal.

[0133] In a modified example, in the charge / discharge control circuit 10b, the short-circuit detection circuit generates a short-circuit detection signal based, for example, on the difference voltage between the external positive electrode voltage VP and the current detection voltage CS.

[0134] In the low-side configuration, the external negative voltage input terminal T15 is reversed in polarity compared to the external positive voltage input terminal T17 in the high-side configuration. Therefore, for example, the condition that the external negative voltage VM exceeds a predetermined voltage in the low-side configuration can be replaced with the condition that the external positive voltage VP falls below a predetermined voltage in the high-side configuration. By replacing these conditions in this way, the modified charge-discharge control circuit 10b can operate similarly to the charge-discharge control circuits 10 and 10a described in embodiments 1 and 2 above.

[0135] In the above-described embodiment 1, the state transition detection circuit 26 is configured to detect a change in the level of the charge control signal Scc and generate a charge control transition time measurement request Sctm having a high level, but is not limited to this configuration. The state transition detection circuit may be configured to latch its internal circuit only when the charge control signal Scc changes, for example, from a high level to a low level, or from a low level to a high level, and generate a charge control transition time measurement request Sctm having a high level. A similar configuration may also be applied to the state transition detection circuit 26a which operates based on a change in the level of at least one of the charge control signal Scc and the discharge control signal Sdc.

[0136] In the embodiments described above, as an example of the protection function for abnormal conditions in the charge / discharge control circuits 10 and 10a, a plurality of operating modes in which the charge / discharge control circuits 10 and 10a can operate have been described. However, the plurality of operating modes related to the protection function are not limited to the above operating modes and may include any operating modes. For example, the plurality of operating modes may include a discharge overcurrent protection mode that operates based on the detection of overcurrent during discharge, and a charge overcurrent protection mode that operates based on the detection of overcurrent during charging. For example, the plurality of operating modes may include a high temperature protection mode that operates when it is detected that the ambient temperature of the secondary battery 11 is higher than a predetermined threshold, a low temperature protection mode that operates when it is detected that the temperature of the secondary battery 11 is lower than a predetermined threshold, and a state control mode that controls the discharge control transistor 12 and the charge control transistor 13 by an external input. For example, a predetermined abnormality detection circuit may detect a charge prohibition abnormal condition and generate a predetermined abnormality detection signal, and the charge / discharge control circuit may operate in an operating mode based on the abnormality, such as a charge overcurrent protection mode or a high temperature protection mode. For example, a predetermined abnormality detection circuit may detect a discharge prohibition abnormal state and generate a predetermined abnormality detection signal, and the charge / discharge control circuit may operate in an operating mode based on the abnormality, such as a discharge overcurrent protection mode or a low temperature protection mode. The charge / discharge control circuit according to this disclosure can operate without changing the level of the charge control signal Scc or the discharge control signal Sdc, even when a signal is generated that aims to change the state of the discharge control transistor 12 or the charge control transistor 13, such as when a predetermined control transition time measurement request Sctm, Sdtm, or Stm is generated, that is, when operating in a charge control transition mode or a discharge control transition mode, such as when an abnormality detection signal related to the above operating mode is generated. Similarly, the charge / discharge control circuit according to this disclosure can operate without changing the level of the charge control signal Scc or the discharge control signal Sdc when a predetermined control transition time measurement request Sctm, Sdtm, or Stm is generated due to the generation of an abnormality detection signal related to the above operating mode.

[0137] In the embodiment described above, the overcharge detection circuit 21 generates an overcharge detection signal Socd having a high level when it detects a charging prohibition abnormal state, but it is not limited to this configuration. The overcharge detection circuit 21 may also generate an overcharge detection signal Socd having a low level when it detects a charging prohibition abnormal state, and the control circuit 20 may be configured to generate a protection delay time measurement request Spdm having a high level based on the overcharge detection signal Socd having a low level. The overcharge detection circuit 21 generating an abnormal detection signal may include the overcharge detection circuit 21 generating an overcharge detection signal Socd having a low level. Similarly, other circuits such as the control circuit 20, short-circuit detection circuit 22, and time measurement circuit 23 may be configured to generate a signal having a low level when predetermined conditions are met. Furthermore, the control circuit 20 may be configured to turn on the charge control transistor 13 when it generates a charge control signal Scc having a low level. Thus, the charge / discharge control circuit according to this disclosure may be configured to operate based on signals of different levels than those in the embodiment described above.

[0138] In the embodiments described above, the charge-discharge control circuits 10 and 10a are configured to operate in each operating mode based on predetermined signals, but the charge-discharge control circuits 10 and 10a are not limited to this configuration. The charge-discharge control circuits 10 and 10a may be configured so that the control circuits 20 and 20a operate in each operating mode based on predetermined signals. For example, at time t22 in the timing chart shown in Figure 14, the control circuit 20a may be configured to transition from the over-discharge protection mode to the normal mode based on the over-discharge recovery delay time elapsed signal Sodrdp, which has a high level, thereby generating a protection delay time measurement request Spdm, which has a low level. Thus, in this disclosure, for example, the generation of another signal by the control circuits 20 and 20a based on a specific signal may include the control circuits 20 and 20a operating in a predetermined operating mode based on that specific signal and generating that other signal based on operating in that predetermined operating mode.

[0139] The charge / discharge control circuits 10, 10a, and 10b described herein can achieve the following effects.

[0140] The charge / discharge control circuits 10, 10a, and 10b, which prevent malfunctions when the switch elements 12 and 13 that control the charging or discharging of the secondary battery 11 are turned on or off, include abnormality detection circuits 21, 22, 22a, and 30, control circuits 20 and 20a, and state transition detection circuits 26 and 26a. The abnormality detection circuits 21, 22, 22a, and 30 detect a charge prohibition abnormal state or a discharge prohibition abnormal state and generate abnormality detection signals Socd, Ssd, and Sodd. The abnormality detection circuits 21, 22, 22a, and 30 detect the resolution of the charge prohibition abnormal state or the discharge prohibition abnormal state and stop generating the abnormality detection signals Socd, Ssd, and Sodd. The control circuits 20 and 20a generate switch control signals Scc and Sdc having a first value for turning off the switch elements 12 and 13 based on the abnormality detection signals Socd, Ssd, and Sodd, or switch control signals Scc and Sdc having a second value for turning on the switch elements 12 and 13 based on the abnormality detection signals Socd and Sodd. The state transition detection circuits 26 and 26a generate first timing request signals Stm, Sctm, and Sdtm based on a change in the value of the switch control signals Scc and Sdc. The state transition detection circuits 26 and 26a stop generating the first timing request signals Stm, Sctm, and Sdtm after a predetermined first period T2 and T5 from the generation of the first timing request signals Stm, Sctm, and Sdtm. When the first timing request signals Stm, Sctm, and Sdtm are generated, the control circuits 20 and 20a hold the switch control signals Scc and Sdc at the values ​​they were at when the first timing request signals Stm, Sctm, and Sdtm were generated.

[0141] With this configuration, the control circuits 20 and 20a control the switch control signals Scc and Sdc so that their levels do not change until predetermined first periods T2 and T5 have elapsed from the time a change in the level of the switch control signals Scc and Sdc occurs. Therefore, the charge / discharge control circuits 10, 10a and 10b can prevent malfunctions caused by false detection of abnormal conditions by the abnormality detection circuit when the switch elements 12 and 13 are on or off. Furthermore, since the predetermined first periods T2 and T5 can be set in advance, any first period T2 and T5 can be set for each device to which the charge / discharge control circuits 10, 10a and 10b are installed. Therefore, the first periods T2 and T5 can be set to a period during which it is necessary to prevent unintended changes in the charge / discharge transistors, and thus the charge / discharge control circuits 10, 10a and 10b can properly protect the battery devices 1, 1a and 1b.

[0142] The charge / discharge control circuits 10, 10a, and 10b further include time measurement circuits 23 and 23a that generate first period elapsed signals Sctp and Sdtp after first periods T2 and T5 following the generation of first timing request signals Stm, Sctm, and Sdtm. The state transition detection circuit stops generating the first timing request signals Stm, Sctm, and Sdtm based on the first period elapsed signals Sctp and Sdtp. With this configuration, the time measurement circuits 23 and 23a can set any first period T2 and T5. Since the first period T2 and T5 can be set to a period during which it is necessary to prevent unintended changes in the charge / discharge transistors, the charge / discharge control circuits 10, 10a, and 10b can properly protect the battery devices 1, 1a, and 1b.

[0143] In the charge / discharge control circuits 10, 10a, and 10b, the switch element includes a first switch element 13 that controls charging. The abnormality detection signal includes a charge abnormality detection signal Socd that is generated based on the detection of a charge prohibition abnormal state. The control circuits 20 and 20a generate a switch control signal Scc having a first value after a predetermined second period T1 based on the generation of the charge abnormality detection signal Socd, or generate a switch control signal Scc having a second value after a predetermined third period based on the cessation of the generation of the charge abnormality detection signal Socd. With this configuration, even if an abnormal state is falsely detected when the switch control signal Scc changes based on the detection of a charge prohibition abnormal state, unintended changes in the state of the switch elements 12 and 13 can be prevented. Therefore, the charge / discharge control circuits 10, 10a, and 10b can prevent malfunctions due to false detection of abnormal states by the abnormality detection circuit when the switch element 13 is on or off.

[0144] In the charge / discharge control circuits 10, 10a, and 10b, the control circuits 20 and 20a generate a second timing request signal Spdm based on the generation of a charging abnormality detection signal Socd, and stop generating the second timing request signal Spdm and generate a switch control signal Scc having a first value based on the second period elapsed signal Socdp. Alternatively, the control circuits 20 and 20a generate a third timing request signal Spdm based on the cessation of the charging abnormality detection signal Socd, and stop generating the third timing request signal Spdm and generate a switch control signal Scc having a second value based on the third period elapsed signal. The time measurement circuits 23, 23a, and 23b further generate a second period elapsed signal Socdp two periods after the generation of the second timing request signal Spdm, and generate a third period elapsed signal three periods after the generation of the third timing request signal Spdm. The control circuits 20 and 20a prohibit the generation of the second and third timing request signals Spdm and Sctm until the first period (T2) has elapsed from the generation of the first timing request signals Stm and Sctm. With this configuration, the control circuits 20 and 20a will not generate the second or third timing request signal Spdm, even if an abnormality detection signal is generated, from the time the switch control signal Scc is changed until after the first period T2. Therefore, the switch control signal Scc is not changed based on the abnormality detection signal. Consequently, the charge / discharge control circuits 10, 10a and 10b can prevent malfunctions caused by false detection of abnormal conditions by the abnormality detection circuit when the switch element 13 is on or off.

[0145] In charge / discharge control circuits 10, 10a, and 10b, the switch element further includes a second switch element 12 that controls discharge. The abnormality detection signal includes a discharge abnormality detection signal Sodd, which is generated based on the detection of a discharge prohibition abnormal state. Control circuits 20 and 20a further generate a fourth timing request signal Spdm based on the generation of the discharge abnormality detection signal Sodd, and generate a switch control signal Sdc having a first value a predetermined fourth period after the generation of the fourth timing request signal Spdm. Alternatively, control circuits 20 and 20a generate a fifth timing request signal Spdm based on the cessation of the generation of the discharge abnormality detection signal Sodd, and generate a switch control signal Sdc having a second value a predetermined fifth period T4 after the generation of the fifth timing request signal Spdm. Control circuits 20 and 20a further prohibit the generation of the fourth timing request signal Spdm and the fifth timing request signal Spdm until a first period T5 has elapsed from the generation of the first timing request signals Stm and Sdtm. With this configuration, even if a false detection of an abnormal state occurs when the switch control signal Scc changes based on the detection of a discharge prohibition abnormal state, it is possible to prevent unintended changes in the state of the switch elements 12 and 13. Therefore, the charge / discharge control circuits 10, 10a, and 10b can prevent malfunctions caused by false detection of abnormal states by the abnormality detection circuit when the switch element 12 is on or off.

[0146] In the charge / discharge control circuits 10, 10a, and 10b, the switch control signal includes a charge control signal Scc for controlling the first switch element 13 and a discharge control signal Sdc for controlling the second switch element 12. The first period includes a predetermined sixth period T2 and a predetermined seventh period T5, which are different from each other. When the state transition detection circuits 26 and 26a generate first timing request signals Stm and Sctm based on a change in the value of the charge control signal Scc, they stop generating the first timing request signals Stm and Sctm after the sixth period T2 from the generation of the first timing request signals Stm and Sctm. When the state transition detection circuits 26 and 26a generate first timing request signals Stm and Sdtm based on a change in the value of the discharge control signal Sdc, they stop generating the first timing request signals Stm and Sdtm after the seventh period T5 from the generation of the first timing request signals Stm and Sdtm. With this configuration, the charge / discharge control circuits 10, 10a, and 10b can prevent the generation of the second to fifth timing request signals Spdm for different periods based on changes in the charge control signal Scc and the discharge control signal Sdc. Therefore, the charge / discharge control circuits 10, 10a, and 10b can flexibly adjust the predetermined period T2 due to the change in the charge control signal Scc and the predetermined period T5 due to the discharge control signal Sdc, thereby protecting the battery devices 1, 1a, and 1b more effectively.

[0147] In the charge / discharge control circuits 10, 10a, and 10b, the first period T2, T5, the second period T1, and the third period are timed by the same time measurement circuits 23, 23a, and 23b, which generate different elapsed signals for the first period (Sctp, Sdtp), the second period (Socdp), and the third period (Socdp). With this configuration, multiple predetermined periods can be timed by the same time measurement circuits 23, 23a, and 23b, making the charge / discharge control circuit smaller compared to one that has a separate time measurement circuit for each predetermined period. Therefore, the charge / discharge control circuits 10, 10a, and 10b can protect the battery devices 1, 1a, and 1b with a simple configuration.

[0148] In the charge / discharge control circuits 10, 10a, and 10b, the switch element includes a second switch element 12 that controls discharge. The abnormality detection signal includes a discharge abnormality detection signal Sodd, which is generated based on the detection of a discharge prohibition abnormal state. The control circuits 20 and 20a generate a switch control signal Sdc with a first value a predetermined fourth period after the generation of the discharge abnormality detection signal Sodd, and generate a switch control signal Sdc with a second value a predetermined fifth period T4 after the cessation of the generation of the discharge abnormality detection signal Sodd. In this way, the control circuits 20 and 20a can operate to turn off the switch element 12 based on the generation of the discharge abnormality detection signal Sodd and to turn on the switch element 12 based on the cessation of the generation of the discharge abnormality detection signal Sodd. Furthermore, the charge / discharge control circuits 10, 10a, and 10b can prevent unintended changes in the state of the switch elements 12 and 13 even if a false detection of an abnormal state occurs when the switch control signal Sdc changes based on the detection of a discharge prohibition abnormal state. Therefore, the charge / discharge control circuits 10, 10a, and 10b can prevent malfunctions caused by false detection of abnormal conditions by the abnormality detection circuit when the switch element 12 is on or off.

[0149] The charge / discharge control circuits 10, 10a, and 10b further include external voltage detection terminals T15 and T17 connected to a charger 2 connected to the charge / discharge control circuits 10, 10a, and 10b, and a charger connection detection circuit 29 that generates a charger connection detection signal Scrd based on the voltages VM and VP of the external voltage detection terminals T15 and T17. The switch element includes a second switch element 12 that controls discharge. The abnormality detection signal includes a discharge abnormality detection signal Ssd that is generated based on the detection of a discharge prohibition abnormality state. The control circuits 20 and 20a generate a switch control signal Sdc having a first value a predetermined fourth period after the generation of the discharge abnormality detection signal Ssd, and generate a switch control signal Sdc having a second value a predetermined fifth period after the generation of the charger connection detection signal Scrd. In this way, the control circuits 20 and 20a can operate to turn off the switch element 12 based on the generation of the discharge abnormality detection signal Ssd and to turn on the switch element 12 based on the charger connection detection signal Scrd. Furthermore, the charge / discharge control circuits 10, 10a, and 10b can prevent unintended changes in the state of the switch elements 12 and 13 even if a false detection of an abnormal state occurs when the switch control signal Sdc changes based on the detection of an abnormal discharge prohibition state. Therefore, the charge / discharge control circuits 10, 10a, and 10b can prevent malfunctions caused by false detection of abnormal states by the abnormality detection circuit when the switch element 12 is ON or OFF.

[0150] In the charge / discharge control circuits 10, 10a, and 10b, the abnormality detection circuit includes at least one of an overcharge detection circuit 21 that detects overcharging of the secondary battery 11 and an over-discharge detection circuit 30 that detects over-discharging of the secondary battery 11. With this configuration, the control circuits 20 and 20a control the switch control signals Scc and Sdc so that their levels do not change until a predetermined first period T2 and T5 has elapsed from the generation or cessation of the abnormality detection signals Socd and Sodd for an abnormal state related to overcharging or an abnormal state related to over-discharging. Therefore, the charge / discharge control circuits 10, 10a, and 10b can prevent malfunctions caused by false detection of abnormal states by the abnormality detection circuit when the switch elements 12 and 13 are turned on or off, resulting from the detection of an abnormal state related to over-discharge or overcharge or recovery from such an abnormal state.

[0151] The charge / discharge control circuits 10, 10a, and 10b further include external voltage detection terminals T15 and T17 connected via resistors to the positive or negative terminal of the load 2 connected to the charge / discharge control circuits 10, 10a, and 10b. The external voltage detection terminals T15 and T17 have external voltages VM and VP corresponding to the voltages of the positive or negative terminals. The abnormality detection circuit 30 detects a charge-prohibition abnormality or a discharge-prohibition abnormality based on the change in external voltages VM and VP when the switch elements 12 and 13 are turned on or off. With such a configuration, fluctuations in external voltages VM and VP may occur when the switch elements 12 and 13 are turned on or off. Since the charge / discharge control circuits 10, 10a, and 10b are configured to detect a predetermined abnormality based on fluctuations in external voltages VM and VP, fluctuations in external voltages VM and VP when the switch elements 12 and 13 are turned on or off may lead to the false detection of an abnormality. In the charge / discharge control circuits 10, 10a, and 10b of this disclosure, the control circuits 20 and 20a control the switch control signals Scc and Sdc so that their levels do not change from the time of the change until after the first periods T2 and T5, respectively, when the levels of the switch control signals Scc and Sdc change. Therefore, even if fluctuations in external voltages VM and VP occur when the switch elements 12 and 13 are turned on or off, and an abnormal condition is falsely detected by the abnormality detection circuit based on these fluctuations, the charge / discharge control circuits 10, 10a, and 10b can prevent malfunction.

[0152] In the charge / discharge control circuits 10, 10a, and 10b, the first periods T2 and T5 are measured by RC delay circuits 235 and 236. With this configuration, the first periods T2 and T5 can be measured with a simple setup.

[0153] The battery devices 1, 1a, and 1b each include the charge / discharge control circuits 10, 10a, and 10b described above, a secondary battery 11, a first switch element 13 for controlling the charging of the secondary battery 11, and a second switch element 12 for controlling the discharging of the secondary battery 11. With this configuration, malfunctions that occur when the switch elements controlling the charging or discharging of the secondary battery are turned on or off can be prevented.

[0154] A charge / discharge control method for preventing malfunctions of switch elements 12 and 13 that control the charging or discharging of a secondary battery 11 when they are turned on or off includes the following processes: The charge / discharge control method includes abnormality detection circuits 21, 22, 22a, and 30 detecting a charge prohibition abnormal state or a discharge prohibition abnormal state and generating abnormality detection signals Socd, Ssd, and Sodd, and detecting the resolution of the charge prohibition abnormal state or the discharge prohibition abnormal state and stopping the generation of abnormality detection signals Socd, Ssd, and Sodd. The charge / discharge control method also includes control circuits 20 and 20a generating switch control signals Sdc and Scc having a first value for turning off the switch elements 12 and 13 based on the abnormality detection signals Socd, Ssd, and Sodd, or switch control signals Sdc and Scc having a second value for turning on the switch elements 12 and 13 based on the abnormality detection signals Socd and Sodd. The charge / discharge control method includes the state transition detection circuits 26 and 26a generating first timing request signals Stm, Sctm, and Sdtm based on a change in the values ​​of the switch control signals Sdc and Scc, and stopping the generation of the first timing request signals Stm, Sctm, and Sdtm after a predetermined first period T2 and T5 from the generation of the first timing request signals Stm, Sctm, and Sdtm. The control circuits 20 and 20a maintain the switch control signals Sdc and Scc at the values ​​at the time of generation of the first timing request signals Stm, Sctm, and Sdtm when the first timing request signals Stm, Sctm, and Sdtm are being generated.

[0155] By operating in this manner, the control circuits 20 and 20a control the switch control signals Scc and Sdc so that their levels do not change until a predetermined first period T2 or T5 has elapsed from the time a change in the level of the switch control signals Scc and Sdc occurs. Therefore, according to the charge / discharge control method, malfunctions caused by false detection of abnormal conditions by the abnormality detection circuit when the switch elements 12 and 13 are on or off can be prevented.

[0156] (Summary of characteristics) As is clear from the above description, this disclosure includes the following embodiments. In the following, reference numerals are enclosed in parentheses solely to indicate their correspondence with the embodiments.

[0157] (Aspect 1) The charge / discharge control circuit (10, 10a, 10b) according to the present disclosure is a charge / discharge control circuit that prevents malfunction of switch elements (12, 13) that control the charging or discharging of a secondary battery (11) when they are on or off, An abnormality detection circuit (21, 22, 22a, 30) detects a charge prohibition abnormal state or a discharge prohibition abnormal state and generates an abnormality detection signal (Socd, SSD, Sodd), and detects that the charge prohibition abnormal state or the discharge prohibition abnormal state has been resolved and stops generating the abnormality detection signal, A control circuit (20, 20a) that generates a switch control signal (Sdc, Scc) having a first value for turning off the switch element, or a switch control signal (20, 20a) having a second value for turning on the switch element, based on the abnormality detection signal, A state transition detection circuit (26, 26a) generates a first timing request signal (Stm, Sctm, Sdtm) based on a change in the value of the switch control signal, and stops generating the first timing request signal after a predetermined first period (T2, T5) from the generation of the first timing request signal, Equipped with, The control circuit holds the switch control signal at the value at the time the first timing request signal was generated when the first timing request signal is generated.

[0158] (Aspect 2) The charge / discharge control circuit (10, 10a, 10b) of aspect 1 further comprises a time measurement circuit (23, 23a, 23b) that generates a first period elapsed signal (Sctp, Sdtp) after the first period (T2, T5) from the generation of the first timing request signal (Stm, Sctm, Sdtm), The state transition detection circuits (26, 26a) stop generating the first timing request signal based on the first period elapsed signal.

[0159] (Aspect 3) In the charge / discharge control circuit (10, 10a, 10b) of aspect 2, the switch element includes a first switch element (13) that controls charging, The abnormality detection signal includes a charging abnormality detection signal (Socd) generated based on the detection of the charging prohibition abnormal state. The aforementioned control circuits (20, 20a) Based on the occurrence of the charging abnormality detection signal, a switch control signal (Scc) having the first value is generated after a predetermined second period (T1), or Based on the cessation of the generation of the charging abnormality detection signal, the switch control signal having the second value is generated after a predetermined third period.

[0160] (Aspect 4) In the charge / discharge control circuit (10, 10a, 10b) of Aspect 3, the control circuit (20, 20a) is Based on the occurrence of the charging abnormality detection signal (Socd), a second timing request signal (Spdm) is generated, and based on the second period elapsed signal (Socdp), the generation of the second timing request signal is stopped and the switch control signal (Scc) having the first value is generated, or Based on the cessation of the charging abnormality detection signal, a third timing request signal (Spdm) is generated, and based on the third period elapsed signal, the generation of the third timing request signal is stopped and the switch control signal having the second value is generated. The time measurement circuits (23, 23a, 23b) further generate a second period elapsed signal after the second period (T1) from the generation of the second timing request signal, and generate a third period elapsed signal after the third period from the generation of the third timing request signal. The control circuit prohibits the generation of the second timing request signal and the third timing request signal from the time the first timing request signal (Stm, Sctm) is generated until the first period (T2) has elapsed.

[0161] (Aspect 5) In the charge / discharge control circuit (10, 10a, 10b) of aspect 4, the switch element further includes a second switch element (12) that controls the discharge, The abnormality detection signal includes a discharge abnormality detection signal (Sodd) generated based on the detection of the discharge prohibition abnormal state. The aforementioned control circuits (20, 20a) further, Based on the generation of the discharge abnormality detection signal, a fourth timing request signal (Spdm) is generated, and after a predetermined fourth period from the generation of the fourth timing request signal, a switch control signal (Sdc) having the first value is generated, or Based on the cessation of the discharge abnormality detection signal, a fifth timing request signal (Spdm) is generated, and a switch control signal having the second value is generated after a predetermined fifth period (T4) from the generation of the fifth timing request signal. The control circuit further prohibits the generation of the fourth timing request signal and the fifth timing request signal from the time the first timing request signal (Stm, Sdtm) is generated until the first period (T5) has elapsed.

[0162] (Aspect 6) In the charge / discharge control circuit (10, 10a, 10b) of Aspect 5, the switch control signal includes a charge control signal (Scc) that controls the first switch element (13) and a discharge control signal (Sdc) that controls the second switch element (12), The first period includes a predetermined sixth period (T2) and a predetermined seventh period (T5), which are different from each other. The state transition detection circuits (26, 26a) are as follows: When the value of the charging control signal changes, the first timing request signal (Stm, Sctm) is generated, and the generation of the first timing request signal is stopped after the sixth period from the generation of the first timing request signal. When the first timing request signal (Stm, Sdtm) is generated based on a change in the value of the discharge control signal, the generation of the first timing request signal is stopped after the seventh period from the generation of the first timing request signal.

[0163] (Aspect 7) In the charge / discharge control circuit (10, 10a, 10b) of Aspect 4 or Aspect 5, the first period (T2, T5), the second period (T1), and the third period are timed by the same time measurement circuit (23, 23a, 23b) that generates different first period elapsed signals (Sctp, Sdtp), second period elapsed signal (Socdp), and third period elapsed signals.

[0164] (Aspect 8) In the charge / discharge control circuit (10, 10a, 10b) of aspect 2, the switch element includes a second switch element (12) that controls the discharge, The abnormality detection signal includes a discharge abnormality detection signal (Sodd) generated based on the detection of the discharge prohibition abnormal state. The aforementioned control circuits (20, 20a) A switch control signal (Sdc) having the first value is generated after a predetermined fourth period following the generation of the discharge abnormality detection signal. A switch control signal having the second value is generated after a predetermined fifth period (T4) following the cessation of the generation of the discharge abnormality detection signal.

[0165] (Aspect 9) In the charge / discharge control circuit (10, 10a, 10b) of Aspect 2, the external voltage detection terminals (T15, T17) connected to the charger (2) connected to the charge / discharge control circuit, A charger connection detection circuit (29) that generates a charger connection detection signal (Scd) based on the voltage (VM, VP) of the external voltage detection terminal, Furthermore, The aforementioned switch element includes a second switch element (12) that controls the discharge, The abnormality detection signal includes a discharge abnormality detection signal (Ssd) generated based on the detection of the discharge prohibition abnormal state. The aforementioned control circuits (20, 20a) A switch control signal (Sdc) having the first value is generated after a predetermined fourth period following the generation of the discharge abnormality detection signal. A switch control signal having the second value is generated after a predetermined fifth period following the generation of the charger connection detection signal.

[0166] (Aspect 10) A charge / discharge control circuit (10, 10a, 10b) according to any of aspects 1 to 8, further comprising external voltage detection terminals (T15, T17) connected via a resistor to the positive or negative electrode of a load (2) connected to the charge / discharge control circuit, The external voltage detection terminal has an external voltage (VM, VP) corresponding to the voltage of the positive or negative electrode. The abnormality detection circuit (30) detects the charging prohibition abnormality state or the discharge prohibition abnormality state based on the change in the external voltage when the switch elements (12, 13) are turned on or off.

[0167] (Aspect 11) In any of the charge / discharge control circuits (10, 10a, 10b) of aspects 1 to 10, the abnormality detection circuit includes at least one of an overcharge detection circuit (21) for detecting overcharging of the secondary battery (11) and an over-discharge detection circuit (30) for detecting over-discharging of the secondary battery.

[0168] (Aspect 12) In any of the charge / discharge control circuits (10, 10a, 10b) of aspects 1 to 11, the first period (T2, T5) is measured by RC delay circuits (235, 236).

[0169] (Aspect 13) The battery device (1, 1a, 1b) relating to this disclosure comprises a charge / discharge control circuit (10, 10a, 10b) described in any one of aspects 1 to 12, Rechargeable battery (11) and, A first switch element (13) controls the charging of the secondary battery, A second switch element (12) controls the discharge of the secondary battery, It is equipped with.

[0170] (Aspect 14) The charge / discharge control method according to the present disclosure is a charge / discharge control method that prevents malfunction of switch elements (12, 13) that control the charging or discharging of a secondary battery (11) when they are on or off, An abnormality detection circuit (21, 22, 22a, 30) detects a charge prohibition abnormal state or a discharge prohibition abnormal state and generates an abnormality detection signal (Socd, SSD, Sodd), and stops generating the abnormality detection signal when it detects that the charge prohibition abnormal state or the discharge prohibition abnormal state has been resolved. The control circuit (20, 20a) generates a switch control signal (Sdc, Scc) having a first value for turning off the switch element, or a switch control signal having a second value for turning on the switch element, The state transition detection circuit (26, 26a) generates a first timing request signal (Stm, Sctm, Sdtm) based on a change in the value of the switch control signal, and stops generating the first timing request signal after a predetermined first period (T2, T5) from the generation of the first timing request signal. Includes, The control circuit holds the switch control signal at the value at the time the first timing request signal was generated when the first timing request signal is generated.

[0171] In this specification, terms such as “First,” “Second,” etc., are used for illustrative purposes only and should not be understood as expressing or implying relative importance or ranking of technical features. Features designated as “First” or “Second” express or imply that they include one or more such features. [Industrial applicability]

[0172] According to this disclosure, it is possible to provide a charge / discharge control circuit, a charge / discharge control method, and a battery device that suppress malfunctions that occur when a switch element controlling the charging or discharging of a secondary battery is turned on or off, compared to the prior art, and therefore can be suitably used in this type of industrial field. [Explanation of Symbols]

[0173] 1, 1a, 1b battery device 2 loads 10, 10a, 10b Charge / Discharge Control Circuit 11 Secondary battery 12 Discharge control transistors 13. Charge control transistor 21 Overcharge detection circuit 20, 20a Control circuit 22, 22a Short-circuit detection circuit 23, 23a, 23b Time measurement circuits 26, 26a State transition detection circuit 30 Over-discharge detection circuit

Claims

1. A charge / discharge control circuit that prevents malfunctions when an on or off switch element controls the charging or discharging of a secondary battery, An abnormality detection circuit that detects an abnormal charge prohibition state or an abnormal discharge prohibition state and generates an abnormality detection signal, and detects that the abnormal charge prohibition state or the abnormal discharge prohibition state has been resolved and stops generating the abnormality detection signal, A control circuit that generates a switch control signal having a first value for turning off the switch element, or a switch control signal having a second value for turning on the switch element, based on the abnormality detection signal. A state transition detection circuit that generates a first timing request signal based on a change in the value of the switch control signal, and stops generating the first timing request signal after a predetermined first period from the generation of the first timing request signal, Equipped with, The control circuit maintains the switch control signal at the value at the time the first timing request signal was generated when the first timing request signal is generated. Charge / discharge control circuit.

2. The system further includes a time measurement circuit that generates a first period elapsed signal after the first period has elapsed since the generation of the first time timing request signal. The charge / discharge control circuit according to claim 1, wherein the state transition detection circuit stops generating the first timing request signal based on the first period elapsed signal.

3. The aforementioned switch element includes a first switch element that controls charging, The abnormality detection signal includes a charging abnormality detection signal generated based on the detection of the charging prohibition abnormal state, The aforementioned control circuit is Based on the occurrence of the charging abnormality detection signal, a switch control signal having the first value is generated after a predetermined second period, or Based on the cessation of the generation of the charging abnormality detection signal, a switch control signal having the second value is generated after a predetermined third period. The charge / discharge control circuit according to claim 2.

4. The aforementioned control circuit is Based on the occurrence of the charging abnormality detection signal, a second timing request signal is generated, and based on the second period elapsed signal, the generation of the second timing request signal is stopped and the switch control signal having the first value is generated, or Based on the cessation of the charging abnormality detection signal, a third timing request signal is generated, and based on the third period elapsed signal, the generation of the third timing request signal is stopped and the switch control signal having the second value is generated. The time measurement circuit further generates a second period elapsed signal after a second period has elapsed since the generation of the second timing request signal, and generates a third period elapsed signal after a third period has elapsed since the generation of the third timing request signal. The control circuit prohibits the generation of the second timing request signal and the third timing request signal from the time the first timing request signal is generated until the first period has elapsed. The charge / discharge control circuit according to claim 3.

5. The aforementioned switch element further includes a second switch element for controlling the discharge, The abnormality detection signal includes a discharge abnormality detection signal generated based on the detection of the discharge prohibition abnormal state, The control circuit further, Based on the generation of the discharge abnormality detection signal, a fourth timing request signal is generated, and after a predetermined fourth period from the generation of the fourth timing request signal, the switch control signal having the first value is generated, or Based on the cessation of the discharge abnormality detection signal, a fifth timing request signal is generated, and a switch control signal having the second value is generated after a predetermined fifth period from the generation of the fifth timing request signal. The control circuit further prohibits the generation of the fourth timing request signal and the fifth timing request signal until the first period has elapsed from the generation of the first timing request signal. The charge / discharge control circuit according to claim 4.

6. The switch control signal includes a charge control signal for controlling the first switch element and a discharge control signal for controlling the second switch element. The first period includes a predetermined sixth period and a predetermined seventh period, which are different from each other. The state transition detection circuit is, When the first timing request signal is generated based on a change in the value of the charging control signal, the generation of the first timing request signal is stopped after the sixth period from the generation of the first timing request signal. When the first timing request signal is generated based on a change in the value of the discharge control signal, the generation of the first timing request signal is stopped after the seventh period from the generation of the first timing request signal. The charge / discharge control circuit according to claim 5.

7. The charge / discharge control circuit according to claim 4, wherein the first period, the second period, and the third period are timed by the same time measurement circuit that generates different first period elapsed signals, second period elapsed signals, and third period elapsed signals.

8. The aforementioned switch element includes a second switch element that controls the discharge, The abnormality detection signal includes a discharge abnormality detection signal generated based on the detection of the discharge prohibition abnormal state, The aforementioned control circuit is A switch control signal having the first value is generated after a predetermined fourth period following the generation of the discharge abnormality detection signal. A switch control signal having the second value is generated after a predetermined fifth period following the cessation of the generation of the discharge abnormality detection signal. The charge / discharge control circuit according to claim 2.

9. An external voltage detection terminal connected to the charger connected to the charge / discharge control circuit, A charger connection detection circuit that generates a charger connection detection signal based on the voltage of the external voltage detection terminal, Furthermore, The aforementioned switch element includes a second switch element that controls the discharge, The abnormality detection signal includes a discharge abnormality detection signal generated based on the detection of the discharge prohibition abnormal state, The aforementioned control circuit is A switch control signal having the first value is generated after a predetermined fourth period following the generation of the discharge abnormality detection signal. A switch control signal having the second value is generated after a predetermined fifth period following the generation of the charger connection detection signal. The charge / discharge control circuit according to claim 2.

10. The charging / discharging control circuit further comprises an external voltage detection terminal connected via a resistor to the positive or negative electrode of a load connected to the aforementioned charging / discharging control circuit, The external voltage detection terminal has an external voltage corresponding to the voltage of the positive or negative electrode. The abnormality detection circuit detects the charging prohibition abnormality state or the discharge prohibition abnormality state based on the change in the external voltage when the switch element is turned on or off. The charge / discharge control circuit according to claim 1.

11. The charge / discharge control circuit according to claim 1, wherein the abnormality detection circuit includes at least one of an overcharge detection circuit for detecting overcharging of the secondary battery and an over-discharge detection circuit for detecting over-discharging of the secondary battery.

12. The charge / discharge control circuit according to claim 1, wherein the first period is measured by an RC delay circuit.

13. A charge / discharge control circuit according to any one of claims 1 to 12, Rechargeable batteries and A first switch element for controlling the charging of the secondary battery, A second switch element that controls the discharge of the secondary battery, A battery device equipped with the following features.

14. A charge / discharge control method for preventing malfunctions when an on or off switch element controls the charging or discharging of a secondary battery, The abnormality detection circuit detects an abnormal charge prohibition state or an abnormal discharge prohibition state and generates an abnormality detection signal, and stops generating the abnormality detection signal when it detects that the abnormal charge prohibition state or the abnormal discharge prohibition state has been resolved. The control circuit generates a switch control signal having a first value for turning off the switch element, or a switch control signal having a second value for turning on the switch element, based on the abnormality detection signal. The state transition detection circuit generates a first timing request signal based on a change in the value of the switch control signal, and stops generating the first timing request signal after a predetermined first period from the generation of the first timing request signal. Includes, The control circuit maintains the switch control signal at the value at the time the first timing request signal was generated when the first timing request signal is generated. Charge / discharge control method.

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