Semiconductor equipment

Abstract

To reduce the on-resistance of semiconductor devices. [Solution] The semiconductor substrate comprises a plurality of trenches, a gate insulating film covering the inner surface of the trenches, a gate electrode disposed within the trenches, a source region of a first conductivity type, a body region of a second conductivity type located below the source region, and a drift region of a first conductivity type in contact with the lower surface of the body region. The plurality of trenches are insulated from the upper electrode and include a plurality of first trenches to which a first voltage can be applied. The plurality of trenches are electrically connected to the upper electrode and include a plurality of second trenches to which a second voltage different from the first voltage can be applied. The first trenches have a constant first width along their entire length in a first direction. The second trenches have a wide region in a portion of their entire length in the first direction that has a second width greater than the first width. In the wide region, the upper electrode and the gate electrode are in contact.

Description

Technical Field

[0001] The technology disclosed in the present specification relates to a semiconductor device.

[0002] Patent Document 1 discloses a trench gate type semiconductor device provided with a plurality of narrow trenches and wide trenches. In this semiconductor device, gate electrodes are provided inside the narrow trenches and the wide trenches. Then, an insulating film is embedded inside the narrow trenches and the wide trenches so as to cover the upper surfaces of the gate electrodes. The thickness of the insulating film at the widthwise central portion thereof is smaller in the wide trench than in the narrow trench. Therefore, by performing full-surface etch-back on the insulating film, only the gate electrodes in the wide trenches can be selectively exposed without using a mask. Thereafter, an upper electrode is formed. It becomes possible to connect the gate electrodes in the wide trenches to the upper electrode without producing a mask.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problem to be Solved by the Invention

[0004] When wide trenches are provided, the number of trenches per unit area decreases by the amount corresponding to the increased width of the trenches. As a result, problems such as an increase in on-resistance may occur.

Means for Solving the Problem

[0005] The semiconductor device (1) disclosed herein comprises a semiconductor substrate (12), an upper electrode (14) provided on the upper surface of the semiconductor substrate, and a lower electrode (16) provided on the lower surface of the semiconductor substrate. The semiconductor substrate comprises a plurality of trenches (20T) located on the upper surface (12a) of the semiconductor substrate. The plurality of trenches extend linearly in a first direction (x) and are spaced apart in a second direction (y) intersecting the first direction. The semiconductor substrate comprises a gate insulating film (20a) covering the inner surface of the trenches. The semiconductor substrate comprises a gate electrode (20b) located within the trenches and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate comprises a source region (30) of a first conductivity type (n) located in the inter-trench region, which is a region sandwiched between the plurality of trenches, and exposed on the upper surface of the semiconductor substrate. The semiconductor substrate comprises a body region (34) of a second conductivity type (p) located in the inter-trench region and positioned below the source region. The semiconductor substrate comprises a drift region (40) of first conductivity type (n) distributed across the lower part of a plurality of trenches, in contact with the lower surface of the body region and the lower part of the trenches. The plurality of trenches include a plurality of first trenches (20T1) that are insulated from the upper electrode and configured to allow the application of a first voltage (gate voltage). The plurality of trenches include a plurality of second trenches (20T2) that are electrically connected to the upper electrode and configured to allow the application of a second voltage (source voltage) different from the first voltage. The first trenches have a constant first width (W1) along their entire length in a first direction. The second trenches have a wide region (WA) in a portion of their entire length in a first direction that has a second width (W2) greater than the first width. In the wide region, the upper electrode and the gate electrode are in contact.

[0006] In this specification, one of the first conductivity type and the second conductivity type means n-type, and the other means p-type.

[0007] In the above structure, a wide region is provided only in a portion of the entire length of the second trench. By bringing the upper electrode and the gate electrode into contact in the wide region, a second voltage can be applied to the second trench. Therefore, the expansion of the width of the second trench can be suppressed in the region where the wide region is not formed. Compared to the case where the width is expanded along the entire length of the second trench, it becomes possible to increase the number of trenches per unit area. [Brief explanation of the drawing]

[0008] [Figure 1] Top view of semiconductor substrate 12. [Figure 2] Enlarged top view of region R2 in Figure 1. [Figure 3] A cross-sectional perspective view along line III-III in Figure 2. [Figure 4] A cross-sectional perspective view along line IV-IV in Figure 2. [Figure 5] A diagram illustrating the planar structure of the electric field relaxation layer 50. [Figure 6] A cross-sectional view illustrating the manufacturing method of semiconductor device 1. [Figure 7] A cross-sectional view illustrating the manufacturing method of semiconductor device 1. [Figure 8] A cross-sectional view illustrating the manufacturing method of semiconductor device 1. [Figure 9] Enlarged top view of the comparative example semiconductor device 101. [Figure 10] An enlarged top view illustrating the first example of trench placement. [Figure 11] An enlarged top view illustrating a second trench configuration example. [Modes for carrying out the invention] [Examples]

[0009] (Outline structure of semiconductor device 1) The semiconductor device 1 of this embodiment will be described below with reference to the drawings. For the purpose of clarity in the illustration, only a portion of the repeatedly formed structure may be given reference numerals. Hereinafter, the direction parallel to the upper surface 12a of the semiconductor substrate 12 will be referred to as the x-direction, the direction parallel to the upper surface 12a and perpendicular to the x-direction will be referred to as the y-direction, and the thickness direction of the semiconductor substrate 12 will be referred to as the z-direction.

[0010] The semiconductor device 1 shown in Figure 1 has a semiconductor substrate 12. The material of the semiconductor substrate 12 is not particularly limited, but may be silicon, silicon carbide (SiC), or nitride semiconductor (e.g., GaN). In this embodiment, silicon carbide is used. The semiconductor substrate 12 has a semiconductor chip shape.

[0011] The semiconductor substrate 12 comprises an element region 10 and a peripheral region 11. The element region 10 is a region in which a device structure that performs a specific function is formed. The peripheral region 11 is a region provided around the element region 10 and is a region in which no device structure is formed. The device structure may be, for example, a MOSFET structure that performs a switching function, a diode structure that performs a rectifying function, or a reverse-conducting IGBT structure that combines an IGBT structure and a diode structure.

[0012] The upper surface 12a of the semiconductor substrate 12 is provided with two source electrodes 14, a gate electrode lead-out section 24, and a plurality of signal electrodes 26. The gate electrode lead-out section 24 is a transmission line for gate signals input from the outside. The gate electrode lead-out section 24 is commonly connected to the gate electrode 20b located in the first trench 20T1, as will be described later. Each of the plurality of signal electrodes 26 is an interface for inputting and outputting gate signals and various sensor signals.

[0013] (Specific structure of semiconductor device 1) FIG. 2 shows an enlarged top view of region R2 in FIG. 1. Region R2 is a region on the right half side of the element region 10. Region R2 includes the boundary BD between the element region 10 and the peripheral region 11. Note that illustration of the source electrode 14 is omitted in FIG. 2. FIGS. 3 and 4 show cross-sectional perspective views of the semiconductor device 1. FIG. 3 is a cross-sectional perspective view taken along line III-III in FIG. 2. FIG. 4 is a cross-sectional perspective view taken along line IV-IV in FIG. 2. In FIGS. 2 to 4, for ease of viewing, n-type regions are shown with gray solid fill, and p-type regions are shown as white outlines.

[0014] The semiconductor device 1 includes a semiconductor substrate 12, a source electrode 14, and a drain electrode 16. The source electrode 14 covers a part of the substrate top surface 12a of the semiconductor substrate 12. Further, as shown in FIG. A and FIG. 4, the drain electrode 16 covers the lower surface 12b of the semiconductor substrate 12.

[0015] The semiconductor substrate 12 mainly includes a drain layer 42, a drift layer 41, a super junction layer (SJ layer) 60, an electric field relaxation layer 50, an n-type layer 54, a drift layer 40, a body region 34, a contact region 32, and a source region 30.

[0016] The drain layer 42 is an n-type region. The drain layer 42 is in ohmic contact with the drain electrode 16 on the lower surface 12b of the semiconductor substrate 12. The drift layer 41 is disposed in contact with the top surface of the drain layer 42. In this embodiment, the drift layer 41 is an n-type region having an n-type impurity concentration lower than that of the drain layer 42.

[0017] The SJ layer 60 is disposed in contact with the top surface of the drift layer 41. The SJ layer 60 includes n-type first columns 61 extending in the x-direction and p-type second columns 62 extending in the x-direction. The plurality of first columns 61 and the plurality of second columns 62 are arranged alternately and repeatedly along the y-direction. That is, the SJ layer 60 has a stripe shape.

[0018] Multiple field relaxation layers 50 are arranged in contact with the upper surface of the SJ layer 60 and below the multiple trenches 20T. The planar structure of the field relaxation layer 50 will be explained using Figure 5. Figure 5 is a cross-sectional view along the VV line in Figure 3. Figure 5 is a cross-sectional view in the plane passing through the trenches 20T. In other words, Figure 5 is a view of the field relaxation layer 50 from vertically upward. In Figure 5, the field relaxation layer 50 is shown by a dotted line. For clarity, the gate insulating film 20a and gate electrode 20b are omitted from the description.

[0019] Each of the multiple field relaxation layers 50 comprises multiple first portions 50a and multiple second portions 50b. The first portions 50a are portions that extend continuously in the x-direction and are spaced apart in the y-direction. The first portions 50a overlap with the first trench 20T1 and the second trench 20T2. The second portions 50b are portions that extend continuously in the y-direction and are spaced apart in the x-direction. In other words, the field relaxation layers 50 have a grid shape. An n-type semiconductor layer, an n-type layer 54, is placed between adjacent field relaxation layers 50. The field relaxation layers 50 are connected to the source electrode 14 via connection regions and contact regions 32 (not shown).

[0020] The drift layer 40 is located in contact with the upper surfaces of the field relaxation layer 50 and the n-type layer 54. The drift layer 40 is also distributed across the lower parts of multiple trenches 20T and is in contact with the lower parts of the trenches 20T. The drift layer 40 is an n-type region having a lower n-type impurity concentration than the source region 30. The body region 34 is in contact with the upper surface of the drift layer 40. The body region 34 is a p-type region.

[0021] Multiple source regions 30 are located above the body region 34 and are exposed on the upper surface 12a of the substrate. The source regions 30 are separated from the drift layer 40 by the body region 34. Each source region 30 is an n-type region having a higher impurity concentration than the drift layer 40. Each source region 30 is located in an inter-trench region, which is a region sandwiched between multiple trenches 20T. Each source region 30 is in contact with the gate insulating film 20a at the upper end of the side surface of the trench 20T. Each source region 30 extends linearly along the y direction. A silicide layer 30S (not shown) is provided at the contact interface between each source region 30 and the source electrode 14. The silicide layer 30S is a Ti-containing layer.

[0022] Multiple contact regions 32 are located in the inter-trench region. Each contact region 32 is a p-type region having a higher impurity concentration than the body region 34. Source regions 30 are adjacent to the ±x-direction sides of the contact regions 32. Each contact region 32 extends linearly along the y-direction and is exposed on the upper surface 12a of the substrate. A silicide layer 32S (not shown) is provided at the contact interface between each contact region 32 and the source electrode 14. The silicide layer 32S is a Ti-containing layer.

[0023] In the element region 10, the contact region 32 and the source region 30 are in contact with the side surfaces of the first trench 20T1 and the second trench 20T2. On the other hand, the contact region 32 is in contact with the side surface of the wide region WA of the second trench 20T2, but the source region 30 is not. This allows the wide region WA to be placed in a region where the source region 30 does not exist (i.e., a region where no device structure is formed).

[0024] As shown in Figure 2, a plurality of trenches 20T are provided on the upper surface 12a of the semiconductor substrate 12. Each of the plurality of trenches 20T extends continuously in the x direction and is spaced apart in the y direction. The plurality of trenches 20T includes a plurality of first trenches 20T1 and a plurality of second trenches 20T2. The first trenches 20T1 are insulated from the source electrode 14 and are configured to allow the application of a gate voltage. The second trenches 20T2 are electrically connected to the source electrode 14 and are configured to allow the application of a source voltage. The regularity of the arrangement of the first trenches 20T1 and the second trenches 20T2 in the y direction can vary. In this embodiment, the first trenches 20T1 and the second trenches 20T2 are arranged alternately, one at a time. That is, the arrangement ratio of the first trenches 20T1 and the second trenches 20T2 is "1:1".

[0025] The first trench 20T1 has a constant first width W1 along its entire length in the x-direction. The second trench 20T2 extends across the element region 10 and the peripheral region 11. In the element region 10, the second trench 20T2 has a constant first width W1. In the peripheral region 11, the second trench 20T2 has a wide region WA. The wide region WA has a second width W2. The second width W2 is larger than the first width W1.

[0026] The first trench 20T1 has its first end E11 on the +x side (right side in Figure 2). The second trench 20T2 has its first end E21 on the +x side. The first end E21 of the second trench protrudes further in the +x direction than the first end E11 of the first trench. The wide region WA is located further in the +x direction than the first end E11 of the first trench. This allows the wide region WA to be placed in a region where the first trench 20T1 to which the gate voltage is applied does not exist (i.e., a region where no device structure is formed).

[0027] The first trench 20T1 has a second end E12 on the -x side (left side in Figure 2). The second trench 20T2 has a second end E22 on the -x side. The second end E12 of the first trench protrudes further in the -x direction than the second end E22 of the second trench. The second end E12 of the first trench is electrically connected to the gate electrode lead-out 24. This allows a gate voltage to be applied to the gate electrode 20b in the first trench 20T1. Furthermore, because the second end E22 of the second trench is located further in the +x direction than the second end E12 of the first trench, insulation between the second trench 20T2 and the gate electrode lead-out 24 can be ensured.

[0028] Figure 3 illustrates the cross-sectional structure of the trench 20T in the element region 10. The trench 20T extends from the upper surface 12a of the substrate toward the depths. The trench 20T penetrates the source region 30 and the body region 34 and reaches the drift layer 40. The trench 20T has a first width W1. Inside the trench 20T are the gate insulating film 20a, the gate electrode 20b, and the upper insulating film 20c. The gate insulating film 20a covers the inner surface of the trench 20T. The gate electrode 20b is positioned within the gate insulating film 20a. The gate electrode 20b is insulated from the semiconductor substrate 12 by the gate insulating film 20a. The gate electrode 20b faces the body region 34 and the source region 30 via the gate insulating film 20a. The gate electrode 20b faces the body region 34, which separates the drift layer 40 from the source region 30, via the gate insulating film 20a. Various materials can be used for the gate electrode 20b. In this embodiment, the gate electrode 20b is made of polysilicon.

[0029] The upper surface of the gate electrode 20b is covered by the upper insulating film 20c. The upper insulating film 20c is embedded inside the trench 20T. That is, no insulating film is placed on the upper surface 12a of the substrate. The gate electrode 20b is insulated from the source electrode 14 by the upper insulating film 20c.

[0030] Figure 4 illustrates the cross-sectional structure of the second trench 20T2 in the wide region WA. The wide region WA has a second width W2. In the wide region WA, the gate electrode 20b is positioned to cover the inner wall and bottom surface of the second trench 20T2. Therefore, the gate electrode 20b has a shape (groove shape TR2) with a depression in the center in the width direction. The upper insulating film 20c covers the sides of the groove shape TR2 of the gate electrode 20b, but does not cover the bottom surface of the groove shape TR2. That is, an opening AP of the upper insulating film 20c is provided at the bottom surface of the groove shape TR2. A source electrode 14 is positioned inside the groove shape TR2 of the gate electrode 20b. The source electrode 14 is in contact with the gate electrode 20b through the opening AP. As a result, the source electrode 14 and the gate electrode 20b are electrically connected in the wide region WA. A source voltage can be applied to the gate electrode 20b in the second trench 20T2. A silicide layer 20bS (not shown) is provided at the contact interface between the gate electrode 20b and the source electrode 14.

[0031] (Operation of semiconductor device 1) The semiconductor device 1 is used with a potential higher than that applied to the source electrode 14 applied to the drain electrode 16. When a potential higher than the gate threshold is applied to the gate electrode 20b, a channel is formed in the area of ​​the body region 34 adjacent to the gate insulating film 20a. The channel connects the source region 30 and the drift layer 40. Then, electrons flow from the source electrode 14 to the drift layer 40 via the source region 30 and the channel. The electrons that flow into the drift layer 40 flow to the drain electrode 16 via the n-type layer 54, the first column 61, the drift layer 41, and the drain layer 42.

[0032] When the potential of the gate electrode 20b is reduced to a potential below the gate threshold, the channel disappears and the semiconductor device 1 turns off. In the SJ layer 60, multiple first columns 61 and multiple second columns 62 are substantially completely depleted, and a wide area of ​​the SJ layer 60 is depleted. In addition, the electric field distribution of the SJ layer 60 is leveled in the depth direction. As a result, the SJ layer 60 can bear a large potential difference, and the semiconductor device 1 can have the characteristic of high breakdown voltage.

[0033] Furthermore, when the semiconductor device 1 is turned off, the potentials of the n-type layer 54 and the drift layer 40 rise. Since the field relaxation layer 50 is connected to the source electrode 14 via a connection region (not shown) and a contact region 32, the field relaxation layer 50 has approximately the same potential as the source electrode 14. Therefore, when the potentials of the n-type layer 54 and the drift layer 40 rise, a reverse voltage is applied to the pn junction interface between the n-type layer 54 and the field relaxation layer 50, and to the pn junction interface between the drift layer 40 and the field relaxation layer 50. Consequently, a depletion layer spreads from the field relaxation layer 50 to the n-type layer 54 and the drift layer 40. This spreading of the depletion layer can suppress the electric field generated at the lower end of the trench 20T. In particular, the first portion 50a of the field relaxation layer 50 is arranged to overlap with the first trench 20T1 (see Figure 5). The first portion 50a makes it possible to effectively suppress the electric field generated at the lower end of the first trench 20T1.

[0034] (Method of manufacturing semiconductor device 1) Referring to Figures 6 to 8, the process of forming the gate electrode 20b, the upper insulating film 20c, and the source electrode 14 in the manufacturing method of the semiconductor device 1 will be described. Figures 6(A) to 8(A) are cross-sectional views of the same area as in Figure 3, and are cross-sectional views of the element region 10. Figures 6(B) to 8(B) are cross-sectional views of the same area as in Figure 4, and are cross-sectional views of the wide region WA. Note that in Figures 6 to 8, only the structure above the drift layer 40 is shown. Furthermore, other processes for manufacturing the semiconductor device 1 can be described by utilizing known manufacturing techniques.

[0035] First, a semiconductor substrate 12 as shown in Figure 6 is prepared. In this semiconductor substrate 12, a first trench 20T1 and a second trench 20T2 having a first width W1 are formed in the element region 10 (see Figure 6(A)). In addition, a second trench 20T2 having a second width W2 is formed in the wide region WA (see Figure 6(B)). A gate insulating film 20a is deposited on the entire inner walls of the first trench 20T1 and the second trench 20T2, and on the entire upper surface 12a of the substrate.

[0036] A gate electrode material 21 (polysilicon) is deposited on this semiconductor substrate 12. In Figure 6, the gate electrode material 21 after deposition is shown by a dotted line. In the device region 10 (Figure 6(A)), the first trench 20T1 and the second trench 20T2 have a relatively narrow first width W1, so the upper surface of the gate electrode material 21 is almost flat. On the other hand, in the wide region WA (Figure 6(B)), the second trench 20T2 has a relatively wide second width W2, so the shape of the trench is transferred to the upper surface of the gate electrode material 21. Therefore, the gate electrode material 21 has a shape with a depression in the center in the width direction (groove shape TR1).

[0037] Next, the gate electrode material 21 is etched back (see Figure 6, arrow Y1). This allows the gate electrode material 21 to be processed into a gate electrode 20b. Various etching methods can be used for etch-back. In this embodiment, anisotropic etching by dry etching was performed. In the element region 10 (Figure 6(A)), the upper surface of the gate electrode 20b is almost flat. On the other hand, in the wide region WA (Figure 6(B)), the groove shape TR1 is transferred by etch-back, so a groove shape TR2 is formed on the gate electrode 20b. In the central part where the groove shape TR2 is formed, the gate electrode 20b has a thickness TH1. On the other hand, at the ends where the groove shape TR2 is not formed, the gate electrode 20b has a thickness TH2. Thickness TH1 is thinner than TH2.

[0038] By depositing an insulating film 22 on the structure shown in Figure 6, the state shown in Figure 7 is achieved. In the element region 10 (Figure 7(A)), the upper surface of the insulating film 22 is almost flat. On the other hand, in the wide region WA (Figure 7(B)), since the gate electrode 20b has a groove shape TR2, the shape of the groove shape TR2 is transferred to the upper surface of the insulating film 22. Therefore, the insulating film 22 has a shape in which the center in the width direction is recessed (groove shape TR3).

[0039] Next, the insulating film 22 is etched back. Various etching methods can be used for etching back. Figure 8 shows the structure after etching back. In the element region 10 (Figure 8(A)), the insulating film 22 and gate insulating film 20a on the substrate upper surface 12a are removed. Therefore, the upper insulating film 20c can be formed on the upper part of the first trench 20T1 and the second trench 20T2. On the other hand, in the wide region WA (Figure 8(B)), since the insulating film 22 has a groove shape TR3, the shape of the groove shape TR3 is transferred to the upper insulating film 20c after etching back. That is, the upper insulating film 20c of the wide region WA covers the side surface of the groove shape TR2 of the gate electrode 20b, but does not cover the bottom surface of the groove shape TR2. This allows an opening AP to be formed in the upper insulating film 20c.

[0040] A source electrode 14 is deposited on the structure shown in Figure 8. The source electrode 14 has a laminated structure of a barrier metal containing Ti and a metal layer. After that, an annealing treatment is performed. As a result, a silicide layer 30S is formed at the contact interface between the source region 30 and the source electrode 14. Also, a silicide layer 32S is formed at the contact interface between the contact region 32 and the source electrode 14. Furthermore, a silicide layer 20bS is formed at the contact interface between the gate electrode 20b exposed in the opening AP and the source electrode 14.

[0041] The silicide layers 30S, 32S, and 20bS are Ti-containing layers. Furthermore, it is preferable that the silicide layers 30S, 32S, and 20bS do not contain Ni. The reason is as follows: The technology described herein features a connection between the source electrode 14 and the gate electrode 20b at the opening AP. If the gate electrode 20b is made of polysilicon, and the barrier metal of the source electrode 14 contains Ni, then the polysilicon may be drawn up by the silicide Ni, causing delamination. Therefore, in the technology described herein, the barrier metal of the source electrode 14 has a structure that contains Ti but does not contain Ni. This makes it possible to reliably ensure contact between the source electrode 14 and the gate electrode 20b.

[0042] As explained above, in a wide region WA having a second width W2, the entire insulating film 22 can be etched back to selectively expose only the gate electrode 20b (Figure 8(B)). The source electrode 14 can be connected to the gate electrode 20b inside the second trench 20T2 without using a photomask. In other words, a self-aligned connection structure between the source and gate can be realized in a wide region WA.

[0043] (Challenges and effects) In trench-gate semiconductor devices, reducing the pitch between trenches (narrowing the pitch) lowers the on-resistance, enabling chip miniaturization and cost reduction. However, narrowing the pitch increases the density of trench gates, thus increasing gate capacitance. As a result, drive losses increase. In other words, there is a trade-off between the reduction in on-resistance due to narrowing the pitch and the increase in drive losses. Therefore, the gate capacitance needs to be appropriately changed depending on the system being used. Specifically, it is necessary to be able to freely set the arrangement ratio of wide trenches with a self-aligned connection structure.

[0044] The problem will be explained using the comparative example semiconductor device 101 shown in Figure 9. Figure 9 is a top view similar to Figure 2 described above. Common parts in the comparative example semiconductor device 101 (Figure 9) and the semiconductor device 1 of this embodiment (Figure 2) are given the same reference numerals, and their explanation will be omitted. In the comparative example semiconductor device 101, the second trench 20T2 has a second width W2 along its entire length in the x direction. That is, the width of the second trench 20T2 is increased within the element region 10. As a result, the number of trenches that can be placed within the element region 10 decreases, which leads to a problem of increased on-resistance. In addition, if the arrangement ratio or position of the second trench 20T2 is changed within the element region 10, the aperture ratio within the element region 10 changes. Therefore, there is a problem that the manufacturing process needs to be reconditioned (e.g., dry etching conditions, film deposition conditions).

[0045] The effects of the technology described herein are explained. In the technology described herein, a wide region WA is provided only in a portion of the entire length of the second trench 20T2. Specifically, the wide region WA is located in the second trench 20T2 in the peripheral region 11 (see Figure 2). The self-aligned connection structure described above can be formed in the wide region WA. This suppresses the expansion of the trench width within the element region 10. Compared to the comparative example semiconductor device 101 (Figure 9), the number of trenches that can be placed within the element region 10 can be increased, thus reducing the on-resistance. Furthermore, if the arrangement ratio of the second trench 20T2 is to be changed, only the arrangement ratio of the wide region WA in the peripheral region 11 needs to be changed. Since the arrangement of trenches within the element region 10 does not change, there is no need to change the design of the element region 10. This makes it possible to reduce the design cost of the semiconductor device 1 and eliminate the need to recondition the manufacturing process. [Examples]

[0046] Example 2 describes a configuration in which N first trenches 20T1 and M second trenches 20T2 are alternately arranged in the y direction. Here, N and M are natural numbers greater than or equal to 1.

[0047] A first trench arrangement example is described. The first arrangement example is one in which multiple first trenches 20T1 are arranged between one second trench 20T2. Figure 10 shows an example of the first arrangement example. Figure 10 is a top view similar to Figure 2. In Figure 10, two first trenches 20T1 are arranged between one second trench 20T2. That is, the arrangement ratio of first trenches 20T1 to second trenches 20T2 is "2:1". In the first arrangement example, the higher the arrangement ratio of first trenches 20T1, the higher the arrangement density of trench gates can be, making it possible to reduce the on-resistance of the semiconductor device 1.

[0048] A second trench arrangement example will be described. The second arrangement example is one in which multiple second trenches 20T2 are arranged between one first trench 20T1. Figure 11 shows an example of the second arrangement example. In Figure 11, two second trenches 20T2 are arranged between one first trench 20T1. That is, the arrangement ratio of the first trench 20T1 to the second trenches 20T2 is "1:2". In the first arrangement example, the gate capacitance can be reduced as the arrangement ratio of the second trenches 20T2 increases, and thus the drive loss of the semiconductor device 1 can be reduced.

[0049] (Modified version of Example 2) The description has described the case where the arrangement ratio of the first trench 20T1 and the second trench 20T2 is the same throughout the entire chip of the semiconductor device 1, but the invention is not limited to this configuration. The arrangement ratio may be different for each region of the chip. This will be explained in detail. The first trench 20T1 generates more heat than the second trench 20T2. This is because the first trench 20T1 controls the current, while the second trench 20T2 does not. As a result, the heat distribution within the chip region can be controlled by adjusting the arrangement ratio of the second trench 20T2.

[0050] For example, the arrangement ratio of the first trench 20T1 may be higher in the outer periphery of the chip than in the inner periphery of the chip. By placing areas with high heat generation in the outer periphery of the chip, where heat is less likely to accumulate and heat dissipation is higher, it becomes possible to suppress warping of the semiconductor device 1 and improve its heat resistance.

[0051] (modified version) The following describes possible modifications that can be used in each of the above embodiments.

[0052] The wide-area WA is not limited to being placed in the peripheral area 11, but may also be placed within the element area 10.

[0053] The layout of the first trench 20T1, the second trench 20T2, the wide area WA, and the gate electrode lead-out section 24 shown in Figure 2 is an example and is not limited to this configuration.

[0054] The configuration of the technology disclosed herein is listed below. [Configuration 1] A semiconductor device (1) comprising a semiconductor substrate (12), an upper electrode (14) provided on the upper surface of the semiconductor substrate, and a lower electrode (16) provided on the lower surface of the semiconductor substrate, The aforementioned semiconductor substrate is A plurality of trenches (20T) are arranged on the upper surface (12a) of the semiconductor substrate, the trenches extending linearly in a first direction (x) and spaced apart in a second direction (y) intersecting the first direction, The gate insulating film (20a) covering the inner surface of the trench, A gate electrode (20b) is disposed within the trench and is insulated from the semiconductor substrate by the gate insulating film, The source region (30) of the first conductivity type (n) is located in the inter-trench region, which is the region sandwiched between the multiple trenches, and is exposed on the upper surface of the semiconductor substrate. A body region (34) of the second conductivity type (p) is located in the trench region and is positioned below the source region, A drift region (40) of the first conductivity type (n) is distributed across the lower parts of multiple trenches, is in contact with the lower surface of the body region and is in contact with the lower part of the trench, It is equipped with, Multiple trenches, Multiple first trenches (20T1) are insulated from the upper electrode and configured to allow the application of a first voltage (gate voltage), Multiple second trenches (20T2) are electrically connected to the upper electrode and configured to allow the application of a second voltage (source voltage) different from the first voltage, It includes, The first trench has a constant first width (W1) along its entire length in the first direction. The second trench has a wide region (WA) in a portion of its total length in the first direction, having a second width (W2) that is greater than the first width. In the aforementioned wide region, the upper electrode and the gate electrode are in contact. Semiconductor equipment. [Configuration 2] The semiconductor substrate has an element region (10) on which a device structure is formed, and a peripheral region (11) provided around the element region where the device structure is not formed. The second trench extends across the element region and the peripheral region, The wide region is the semiconductor device according to configuration 1, which is located in the peripheral region. [Configuration 3] The semiconductor substrate further comprises a second conductivity type contact region (32) which is positioned on the upper surface of the semiconductor substrate and is in contact with the upper electrode. In the element region, the contact region and the source region are in contact with the side surfaces of the first trench and the second trench, The semiconductor device according to configuration 2, wherein the contact area is in contact with the side surface of the wide area of ​​the second trench, but the source area is not in contact with it. [Structure 4] The first trench has a first trench end (E11) on one side (+x) in the first direction, The second trench has a first end (E21) of the second trench on one side in the first direction. The first end of the second trench protrudes further in one direction than the first end of the first trench. The semiconductor device according to any one of configurations 1-3, wherein the wide region is located on one side in the first direction relative to the first end of the first trench. [Composition 5] The first trench has a second end (E12) of the first trench on the other side (-x) in the first direction, The second trench has a second end (E22) on the other side in the first direction, The second end of the first trench protrudes further in the other direction than the second end of the second trench. The semiconductor device according to any one of configurations 1-4, wherein the second end of the first trench is electrically connected to the supply unit (24) for the first voltage (gate voltage). [Composition 6] The first trench and the second trench further include an insulating film (20c) positioned above the gate electrode, In the aforementioned wide region, the insulating film is provided with an opening (AP), A semiconductor device according to any one of configurations 1 to 5, wherein the upper electrode and the gate electrode are in contact through the opening. [Composition 7] The semiconductor device according to configuration 6, wherein the insulating film is not disposed on the upper surface of the semiconductor substrate. [Structure 8] N of the first trenches and M of the second trenches are arranged alternately in the second direction. N and M are natural numbers greater than or equal to 1. A semiconductor device described in any one of configurations 1-7, wherein the values ​​of N and M are different. [Composition 9] The aforementioned gate electrode contains polysilicon, A semiconductor device according to any one of configurations 1-8, wherein a silicide layer containing Ti is present at the contact interface between the upper electrode and the upper surface of the semiconductor substrate, and at the contact interface between the upper electrode and the gate electrode in the wide region. [Configuration 10] The semiconductor substrate further comprises a plurality of second conductivity type (p-type) field relaxation layers (50) arranged below the plurality of trenches, A semiconductor device according to any one of configurations 1-9, wherein a first conductivity type semiconductor layer (54) is arranged between adjacent electric field relaxation layers. [Composition 11] Each of the aforementioned electric field relaxation layers has a first portion (50a) that extends continuously in the first direction and a second portion (50b) that extends continuously in the second direction. The semiconductor device according to configuration 10, wherein, in a vertical upward view of the upper surface of the semiconductor substrate, at least a portion of the first part overlaps with the first trench. [Composition 12] The semiconductor substrate further comprises a superjunction layer (60) located below the plurality of electric field relaxation layers, The semiconductor device according to configuration 10 or 11, wherein in the superjunction layer, a first column (61) of a first conductivity type (n type) extending in a third direction (x) and a second column (62) of a second conductivity type (p type) extending in the third direction are alternately and repeatedly arranged along a fourth direction (y) intersecting the third direction.

[0055] According to configuration 2, when changing the arrangement of the second trench, it is not necessary to change the design of the element region. This makes it possible to reduce the design cost of the semiconductor device.

[0056] According to configuration 3, the wide region can be placed in a region where the source region does not exist (i.e., a region where the device structure is not formed).

[0057] According to configuration 4, the wide region can be placed in a region where there is no first trench to which the first voltage is applied (i.e., a region where no device structure is formed).

[0058] According to configuration 5, a gate voltage can be applied to the gate electrode in the first trench.

[0059] According to configuration 6, a source voltage can be applied to the gate electrode in the second trench.

[0060] According to configuration 8, the arrangement ratio of the first trench and the second trench can be arbitrarily adjusted.

[0061] According to configuration 9, it is possible to suppress the absorption of the polysilicon of the gate electrode into the silicide.

[0062] According to configuration 10, it is possible to improve the voltage withstand capability of the semiconductor device.

[0063] According to configuration 11, an electric field relaxation layer can be placed directly below the first trench, extending along the entire length of the first trench. This makes it possible to enhance the electric field relaxation effect in the first trench.

[0064] According to configuration 12, a wide area of ​​the superjunction layer can be depleted when the semiconductor device is turned off. This makes it possible to increase the voltage resistance of the semiconductor device.

[0065] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0066] 1: Semiconductor device 12: Semiconductor substrate 12a: Top surface of substrate 14: Source electrode 16: Drain electrode 20a: Gate insulating film 20b: Gate electrode 20c: Top insulating film 20T: Trench 20T1: First trench 20T2: Second trench 30: Source region 34: Body region 40: Drift layer W1: First width W2: Second width WA: Wide region

Claims

1. A semiconductor device (1) comprising a semiconductor substrate (12), an upper electrode (14) provided on the upper surface of the semiconductor substrate, and a lower electrode (16) provided on the lower surface of the semiconductor substrate, The aforementioned semiconductor substrate is A plurality of trenches (20T) arranged on the upper surface (12a) of the semiconductor substrate, the plurality of trenches extending linearly in a first direction (x) and spaced apart in a second direction (y) intersecting the first direction, The gate insulating film (20a) covering the inner surface of the trench, A gate electrode (20b) is disposed within the trench and is insulated from the semiconductor substrate by the gate insulating film, The source region (30) of the first conductivity type (n) is located in the inter-trench region, which is the region sandwiched between the multiple trenches, and is exposed on the upper surface of the semiconductor substrate. A body region (34) of the second conductivity type (p) is located in the trench region and is positioned below the source region, A drift region (40) of the first conductivity type (n) is distributed across the lower parts of multiple trenches, is in contact with the lower surface of the body region and is in contact with the lower part of the trench, It is equipped with, Multiple trenches, A plurality of first trenches (20T1) are insulated from the upper electrode and configured to allow the application of a first voltage (gate voltage), Multiple second trenches (20T2) are electrically connected to the upper electrode and configured to allow the application of a second voltage (source voltage) different from the first voltage, It includes, The first trench has a constant first width (W1) along its entire length in the first direction. The second trench has a wide region (WA) in a portion of its total length in the first direction, having a second width (W2) that is greater than the first width. In the aforementioned wide region, the upper electrode and the gate electrode are in contact. Semiconductor equipment.

2. The semiconductor substrate has an element region (10) on which a device structure is formed, and a peripheral region (11) provided around the element region where the device structure is not formed. The second trench extends across the element region and the peripheral region, The semiconductor device according to claim 1, wherein the wide region is located in the peripheral region.

3. The semiconductor substrate further comprises a second conductivity type contact region (32) which is positioned on the upper surface of the semiconductor substrate and is in contact with the upper electrode. In the element region, the contact region and the source region are in contact with the side surfaces of the first trench and the second trench, The semiconductor device according to claim 2, wherein the contact area is in contact with the side surface of the wide area of ​​the second trench, but the source area is not in contact with it.

4. The first trench has a first trench end (E11) on one side (+x) in the first direction, The second trench has a first end (E21) of the second trench on one side in the first direction. The first end of the second trench protrudes further in one direction than the first end of the first trench. The semiconductor device according to claim 1, wherein the wide region is located on one side in the first direction than the first end of the first trench.

5. The first trench has a second end (E12) of the first trench on the other side (-x) in the first direction. The second trench has a second end (E22) on the other side in the first direction, The second end of the first trench protrudes further in the other direction than the second end of the second trench. The semiconductor device according to claim 1, wherein the second end of the first trench is electrically connected to the supply unit (24) for the first voltage (gate voltage).

6. The first trench and the second trench further include an insulating film (20c) positioned above the gate electrode, In the aforementioned wide region, the insulating film is provided with an opening (AP), The semiconductor device according to claim 1, wherein the upper electrode and the gate electrode are in contact through the opening.

7. The semiconductor device according to claim 6, wherein the insulating film is not disposed on the upper surface of the semiconductor substrate.

8. N first trenches and M second trenches are arranged alternately in the second direction. N and M are natural numbers greater than or equal to 1. The semiconductor device according to claim 1, wherein the values ​​of N and M are different.

9. The aforementioned gate electrode contains polysilicon, A silicide layer containing Ti is present at the contact interface between the upper electrode and the upper surface of the semiconductor substrate, and at the contact interface between the upper electrode and the gate electrode in the wide region, according to claim 1.

10. The semiconductor substrate further comprises a plurality of second conductivity type (p-type) field relaxation layers (50) arranged below the plurality of trenches, The semiconductor device according to claim 1, wherein a first conductivity type semiconductor layer (54) is disposed between adjacent electric field relaxation layers.

11. Each of the aforementioned electric field relaxation layers has a first portion (50a) that extends continuously in the first direction and a second portion (50b) that extends continuously in the second direction. The semiconductor device according to claim 10, wherein, in a vertical upward view of the upper surface of the semiconductor substrate, at least a portion of the first portion overlaps with the first trench.

12. The semiconductor substrate further comprises a superjunction layer (60) located below the plurality of electric field relaxation layers, The semiconductor device according to claim 10, wherein in the superjunction layer, a first column (61) of a first conductivity type (n type) extending in a third direction (x) and a second column (62) of a second conductivity type (p type) extending in the third direction are alternately and repeatedly arranged along a fourth direction (y) intersecting the third direction.

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