Semiconductor equipment

Abstract

This helps to prevent connection problems from occurring. [Solution] The cathode layer and the anode layer are arranged along a first direction, the cathode layer is positioned to include a position facing the drain wiring portion 71 in the stacking direction of the support substrate and the component substrate, the anode layer is positioned to include a position facing the source wiring portion 61 in the stacking direction, the source through via 91c is positioned to connect the source wiring portion 60 and the anode layer, and the drain through via 92c is positioned to connect the drain wiring portion 70 and the cathode layer.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device equipped with a high electron mobility transistor (HEMT). [Background technology]

[0002] Conventionally, semiconductor devices in which HEMTs are formed using nitride semiconductor layers have been proposed. However, HEMTs do not have parasitic diodes composed of n-type and p-type layers. Therefore, semiconductor devices in which only HEMTs are formed have low avalanche withstand capability.

[0003] Therefore, for example, Non-Patent Document 1 proposes a semiconductor device in which a semiconductor substrate is constructed by laminating a nitride semiconductor layer on a support substrate having a silicon carbide layer, a diode having a p-type anode layer and an n-type cathode layer is formed on the silicon carbide layer, and a HEMT is formed on the nitride semiconductor layer (see, for example, Non-Patent Document 1).

[0004] Specifically, in this semiconductor device, a gallium nitride (hereinafter also referred to as GaN) layer and an aluminum gallium nitride (hereinafter also referred to as AlGaN) layer are stacked as a nitride semiconductor layer, and a two-dimensional electron gas layer is induced on the GaN layer side of the AlGaN / GaN interface. On the nitride semiconductor layer, if one direction in the plane direction of the semiconductor substrate is defined as the first direction and the direction intersecting the first direction is defined as the second direction, then the source electrode and drain electrode, with the first direction being the longitudinal direction, are arranged in the second direction. The anode layer and cathode layer formed in the silicon carbide layer are arranged in the second direction such that the anode layer faces the source electrode and the cathode layer faces the drain electrode. The anode layer is connected to the source electrode through a source through-via formed in the nitride semiconductor layer. The cathode layer is connected to the drain electrode through a drain through-via formed in the nitride semiconductor layer. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] A. Nakajima, H. Hirai, Y. Miura, and S. Harada, “1.2 kV GaN / SiC-based Hybrid High Electron Mobility Transistor with Non-destructive Breakdown”, IEDM Tech. Dig., 2021, P778 [Overview of the project] [Problems that the invention aims to solve]

[0006] Incidentally, the present inventors have been studying a semiconductor device that can handle high currents, in which the source electrode is configured to include a comb-shaped source comb electrode and the drain electrode is configured to include a comb-shaped drain comb electrode, and in a second direction, the source comb electrode and the drain electrode are arranged alternately. In this case, when a diode is formed in the silicon carbide layer as described above, the anode layer and cathode layer are formed such that the anode layer is formed at a position facing each source comb electrode and the cathode layer is formed at a position facing each drain comb electrode. In other words, the anode layer and cathode layer are formed alternately and repeatedly in the second direction. Each anode layer is connected to each source comb electrode through a source through via, and each cathode layer is connected to each drain comb electrode through a drain through via.

[0007] In such semiconductor devices, the source electrode includes a comb-shaped source comb electrode, and the drain electrode also includes a comb-shaped drain comb electrode. This tends to make the semiconductor device larger, and thus more susceptible to the effects of warping and distortion. Consequently, misalignment can occur between the source comb electrode and anode layer and the drain comb electrode and anode layer, potentially leading to connection failures. While it might be possible to address this misalignment by increasing the width of the source and drain comb electrodes in the second direction, this configuration reduces the area in which the HEMT actually operates.

[0008] This disclosure aims to provide a semiconductor device that can suppress the occurrence of connection failures. [Means for solving the problem]

[0009] According to one aspect of this disclosure, the semiconductor device includes a support substrate (10) including a silicon layer (13) on which a diode is formed, comprising a cathode layer (132) of a first conductivity type and an anode layer (131) of a second conductivity type; a component substrate (20) including a first semiconductor layer (22) disposed on the support substrate and composed of a first GaN-based semiconductor constituting a drift region, and a second semiconductor layer (23) disposed on the first semiconductor layer and composed of a second GaN-based semiconductor having a larger bandgap energy than the first GaN-based semiconductor; and a source electrode (60) having a source wiring portion (61) disposed on the second semiconductor layer and extending in the second direction, and a plurality of source comb-tooth electrodes (62) protruding from the source wiring portion in the first direction, with one direction in the planar direction of the component substrate being the first direction and the direction intersecting the first direction being the second direction; a drain wiring portion (71) disposed on the second semiconductor layer and extending in the second direction, and protruding in one direction from the drain wiring portion in the second direction The device comprises a drain electrode (70) having a plurality of drain comb electrodes (72) arranged alternately with source comb electrodes, a gate electrode (80) having a gate comb electrode (82) arranged between source comb electrodes and drain comb electrodes in a second direction, a source through via (91c) formed on the component substrate and electrically connecting the anode layer and the source electrode, and a drain through via (92c) formed on the component substrate and electrically connecting the cathode layer and the drain electrode, wherein the cathode layer and the anode layer are arranged along a first direction, the cathode layer is arranged to include a position facing the drain wiring portion in the stacking direction of the support substrate and the component substrate, the anode layer is arranged to include a position facing the source wiring portion in the stacking direction, the source through via is arranged to connect the source wiring portion and the anode layer, and the drain through via is arranged to connect the drain wiring portion and the cathode layer.

[0010] According to this, the anode layer and the cathode layer are arranged along a first direction intersecting the arrangement direction of the source comb-tooth electrodes and the drain comb-tooth electrodes. The through via for the anode layer is arranged to connect the source wiring portion and the anode layer. The through via for the cathode layer is arranged to connect the drain wiring portion and the cathode layer. For this reason, the connectable region of the source electrode connected to the through via for the anode layer and the anode layer is widened, and the connectable region of the drain electrode connected to the through via for the cathode layer and the cathode layer is widened. Therefore, the occurrence of connection defects can be suppressed.

[0011] Note that the reference numerals in parentheses attached to the respective components and the like indicate an example of the correspondence between the components and the like and the specific components and the like described in the embodiments to be described later. Brief Description of the Drawings

[0012] [Figure 1] It is a plan view of the semiconductor device in the first embodiment. [Figure 2] It is a cross-sectional view taken along the line II-II in Figure 1. [Figure 3A] It is a cross-sectional view taken along the line IIIA-IIIA in Figure 1. [Figure 3B] It is a cross-sectional view taken along the line IIIB-IIIB in Figure 1. [Figure 4] It is an enlarged view of region IV in Figure 1. [Figure 5] It is a plan view of the support substrate. [Figure 6] It is a diagram for explaining a support wafer for manufacturing a semiconductor device. [Figure 7] It is a cross-sectional view of the semiconductor device in the second embodiment. [Figure 8] It is a cross-sectional view of the semiconductor device in the third embodiment. [Figure 9] It is a plan view of the support substrate in the fourth embodiment. Modes for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that in the respective following embodiments, portions that are identical or equivalent to each other are denoted by identical reference numerals in the description.

[0014] (First Embodiment) A semiconductor device according to the first embodiment will be described with reference to FIG. 1, FIG. 2, FIG. 3A, FIG. 3B, FIG. 4, and FIG. 5. Note that in FIG. 1, source comb electrodes 62, drain comb electrodes 72, gate comb electrodes 82 and the like, which will be described later, are omitted from illustration.

[0015] The semiconductor device of the present embodiment includes a semiconductor substrate 1 in which a support substrate 10 containing silicon and a constituent substrate 20 disposed on the support substrate 10 and provided with a HEMT are stacked. Hereinafter, the surface of the semiconductor substrate 1 on the support substrate 10 side is also referred to as the other surface 1b, and the surface of the semiconductor substrate 1 on the constituent substrate 20 side is also referred to as one surface 1a. Further, in the following description, the thickness (i.e., depth) direction of the semiconductor substrate 1 is defined as the z-axis direction, one direction parallel to the one surface 1a of the semiconductor substrate 1 (i.e., one direction orthogonal to the z-axis direction) is defined as the x-axis direction, and the direction orthogonal to both the x-axis direction and the z-axis direction is defined as the y-axis direction. The z-axis direction is also the normal direction to the one surface 1a of the semiconductor substrate 1, and is also the stacking direction of the support substrate 10 and the constituent substrate 20. The y-axis direction is also one direction in the plane direction of the constituent substrate 20, and may also be referred to as a first direction. The x-axis direction may also be referred to as a second direction, and the z-axis direction may also be referred to as a third direction. The semiconductor substrate 1 of the present embodiment has, for example, a planar rectangular shape, the length in the lateral direction is 5 mm as the length along the y-axis direction, and the length in the longitudinal direction is 6 mm as the length along the x-axis direction.

[0016] The constituent substrate 20 is configured by sequentially stacking a buffer layer 21, an undoped GaN layer 22, and an undoped AlGaN layer 23 along the z-axis direction. The buffer layer 21, the GaN layer 22, and the AlGaN layer 23 are each constituted by an epitaxial layer epitaxially grown on the support substrate 10.

[0017] The buffer layer 21 is composed of, for example, an undoped GaN layer. The buffer layer 21 is used to adjust the withstand voltage of the HEMT, and its thickness is adjusted as appropriate according to the required withstand voltage.

[0018] The GaN layer 22 and the AlGaN layer 23 are stacked in order, forming a heterojunction structure. In this embodiment, the semiconductor device uses the GaN layer 22 and the AlGaN layer 23 as channel-forming layers and operates by utilizing a two-dimensional electron gas layer 24 induced by the piezoelectric effect and spontaneous polarization effect on the GaN layer 22 side of the AlGaN / GaN interface.

[0019] Specifically, the GaN layer 22 constitutes the electron transport layer that operates as a drift region and corresponds to a first semiconductor layer made of a first GaN-based semiconductor material. The AlGaN layer 23 constitutes the electron supply layer and corresponds to a second semiconductor layer made of a second GaN-based semiconductor material and is composed of a GaN-based semiconductor material with a larger bandgap energy than the GaN-based semiconductor material that constitutes the GaN layer 22. As described above, the first semiconductor layer is composed of an undoped GaN layer and the second semiconductor layer is composed of an undoped AlGaN layer 23.

[0020] In this embodiment, the semiconductor device has an active layer region 30 in which a two-dimensional electron gas layer 24 is generated in the GaN layer 22 of the semiconductor substrate 1. That is, the active layer region 30 is the active region in which the HEMT operates. As shown in Figure 1, the active layer region 30 in this embodiment is rectangular in shape with the x-axis direction as the longitudinal direction.

[0021] Furthermore, in this embodiment, the semiconductor device has an element isolation region 40 that is different from the active layer region 30. The element isolation region 40 in this embodiment is arranged to surround the active layer region 30 and is electrically isolated from the active layer region 30. Specifically, the element isolation region 40 is formed by ion implantation of Ar ions and N ions into the GaN layer 22 and AlGaN layer 23 located in the element isolation region 40 to form the element isolation layer 41. In this embodiment, the element isolation region 40 is electrically isolated from the active layer region 30 in this way. Note that the element isolation layer 41 is formed to a depth greater than the two-dimensional electron gas layer 24 of the GaN layer 22, so as not to operate as a HEMT.

[0022] An interlayer insulating film 50 is formed on the AlGaN layer 23 (i.e., on one surface 1a of the semiconductor substrate 1), and a source electrode 60, a drain electrode 70, and a gate electrode 80 are arranged on the interlayer insulating film 50. The interlayer insulating film 50 is composed of, for example, an oxide film.

[0023] As shown in Figure 4, the source electrode 60 has a comb-like shape with a source wiring section 61 and a source comb-tooth electrode 62. The drain electrode 70 has a comb-like shape with a drain wiring section 71 and a drain comb-tooth electrode 72.

[0024] Specifically, the source wiring portion 61 of the source electrode 60 and the drain wiring portion 71 of the drain electrode 70 are arranged on the element isolation region 40 so as to face each other in the y-axis direction with the active layer region 30 in between, and extend in the x-axis direction. The source comb-shaped electrodes 62 protrude from the source wiring portion 61 toward the drain wiring portion 71 in the y-axis direction, and multiple electrodes are arranged at equal intervals in the x-axis direction. The drain comb-shaped electrodes 72 protrude from the drain wiring portion 71 toward the source wiring portion 61 in the y-axis direction, and multiple electrodes are arranged at equal intervals in the x-axis direction. The source comb-shaped electrodes 62 and the drain comb-shaped electrodes 72 are arranged on the active layer region 30 so as to interlock with each other's comb teeth.

[0025] Furthermore, since each source comb-tooth electrode 62 is positioned to protrude from one source wiring section 61, the width in the x-axis direction is made sufficiently longer than the width of the source comb-tooth electrode 62. Similarly, since each drain comb-tooth electrode 72 is positioned to protrude from one drain wiring section 71, the width in the x-axis direction is made sufficiently longer than the width of the drain comb-tooth electrode 72.

[0026] The source comb electrode 62 is electrically connected to the AlGaN layer 23 through a contact hole 51 formed in the interlayer insulating film 50. The drain comb electrode 72 is electrically connected to the AlGaN layer 23 through a contact hole 52 formed in the interlayer insulating film 50. The source comb electrode 62 (i.e., source electrode 60) and the drain comb electrode 72 (i.e., drain electrode 70) are made of an ohmic metal that makes ohmic contact with the AlGaN layer 23, for example, a Ti / Al layer.

[0027] In this embodiment, the source pad connected to the external circuit is formed from a part of the source wiring section 61. Similarly, the drain pad connected to the external circuit is formed from a part of the drain wiring section 71. However, the source pad may be located at a different location, extending from the source wiring section 61. Similarly, the drain pad may be located at a different location, extending from the drain wiring section 71.

[0028] The gate electrode 80 has a configuration comprising a gate wiring section 81, gate comb-tooth electrodes 82, and a gate pad section 83. In this embodiment, the gate pad section 83 is located at both ends of the source wiring section 61 in the x-axis direction. The gate wiring section 81 extends from the gate pad section 83 and is arranged to extend in the x-axis direction within the element isolation region 40. More specifically, when viewed from the z-axis direction, the gate wiring section 81 is located between the source wiring section 61 and the active layer region 30. Multiple gate comb-tooth electrodes 82 are arranged to protrude from the gate wiring section 81 toward the drain wiring section 71 in the y-axis direction, forming a comb-like shape. Each gate comb-tooth electrode 82 is located between the source comb-tooth electrode 62 and the drain comb-tooth electrode 72.

[0029] The gate comb electrode 82 is arranged on the AlGaN layer 23 via an interlayer insulating film 50. The gate comb electrode 82 (i.e., gate electrode 80) is composed of a Schottky electrode made of Ni, for example. An insulating film is appropriately placed between the gate electrode 80 and the source electrode 60 to electrically insulate them. The sum of the lengths of each gate comb electrode 82 in the y-axis direction is appropriately changed according to the required performance, for example, to 50 mm or more. When the sum of the lengths of each gate comb electrode 82 in the y-axis direction is 50 mm or more, for example, 17 gate comb electrodes 82 are provided, each with a y-axis length of 3 mm in the portion located on the active layer region 30.

[0030] As shown in Figure 2, the support substrate 10 has a silicon layer 13, and in this embodiment, it is made of a QST (Qromis Substrate Technology: registered trademark) substrate. In this embodiment, the support substrate 10 has a core layer 11, a design layer 12 disposed on the core layer 11, and a silicon layer 13 disposed on the design layer 12.

[0031] The core layer 11 is intended to bring the thermal expansion coefficient of the support substrate 10 closer to that of GaN, and in this embodiment, it is composed of AlN (aluminum nitride) or the like, which has a thermal expansion coefficient close to that of GaN. The design layer 12 absorbs the irregularities on the surface of the core layer 11 and flattens the surface opposite to the core layer 11, and in this embodiment, it is composed of an oxide film.

[0032] The silicon layer 13 is made of Si(111) with its main surface (i.e., the surface facing the constituent substrate 20) being a (111) plane, and has a thickness of approximately 0.3 to 3.0 μm. A diode having a p-type anode layer 131 and an n-type cathode layer 132 is formed in the silicon layer 13, as shown in Figure 5. Specifically, the anode layer 131 and the cathode layer 132 are arranged along the y-axis direction. That is, the anode layer 131 and the cathode layer 132 are arranged in a direction intersecting the arrangement direction of the source comb-tooth electrode 62 and the drain comb-tooth electrode 72. In this embodiment, the anode layer 131 and the cathode layer 132 are formed such that both the anode layer 131 and the cathode layer 132 are present in the portion facing the active layer region 30 in the z-axis direction. The thickness of the silicon layer 13 is appropriately set according to the required avalanche operating current.

[0033] The anode layer 131 of this embodiment has a p-type anode layer connecting layer 131a and an anode layer contact layer 131b located on the opposite side of the anode layer connecting layer 131a from the cathode layer 132, with a higher concentration of p-type impurities than the anode layer connecting layer 131a. The cathode layer 132 has an n-type cathode layer connecting layer 132a and a cathode layer contact layer 132b located on the opposite side of the cathode layer connecting layer 132a from the anode layer 131, with a higher concentration of n-type impurities than the cathode layer connecting layer 132a.

[0034] Specifically, the anode contact layer 131b is formed to extend in the x-axis direction, including a portion that faces the source wiring portion 61 in the z-axis direction. The cathode contact layer 132b is formed to extend in the x-axis direction, including a portion that faces the drain wiring portion 71 in the z-axis direction.

[0035] Furthermore, as shown in Figure 3A, a via holes 91a for the anode layer are formed on the semiconductor substrate 1 (i.e., the constituent substrate 20) in the portion that overlaps with the source wiring portion 61 in the z-axis direction, exposing the anode layer contact layer 131b. In this embodiment, multiple anode layer via holes 91a are arranged along the x-axis direction, which is the longitudinal direction of the source wiring portion 61. An insulating film 91b is placed in each anode layer via hole 91a, and a through-via 91c for the anode layer is placed on the insulating film 91b to connect the source wiring portion 61 and the anode layer contact layer 131b.

[0036] Similarly, as shown in Figure 3B, the semiconductor substrate 1 (i.e., the constituent substrate 20) has cathode layer via holes 92a formed in the portion that overlaps with the drain wiring portion 71 in the z-axis direction, exposing the cathode layer contact layer 132b. In this embodiment, multiple cathode layer via holes 92a are arranged along the x-axis direction, which is the longitudinal direction of the drain wiring portion 71. An insulating film 92b is placed in each cathode layer via hole 92a, and a through-via 92c for the cathode layer is placed on the insulating film 92 to connect the drain wiring portion 71 and the cathode layer contact layer 132b.

[0037] Note that the insulating films 91b and 92b are formed of an oxide film or the like, and the through vias 91c for the anode layer and the through vias 92c for the cathode layer are configured, for example, by embedding a copper plating film or the like on a barrier metal containing a Ni silicide layer, Ti or the like. However, the configurations of the through vias 91c for the anode layer and the through vias 92c for the cathode layer can be modified as appropriate. For example, the through via 91c for the anode layer may be configured such that the material constituting the source wiring portion 61 enters the via hole 91a for the anode layer. Similarly, the through via 92c for the cathode layer may be configured such that the material constituting the drain wiring portion 71 enters the via hole 92a for the cathode layer.

[0038] Further, for the anode layer 131 and the cathode layer 132 formed in the silicon layer 13, the impurity concentration and the length in the y-axis direction are appropriately adjusted according to the required avalanche withstand capability. For example, when avalanche breakdown is to occur at 650V, the p-type impurity concentration of the connection layer 131a for the anode layer in the anode layer 131 is 1.0×10 16 or more and 1.0×10 18 cm -3 or less. For the cathode layer 132, the n-type impurity concentration of the connection layer 132a for the cathode layer is 1.0×10 16 cm -3 or less. Further, the contact layer 131b for the anode layer has a higher p-type impurity concentration than the connection layer 131a for the anode layer, for example, the p-type impurity concentration is 1.0×10 19 cm -3 . The contact layer 132b for the cathode layer has a higher n-type impurity concentration than the connection layer 132a for the cathode layer, for example, the n-type impurity concentration is 1.0×10 19 cm -3 . As for the lengths of the anode layer 131 and the cathode layer 132 in the y-axis direction, for example, the length of the anode layer 131 is 4000 μm or more, and the length of the cathode layer 132 is 1000 μm or less.

[0039] The above describes the configuration of the semiconductor device in this embodiment. In this embodiment, n-type corresponds to the first conductivity type, and p-type corresponds to the second conductivity type. Next, the manufacturing method of the semiconductor device in this embodiment will be described.

[0040] First, as shown in Figure 6, a wafer-shaped support wafer 200 having multiple device formation regions RA is prepared. The support wafer 200 is divided into each device formation region RA to constitute the support substrate 10, and is constructed by stacking the core layer 11, design layer 12, and silicon layer 13 described above. Alignment marks 201, such as recesses, are formed on the outer edge of the support wafer 200, beyond the device formation regions RA. In this embodiment, four alignment marks 201 are formed. Furthermore, each alignment mark 201 is formed so that the spacing between them in the circumferential direction of the support wafer 200 is equal. Although omitted in Figure 6, dicing lines are set between each device formation region RA.

[0041] Then, a diode having an anode layer 131 and a cathode layer 132 is formed in the silicon layer 13 of each device formation region RA of the support wafer 200 by appropriately ion implanting p-type impurities and n-type impurities using alignment marks. In this embodiment, one anode layer 131 and one cathode layer 132 are formed in the silicon layer 13 of each device formation region RA so that the anode layer 131 and cathode layer 132 are arranged along the y-axis direction. Therefore, compared to, for example, the case where multiple anode layers 131 and cathode layers 132 are alternately formed along the x-axis direction in the silicon layer 13 of each device formation region RA, detailed alignment is not required. Consequently, the number of alignment marks 201 formed on the support wafer 200 can be reduced, and the number of device formation regions RA can be increased, thereby improving yield.

[0042] Subsequently, if necessary, the surface of the silicon layer 13 of the support wafer 200 is polished using CMP (Chemical Mechanical Polishing) or the like. When polishing is performed, the thickness of the silicon layer 13 and the depth of the anode layer 131 and cathode layer 132 formed on the silicon layer 13 are adjusted as appropriate.

[0043] Next, although not specifically shown in the diagram, a buffer layer 21, a GaN layer 22, and an AlGaN layer 23 are epitaxially grown sequentially on the support wafer 200. Epitaxial growth is carried out at, for example, around 1000-1200°C. However, epitaxial growth may cause warping, thermal distortion, etc.

[0044] Then, a predetermined semiconductor manufacturing process is performed to form through-vias 91c for the anode layer that connect the source wiring section 61 to the anode layer 131, and through-vias 92c for the cathode layer that connect the drain wiring section 71 to the cathode layer 132, etc. Also, a source electrode 60, a drain electrode 70, a gate electrode 80, etc. Here, a semiconductor device in which the anode layer 131 and the cathode layer 132 are arranged alternately in the x-axis direction, with through-vias 91c for the anode layer positioned to connect the source comb electrode 62 to the anode layer 131 and through-vias 92c for the cathode layer positioned to connect the drain comb electrode 72 to the cathode layer 132 is used as a comparative example semiconductor device. Furthermore, comparing the semiconductor device of this embodiment with the semiconductor device of the comparative example, in the semiconductor device of this embodiment, the connectable area of ​​the source electrode 60 and the anode layer 131 connected to the through-via 91c for the anode layer is wider, and the connectable area of ​​the drain electrode 70 and the cathode layer 132 connected to the through-via 92c for the cathode layer is also wider. Therefore, even if warping or thermal distortion occurs in the semiconductor device of this embodiment, connection failures can be suppressed compared to the semiconductor device of the comparative example.

[0045] Subsequently, the semiconductor device described above is manufactured by dividing the support wafer 200 into chip units along each device formation area RA.

[0046] As described above, in this embodiment, the anode layer 131 and the cathode layer 132 are arranged along the y-axis direction intersecting the arrangement direction of the source comb-tooth electrode 62 and the drain comb-tooth electrode 72. The anode layer through-via 91c is arranged to connect the source wiring section 61 and the anode layer 131. The cathode layer through-via 92c is arranged to connect the drain wiring section 71 and the cathode layer 132. As a result, the connectable area of ​​the source electrode 60 and the anode layer 131 connected to the anode layer through-via 91c is widened, and the connectable area of ​​the drain electrode 70 and the cathode layer 132 connected to the cathode layer through-via 92c is widened. Therefore, connection failures can be suppressed. Furthermore, since the semiconductor device of this embodiment has a source comb-tooth electrode 62 and a drain comb-tooth electrode 72, it can easily handle high currents. Furthermore, in the semiconductor device of this embodiment, connection failures can be suppressed as described above, so there is no need to increase the width in the x-axis direction of the source comb-tooth electrode 62 and the drain comb-tooth electrode 72, and the area in which the HEMT actually operates is not reduced.

[0047] (1) In this embodiment, the silicon layer 13 is made of Si(111), and a QST substrate can be used as the support substrate 10. Therefore, design changes can be minimized, and a highly versatile semiconductor device can be made. In addition, although the constituent substrate 20 is an epitaxial layer, connection failures can be suppressed as described above.

[0048] (Second Embodiment) A second embodiment will now be described. In this embodiment, a GaN thin-film substrate is placed on the silicon layer 13, compared to the first embodiment. Other aspects are the same as in the first embodiment, so a detailed explanation will be omitted here.

[0049] In the semiconductor device of this embodiment, as shown in Figure 7, the support substrate 10 is constructed by arranging a GaN thin-film substrate 14 on a silicon layer 13. The silicon layer 13 and the GaN thin-film substrate 14 are joined by surface activation bonding. The GaN thin-film substrate 14 is obtained by cutting a GaN ingot manufactured by the amonothermal method, and has a thickness of approximately 1 to 20 μm.

[0050] Furthermore, although not specifically shown in the figures, the through-via 91c for the anode layer is formed to penetrate the GaN thin-film substrate 14 and reach the anode layer 131 of the silicon layer 13. Similarly, the through-via 92c for the cathode layer is formed to penetrate the GaN thin-film substrate 14 and reach the cathode layer 132 of the silicon layer 13.

[0051] When manufacturing such a semiconductor device, a support wafer 200 is prepared, in which a GaN thin-film substrate 14 is placed on a silicon layer 13. Then, an epitaxial layer containing GaN is grown on the GaN thin-film substrate 14 on the support wafer 200. In this process, since the epitaxial layer containing GaN (i.e., the constituent substrate 20) is grown on the GaN thin-film substrate 14, the epitaxial layer is constructed using homoepitaxial growth. Therefore, the constituent substrate 20 is constructed as a HEMT with fewer defects and suppressed degradation of performance.

[0052] In this embodiment, the constituent substrate 20 is epitaxially grown on the GaN thin film substrate 14. Therefore, the crystal orientation of the silicon layer 13 can be changed as appropriate.

[0053] According to the embodiment described above, the anode layer 131 and the cathode layer 132 are arranged along the y-axis direction intersecting the arrangement direction of the source comb-tooth electrode 62 and the drain comb-tooth electrode 72. The through-via 91c for the anode layer is arranged to connect the source wiring section 61 and the anode layer 131. The through-via 92c for the cathode layer is arranged to connect the drain wiring section 71 and the cathode layer 132. Therefore, the same effects as in the first embodiment can be obtained.

[0054] (1) In this embodiment, the support substrate 10 is constructed by placing a GaN thin film substrate 14 on a silicon layer 13. As a result, the number of defects that may be included in the constituent substrate 20 is reduced, and a HEMT is constructed in which a decrease in performance is suppressed.

[0055] (Third embodiment) A third embodiment will now be described. In this embodiment, a barrier layer is placed between the GaN thin-film substrate 14 and the silicon layer 13, compared to the second embodiment. Other aspects are the same as in the second embodiment, so a detailed explanation will be omitted here.

[0056] In the semiconductor device of this embodiment, as shown in Figure 8, a barrier layer 15 is arranged between the GaN thin film substrate 14 and the silicon layer 13. The GaN thin film substrate 14 is bonded to the barrier layer 15 by surface activation bonding.

[0057] The barrier layer 15 is intended to suppress the reaction between the Ga of the GaN thin-film substrate 14 and the silicon layer 13 when growing the epitaxial layer (i.e., the constituent substrate 20), and is composed of a material having a melting point of 1500°C or higher. For example, the barrier layer 15 is composed of a high-melting-point metal such as W (tungsten) or Ta (tantalum). The barrier layer 15 is composed of a polycrystalline film or single-crystal film such as AlN (aluminum nitride). The barrier layer 15 is composed of a single-crystal film such as SiC (silicon carbide) or Al2O3 (aluminum oxide). The barrier layer 15, composed of such a material, is then placed on the silicon layer 13 by, for example, a sputtering method. However, it is preferable that the barrier layer 15 has a small difference in thermal expansion coefficient with the GaN thin-film substrate 14 and the epitaxial layer (i.e., the constituent substrate 20), and is preferably composed of an AlN single-crystal film.

[0058] According to the embodiment described above, the anode layer 131 and the cathode layer 132 are arranged along the y-axis direction intersecting the arrangement direction of the source comb-tooth electrode 62 and the drain comb-tooth electrode 72. The through-via 91c for the anode layer is arranged to connect the source wiring section 61 and the anode layer 131. The through-via 92c for the cathode layer is arranged to connect the drain wiring section 71 and the cathode layer 132. Therefore, the same effects as in the first embodiment can be obtained.

[0059] (1) In this embodiment, a barrier layer 15 made of a material having a melting point of 1500°C or higher is placed between the GaN thin film substrate 14 and the silicon layer 13. Therefore, the reaction between the Ga of the GaN thin film substrate 14 and the silicon layer 13 can be suppressed. Consequently, a deterioration in the quality of the epitaxial layer can be suppressed. In addition, changes in the characteristics of the diode formed in the silicon layer 13 can be suppressed.

[0060] (Fourth Embodiment) A fourth embodiment will now be described. This embodiment is a modification of the diode configuration compared to the first embodiment. Other aspects are the same as in the first embodiment, so a detailed explanation will be omitted here.

[0061] In the semiconductor device of this embodiment, as shown in Figure 9, the cathode layer 132 is formed only in the portion that is different from the portion facing the active layer region 30 in the z-axis direction. In other words, the portion of the silicon layer 13 that faces the active layer region 30 in the z-axis direction is entirely the anode layer 131. To put it another way, the cathode layer 132 is not formed in the portion of the silicon layer 13 that faces the active layer region 30 in the z-axis direction.

[0062] For example, if avalanche breakdown is to be performed at 650V, the anode layer 131 has a p-type impurity concentration of 1.0 × 10⁻¹⁶ in the anode layer connecting layer 131a. 16 The above 1.0 × 10 18 cm -3The following is stated: The cathode layer 132 has an n-type impurity concentration of 1.0 × 10⁻¹⁶ in the cathode layer connecting layer 132a. 14 cm -3 The following is specified. The lengths of the anode layer 131 and the cathode layer 132 in the y-axis direction are, for example, that the length of the anode layer 131 is 4800 μm or more, and the length of the cathode layer 132 is 200 μm or less.

[0063] According to the embodiment described above, the anode layer 131 and the cathode layer 132 are arranged along the y-axis direction intersecting the arrangement direction of the source comb-tooth electrode 62 and the drain comb-tooth electrode 72. The through-via 91c for the anode layer is arranged to connect the source wiring section 61 and the anode layer 131. The through-via 92c for the cathode layer is arranged to connect the drain wiring section 71 and the cathode layer 132. Therefore, the same effects as in the first embodiment can be obtained.

[0064] (1) In this embodiment, the portion of the silicon layer 13 that overlaps with the active layer region 30 in the z-axis direction is entirely the anode layer 131. In conventional semiconductor devices with HEMTs, the portion located on the opposite side of the buffer layer 21 from the GaN layer 22 is connected to the source electrode 60 in order to reduce current collapse and stabilize the potential to improve breakdown voltage characteristics. Therefore, as in this embodiment, by making only the anode layer 131 the portion of the silicon layer 13 that overlaps with the active layer region 30, the effect of reducing current collapse and breakdown voltage characteristics can be made the same as in the conventional, and the complexity of the design can be suppressed.

[0065] (Other embodiments) This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and idea of ​​this disclosure.

[0066] For example, in each of the above embodiments, an example was described in which a through-via 91c for the anode layer is placed in the via hole 91a for the anode layer via an insulating film 91b, and a through-via 92c for the cathode layer is placed in the via hole 92a for the cathode layer via an insulating film 92b. However, the buffer layer 21, GaN layer 22, and AlGaN layer 23 in this embodiment are undoped and are insulating layers. Therefore, an insulating film 91b is not required to be placed in the via hole 91a for the anode layer, nor is an insulating film 92b required to be placed in the via hole 92a for the cathode layer.

[0067] Furthermore, the configuration of the support substrate 10 can be modified as appropriate. For example, the support substrate 10 may have a design layer on the opposite side of the core layer 11 from the design layer 12. In addition, the support substrate 10 may be composed of ScAlMgO4 (i.e., a so-called SAM substrate) instead of AlN.

[0068] Furthermore, the above embodiments can be combined as appropriate. For example, the fourth embodiment may be combined with the second and third embodiments.

[0069] [Disclosure of the Invention] The above disclosure can be understood from the following perspectives, for example. [First point of view] A semiconductor device, A support substrate (10) includes a silicon layer (13) on which a diode is formed, comprising a first conductivity type cathode layer (132) and a second conductivity type anode layer (131), A constituent substrate (20) includes a first semiconductor layer (22) disposed on the support substrate and composed of a first gallium nitride-based semiconductor that constitutes a drift region, and a second semiconductor layer (23) disposed on the first semiconductor layer and composed of a second gallium nitride-based semiconductor having a larger bandgap energy than the first gallium nitride-based semiconductor, If one direction in the planar direction of the constituent substrate is defined as the first direction and the direction intersecting the first direction is defined as the second direction, then the source electrode (60) is arranged on the second semiconductor layer and has a source wiring portion (61) extending in the second direction and a plurality of source comb-tooth electrodes (62) protruding from the source wiring portion in the first direction, A drain electrode (70) having a drain wiring portion (71) arranged on the second semiconductor layer and extending in the second direction, and a plurality of drain comb electrodes (72) protruding from the drain wiring portion in one direction and arranged alternately with the source comb electrode in the second direction, A gate electrode (80) having a gate comb electrode (82) positioned between the source comb electrode and the drain comb electrode arranged in the second direction, A source through-via (91c) is formed on the aforementioned substrate and electrically connects the anode layer and the source electrode, The component substrate includes a drain through-via (92c) formed thereon, which electrically connects the cathode layer and the drain electrode, The cathode layer and the anode layer are arranged along the first direction, The cathode layer is arranged in the stacking direction of the support substrate and the component substrate, including a position facing the drain wiring portion. The anode layer is arranged to include a position facing the source wiring portion in the stacking direction, The source through via is arranged to connect the source wiring section and the anode layer. The drain through via is arranged to connect the drain wiring section and the cathode layer in a semiconductor device. [Second perspective] The silicon layer is Si(111), The semiconductor device according to the first aspect, wherein the constituent substrate is an epitaxial layer. [Third perspective] The aforementioned substrate is an epitaxial layer, The semiconductor device according to the first or second aspect, wherein a gallium nitride thin film substrate (14) made of gallium nitride is disposed between the support substrate and the component substrate. [Fourth perspective] The semiconductor device according to the third aspect, wherein a barrier layer (15) made of a material having a melting point of 1500°C or higher is disposed between the gallium nitride thin film substrate and the constituent substrate. [Fifth perspective] The aforementioned substrate has an active layer region (30) through which current flows and an element isolation region (40) that is different from the active layer region. The semiconductor device according to any one of the first to fourth views, wherein the portion of the silicon layer facing the active layer region in the stacking direction is entirely the anode layer. [Explanation of Symbols]

[0070] 10 Support substrate 13 Silicon layer 20 component boards 22 GaN layer (first semiconductor layer) 23 AlGaN layer (second semiconductor layer) 60 source electrodes 61 Source wiring section 62 Comb-tooth electrodes for the source 70 Drain electrode 71 Drain wiring section 72 Drain comb-tooth electrodes 91c Through-Via for Source 92c drain through-via 131 Anode Layer 132 Cathode Layer

Claims

1. A semiconductor device, A support substrate (10) including a silicon layer (13) on which a diode is formed, comprising a first conductivity type cathode layer (132) and a second conductivity type anode layer (131), A constituent substrate (20) includes a first semiconductor layer (22) disposed on the support substrate and composed of a first gallium nitride-based semiconductor that constitutes a drift region, and a second semiconductor layer (23) disposed on the first semiconductor layer and composed of a second gallium nitride-based semiconductor having a larger bandgap energy than the first gallium nitride-based semiconductor, If one direction in the planar direction of the constituent substrate is defined as the first direction and the direction intersecting the first direction is defined as the second direction, then the source electrode (60) is arranged on the second semiconductor layer and has a source wiring portion (61) extending in the second direction and a plurality of source comb-tooth electrodes (62) protruding from the source wiring portion in the first direction, A drain electrode (70) having a drain wiring portion (71) arranged on the second semiconductor layer and extending in the second direction, and a plurality of drain comb electrodes (72) protruding from the drain wiring portion in one direction and arranged alternately with the source comb electrode in the second direction, A gate electrode (80) having a gate comb electrode (82) positioned between the source comb electrode and the drain comb electrode arranged in the second direction, A source through-via (91c) is formed on the aforementioned substrate and electrically connects the anode layer and the source electrode, The component substrate includes a drain through-via (92c) formed thereon, which electrically connects the cathode layer and the drain electrode, The cathode layer and the anode layer are arranged along the first direction, The cathode layer is arranged in the stacking direction of the support substrate and the component substrate, including a position facing the drain wiring portion. The anode layer is arranged to include a position facing the source wiring portion in the stacking direction, The source through via is arranged to connect the source wiring section and the anode layer. The drain through via is arranged to connect the drain wiring section and the cathode layer in a semiconductor device.

2. The silicon layer is Si(111), The semiconductor device according to claim 1, wherein the constituent substrate is an epitaxial layer.

3. The aforementioned substrate is an epitaxial layer, The semiconductor device according to claim 1, wherein a gallium nitride thin film substrate (14) made of gallium nitride is disposed between the support substrate and the component substrate.

4. The semiconductor device according to claim 3, wherein a barrier layer (15) made of a material having a melting point of 1500°C or higher is disposed between the gallium nitride thin film substrate and the constituent substrate.

5. The aforementioned substrate has an active layer region (30) through which current flows and an element isolation region (40) that is different from the active layer region. The semiconductor device according to any one of claims 1 to 4, wherein all portions of the silicon layer facing the active layer region in the stacking direction are the anode layer.

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