Imaging device

Abstract

To provide an imaging device that can be miniaturized while suppressing noise degradation. [Solution] An imaging device comprising a substrate, a photoelectric conversion film disposed on the substrate that converts light into electric charge, an electrode for collecting the electric charge, a first transistor whose gate is electrically connected to the electrode, and a second transistor which is a charge storage region in which either the source or drain is electrically connected to the electrode, wherein the substrate includes a recess, the first transistor is disposed in the recess and has a fin structure, and the second transistor is not disposed in the recess.

Description

Technical Field

[0001] The present disclosure relates to an imaging apparatus.

Background Art

[0002] CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used in digital cameras and the like. As an imaging apparatus using such an image sensor, a stacked imaging apparatus having a structure in which a photoelectric conversion unit is disposed on the light incident side of a semiconductor substrate has been proposed.

[0003] For example, Patent Document 1 discloses an imaging apparatus in which a circuit of an imaging cell including a photoelectric conversion unit and a peripheral circuit are formed on the same semiconductor substrate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Imaging apparatuses are required to be miniaturized. Miniaturization also reduces the transistor size, giving rise to the problem of noise degradation.

[0006] Accordingly, the present disclosure provides an imaging apparatus capable of suppressing noise degradation while achieving miniaturization.

Means for Solving the Problems

[0007] An imaging device according to one aspect of the present disclosure comprises a substrate, a photoelectric conversion film disposed on the substrate and converting light into electric charge, an electrode for collecting the electric charge, a first transistor whose gate is electrically connected to the electrode, and a second transistor which is a charge storage region in which either the source or drain is electrically connected to the electrode, wherein the substrate includes a recess, the first transistor is disposed in the recess and has a fin structure, and the second transistor is not disposed in the recess. [Effects of the Invention]

[0008] According to this disclosure, it is possible to miniaturize the imaging device while suppressing noise degradation. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a block diagram showing an example of a schematic configuration of an imaging device according to Embodiment 1. [Figure 2] Figure 2 is a diagram showing the circuit configuration of the imaging device according to Embodiment 1. [Figure 3A] Figure 3A is a schematic cross-sectional view showing an example of the device structure of an imaging device according to Embodiment 1. [Figure 3B] Figure 3B is a schematic plan view (i) and cross-sectional view (ii) showing an example of a planar layout in the imaging device according to Embodiment 1. [Figure 4A] Figure 4A is a plan view showing an example of a modified transistor arranged on the charge storage side in Embodiment 1. [Figure 4B] Figure 4B is a bird's-eye view showing an example of a modified transistor arranged on the charge storage side in Embodiment 1. [Figure 5A] Figure 5A is a cross-sectional view illustrating the process of forming the recessed portion of the pixel substrate. [Figure 5B] Figure 5B is a cross-sectional view illustrating the process of forming the recessed portion of the pixel substrate. [Figure 5C] Figure 5C is a cross-sectional view illustrating the process of forming the recessed portion of the pixel substrate. [Figure 5D] Figure 5D is a cross-sectional view illustrating the process of forming the recessed portion of the pixel substrate. [Figure 6] Figure 6 is a block diagram showing an example of the configuration of the camera system according to Embodiment 2. [Modes for carrying out the invention]

[0010] (Summary of this disclosure) As an overview of one aspect of this disclosure, an example of an imaging device related to this disclosure is shown below.

[0011] For example, an imaging device according to a first aspect of the present disclosure includes a substrate including a first surface on the light incident side and a second surface facing the first surface, a photoelectric conversion unit located on the first surface side of the first substrate and converting incident light into electric charge, a first wiring located on the first surface side of the substrate and closer to the first substrate than the photoelectric conversion unit, and the substrate is provided with a pixel transistor and a charge storage region, the amplification transistor having a fin-shaped three-dimensional transistor structure. There is a recessed shape between the charge storage region and the fin-shaped amplification transistor, and the bottom surface of the fin is located below the surface of the charge storage region.

[0012] The charge storage region includes a reset transistor and an overflow (OF) transistor that share a source-drain diffusion layer on either side of the charge storage region, and the transistors that share the diffusion layer with the charge storage region have a planar structure. Furthermore, there may be an STI isolation between the fin-shaped amplification transistor and the charge storage region, and there may be an impurity-doped layer between the charge storage region and the recessed portion 31C to prevent leakage.

[0013] To form three-dimensional shapes such as columnar or fin shapes, etching the substrate requires shaping by first forming a deposited layer on the substrate and then etching that portion. In this case, by etching the substrate at a position separated from the diffusion layer of the charge accumulation region to create a three-dimensional gate structure, direct damage to the charge accumulation region can be suppressed. If the fin shape is formed on the upper side of the substrate and the entire front surface other than the fin is etched, plasma damage will occur directly to the charge accumulation region as well. Furthermore, the charge accumulation region side can proceed with subsequent process steps without any steps.

[0014] This suppresses etching damage to the charge storage region, allowing the amplification transistor to be formed as a fin-shaped transistor. Therefore, even when the imaging device is miniaturized, the effective gate length and gate width of the amplification transistor can be increased, preventing noise degradation. Furthermore, in the imaging device according to this embodiment, the transistor sharing the charge storage region and the diffusion layer has a planar-type transistor structure. This also reduces damage to the charge storage region and suppresses dark current degradation.

[0015] In detail, when miniaturizing pixels, the area of ​​the pixel region plane decreases, so the area of ​​the transistor elements within the pixel region also decreases, resulting in smaller gate length, gate width, and gate area. Noise deteriorates proportionally as the gate length and gate width of the transistor decrease. In this case, by making the gate of the pixel transistor a three-dimensional shape such as a fin shape, the effective gate width increases even within the same pixel region area, and the gate area increases, and as a result, noise deterioration can be suppressed even in the miniaturized pixel region. Forming a fin-shaped three-dimensional structure requires processing such as etching, but during this process, damage such as plasma damage occurs to the substrate. Also, stress can occur near the recessed sides, and stress-induced defects may occur. Therefore, by forming the charge storage region spaced apart from the Fin-shaped amplification transistor with the recessed part in between, damage to the charge storage region and the occurrence of defects can be suppressed, and as a result, dark current deterioration can be suppressed.

[0016] In an imaging device of photoelectric conversion film stacked type, charges from the photoelectric conversion film stay in the charge accumulation region for a long time via the poly plug, so compared with a photodiode-type imaging device formed on a silicon substrate, the influence on dark current caused by damage to the charge accumulation region is characterized to be larger, and such degradation can be reduced.

[0017] Note that in the present specification, that the imaging device can be miniaturized means that the area of the substrate in a plan view can be reduced.

[0018] Further, in the imaging device according to the second aspect of the present disclosure, in a plan view, with the recessed portion as a boundary, a reset transistor and an OF- transistor are formed on the right side of the recessed portion with the charge accumulation region interposed therebetween. Further, on the left side of the recessed portion, an amplifying transistor and a select transistor are formed in an arrangement sharing a source-drain diffusion layer, and the gate structure of the amplifying transistor has a Fin structure. The Fin structure increases the gate width of the amplifying transistor. The number of Fins may be two or more. In this manner, degradation of random noise can be reduced by increasing the effective gate length and gate width of the amplifying transistor. Both the amplifying transistor and the select transistor may be of Fin type.

[0019] The reset transistor and the OF- transistor that share the charge accumulation region may be of planar type.

[0020] By making the transistor that includes the charge accumulation region as one of the source or the drain be of planar type, and disposing the Fin-type transistors that are susceptible to damage from etching for forming the recess at a distance, damage and defects to the charge accumulation region can be suppressed, and degradation of dark current can be suppressed.

[0021] On the left side of the recess where the amplification transistor is located, the substrate is recessed to form a fin-type channel. The right side, where the charge storage region is located, is not recessed, so the substrate surface is located above the bottom surface of the fin that forms the recess. In this case, the STI may be formed before etching the fin shape, and then the fin gate may be formed. Since a defect layer may be formed on the side wall 31d of the recess due to plasma damage or stress during etching, a dark current prevention layer may be formed on this side wall 31d by injecting p-type impurities, such as boron.

[0022] Embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments described below are either comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. The various embodiments described herein can be combined with each other as long as they do not conflict. Furthermore, components in the following embodiments that are not described in an independent claim will be described as optional components. In each figure, components having substantially the same function are indicated by a common reference numeral, and redundant descriptions may be omitted or simplified.

[0023] Furthermore, the various elements shown in the drawings are for illustrative purposes only, and their dimensional ratios and appearance may differ from those of the actual object. In other words, each drawing is a schematic representation and not necessarily a strictly accurate depiction. Therefore, for example, the scale in each drawing may not necessarily match.

[0024] Furthermore, in this specification, terms indicating relationships between elements such as orthogonal and parallel, terms indicating the shape of elements such as circular or rectangular, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent.

[0025] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather to terms defined by the relative positional relationship based on the stacking order in the stacked configuration. Specifically, the light-incident side of the imaging device is defined as "upper," and the side opposite the light-incident side is defined as "lower." Similarly, for the "upper surface" and "lower surface" of each component, the surface on the light-incident side of the imaging device is defined as the "upper surface," and the surface opposite the light-incident side is defined as the "lower surface." It should be noted that terms such as "upper," "lower," "upper surface," and "lower surface" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device when in use. In addition, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other. Furthermore, in this specification, "plan view" refers to a view of the semiconductor substrate from the direction normal to the main surface (e.g., the top and bottom surfaces) (in other words, the direction of the thickness of the semiconductor substrate).

[0026] Furthermore, in this specification and the drawings, the X, Y, and Z axes represent the three axes of a three-dimensional Cartesian coordinate system. In the following embodiments, the Z-axis direction is the thickness direction of the semiconductor substrate and the stacking direction of the semiconductor substrate. Also, the negative side of the Z-axis is defined as "downward," and the positive side of the Z-axis is defined as "upward."

[0027] Furthermore, in this specification, when a transistor is said to be placed on a certain surface of a semiconductor substrate, it means that the gate, source, and drain of the transistor are placed on either side of that surface.

[0028] Furthermore, in this specification, "connection" means an electrical connection unless otherwise specified.

[0029] Furthermore, in this specification, for convenience, not only visible light but also invisible light such as ultraviolet light and near-infrared light will be referred to as "light."

[0030] Furthermore, in this specification, ordinal numbers such as "first," "second," etc., unless otherwise specified, do not refer to the number or order of constituent elements, etc., but are used for the purpose of avoiding confusion and distinguishing similar constituent elements, etc.

[0031] (Embodiment 1) The imaging device according to Embodiment 1 will be described below.

[0032] [composition] First, the schematic configuration of the imaging device according to this embodiment will be described. Figure 1 is a block diagram showing an example of the schematic configuration of the imaging device 100 according to this embodiment.

[0033] As shown in Figure 1, the imaging device 100 comprises a pixel substrate 31 which is a semiconductor substrate, a pixel array 14A formed on the pixel substrate 31, a circuit board 41 which is a semiconductor substrate, peripheral circuits 4 formed on the circuit board 41, and a first via 71 for connecting the pixel array 14A and the peripheral circuits 4. The peripheral circuits 4 include circuits for driving the pixel array 14A and circuits for processing signals output by the pixel array 14A. In the example shown in Figure 1, the peripheral circuits 4 include a vertical scanning circuit 15, a column signal processing circuit 19, a horizontal signal readout circuit 20, and a voltage control circuit 30. Multiple column signal processing circuits 19 are provided corresponding to each column of the pixel array 14A, as will be described later, but in Figure 1, they are shown as a single block. The peripheral circuits 4 may further include other circuits such as memory, analog circuits, and logic circuits. Also, some of the peripheral circuits 4 may be arranged on the pixel substrate 31. Furthermore, at least one of the in-pixel elements such as transistors in the pixel array 14A and a part of the peripheral circuit 4 may be formed on one or more other semiconductor substrates stacked on the pixel substrate 31 and the circuit substrate 41.

[0034] In the example shown in Figure 1, the voltage control circuit 30 and the pixel array 14A are electrically connected via the first via 71 and the counter electrode signal line 16. The vertical scanning circuit 15 and the pixel array 14A are electrically connected via the first via 71 and the address signal line 26, and via the first via 71 and the reset signal line 27. The column signal processing circuit 19 and the pixel array 14A are electrically connected via the first via 71 and the vertical signal line 17. Depending on the arrangement of the in-pixel elements of the pixel array 14A and the circuits of the peripheral circuits 4, some of the electrical connections via the first via 71 may be made without using the first via 71.

[0035] Next, the circuit configuration of the imaging device 100 according to this embodiment will be described. Figure 2 is a diagram showing the circuit configuration of the imaging device 100 according to this embodiment.

[0036] As shown in Figure 2, the pixel array 14A is composed of multiple pixels 14. In a plan view, the multiple pixels 14 are arranged in a matrix, that is, in the row and column directions, to form a pixel array region. In this specification, the row and column directions refer to the directions in which the rows and columns extend, respectively. That is, the vertical direction is the column direction, and the horizontal direction is the row direction. In Figure 2, four pixels 14 arranged in 2 rows and 2 columns are shown as representative. The number of multiple pixels 14 is not particularly limited. Furthermore, the multiple pixels 14 may be arranged in one dimension, that is, along one direction. In other words, the imaging device 100 may be a line sensor.

[0037] Each pixel 14 includes a photoelectric conversion unit 10 and a charge detection circuit 25. The charge detection circuit 25 includes an amplifying transistor 11, a reset transistor 12, and an address transistor 13. The photoelectric conversion unit 10 includes a pixel electrode 50, a photoelectric conversion layer 51, and an upper electrode 52. The specific configuration of the photoelectric conversion unit 10 will be described later.

[0038] The imaging device 100 includes a voltage control element for applying a predetermined voltage to the upper electrode 52. The voltage control element includes, for example, a voltage generation circuit such as a voltage control circuit and a constant voltage source, and a voltage reference line such as a ground wire. The voltage applied by the voltage control element is called the control voltage. In this embodiment, the imaging device 100 includes a voltage control circuit 30 as the voltage control element.

[0039] The voltage control circuit 30 may generate a constant control voltage, or it may generate multiple control voltages with different values. Alternatively, for example, the voltage control circuit 30 may generate a control voltage that changes continuously within a predetermined range. Based on a command from an operator operating the imaging device 100, or a command from another control unit of the imaging device 100, the voltage control circuit 30 determines the value of the control voltage to be generated and generates the control voltage of the determined value.

[0040] For example, the voltage control circuit 30 generates two or more different control voltages and applies these control voltages to the upper electrode 52, thereby changing the spectral sensitivity characteristics of the photoelectric conversion layer 51. This change in spectral sensitivity characteristics includes a spectral sensitivity characteristic in which the sensitivity of the photoelectric conversion layer 51 to the light to be detected becomes zero. As a result, for example, in the imaging device 100, while the pixels 14 read out the detection signal row by row, the voltage control circuit 30 applies a control voltage to the upper electrode 52 that makes the sensitivity of the photoelectric conversion layer 51 zero, thereby almost eliminating the influence of incident light during the reading out of the detection signal. Therefore, even if the detection signal is read out substantially row by row, global shutter operation can be achieved.

[0041] In this embodiment, as shown in Figure 2, the voltage control circuit 30 changes the voltage between the pixel electrode 50 and the upper electrode 52 by applying a control voltage to the upper electrode 52 of the pixels 14 arranged in the row direction via the counter electrode signal line 16, thereby switching the spectral sensitivity characteristics of the photoelectric conversion unit 10. Alternatively, the voltage control circuit 30 realizes electronic shutter operation by applying a control voltage during imaging to obtain spectral sensitivity characteristics in which sensitivity to light becomes zero at a predetermined timing. The voltage control circuit 30 may also apply the control voltage to the pixel electrode 50.

[0042] The photoelectric conversion unit 10 converts incident light into electric charge. When light is incident on the photoelectric conversion unit 10, electrons and holes are generated as electric charge, for example. In order for light to be incident on the photoelectric conversion unit 10 and electrons to be collected as signal charge on the pixel electrode 50, the pixel electrode 50 is set to a relatively higher potential than the upper electrode 52. As a result, electrons move toward the pixel electrode 50. At this time, a current flows from the pixel electrode 50 toward the upper electrode 52. Also, in order for light to be incident on the photoelectric conversion unit 10 and holes to be collected as signal charge on the pixel electrode 50, the pixel electrode 50 is set to a relatively lower potential than the upper electrode 52. As a result, holes move toward the pixel electrode 50. At this time, a current flows from the upper electrode 52 toward the pixel electrode 50.

[0043] The pixel electrode 50 is connected to the gate electrode of the amplification transistor 11, and the signal charge collected by the pixel electrode 50 is stored in the charge storage node 24 located between the pixel electrode 50 and the gate electrode of the amplification transistor 11. In the following explanation, the signal charge will mainly be assumed to be a hole, but the signal charge may also be an electron.

[0044] The signal charge stored in the charge storage node 24 is applied to the gate electrode of the amplification transistor 11 as a voltage corresponding to the amount of signal charge. The amplification transistor 11 outputs a voltage corresponding to the voltage applied to the gate electrode. The address transistor 13 selectively reads out the voltage output from the amplification transistor 11 as the signal voltage. The address transistor 13 is also called a row selection transistor. The reset transistor 12 has one of its sources and drains connected to the pixel electrode 50 and resets the signal charge stored in the charge storage node 24. In other words, the reset transistor 12 resets the potential of the gate electrode of the amplification transistor 11 and the pixel electrode 50.

[0045] To selectively perform the above-described operations on multiple pixels 14, the imaging device 100 includes a power line 21, a vertical signal line 17, an address signal line 26, and a reset signal line 27. The power line 21, vertical signal line 17, address signal line 26, and reset signal line 27 are connected to the pixels 14, respectively. Specifically, the power line 21 is connected to either the source or the drain of the amplification transistor 11. The vertical signal line 17 is connected to either the source or the drain of the address transistor 13. The address signal line 26 is connected to the gate electrode of the address transistor 13. The reset signal line 27 is connected to the gate electrode of the reset transistor 12.

[0046] Each of the amplification transistors 11, reset transistor 12, and address transistor 13 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Each of the amplification transistors 11, reset transistor 12, and address transistor 13 is an n-channel MOSFET, but may also be a p-channel MOSFET. Each of the amplification transistors 11, reset transistor 12, and address transistor 13 is an in-pixel element of pixel 14. Pixel 14 may also have other elements as in-pixel elements, such as transistors other than the amplification transistor 11, reset transistor 12, and address transistor 13, and capacitive elements.

[0047] In the example shown in Figure 2, the peripheral circuit 4 includes, in addition to the vertical scanning circuit 15, the horizontal signal readout circuit 20, the multiple column signal processing circuits 19, and the voltage control circuit 30 described above, multiple load circuits 18 and multiple differential amplifiers 22. The vertical scanning circuit 15 is also called a row scanning circuit. The horizontal signal readout circuit 20 is also called a column scanning circuit. The column signal processing circuit 19 is also called a row signal storage circuit. The differential amplifiers 22 are also called feedback amplifiers.

[0048] The vertical scanning circuit 15 is connected to the address signal line 26 and the reset signal line 27. The vertical scanning circuit 15 may also be connected to the address signal line 26 and the reset signal line 27 via a first via 71 (not shown in Figure 2). The vertical scanning circuit 15 selects a row of pixels 14 arranged in each row of the pixel array 14A, reads the signal voltage, and resets the potential of the pixel electrodes 50. The power supply line 21 functions as a source follower power supply, supplying a predetermined power supply voltage to each pixel 14. The power supply line 21 may be supplied with a predetermined power supply voltage via a first via 71 (not shown in Figure 2).

[0049] The horizontal signal readout circuit 20 is electrically connected to a plurality of column signal processing circuits 19. The column signal processing circuits 19 are electrically connected to the pixels 14 located in each column of the pixel array 14A via vertical signal lines 17 corresponding to each column of the pixel array 14A. The load circuit 18 is electrically connected to each vertical signal line 17. The load circuit 18 and the amplifying transistor 11 form a source follower circuit. In addition, at least one of each column signal processing circuit 19 and each load circuit 18 may be connected to the vertical signal line 17 via a first via 71, which is not shown in Figure 2.

[0050] Multiple differential amplifiers 22 are provided corresponding to each row of the pixel array 14A. The negative input terminals of the differential amplifiers 22 are connected to the corresponding vertical signal lines 17. The output terminals of the differential amplifiers 22 are connected to the pixels 14 via feedback lines 23 corresponding to each row of the pixel array 14A. The output terminals of the differential amplifiers 22 may also be connected to the feedback lines 23 via a first via 71, which is not shown in Figure 2.

[0051] The vertical scanning circuit 15 applies a row selection signal to the gate electrode of the address transistor 13 via the address signal line 26, which controls the on / off state of the address transistor 13. This scans and selects the row to be read. A signal voltage is read from the pixel 14 of the selected row to the vertical signal line 17. The vertical scanning circuit 15 also applies a reset signal to the gate electrode of the reset transistor 12 via the reset signal line 27, which controls the on / off state of the reset transistor 12. This selects the row of pixel 14 that is to be reset. The vertical signal line 17 transmits the signal voltage read from the pixel 14 selected by the vertical scanning circuit 15 to the column signal processing circuit 19.

[0052] The column signal processing circuit 19 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion).

[0053] The horizontal signal readout circuit 20 sequentially reads signals from multiple column signal processing circuits 19 to the horizontal common signal line 28.

[0054] The differential amplifier 22 is connected via a feedback line 23 to the other end of the source and drain of the reset transistor 12, which is not connected to the pixel electrode 50. Therefore, when the address transistor 13 and the reset transistor 12 are conducting, the differential amplifier 22 receives the output value of the address transistor 13 at its negative input terminal. The differential amplifier 22 performs feedback operation so that the gate potential of the amplification transistor 11 becomes a predetermined feedback voltage. At this time, the output voltage value of the differential amplifier 22 is, for example, a positive voltage of 0V or near 0V. The feedback voltage refers to the output voltage of the differential amplifier 22. Note that the imaging device 100 does not necessarily have a differential amplifier 22. For example, a predetermined reset voltage may be supplied to the other end of the drain and source of the reset transistor 12. The reset voltage is, for example, a voltage of 0V or near 0V.

[0055] Next, the device structure of the imaging device 100 according to this embodiment will be described. Figure 3A is a schematic cross-sectional view showing an example of the device structure of the imaging device 100 according to this embodiment. In Figure 3A, for ease of viewing, the shading indicating the cross-section of insulating layers such as the interlayer insulating layer within the wiring layers 61, 62, and 63, and insulating layer 55 has been omitted. Also, in Figure 3A, for ease of viewing, the dimensions such as thickness, length, and width of each component have been appropriately adjusted from their actual size. These adjustments are also made in the following cross-sectional views.

[0056] As shown in Figure 3A, the imaging device 100 comprises a photoelectric conversion unit 10, a pixel substrate 31, a circuit board 41, wiring layers 61, 62, and 63, an insulating layer 55, a first via 71, a second via 72, a third via 73, and a first bonding surface 81. The imaging device 100 has a structure in which the circuit board 41, wiring layer 63, wiring layer 62, pixel substrate 31, wiring layer 61, insulating layer 55, and photoelectric conversion unit 10 are stacked in this order along the Z-axis direction.

[0057] As shown in Figure 3A, the pixel substrate 31 and the circuit board 41 are stacked via a first bonding surface 81 located between the pixel substrate 31 and the circuit board 41. The pixel substrate 31 and the circuit board 41 are, for example, p-type or n-type semiconductor substrates in which various impurity regions are formed. The pixel substrate 31 and the circuit board 41 may each be silicon substrates. In this embodiment, the pixel substrate 31 is an example of a first substrate, and the circuit board 41 is an example of a second substrate. Wells may be formed in each of the pixel substrate 31 and the circuit board 41.

[0058] The pixel substrate 31 includes an upper surface 31a, which is the light incident side, and a lower surface 31b, which is the side opposite to the light incident side and facing the upper surface 31a. In this embodiment, the upper surface 31a is an example of a first surface, and the lower surface 31b is an example of a second surface. A transistor Tr11, which is an example of a first transistor, is arranged on the upper surface 31a of the pixel substrate 31. Transistor Tr11 is a transistor included in the pixel 14, for example, the amplification transistor 11 described above, and has a Fin-type three-dimensional transistor structure. The Fin-type gate has a recessed portion 31c in the substrate between it and the charge storage region 91. The charge storage region 91 is, for example, located between the reset transistor 12 and the OF transistor 14 and shares a diffusion layer. For example, the amplification transistors 11 and reset transistors 12 of multiple pixels 14 are arranged on the upper surface 31a.

[0059] Furthermore, a charge storage region 91 is formed on the pixel substrate 31 for storing the charge generated by the photoelectric conversion unit 10. The charge storage region 91 is part of the charge storage node 24 described above and is electrically connected to the pixel electrode 50 of the photoelectric conversion unit 10 via a plug 92. The charge storage region 91 is an example of a charge storage unit. The charge storage region 91 is an impurity region formed, for example, by injecting n-type or p-type impurities from the upper surface 31a side of the pixel substrate 31. In one example, the charge storage region 91 is an n-type impurity region formed in a p-type semiconductor substrate or a p-type well. The charge storage region 91 may function as one of the source and drain of the reset transistor 12 connected to the pixel electrode 50. The plug 92 is a contact plug located within the wiring layer 61 and in contact with the charge storage region 91. The plug 92 is formed, for example, of polysilicon doped with impurities. The diameter of the plug 92 is, for example, between 10 nm and 100 nm. The charge storage region 91 and the plug 92 are included in each of the multiple pixels 14. In the example shown in Figure 3, the plug 92 is connected to the pixel electrode 50 via a via, but the plug 92 may also be directly connected to the pixel electrode 50. The charge storage region 91 has a recessed portion 31C in the substrate between it and the Fin-type amplification transistor. The charge storage region 91 is also located, for example, between the reset transistor 12 and the OF transistor 14 and shares a diffusion layer.

[0060] The circuit board 41 is located on the lower surface 31b side of the pixel board 31. The circuit board 41 includes an upper surface 41a, which is the light incident side. In this embodiment, the upper surface 41a is an example of a third surface. A transistor Tr21, which is an example of a second transistor, is placed on the upper surface 41a of the circuit board 41. Transistor Tr21 is a transistor included in the peripheral circuit 4. Note that in Figure 3, for ease of viewing, only one transistor Tr21 is shown on the upper surface 41a. Multiple transistors, which are at least some of the transistors included in each circuit of the peripheral circuit 4, may be placed on the upper surface 41a.

[0061] In the pixel substrate 31 and the circuit board 41, transistors are arranged on the upper surfaces 31a and 41a, respectively, and the pixel substrate 31 and the circuit board 41 are stacked in a face-to-back orientation.

[0062] The photoelectric conversion unit 10 is located on the upper surface 31a side of the pixel substrate 31. The photoelectric conversion unit 10 is laminated on the upper surface 31a of the pixel substrate 31 via a wiring layer 61 and an insulating layer 55 located above the wiring layer 61.

[0063] As described above, the photoelectric conversion unit 10 includes a pixel electrode 50, a photoelectric conversion layer 51, and an upper electrode 52. The photoelectric conversion unit 10 may further include other layers such as a charge blocking layer, a buffer layer, or a charge transport layer in at least one of the spaces between the pixel electrode 50 and the photoelectric conversion layer 51, and between the photoelectric conversion layer 51 and the upper electrode 52. Although not shown in Figure 3, an insulating protective layer, a color filter, and a macro lens may be further provided above the photoelectric conversion unit 10.

[0064] The pixel electrode 50 is located on the upper surface of the insulating layer 55 in the pixel array region R1, which is the region where the pixel array 14A is arranged in a plan view. The pixel electrode 50 is a film-like electrode. The pixel electrode 50 may include at least one selected from metals, metal compounds, and polysilicon doped with impurities to impart conductivity. Examples of metals include copper, titanium, tantalum, and aluminum. Examples of metal compounds include metal nitrides. Examples of metal nitrides include titanium nitride and tantalum nitride. The pixel electrode 50 may contain metal nitride as its main component. The pixel electrode 50 collects one of the positive and negative charges generated in the photoelectric conversion layer 51. The pixel electrode 50 is electrically isolated from the pixel electrodes 50 of other adjacent pixels 14 by being spatially separated from them.

[0065] The photoelectric conversion layer 51 is located above the pixel electrode 50 and covers the pixel electrode 50. The photoelectric conversion layer 51 contains an organic semiconductor material or an inorganic semiconductor material such as amorphous silicon or quantum dots, and receives light incident through the upper electrode 52 to generate positive and negative charges through photoelectric conversion. In other words, the photoelectric conversion layer 51 converts light into charge. The positive and negative charges are, for example, hole-electron pairs. The photoelectric conversion layer 51 is formed continuously, for example, across multiple pixels 14. The photoelectric conversion layer 51 is shared by multiple pixels 14. In other words, the photoelectric conversion layer 51 is formed monolithically on the upper surface 31a side of the pixel substrate 31. The photoelectric conversion layer 51 may be provided separately for each pixel 14 or for each block of two or more pixels 14.

[0066] The upper electrode 52 is located above the photoelectric conversion layer 51 and covers the photoelectric conversion layer 51. The upper electrode 52 is a film-like electrode. In the example shown in Figure 3, the upper electrode 52 and the photoelectric conversion layer 51 are aligned in terms of their side positions in a plan view. The upper electrode 52 is formed from a transparent conductive material such as ITO (Indium Tin Oxide) and is positioned on the light-receiving surface side of the photoelectric conversion layer 51. The upper electrode 52 is formed continuously across multiple pixels 14, similar to the photoelectric conversion layer 51. That is, the upper electrodes 52 of multiple pixels 14 are electrically connected to each other. In other words, the upper electrode 52 is formed monolithically on the upper surface 31a side of the pixel substrate 31. The upper electrode 52 may be provided separately for each pixel 14 or for each block of two or more pixels 14.

[0067] The potential of the upper electrode 52 is controlled by the voltage control circuit 30 described above. When the imaging device 100 is in operation, the potential of the upper electrode 52 is controlled to make it different from the potential of the pixel electrode 50, so that the signal charge generated by photoelectric conversion can be collected by the pixel electrode 50. For example, the voltage control circuit 30 controls the potential of the upper electrode 52 so that the potential of the upper electrode 52 is higher than the potential of the pixel electrode 50. Specifically, when the imaging device 100 is in operation, a predetermined voltage is applied to the upper electrode 52 by the voltage control circuit 30. A specific example of the predetermined voltage is a positive voltage of about 10V. As a result, the holes from the hole-electron pairs generated in the photoelectric conversion layer 51 can be collected as signal charges by the pixel electrode 50. The signal charges collected by the pixel electrode 50 are stored in a charge storage region 91 connected to the pixel electrode 50 and detected by the charge detection circuit 25. When electrons are used as the signal charge, a predetermined voltage is applied to the upper electrode 52 such that the potential of the upper electrode 52 is lower than the potential of the pixel electrode 50.

[0068] In the example shown in Figure 3A, the imaging device 100 further includes a shield electrode 53. The shield electrode 53 is located on the upper surface of the insulating layer 55. The shield electrode 53 is a film-like electrode. The shield electrode 53 faces the upper electrode 52 via the photoelectric conversion layer 51. The shield electrode 53 and the pixel electrode 50 are located on the same plane and are adjacent to each other with a predetermined gap between them. The shield electrode 53 is arranged, for example, to surround the pixel electrode 50 in a plan view. The shield electrode 53 may include at least one selected from metals, metal compounds, and polysilicon doped with impurities to impart conductivity. Examples of metals include copper, titanium, tantalum, and aluminum. Examples of metal compounds include metal nitrides.

[0069] The shield electrode 53 is positioned between two adjacent pixels 14 in a plan view, and suppresses color mixing between the two adjacent pixels 14. The shield electrode 53 is maintained at a predetermined potential, for example, when the imaging device 100 is operating. The predetermined potential is not particularly limited as long as it can suppress color mixing between adjacent pixels 14. Note that the imaging device 100 does not necessarily have to be equipped with the shield electrode 53.

[0070] The insulating layer 55 is located between the wiring layer 61 and the photoelectric conversion unit 10. The photoelectric conversion unit 10 is laminated on the upper surface of the insulating layer 55. The insulating layer 55 is a layer that is bonded to the support substrate during the manufacturing of the imaging device 100. Note that the imaging device 100 does not necessarily have an insulating layer 55. In this case, for example, the photoelectric conversion unit 10 covers the upper surface of the wiring layer 61.

[0071] The wiring layer 61 is located between the pixel substrate 31 and the photoelectric conversion unit 10. The wiring layer 61 is located on the upper surface 31a side of the pixel substrate 31 and covers the upper surface 31a of the pixel substrate 31. The wiring layer 61 includes a plurality of wirings including wiring 61a, an interlayer insulating layer between the wirings, and a plurality of vias that make electrical connections across the interlayer insulating layer. In addition, a MIM (Metal-Insulator-Metal) capacitance may be formed within the wiring layer 61. In this specification, wirings are flat conductors extending in a direction perpendicular to the thickness direction of the semiconductor substrate such as the pixel substrate 31, and vias are columnar conductors extending in a direction parallel to the thickness direction of the semiconductor substrate such as the pixel substrate 31. Note that in Figure 3, for ease of viewing, the structure within the wiring layer 61 is simplified, and the layer configuration of the interlayer insulating layer is omitted. This is also the case for other cross-sectional views and other wiring layers.

[0072] The wiring 61a is an example of a first wiring, located on the upper surface 31a side of the pixel substrate 31, and closer to the pixel substrate 31 than the photoelectric conversion unit 10. The wiring 61a electrically connects the first via 71 and the pixel 14. The wiring 61a electrically connects, for example, the first via 71 and the transistor Tr11.

[0073] The wiring layer 62 is located between the pixel substrate 31 and the wiring layer 63. The wiring layer 62 is joined to the wiring layer 63 by a first bonding surface 81. The wiring layer 62 is located on the lower surface 31b side of the pixel substrate 31 and covers the lower surface 31b of the pixel substrate 31. The wiring layer 62 includes a plurality of wirings, including wiring 62a and pad wiring 62p, an interlayer insulating layer between the wirings, and a plurality of vias that make electrical connections across the interlayer insulating layer.

[0074] The wiring 62a is an example of a second wiring and is located between the lower surface 31b of the pixel substrate 31 and the first bonding surface 81. The wiring 62a electrically connects the first via 71 and the pad wiring 62p.

[0075] The pad wiring 62p is formed in the insulating layer at the lowest side of the wiring layer 62, that is, closest to the wiring layer 63. The pad wiring 62p forms the metal joint 81a at the first joint surface 81.

[0076] The wiring layer 63 is located between the wiring layer 62 and the circuit board 41. The wiring layer 63 is located on the upper surface 41a side of the circuit board 41 and covers the upper surface 41a of the circuit board 41. The wiring layer 63 includes multiple wirings, including wiring 63a and pad wiring 63p, an interlayer insulating layer between the wirings, and multiple vias that make electrical connections across the interlayer insulating layer. In addition, MIM capacitance may be formed within the wiring layer 63.

[0077] Wiring 63a is an example of a third wiring and is located between the upper surface 41a of the circuit board 41 and the first bonding surface 81. Wiring 63a electrically connects the pad wiring 63p to the peripheral circuit 4. Wiring 63a electrically connects, for example, the pad wiring 63p to the transistor Tr21. Wiring 63a and wiring 62a are electrically connected via the first bonding surface 81.

[0078] The pad wiring 63p is formed in the uppermost part of the wiring layer 63, that is, within the insulating layer closest to the wiring layer 62. The pad wiring 63p forms the metal joint 81a at the first joint surface 81.

[0079] Each of the wirings and vias in the wiring layers 61, 62, and 63 contains at least one selected from the group consisting of, for example, copper, aluminum, tungsten, cobalt, and ruthenium. In addition, the insulating layers, such as the interlayer insulating layers in the wiring layers 61, 62, and 63, contain, for example, silicon oxide or silicon carbonitride.

[0080] The first via 71 penetrates at least a portion of the pixel substrate 31, and at least a portion of it is located within the pixel substrate 31. The first via 71 is, for example, a TSV (Through Silicon Via). Wiring 61a and wiring 62a are electrically connected via the first via 71. The first via 71 is in contact with wiring 62a.

[0081] The first via 71 is, for example, an nTSV (nanoTSV) having a diameter on the nano-order. The diameter of the first via 71 is, for example, less than 1000 nm. The diameter of the first via 71 may be 100 nm or less, or 10 nm or less. Alternatively, the diameter of the first via 71 may be, for example, 1 nm or more. The diameter of the first via 71 may be 5 nm or more. Furthermore, the first via 71 may be a μTSV (microTSV) having a diameter on the microm order.

[0082] The first via 71 includes, for example, at least one selected from the group consisting of copper, aluminum, tungsten, cobalt, and ruthenium. The first via 71 may contain copper as the main component, where the main component means the component that is present in the most abundant amount by mass. In one example, the main component is a component that makes up more than 50% by mass. The main component may also be a component that makes up more than 80% by mass.

[0083] The first via 71 is formed, for example, by drilling a hole in the thickness direction of the pixel substrate 31 and depositing a metal such as copper into the hole. When forming a hole, the tip of the hole becomes narrower. In the example shown in Figure 3, the upper side of the first via 71 is narrower than the lower side, so the first via 71 is formed from the lower surface 31b side of the pixel substrate 31. The diameter of the first via 71 exemplified above is the maximum diameter of the first via 71, and in the example shown in Figure 3, it is the diameter of the lowest part of the first via 71.

[0084] The second via 72 is located within the pixel substrate 31. In the example shown in Figure 3, the second via 72 is formed within an isolation region 95 formed in the pixel substrate 31. The isolation region 95 is an isolation region that separates the pixel array 14A from the peripheral portion of the pixel array 14A. The isolation region 95 is located within the pixel substrate 31. The isolation region 95 is, for example, an STI (Shallow Trench Isolation) structure. The STI structure is formed in the pixel substrate 31 by an STI process. The second via 72 is, for example, an embedded via formed by embedding metal in a trench for forming the STI structure. The second via 72 includes, for example, at least one selected from the group consisting of copper, aluminum, tungsten, cobalt, and ruthenium.

[0085] As shown in Figure 3A, a liner film 71a is formed on the radial outer surface of the first via 71. The first via 71 and the pixel substrate 31 are separated by the liner film 71a. Similarly, a liner film 72a is formed on the radial outer surface of the second via 72. The second via 72 and the pixel substrate 31 are separated by the liner film 72a. The liner films 71a and 72a include an insulating film made of at least an insulating material such as silicon oxide. The liner films 71a and 72a may have a laminated structure of an insulating film and a metal nitride such as titanium nitride or a metal such as titanium.

[0086] The third via 73 is partially located within the pixel substrate 31. In the example shown in Figure 3, the third via 73 is partially formed within an isolation region 95 formed in the pixel substrate 31. The third via 73 electrically connects the wiring 61a and the first via 71. The third via 73 is in contact with the wiring 61a. The third via 73 includes, for example, at least one selected from the group consisting of copper, aluminum, tungsten, cobalt, and ruthenium. The third via 73 is formed, for example, by forming a hole in the isolation region 95 within the pixel substrate 31 and the insulating layer on the isolation region 95 by etching or the like, and depositing a metal such as copper in the hole.

[0087] The wiring 61a and the first via 71 are electrically connected via the second via 72. Furthermore, the wiring 61a and the second via 72 are electrically connected via the third via 73. Therefore, the wiring 61a and the first via 71 are electrically connected via the second via 72 and the third via 73. The first via 71 and the second via 72 are directly connected within the pixel substrate 31, and the second via 72 and the third via 73 are directly connected within the pixel substrate 31. The length of the first via 71 may be longer than the lengths of the second via 72 and the third via 73. The first via 71, the second via 72, and the third via 73 overlap each other in a plan view. Also, the first via 71, the second via 72, and the third via 73 overlap with the separation region 95 formed on the pixel substrate 31 in a plan view.

[0088] The first bonding surface 81 is located between the pixel substrate 31 and the circuit board 41. In the example shown in Figure 3, the lower surface of the wiring layer 62 and the upper surface of the wiring layer 63 are bonded at the first bonding surface 81. In other words, the first bonding surface 81 is located at the interface between the wiring layer 62 and the wiring layer 63. Furthermore, the first bonding surface 81 is the surface where the wafer containing the pixel substrate 31 and the wafer containing the circuit board 41 are bonded by hybrid bonding, and includes a metal bonding surface 81a and an insulating film bonding surface 81b. In Figure 3, for clarity, some of the metal bonding surfaces 81a and insulating film bonding surfaces 81b are indicated by reference numerals, but metal bonding surfaces 81a and insulating film bonding surfaces 81b are formed throughout the entire first bonding surface 81.

[0089] The metal joint 81a is formed by joining the pad wiring 62p and the pad wiring 63p. For example, if the pad wirings 62p and 63p mainly contain copper, the metal joint 81a is a Cu-Cu joint. The insulating film joint 81b is formed by joining the insulating layer of the same layer as the pad wiring 62p included in the wiring layer 62 and the insulating layer of the same layer as the pad wiring 63p included in the wiring layer 63.

[0090] As described above, in the imaging device 100 according to this embodiment, the amplification transistor 11, which has a fin-shaped three-dimensional transistor structure, is spaced apart from the charge storage region, with a recessed portion 31C between them. By making the gate of the pixel transistor a fin-shaped or other three-dimensional shape, the effective gate width increases even within the same pixel region area, and the gate area increases, and as a result, noise degradation can be suppressed even in a miniaturized pixel region. Forming a fin-shaped three-dimensional structure requires processing such as etching, but at this time, damage such as plasma damage occurs to the substrate. Also, stress can occur near the recessed side surface, and stress-induced defects may occur. Therefore, by forming the charge storage region spaced apart from the fin-shaped amplification transistor with the recessed portion 31C in between, damage to the charge storage region and the occurrence of defects can be suppressed, and as a result, dark current degradation can be suppressed.

[0091] To form three-dimensional shapes such as columnar or fin shapes, etching the substrate requires shaping by first forming a deposited layer on the substrate and then etching that portion. In this case, by etching the substrate at a position separated from the diffusion layer of the charge accumulation region to create a three-dimensional gate structure, direct damage to the charge accumulation region can be suppressed. If the fin shape is formed on the upper side of the substrate and the entire front surface other than the fin is etched, plasma damage will occur directly to the charge accumulation region as well. Furthermore, the charge accumulation region side can proceed with subsequent process steps without any steps.

[0092] In photoelectric conversion film stacked imaging devices, the charge from the photoelectric conversion film remains in the charge storage region for a long time via polyplugs. Compared to photodiode type imaging devices formed on a silicon substrate, this device has the characteristic of having a greater impact on dark current due to damage to the charge storage region, and its degradation can be reduced.

[0093] Fin refers to a structure that controls the channel region by surrounding it with electrodes in a three-dimensional manner, similar to a fish's dorsal fin.

[0094] [Flat layout] Next, the planar layout of the imaging device 100 according to this embodiment will be described. Figure 3B is a schematic plan view (i) and cross-sectional view (ii) showing an example of the planar layout of the imaging device 100 according to this embodiment. In Figure 3B(i), the arrangement of the amplification transistor 11, charge storage region 91, selection transistor, reset transistor, and OF transistor is schematically shown in a plan view. Also in Figure 3B(i), the pixel region R2, which is the region where the pixels 14 are arranged in a plan view, is shown as a dotted rectangle. In a plan view, the charge storage region is on the right side and the amplification transistor is on the left side. The right side is the charge storage region side and the left side is the amplification transistor side, and for example, a recessed portion is formed between the amplification transistor side and the charge storage side.

[0095] A reset transistor and an OF-transistor are formed to the right of the recess, with a charge storage region in between. An amplifying transistor and a select transistor are formed to the left of the recess, sharing a source-drain diffusion layer, and the gate structure of the amplifying transistor is a fin structure. The fin structure increases the gate width of the amplifying transistor. Multiple fins (two or more) may be used. In this way, random noise can be reduced by increasing the effective gate length and gate width of the amplifying transistor.

[0096] Both the amplifying transistor and the selecting transistor may be of the Fin type.

[0097] The reset transistor and OF-transistor, which share a charge storage region, may also be of the planar type.

[0098] By using a planar transistor that includes a charge storage region as either the source or drain, and spacing out the fin-type transistors that are susceptible to etching damage, damage and defects to the charge storage region can be suppressed, thereby reducing the degradation of dark current.

[0099] Figure 3B(ii) shows a schematic diagram of the cross-section of the XY line in Figure 3B(i).

[0100] On the left side of the recess where the amplification transistor is located, the substrate is recessed to form a fin-type channel. On the right side, where the charge storage region is located, the substrate surface is not recessed, so it is located above the bottom surface of the fin that forms the recess. In this case, it is also possible to form the STI before etching the fin shape and then form the fin gate.

[0101] Since a defect layer may form on the side wall 31d of the recessed portion due to plasma damage or stress during etching, a dark current prevention layer may be formed in this side wall region by injecting p-type impurities, such as boron.

[0102] [Modified example of a transistor on the charge storage region side] Next, we will describe a modified transistor in which the charge storage region and the diffusion layer are shared on the charge storage region side. In the following, we will focus on the differences from Embodiment 1, and omit or simplify the explanation of the common points. Figures 4A and 4B show the plan view and bird's-eye view of the charge storage region, reset transistor, and OF-transistor.

[0103] Transistors that share a charge storage region and a diffusion layer, such as reset transistors and OF transistors, may have a three-dimensional gate structure. However, in order to suppress etching damage to the charge storage region, it is preferable that the etching width d1 on the side in contact with the charge storage diffusion layer is longer than the diffusion region width W1 that forms the charge storage region. As a result, the end of d1 that is spaced apart from the diffusion region (dashed line) that acts as charge storage becomes the side surface of the recess, and etching damage to the charge storage layer is suppressed. In this case, the gate width of the reset transistor is W1 on the side in contact with the charge storage layer and W2 on the side that is not in contact, resulting in an asymmetrical gate width structure.

[0104] In the reset transistor shown in Figure 4B, the gate width on the side in contact with the charge storage region is wider than the gate width on the side not in contact with the charge storage region, resulting in an asymmetrical gate width. This asymmetrical structure reduces the impact of 3D gate etching damage on the diffusion layer that directly forms the charge storage region.

[0105] By also adopting a three-dimensional transistor structure for the transistor in the charge storage region, the gate width can be increased.

[0106] In this case, the substrate region containing the charge accumulation region is surrounded by etched recesses, but the charge accumulation region and the etched recesses are spaced apart, making them less susceptible to etching damage.

[0107] [Manufacturing method] Next, a method for manufacturing the recessed portion of the imaging device 100 according to this embodiment will be described.

[0108] The details of the manufacturing method for the recessed portion of the imaging device 100 will be described below with reference to the drawings. Figures 5A to 5C are cross-sectional views illustrating the process of forming the recessed portion and the fin-shaped portion of the amplification transistor. In the manufacturing of the imaging device 100, conventionally known methods such as semiconductor integrated circuit formation processes can be used for forming impurity regions and isolation regions in the semiconductor substrate such as the pixel substrate 31, as well as for forming interlayer insulating layers, wiring, vias, and electrodes.

[0109] First, prepare the pixel substrate 31 as shown in Figure 5A. Figure 5A shows the state in which the charge storage region 91 and the STI isolation region 95 have been formed on the upper surface 31a of the pixel substrate 31. The silicon substrate is etched to form the fin structure of the amplification transistor, but the STI isolation may be formed before fin etching.

[0110] Next, as shown in Figure 5B, the substrate is etched to form a fin-shaped gate. Etching damage occurs to the substrate at this time. Damage and stress-induced defect layers may form on the side wall 31d on the charge storage region side of the etched portion. After this, boron may be injected between the fin etch layer and the charge storage region to form a leak prevention layer.

[0111] Next, a gate oxide film is formed on the fin-shaped surface, as shown in Figure 5C.

[0112] (Embodiment 2) Next, Embodiment 2 will be described. Embodiment 2 describes a camera system equipped with an imaging device according to the present disclosure.

[0113] Figure 6 is a block diagram showing an example of the configuration of the camera system 400 according to this embodiment.

[0114] As shown in Figure 6, the camera system 400 according to this embodiment comprises a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing circuit 604. The camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0115] The lens optical system 601 focuses light onto the imaging surface of the imaging device 602. The lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. As the imaging device 602, for example, an imaging device according to either Embodiment 1 or a modified version thereof described above may be used.

[0116] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

[0117] The camera signal processing circuit 604 has the function of processing the output signal from the imaging device 602. The camera signal processing circuit 604 receives output data from the imaging device 602 and performs processing such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The imaging device 602 and the camera signal processing circuit 604 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With such a configuration, the electronic device that includes the imaging device 602 as part can be made smaller.

[0118] (Other embodiments) The imaging apparatus and camera system relating to this disclosure have been described above based on embodiments, but this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to the embodiments that a person skilled in the art could conceive, as well as other forms constructed by combining some of the components of the embodiments, are also included in the scope of this disclosure.

[0119] Furthermore, in the above embodiment, for example, the photoelectric conversion unit 10 included a pixel electrode 50, a photoelectric conversion layer 51, and an upper electrode 52, but is not limited to this. The photoelectric conversion unit 10 may also be a photodiode.

[0120] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or their equivalents. [Industrial applicability]

[0121] The imaging device and camera system described herein are useful for, for example, image sensors, digital cameras, etc. The imaging device and camera system described herein can be used for medical cameras, robot cameras, security cameras, cameras mounted on vehicles, etc. [Explanation of Symbols]

[0122] 10 Photoelectric conversion unit 11 Amplifying transistors 12 Reset transistor 13 Address Transistors 14 pixels 14A Pixel Array 15 Vertical scanning circuit 16 Opposite electrode signal line 17 Vertical signal line 18 Load circuit 19-column signal processing circuit 20 Horizontal signal readout circuit 21 Power line 22 Differential Amplifier 23 Feedback Line 24 Charge Storage Nodes 25 Charge detection circuit 26 Address signal line 27 Reset signal line 28 Horizontal common signal line 30 Voltage control circuit 31, 32 pixel substrate 31a, 32a, 41a, 42a top surface 31b, 32b, 41b bottom side 31c Excavation 31d Side wall of the excavated section 31W, 41W wafers 41, 42 Circuit board 50 Pixel Electrodes 51 Photoelectric conversion layer 52 Upper electrode 53 Shielding electrode 55, 62I, 63I insulating layer 56 Support substrate 61, 62, 62M, 63, 63M, 64, 65, 66, 132, 143, 161, 171, 176 wiring layer 61a, 62a, 63a, 63b, 64a, 65a, 66a Wiring 61p, 62p, 63p, 64p, 65p, 66p pad wiring 71 First Beer 71a, 72a, 74a, 75a Liner film 71G Via Group 1 72 Second Beer 73 Third Beer 74. 4th Beer 75. 5th Beer 76. 6th Beer 81 1st joint surface 81a, 82a, 83a metal joining 81b, 82b, 83b Insulating film junction 82 Second joint surface 83 Third joint surface 91 Charge storage region 92 plugs 95, 96 separation area 100 Imaging device 101, 101A, 102, 103, 103A, 104, 105, 106, 107, 200, 602 Imaging devices 400 Camera System 601 Lens Optics 603 System Controller 604 Camera signal processing circuit R1 Pixel array region Tr11, Tr12, Tr13, Tr14, Tr21 Transistors

Claims

1. circuit board and A photoelectric conversion film disposed on the aforementioned substrate, which converts light into electric charge, An electrode for collecting the aforementioned charge, A first transistor whose gate is electrically connected to the electrode, A second transistor, which is a charge storage region in which either the source or drain is electrically connected to the electrode, Equipped with, The substrate includes a recessed portion, The first transistor is positioned in the recessed portion and has a fin structure. The second transistor is not placed in the recessed portion. Imaging device.

2. The second transistor is of the Planar type. The imaging apparatus according to claim 1.

3. Including an impurity region arranged to surround the first transistor, The imaging apparatus according to claim 1.

4. The substrate includes a first surface on the light incident side and a second surface opposite to the first surface. The first transistor has a gate electrode whose bottom surface is lower than the first surface of the substrate. The imaging apparatus according to claim 1.

5. The second transistor is a reset transistor. The imaging apparatus according to claim 1.

6. Either the source or the drain is the charge storage region, and the system further comprises a third transistor different from the second transistor. The aforementioned third transistor is of the Planar type. The imaging apparatus according to claim 1 or 2.

7. The aforementioned third transistor is an OF transistor. The imaging device according to claim 6.

8. In the second transistor, the gate width in contact with either the source or the drain is narrower than the gate width in contact with the other of the source or the drain. The imaging apparatus according to claim 1.

9. The first transistor further comprises an impurity region arranged to surround it. The imaging apparatus according to claim 1.

10. The substrate and the impurity region have the same conductivity type. The imaging device according to claim 9.

Images