Capacitor board unit

Abstract

The apparent current flowing through multiple capacitors tends to flow more easily through the capacitor with the lowest effective resistance in the electrical circuit, causing the capacitor to heat up locally. [Solution] Each capacitor board 10A (10B) has multiple via holes (reference potential connection parts) for connecting to a reference potential, spaced apart along the first direction D1, on one side of the other side of the second direction D2 of one capacitor board 10A. On the other side of the other capacitor board 10B, connection terminals (other potential connection parts) 14A to 14D for connecting to other potentials having a potential difference from the reference potential, spaced apart along the first direction D1, and the pair of capacitor boards 10A and 10B are electrically connected in series by connecting the connection terminals (inter-board connection parts) 13A to 13D with electrical wiring 31A to 31D.

Description

Technical Field

[0001] The present invention relates to a capacitor substrate unit.

Background Art

[0002] Conventionally, power units mounted with a plurality of capacitors have been proposed. For example, Patent Document 1 proposes a unit in which a plurality of capacitors are divided into two groups and arranged on a wiring substrate. The plurality of capacitors are connected in series, and a pair of connection terminals are provided at both ends thereof.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, since the apparent current flowing to the plurality of capacitors flows between the pair of connection terminals provided at both ends thereof, this current tends to flow substantially to the capacitors with low impedance in the electric circuit, and the capacitors are prone to local heat generation.

[0005] The present invention has been made in view of such points, and an object thereof is to provide a capacitor substrate unit capable of suppressing local heat generation of capacitors even when a plurality of capacitors are mounted.

Means for Solving the Problems

[0006] In view of the above problems, the capacitor board unit according to the present invention is a capacitor board unit comprising a pair of capacitor boards on which a plurality of capacitors are mounted on a wiring board, wherein each capacitor board has a plurality of capacitor groups in which the plurality of capacitors are arranged in a line along a first direction and are electrically connected in parallel via opposing wiring patterns formed on the wiring board along the first direction, wherein the plurality of capacitor groups of each capacitor board are arranged in a line in a second direction perpendicular to the first direction and are electrically connected in series via wiring patterns connected to adjacent capacitor groups, and on one side of each capacitor board in the second direction, the first direction Multiple inter-board connection portions are provided at intervals along the direction, and on one side of the other side of one of the pair of capacitor boards in the second direction, multiple reference potential connection portions for connecting to a reference potential are provided at intervals along the first direction, and on one side of the other side of the other capacitor board in the second direction, multiple other potential connection portions for connecting to other potentials having a potential difference from the reference potential are provided at intervals along the first direction, and the pair of capacitor boards are electrically connected in series by connecting each of the inter-board connection portions with electrical wiring.

[0007] According to the present invention, since multiple capacitors are mounted on each wiring board of a pair of capacitor boards, the heat generated by the multiple capacitors can be shared among the capacitor boards. Here, on one side of each capacitor board in the second direction, multiple inter-board connection points are provided at intervals along the first direction. Furthermore, on the other side of one of the pair of capacitor boards in the second direction, multiple reference potential connection points for connecting to a reference potential are provided at intervals along the first direction. In addition, on the other side of the other capacitor board in the pair of capacitor boards in the second direction, multiple other potential connection points for connecting to other potentials having a potential difference from the reference potential are provided at intervals along the first direction. As a result, multiple current paths are formed between the multiple reference potential connection points and the multiple inter-board connection points on one capacitor board. Furthermore, multiple current paths are formed between the multiple other potential connection points and the multiple inter-board connection points on the other capacitor board. In addition, since the inter-board connection points of each capacitor board are connected to each other by electrical wiring, multiple current paths are also formed between each capacitor board. Therefore, even when a pair of capacitor boards are connected, multiple current paths are formed in the multiple capacitors mounted on the wiring board of each capacitor board, and the current is divided. As a result, localized heating of the capacitors mounted on the wiring board can be suppressed.

[0008] In a more preferred embodiment, the lengths of the electrical wiring are the same. In this embodiment, by making the lengths of the electrical wiring connected to each inter-board connection between capacitor boards the same, the resistance of the electrical wiring becomes equal. This makes it possible to equalize the current flowing through the electrical wiring to each inter-board connection, and as a result, the heat generated by the multiple capacitors mounted on the wiring board of each capacitor board can be uniformly distributed.

[0009] In a more preferred embodiment, each capacitor substrate has a plurality of capacitor groups on both sides of the wiring substrate, the capacitor substrate is housed in a housing case, the bottom wall of the housing case is made of a metal material, a spacer is provided between the capacitor substrate and the bottom wall, and the space formed between the capacitor substrate and the bottom wall of the housing case by the spacer is filled with an insulating filler.

[0010] According to this embodiment, the spacer formed on the capacitor substrate ensures a space for filling material between the capacitor substrate and the bottom wall of the housing case, thereby reducing the formation of gaps due to insufficient filling of the material between them. As a result, the heat generated by the capacitor substrate can be efficiently dissipated through the metal bottom wall of the housing case via the filling material.

[0011] In a more preferred embodiment, each wiring board has a plurality of through holes formed between adjacent wiring patterns. In this embodiment, it becomes easier to fill the space between the capacitor board and the bottom wall of the housing case from the surface side of the capacitor board through the plurality of through holes formed in the wiring board.

[0012] In a more preferred embodiment, the reference potential connection portion is formed on the wiring board, and the group of capacitors arranged on one side of the other capacitor board is connected to the reference potential by electrically connecting each of the reference potential connection portions and the bottom wall which becomes the reference potential via the metal spacer, and the group of capacitors arranged on one side of the other capacitor board is connected to the other potential by electrically connecting each of the other potential connection portions and the busbar which becomes the other potential via current collection wiring.

[0013] In this embodiment, on one capacitor board, each reference potential connection point is electrically connected to the bottom wall of the housing case, which is the reference potential, via a metal spacer. This connects the group of capacitors located on one side of the other capacitor board to the reference potential (e.g., ground potential). As a result, the group of capacitors located on one side of the other board can be connected to the reference potential via the spacer and the bottom wall of the housing case in a simple structure, without the need to provide wiring for the reference potential.

[0014] Furthermore, on the other capacitor board, the other potential connection points and the busbars, which are at a different potential, are connected to each other via current collection wiring, so that the group of capacitors located on one side of the other board is connected to a different potential. This allows the charge stored in the group of capacitors connected in series on the pair of capacitor boards to be collected from the other potential connection points to the busbars via the current collection wiring. [Effects of the Invention]

[0015] According to the present invention, even when multiple capacitors are installed, it is possible to suppress localized heating of the capacitors. [Brief explanation of the drawing]

[0016] [Figure 1] This is a schematic circuit diagram of an inverter circuit as an example of a circuit to which the capacitor board unit according to an embodiment of the present invention is applied. [Figure 2] Figure 1 is a schematic plan view of the capacitor board unit shown. [Figure 3] Figure 2 shows the capacitor board unit, specifically the electrical circuit diagram of one side of the capacitor board. [Figure 4] Figure 3 is a schematic layout diagram showing the physical positional relationship between the capacitors mounted on each capacitor board and the wiring patterns, etc. [Figure 5] Figure 2 is a schematic perspective view of the substrate housing that constitutes the capacitor board unit shown. [Figure 6]It is an exploded perspective view of the substrate container shown in FIG. 5. [Figure 7] It is an exploded perspective view of the capacitor substrate shown in FIG. 5. [Figure 8] It is a cross-sectional view as viewed from the arrow direction along the line A-A shown in FIG. 5. [Figure 9] It is a cross-sectional view as viewed from the arrow direction along the line B-B shown in FIG. 5. [Figure 10] It is an image diagram of high-frequency current flowing through a plurality of capacitors mounted on each capacitor substrate shown in FIG. 4. [Mode for Carrying Out the Invention]

[0017] Hereinafter, the capacitor substrate unit 1 according to the embodiment of the present invention will be described with reference to FIG. 1 to FIG. 10.

[0018] The capacitor substrate unit 1 according to the present embodiment is a unit on which a plurality of capacitors functioning as bypass capacitors for the DC line of a high-voltage inverter with an absolute potential value of several kV to several tens of kV are mounted. Note that, among the capacitor substrate unit 1, the substrate on which the capacitor 11 is mounted is referred to as a capacitor substrate 10A (10B).

[0019] FIG. 1 is a schematic circuit diagram of an inverter circuit 100 as an example of a circuit to which the capacitor substrate unit 1 is applied. The inverter circuit 100 includes a first switching unit 110, a second switching unit 120, an output node 13, and the capacitor substrate unit 1. Further, the inverter circuit 100 has a first input terminal 101, a second input terminal 102, a first output terminal 103, and a second output terminal 104. The first input terminal 101 is connected to a reference potential such as a ground potential, for example. Note that the reference potential may be not only 0V but also a potential having a predetermined potential difference from 0V.

[0020] A DC power supply 200 is connected between the first input terminal 101 and the second input terminal 102 to supply a DC voltage. The DC power supply 200 supplies a DC voltage of, for example, 12kV, but since the first output terminal 103 of the DC power supply 200 is connected to a reference potential, a negative voltage such as -12kV is applied to the inverter circuit 100.

[0021] The first output terminal 103 is connected to a reference potential, such as ground potential. The second output terminal 104 is connected to the output node 130, which is the connection point between the first switching unit 110 and the second switching unit 120. An RLC load 300 is connected between the first output terminal 103 and the second output terminal 104.

[0022] The first switching section 110 and the second switching section 120 are each configured by connecting multiple switching elements in series. The switching elements are, for example, MOSFETs (metal-oxide-semiconductor field-effect transistors), but other switching elements such as IGBTs (Insulated Gate Bipolar Transistors) may also be used. Although not shown in Figure 1, the first switching section 110 and the second switching section 120 are equipped with drivers and the like for driving the switching elements.

[0023] In such an inverter circuit 100, with a DC voltage applied to the inverter circuit 100 from the DC power supply 200, the first switching unit 110 and the second switching unit 120 repeatedly switch on and off alternately. That is, when the first switching unit 110 is on, the second switching unit 120 is off, and when the first switching unit 110 is off, the second switching unit 120 is on. By performing this switching operation, pulsed voltages of -12kV and 0kV are generated between the first output terminal 103 and the second output terminal 104, and these pulsed voltages are applied to the RLC load 300. As a result, AC current flows through the capacitor board unit 1.

[0024] The frequency of pulsed voltage waveforms is typically around several hundred kHz. However, depending on the application, various frequencies are used, such as several tens of kHz or around 1 MHz. Thus, the frequency of pulsed voltage waveforms is relatively high, belonging to what is known as the high-frequency band.

[0025] The capacitor board unit 1 described above, which functions as a bypass capacitor, is used not only to stabilize DC current but also to supply current containing high-frequency components, such as surges during switching of a high-voltage inverter. Generally, a bypass capacitor should be a type of capacitor with a low DC equivalent resistance (ESR), and in this embodiment, a ceramic capacitor is used as capacitor 11.

[0026] Generally, a single capacitor that possesses both high voltage resistance of several kV to tens of kV and low ESR does not exist. Therefore, in the following embodiment, the capacitor board unit 1 connects multiple capacitors 11 in series and parallel, treating these multiple capacitors 11 as a single capacitor, thereby achieving both high voltage resistance and low ESR.

[0027] However, when multiple capacitors are connected in series and parallel, variations in equivalent series inductance (ESL) occur physically within the capacitor board, and high-frequency currents may flow only through areas with low ESL. In other words, in a capacitor board with multiple capacitors connected in series and parallel, current may not flow uniformly through each capacitor on the board.

[0028] According to the inventor's findings, when current is passed between a pair of terminals formed on both sides of an electrical circuit composed of multiple capacitors on a single capacitor board, a large amount of current flows through the capacitor on the path with the lowest electrical impedance. As a result, variations occur in the amount of heat generated by each of the multiple capacitors, causing localized heating of the capacitors. In consideration of these points, the details of a capacitor board unit 1, one embodiment of the inventor's design, are described below.

[0029] As shown in Figure 2, the capacitor board unit 1 comprises a pair of capacitor boards 10A and 10B, each having multiple capacitors 11, 11, ... mounted on a wiring board 15. In this embodiment, the capacitors 11 are ceramic capacitors. Each capacitor board 10A (10B) is housed in a housing case 20. In this embodiment, each capacitor board 10A (10B), when housed in the housing case 20, constitutes a board housing 50A (50B). With the board housings 50A and 50B placed side by side, each capacitor board 10A and 10B is connected to each other by electrical wiring 31A to 31D, which will be described later.

[0030] In this embodiment, as will be described later, one capacitor board 10A is electrically connected to a reference potential (for example, ground potential). The other capacitor board 10B is connected to a busbar 40 at a different potential (for example, -12kV) via a plurality of current collection wires 32A to 32D. As shown in Figure 2, each capacitor board 10A (10B) has a plurality of capacitor groups 11A on one side, each consisting of a plurality of capacitors 11 (for example, 20 in a row), and each group has a plurality of such groups (for example, 10).

[0031] As shown in Figure 7, which will be described later, the wiring board 15 has multiple (e.g., 10) wiring patterns 15f formed along the first direction D1, spaced apart in the second direction D2. Specifically, the spacing between the wiring patterns 15f is equal. Of the multiple wiring patterns 15f, 15f, ..., the wiring patterns 15f at both ends are electrically connected to connection terminals 13A~13D, 14A~14D, conductive via holes 17A~17E, etc., which will be described later.

[0032] The multiple capacitors 11 constituting each capacitor group 11A (20 on one side of the circuit board) are arranged in a line along the first direction D1 (see Figures 2 and 5-7) and are electrically connected in parallel via opposing wiring patterns 15f, 15f (see Figures 3 and 7).

[0033] Figure 3 is an electrical circuit diagram of one side of the capacitor board unit 1 shown in Figure 1, on the capacitor board 10A (10B). Figure 4 is a schematic arrangement diagram showing the physical positional relationship between the capacitor 11 mounted on each capacitor board 10A (10B) and the wiring pattern 15f, etc. Note that since each capacitor board 10A (10B) has basically the same structure, only one is shown in the diagram.

[0034] As shown in Figures 2 and 3, opposing wiring patterns 15f, 15f are connected at one end by a resistor 12. By providing the resistor 12, it is possible to discharge the multiple capacitors 11 while ensuring the voltage balance of the multiple capacitors 11. As shown in Figure 7, the wiring board 15 has multiple through holes 15a, 15a, ... formed between opposing wiring patterns 15f along the first direction D1.

[0035] Furthermore, the multiple capacitor groups 11A, 11A, ... on each capacitor board 10A (10B) are arranged in a line in a second direction D2 perpendicular to the first direction D1 (see Figures 2 and 5), and are electrically connected in series via a wiring pattern 15f connected to adjacent capacitor groups 11A (see Figure 3). In this embodiment, adjacent capacitor groups 11A are connected to a common wiring pattern 15f (see Figure 7).

[0036] In addition to describing the wiring pattern 15f and capacitors 11 on the surface of the wiring board 15, the back surface of the wiring board 15 also has the same wiring pattern 15f as the surface, and multiple capacitors 11, 11, ... are connected to this wiring pattern 15f, just as on the surface. In particular, in this embodiment, each capacitor board 10A (10B) has a symmetrical structure with respect to a virtual plane that passes through the center of the thickness of the wiring board 15.

[0037] Specifically, as shown in Figure 7, each capacitor board 10A (10B) has multiple capacitor groups 11A on both sides, each consisting of multiple capacitors 11 (for example, 20 in a row), and these groups (for example, 10) are provided. Therefore, each capacitor board 10A (10B) has 400 capacitors 11 mounted on it. Mounting capacitors 11 on both sides of each capacitor board 10A (10B) in this way allows for a larger capacitance compared to mounting them on only one side. Of course, capacitors 11 may be mounted on only one side of each capacitor board 10A (10B), or on both sides.

[0038] As shown in Figure 7, multiple (e.g., four) first mounting holes 15b are formed on both sides of the wiring board 15 in the second direction D2, spaced apart along the first direction D1. On one side of the wiring board 15 in the second direction D2, connection terminals 14A to 14D are attached to the first mounting holes 15b. On the other side of the wiring board 15 in the second direction D2, connection terminals 13A to 13D are attached to the first mounting holes 15b. The first mounting holes 15b are conductive via holes, and by attaching each connection terminal 13A to 13D and 14A to 14D, each connection terminal 13A to 13D and 14A to 14D becomes electrically connected to the wiring patterns 15f formed on both sides of the wiring board 15.

[0039] The connection terminals 13A to 13D of the pair of capacitor boards 10A and 10B are an example of the "inter-board connection portion" as defined in this invention. Furthermore, the connection terminals 14A to 14D of the other capacitor board 10B are an example of the "other potential connection portion" of this invention. As will be described later, the via holes 17A to 17E provided on one side of the other side of the second direction D2 of one capacitor board 10A are given as an example of the "reference potential connection portion" of this invention, but the "reference potential connection portion" may also be the connection terminals 14A to 14D of one capacitor board 10A.

[0040] Furthermore, on both sides of the wiring board 15 in the second direction D2, multiple (e.g., five) second mounting holes 15c are formed at intervals along the first direction D1. Each of the aforementioned first mounting holes 15b is formed between the second mounting holes 15c along the first direction D1. The second mounting holes 15c function as conductive via holes 17A to 17E. Each first mounting hole 15b and each second mounting hole 15c is electrically connected to the wiring patterns 15f at both ends formed on both sides of the wiring board 15.

[0041] In this embodiment, via holes 17A to 17E, spaced apart along the first direction D1 on one side of the second direction D2 of one capacitor substrate 10A, are connected to a reference potential (e.g., ground potential). The via holes 17A to 17E are an example of the "multiple reference potential connection points" of the present invention. Metal spacers 31 are attached from the back side of the wiring board 15 to cover the second mounting hole 15c and to be electrically connected to each via hole 17A to 17E. The metal spacers 31 are made of a conductive material such as stainless steel, aluminum, or copper, and are electrically connected to the conductive via holes 17A to 17E. Spacers 31 are also attached to the second mounting hole 15c formed on one side of the second direction D2 of one capacitor substrate 10A, and to the second mounting holes 15c formed on both sides of the second direction D2 of the other capacitor substrate 10B. These spacers 31 are made of an insulating material such as ceramics or resin.

[0042] In this embodiment, the pair of capacitor boards 10A and 10B are electrically connected in series by connecting their respective connection terminals 13A to 13D (inter-board connection parts) with electrical wiring 31A to 31D, thereby connecting the capacitor group 11A of capacitor board 10A and the capacitor group 11A of capacitor board 10B. As described above, on one side of each capacitor board 10A (10B) in the second direction, there are multiple (for example, four) connection terminals 13A to 13D electrically connected to the wiring pattern 15f, spaced apart along the first direction D1.

[0043] The connection terminals 13A to 13D located at the same positions on capacitor boards 10A and 10B are electrically connected via electrical wiring 31A to 31D. For example, connection terminal 13A of capacitor board 10A and connection terminal 13A of capacitor board 10B are connected via electrical wiring 31A. Electrical wiring 31A to 31D is wiring in which the wire is coated with silicone resin. In this embodiment, it is preferable that the electrical wiring 31A to 31D connected to the respective connection terminals 13A to 13D of capacitor boards 10A and 10B are of the same length in order to match the equivalent DC resistance (ESR) and equivalent series inductance (ESL). It is also preferable that the electrical wiring 31A to 31D are made of the same type of wire.

[0044] As shown in Figure 6, each capacitor board 10A (10B) is housed in a housing case 20 for the capacitor board 10A (10B). The housing case 20 has an opening on the surface side of each capacitor board 10A (10B). The housing case 20 has a bottom wall 25, first side walls 21, 21 that rise from the periphery of the bottom wall 25, and a pair of second side walls 22, 22. The pair of first side walls 21, 21 extend along a first direction D1, and the pair of second side walls 22, 22 extend along a second direction D2 so as to sandwich both end faces of the pair of first side walls 21, 21. A recess 23 is formed on the outer surface of the first side wall 21 along the depth direction of the housing case 20, and a fixing hole 27a is provided at the bottom of the recess 23. By inserting fasteners (not shown) through the fixing holes 27a in the first side wall 21 and the fixing holes 27b in the bottom wall 25, the first side wall 21 and the bottom wall 25 can be connected, and the storage case 20 can be fixed to external equipment, etc.

[0045] In this embodiment, the first side wall 21 and the second side wall 22 are made of ceramics or resin. Furthermore, the bottom wall 25 of the housing case 20 facing each capacitor substrate 10A (10B) may be made of ceramics such as alumina, but in this embodiment it is made of a metal material such as aluminum or copper. A spacer 31 is provided between each capacitor substrate 10A (10B) and the bottom wall 25.

[0046] As shown in Figures 7 and 8, in this embodiment, the spacer 31 is a stepped cylindrical body having a small diameter portion 31a and a large diameter portion 31b. The small diameter portion 31a of the spacer 31 is housed in a positioning hole 26 formed in the bottom wall 25, while the large diameter portion 31b of the spacer 31 supports the capacitor substrate 10A (10B) relative to the bottom wall 25. A screw hole is formed on the end face of the large diameter portion 31b, extending axially from the top surface. The spacer 31 can be fixed to the capacitor substrate 10A (10B) by inserting a retaining screw (not shown) through the second mounting hole 15c of the wiring board 15 and screwing it into the screw hole of the spacer 31.

[0047] In this embodiment, as described above, via holes (reference potential connection points) 17A to 17E are formed in the wiring board. The bottom wall 25 of the housing case 20 is at the reference potential. In one capacitor board 10A, the group of capacitors 11A located on one side of the other second direction D2 is connected to the reference potential by making electrical connections between each via hole 17A to 17E and the bottom wall 25 of the housing case 20 via a metal spacer 31. This allows the group of capacitors 11A located on one side of the other second direction D2 to be connected to the reference potential via the metal spacer 31 and the bottom wall 25 of the housing case 20, with a simple structure, without the need to provide wiring for the reference potential.

[0048] Furthermore, on the other capacitor board 10B, the connection terminals (other potential connection points) 14A to 14D and the busbar 40, which is at a different potential, are connected via current collection wiring 32A to 32D. As a result, the capacitor group 11A located on one side of the other side of the second direction D2 is connected to a different potential. This allows the charge stored in the capacitor group connected in series on the pair of capacitor boards 10A and 10B to be collected from the connection terminals 14A to 14D to the busbar 40 via current collection wiring 32A to 32D.

[0049] As shown in Figures 6 and 7, in this embodiment, the space formed between each capacitor substrate 10A (10B) and the bottom wall 25 of the housing case 20 by the spacer 31 is filled with an insulating filler material M. In this embodiment, the entire surface of each capacitor substrate 10A (10B) is covered with the filler material M. In this embodiment, the filler material M is filled from the position indicated by the dashed line in Figures 8 and 9 up to the bottom surface of the bottom wall 25. In this embodiment, the spacer 31 formed on the capacitor substrate 10A (10B) creates a space to secure the filler material M between the capacitor substrate 10A (10B) and the bottom wall 25 of the housing case 20, thereby reducing the formation of gaps between them due to insufficient filling of the filler material M.

[0050] In this embodiment, the filler M is preferably made of a molding material (molding material) made of, for example, silicone resin. This ensures that the thermal conductivity of the filler M is 1 W / mK or higher, thereby ensuring the cooling efficiency of the capacitor substrate 10A (10B). Furthermore, since silicone resin has a dielectric breakdown strength of 20 kV / mm, it is possible to ensure insulation between the capacitor 11 of the capacitor substrate 10A (10B) and the bottom wall 25 of the housing case 20.

[0051] In particular, each wiring board 15 is provided with multiple through holes 15a, 15a, ... between adjacent wiring patterns 15f, 15f. This makes it easier to fill the back side of each capacitor board 10A (10B) with filler material M between the capacitor board 10A (10B) and the bottom wall 25 of the housing case 20, through the through holes 15a.

[0052] In this way, the metal bottom wall 25 functions as a heat sink, and the heat generated by each capacitor board 10A (10B) can be efficiently dissipated from the bottom wall 25 of the housing case 20 via the filler material M. In this embodiment, since the multiple capacitors 11, 11, ... on the back side of each capacitor board 10A (10B) are arranged facing the metal bottom wall 25, the heat generated by these capacitors 11, 11, ... can be dissipated from the bottom wall 25 via the filler material M. In this embodiment, a filler material M is used, but if the amount of heat generated by the capacitors 11 is small, a heat dissipation sheet may be placed in place of the filler material M so as to be in contact with the capacitors 11 on the back side of the capacitor board 10A (10B) and the bottom wall 25 of the housing case 20.

[0053] In the capacitor board unit 1 of this embodiment, for example, multiple capacitors 11, 11, ... can function as a single capacitor for bypassing the DC line of a high-voltage inverter. Furthermore, since multiple capacitors 11, 11, ... are mounted on multiple wiring boards 15, the heat generated by the multiple capacitors 11, 11, ... can be shared among the capacitor boards 10A (10B).

[0054] As described above, on one side of the capacitor board 10A in the other direction D2, multiple via holes (reference potential connection points) 17A to 17E for connecting to a reference potential are provided at intervals along the first direction. On the other side of the capacitor board 10B in the other direction D2, multiple connection terminals (other potential connection points) 14A to 14D for connecting to other potentials having a potential difference from the reference potential are provided at intervals along the first direction D1. Furthermore, by connecting the respective connection terminals (inter-board connection points) 13A to 13D of the capacitor boards 10A and 10B via electrical wiring 31A to 31D, the multiple capacitor groups 11A, 11A… of the two capacitor boards 10A and 10B are electrically connected in series. As a result, multiple current paths are formed on one capacitor board 10A between the via holes 17A to 17E and the multiple connection terminals 13A to 13D. Furthermore, on the other capacitor board 10A, multiple current paths are formed between multiple connection terminals 14A to 14D and multiple connection terminals 13A to 13D. On each capacitor board 10A and 10B, the multiple connection terminals 13A to 13D, which are formed at intervals along the first direction D1, ensure a uniform current path for the multiple capacitors 11, 11, ... on each capacitor board 10A and 10B, and the apparent current I flowing through the capacitor board 10A (10B) can be distributed almost uniformly, as shown in Figure 10. Of course, the current I cannot be distributed uniformly, and some variation will occur, but it is possible to suppress localized heating of the capacitor 11.

[0055] In particular, by making the lengths of the electrical wiring 31A to 31D connected to the respective terminals 13A to 13D of capacitor boards 10A and 10B the same, the resistance of the electrical wiring 31A to 31D becomes equal. This makes it possible to equalize the high-frequency current I flowing through the electrical wiring 31A to 31D to each terminal 13A to 13D. As a result, the uniformity of the current distribution I can be further improved. That is, the current I flows almost uniformly in the second direction D2. In other words, the variation in the first direction D1 can be reduced, and thus the variation in heat generation of each capacitor 11 can be reduced.

[0056] Although embodiments of the present invention have been described in detail above, the present invention is not limited to the embodiments described above, and various design modifications can be made without departing from the spirit of the invention as described in the claims. [Explanation of Symbols]

[0057] 1: Capacitor board unit, 10A, 10B: Capacitor board, 11: Capacitor, 11A: Capacitor group, 13A~13D: Connection terminals (inter-board connection), 14A~14D: Connection terminals (other potential connection), 15: Wiring board, 15a: Through hole, 15f: Wiring pattern, 17A~17E: Via hole (reference potential connection), 20: Housing case, 25: Bottom wall, 31: Spacer

Claims

1. A capacitor board unit comprising a pair of capacitor boards on which multiple capacitors are mounted on a wiring board, Each capacitor board has a plurality of capacitor groups in which a plurality of capacitors are arranged in a line along a first direction, and are electrically connected in parallel via opposing wiring patterns formed on the wiring board along the first direction. The multiple capacitor groups on each capacitor board are arranged in a second direction perpendicular to the first direction, and are electrically connected in series via the wiring patterns connected to adjacent capacitor groups. Each capacitor board has a plurality of inter-board connection portions provided on one side in the second direction, spaced apart along the first direction. Of the pair of capacitor boards, one of the capacitor boards has a plurality of reference potential connection points for connecting to a reference potential, which are provided at intervals along the first direction on the other side of the second direction. Of the pair of capacitor boards, on one side of the other capacitor board in the second direction, a plurality of other potential connection points for connecting to other potentials having a potential difference with respect to the reference potential are provided at intervals along the first direction. A capacitor board unit characterized in that the pair of capacitor boards are electrically connected in series by connecting the inter-board connection portions of each board with electrical wiring, thereby connecting a plurality of capacitor groups on the pair of capacitor boards in series.

2. The capacitor board unit according to claim 1, characterized in that the length of the electrical wiring is the same.

3. Each capacitor board has a plurality of capacitor groups on both sides of the wiring board. The capacitor board is housed in a housing case. The bottom wall of the aforementioned storage case is made of a metal material. A spacer is provided between the capacitor substrate and the bottom wall. The capacitor board unit according to claim 1, characterized in that the space formed between the capacitor board and the bottom wall of the housing case by the spacer is filled with an insulating filler material.

4. The capacitor board unit according to claim 3, characterized in that each of the wiring boards has a plurality of through holes formed between opposing wiring patterns.

5. The reference potential connection portion is formed on the wiring board, The group of capacitors arranged on one side of the other capacitor board is connected to the reference potential by electrically connecting each of the reference potential connection portions and the bottom wall which becomes the reference potential via the metal spacer. The capacitor board unit according to claim 3, characterized in that the group of capacitors arranged on one side of the other capacitor board is connected to the other potential by electrically connecting each of the other potential connection parts and the busbar which becomes the other potential via current collection wiring.

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