Information processing device, information processing system, and information processing method

Abstract

The present invention provides an information processing device, an information processing system, and an information processing method that can suppress the increase in processing time caused by data movement between the CPU and multiple high-speed circuits. [Solution] An information processing device comprising: a plurality of acceleration circuits that perform specific arithmetic processing; a CPU that holds a plurality of transfer data to be transferred to one or more of the acceleration circuits and a plurality of data transfer instructions that instruct the transfer of the transfer data to one or more of the acceleration circuits, wherein each of the acceleration circuits is provided with a plurality of data writing circuits that each write the transfer data to the acceleration circuit; a write destination determination circuit that outputs a write instruction signal to one or more of the data writing circuits instructing the writing of the transfer data to the acceleration circuit in accordance with the data transfer instructions output from the CPU; and a data transfer circuit that transfers the transfer data output from the CPU to each of the data writing circuits.

Description

Technical Field

[0001] The present invention relates to an information processing apparatus, an information processing system, and an information processing method.

Background Art

[0002] In the control of industrial equipment such as industrial robots and power supply systems, it is necessary to realize real-time control with an inexpensive edge device such as an embedded system. As a method for speeding up processing in edge devices, the use of a GPU (Graphics Processing Unit) can be considered. However, for complex processing in the control field, the GPU is not cost-effective, and speedup based on a CPU (Central Processing Unit) is required. As one of the CPU-based processing speedup methods, for example, hardware specialized for specific arithmetic processing is provided in the edge device separately from the CPU, and the specific processing is executed in parallel, thereby speeding up the processing of the entire edge device. Examples of hardware specialized for specific arithmetic processing include a plurality of circuits, processing units, LSI (Large Scale Integration), etc. (hereinafter referred to as speedup circuits).

[0003] One example of a technology related to speeding up CPU-based processing is Patent Document 1. This publication discloses a data transfer device comprising "a memory for storing data, storage means for storing data transfer instructions instructed by the CPU, a plurality of counters set with addresses of the storage means in which data transfer instructions corresponding to each of the plurality of programs are stored, a plurality of registers for storing addresses corresponding to each of the counter identifiers of the plurality of counters, and execution means that, based on a data transfer request from the DMA device, switches the plurality of counters and performs DMA data transfer between the memory and the DMA device in accordance with the data transfer instructions stored in the storage means using the addresses set in the plurality of counters, and outputs the counter identifier of the counter storing the address of the data transfer instruction to be executed to the DMA device." [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2014-48954 [Overview of the project] [Problems that the invention aims to solve]

[0005] In the above technology, for example, state information such as the motor angle and operating status of the controlled equipment, as well as surrounding information from cameras and sensors, is acquired. Command values ​​are calculated from this information, and these command values ​​are converted into a drive format for the controlled equipment, such as pulses, for control. This information acquisition, command value calculation, and control according to the command values ​​are each performed by separate devices, and control of industrial equipment is realized by sending and receiving data between these devices. The number of information acquisition devices and controlled equipment is increasing. In addition, the amount of data sent and received between devices is increasing due to improvements in the resolution of the acquired information and the increasing complexity of the control content. Therefore, edge devices are required to process large amounts of data. Furthermore, when deriving the optimal solution for the entire factory or facility equipped with multiple industrial devices, not just individual industrial devices, edge devices require calculations using even larger amounts of data.

[0006] In edge devices like those described above, this large amount of data is stored in memory, transferred to general-purpose arithmetic units and multiple acceleration circuits, processed by the arithmetic units and each acceleration circuit, and then the processing results are stored back in memory. Since calculations for controlling industrial equipment require real-time processing, efforts are being made to accelerate processing using not only arithmetic units but also multiple acceleration circuits. However, the movement of this large amount of data between memory and each acceleration circuit is becoming a problem as a factor that increases processing time in edge devices.

[0007] In conventional examples such as those disclosed in Patent Document 1, the data transfer unit can be realized with one DMA port, one DMA device, and one interface with a CPU, enabling simultaneous parallel data transfer according to multiple programs while suppressing an increase in circuit size and wiring. However, since data transfer to each high-speed circuit is processed sequentially, there is a problem in that it is not possible to suppress the increase in processing time when transferring large amounts of data to many high-speed circuits.

[0008] In view of the above problems, the present invention aims to provide an information processing device, an information processing system, and an information processing method that can shorten the data transfer time between a CPU and multiple high-speed circuits and suppress the increase in processing time caused by the movement of large amounts of data. [Means for solving the problem]

[0009] The present invention includes several means for solving at least part of the above problems, one example being as follows: an information processing device comprising a plurality of speed-up circuits that perform a specific arithmetic processing, a CPU that holds a plurality of transfer data to be transferred to one or more of the speed-up circuits and a plurality of data transfer instructions that instruct the transfer of the transfer data to one or more of the speed-up circuits, wherein each of the speed-up circuits is provided with a plurality of data writing circuits that each write the transfer data to the speed-up circuit, a write destination determination circuit that outputs a write instruction signal to one or more of the data writing circuits instructing the writing of the transfer data to the speed-up circuit in accordance with the data transfer instructions output from the CPU, and a data transfer circuit that transfers the transfer data output from the CPU to each of the data writing circuits. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide an information processing device, an information processing system, and an information processing method that can shorten the data transfer time between the CPU and multiple high-speed circuits, and suppress the increase in processing time caused by the movement of large amounts of data.

[0011] Other issues, configurations, and effects not mentioned above will be clarified by the following description of the embodiments. [Brief explanation of the drawing]

[0012] [Figure 1] This is an example of a functional block diagram of the control device according to Example 1. [Figure 2] This is an example of a functional block diagram of the information processing device according to Example 1. [Figure 3]This is an example of a functional block diagram of the speedup circuit according to Embodiment 1. [Figure 4] This is a diagram illustrating an example of the configuration of the high-speed operation data holding unit according to Embodiment 1. [Figure 5] This is an example of a functional block diagram of the memory according to Embodiment 1. [Figure 6] This is a diagram illustrating an example of the configuration of the instruction holding unit according to Embodiment 1. [Figure 7] This is a diagram illustrating an example of the configuration of the general-purpose data holding unit according to Embodiment 1. [Figure 8] This is a diagram illustrating an example of the configuration of the operation code of the data transfer instruction according to Embodiment 1. [Figure 9] This is an example of a functional block diagram of the write destination determination circuit according to Embodiment 1. [Figure 10] This is a diagram illustrating an example of the configuration of the write enable signal according to Embodiment 1. [Figure 11] This is a flowchart illustrating an example of signal output processing by the write signal output unit according to Embodiment 1. [Figure 12] This is a flowchart illustrating an example of transfer processing by the data transfer circuit according to Embodiment 1. [Figure 13] This is a flowchart illustrating an example of write processing by the data write circuit according to Embodiment 1. [Figure 14] This is a diagram illustrating an example of the configuration of the instruction holding unit according to Embodiment 2. [Figure 15] This is a diagram illustrating an example of the configuration of the general-purpose data holding unit according to Embodiment 2. [Figure 16] This is a diagram illustrating an example of the configuration of the operation code of the data transfer instruction according to Embodiment 2. [Figure 17] This is a diagram illustrating an example of the configuration of the operation code of the group management instruction according to Embodiment 2. [Figure 18] This is an example of a functional block diagram of the write destination determination circuit according to Embodiment 2. [Figure 19] This is a diagram illustrating an example of the configuration of the group configuration information according to Embodiment 2. [Figure 20]This is a diagram illustrating an example of the configuration of a write enable signal according to Embodiment 2. [Description of Embodiments]

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments are examples for describing the present invention, and are appropriately omitted and simplified for clarity of explanation. The present invention can also be implemented in various other forms. Unless otherwise specifically limited, each constituent element may be singular or plural.

[0014] The positions, sizes, shapes, ranges, and the like of the respective constituent elements shown in the drawings may not represent the actual positions, sizes, shapes, ranges, and the like in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, ranges, and the like disclosed in the drawings. When there are a plurality of constituent elements having the same or similar functions, different subscripts may be appended to the same reference numeral for description. In addition, when it is not necessary to distinguish between these plurality of constituent elements, the subscripts may be omitted for description.

[0015] In the embodiments, processing performed by executing a program may be described. Here, a computer executes the program by a processor (e.g., CPU, GPU), and performs processing defined by the program while using storage resources (e.g., memory), interface devices (e.g., communication ports), and the like. Therefore, the subject of the processing performed by executing the program may be the processor. Similarly, the subject of the processing performed by executing the program may be a controller, apparatus, system, computer, or node having the processor.

[0016] The main component of the processing performed by executing the program can be an arithmetic unit, and may include dedicated circuits for specific processing. Here, dedicated circuits include, for example, FPGAs (Field Programmable Gate Arrays), ASICs (Application Specific Integrated Circuits), and CPLDs (Complex Programmable Logic Devices).

[0017] The program may be installed on the computer from the program source. The program source may be, for example, a program distribution server or a storage medium readable by the computer. If the program source is a program distribution server, the program distribution server includes a processor and storage resources to store the program to be distributed, and the processor of the program distribution server may distribute the program to other computers. In addition, in the embodiment, two or more programs may be implemented as one program, or one program may be implemented as two or more programs. [Examples]

[0018] Figure 1 shows an example of a functional block diagram of a control device according to Embodiment 1. In Figure 1, the control device 100 mainly comprises an information processing device 110 that generates control command values ​​and analyzes information based on acquired data, and a communication device 120 that receives data and transmits control command values. The control device 100 controls one or more control objects 130-1 to 130-n (n is an integer, and hereinafter, control objects 130-1 to 130-n or one or more control objects collectively referred to as control object 130), such as industrial equipment. The communication device 120 receives various data such as status information from the control object 130 and transmits control command values ​​to the control object 130. The communication device 120 can also send and receive various data with one or more peripheral devices 140, such as devices that collect peripheral information such as sensors and cameras, and devices that generate operation plans for the control object.

[0019] Figure 2 shows an example of a functional block diagram of an information processing device according to Embodiment 1. In Figure 2, the information processing device 110 includes a CPU 201, a plurality of high-speed circuits 202-1 to 202-n, a plurality of data writing circuits 203-1 to 203-n, a write destination determination circuit 204, and a data transfer circuit 205.

[0020] CPU 201 holds data and instructions and performs arithmetic processing. Multiple acceleration circuits 202-1 to 202-n (hereinafter referred to as acceleration circuits 202-1 to 202-n, or one or more acceleration circuits collectively as acceleration circuit 202) execute arithmetic processing related to the controlled objects 130-1 to 130-n in parallel. Multiple data writing circuits 203-1 to 203-n (hereinafter referred to as data writing circuits 203-1 to 203-n, or one or more data writing circuits collectively as data writing circuit 203) write data to acceleration circuits 202-1 to 202-n, respectively. The write destination determination circuit 204 controls the writing process of data writing circuits 203-1 to 203-n. The data transfer circuit 205 transfers various data held by CPU 201 to data writing circuits 203-1 to 203-n. The data transfer circuit 205 may also simultaneously transfer data to the data writing circuits 203-1 to 203-n.

[0021] The CPU 201 includes an arithmetic unit 206 that performs multiple types of operations according to the operation instruction, such as arithmetic operations like addition, subtraction, multiplication, and division, logical operations like AND and OR, and bit shifts, and a memory 207 that holds data such as common data and target data, as well as data transfer instructions and operation instructions, as will be described later.

[0022] The high-speed circuits 202-1 to 202-n can process large amounts of data faster than the CPU 201 by executing multiple arithmetic operations in parallel. Figure 2 shows an example in which the information processing device 110 is equipped with the same number of high-speed circuits 202-1 to 202-n as the number of controlled objects 130-1 to 130-n. In this case, a high-speed circuit 202-1 to 202-n is provided for each controlled object 130-1 to 130-n, and each high-speed circuit 202-1 to 202-n is configured to execute the corresponding arithmetic operations for each controlled object 130-1 to 130-n. However, the number of high-speed circuits 202 is not limited to this, and may be any number required for parallel processing in the information processing device 110. For example, one or more high-speed circuits 202 may be provided for each controlled object 130, or conversely, one high-speed circuit 202 may be provided for multiple controlled objects 130. Alternatively, if the information processing device 110 performs image processing, the high-speed circuit 202 may be provided in units of regions or processing ranges of the image to be processed, which is divided into multiple regions.

[0023] The data writing circuits 203-1 to 203-n are provided specifically for each of the high-speed circuits 202-1 to 202-n. As will be described later, the data writing circuits 203-1 to 203-n take common data, target data, and write instruction signals transferred from the data transfer circuit 205 as input, and according to the value of the write instruction signal, they execute the writing of the input common data and target data to the corresponding high-speed circuits 202-1 to 202-n.

[0024] The write destination determination circuit 204 determines which of the acceleration circuits 202-1 to 202-n to write the data to based on the data transfer instruction sent from the CPU 201, and outputs a 1-bit write instruction signal to each of the data writing circuits 203-1 to 203-n, as well as a transfer activation signal to the data transfer circuit 205. The data transfer circuit 205 simultaneously transfers the common data and target data sent from the CPU 201 to each of the data writing circuits 203-1 to 203-n according to the value of the transfer activation signal output from the write destination determination circuit 204.

[0025] Figure 3 shows an example of a functional block diagram of the high-speed circuit according to Embodiment 1. Figure 3 shows the configuration of high-speed circuit 202-1 as a representative example, but the configurations of the other high-speed circuits 202-2 to 202-n are similar. The high-speed circuit 202 includes a high-speed calculation data holding unit 301 (shown as high-speed calculation data holding unit 301-1 in Figure 3 as part of the configuration of high-speed circuit 202-1) that holds common data, target data, and calculation result data written by a dedicated data writing circuit 203, and a high-speed arithmetic unit 302 (shown as high-speed arithmetic unit 302-1 in Figure 3 as part of the configuration of high-speed circuit 202-1) that executes calculation processing using the common data and target data held by the high-speed calculation data holding unit 301 as input.

[0026] The high-speed arithmetic unit 302 performs arithmetic operations such as addition, subtraction, multiplication, and division, logical operations such as AND and OR, and multiple other types of arithmetic operations such as bit shifts. The high-speed arithmetic unit 302 may perform arithmetic operations according to arithmetic instructions sent from the CPU 201. For example, a dedicated instruction holding unit may be provided in the high-speed circuit 202-1, and the high-speed arithmetic unit 302 may perform arithmetic operations according to arithmetic instructions read from there, or it may determine its processing operation according to information and instructions input from outside the information processing device 110, or it may always perform predetermined calculations.

[0027] Figure 4 shows an example of the configuration of the high-speed calculation data storage unit according to Embodiment 1. Figure 4 shows the configuration of the high-speed calculation data storage unit 301-1 provided in the high-speed circuit 202-1 as a representative example, but the configurations of the other high-speed calculation data storage units 301-2 to 301-n are similar. The high-speed calculation data storage unit 301 stores multiple common data used for calculation processing in common by all high-speed circuits 202, multiple target data used for calculation processing only by the high-speed circuit 202 to which it belongs, and multiple calculation result data from the high-speed arithmetic unit 302.

[0028] Common data includes, for example, peripheral information collected by cameras and sensors input from peripheral devices 140, information such as the overall plan transmitted from data centers and servers, or status information of the control device 100. Target data is information specific to each controlled object 130, such as the status and operation plan of each controlled object 130.

[0029] Furthermore, the high-speed calculation data storage unit 301 stores only the target data related to the control target 130 that the high-speed circuit 202 to which it belongs corresponds. For example, in the example shown in Figure 4, the high-speed calculation data storage unit 301-1 belonging to the high-speed circuit 202-1 stores only the target data related to the control target 130-1 that the high-speed circuit 202-1 corresponds to (shown as target 1 data in Figure 4, and hereafter the target data related to each control target 130-1 to 130-n will be referred to as target 1 data to target n data).

[0030] Figure 5 shows an example of a functional block diagram of the memory according to Embodiment 1. The memory 207 includes an instruction holding unit 501 that holds various instructions such as arithmetic instructions and data transfer instructions, and a general-purpose data holding unit 502 that holds CPU arithmetic data used by the arithmetic unit 206 for calculations, as well as common data and target data that are transferred to the acceleration circuits 202-1 to 202-n. The instruction holding unit 501 transmits arithmetic instructions to the arithmetic unit 206 and data transfer instructions to the write destination determination circuit 204 and the data transfer circuit 205. The general-purpose data holding unit 502 transmits CPU arithmetic data to the arithmetic unit 206, receives and holds calculation result data from the arithmetic unit 206, and also transmits common data and target data to the data transfer circuit 205 (hereinafter, the common data and target data transmitted from the general-purpose data holding unit 502 to the data transfer circuit 205, and then transferred from the data transfer circuit 205 to each data writing circuit 203-1 to 203-n are collectively referred to as transferred data).

[0031] Figure 6 shows an example of the configuration of the instruction holding unit according to Embodiment 1. Each instruction holding unit 501 holds multiple data transfer instructions and arithmetic instructions. Although only data transfer instructions and arithmetic instructions are shown in Figure 6, the instruction holding unit 501 may also hold various other instructions. Data transfer instructions include instructions for transferring common data and instructions for transferring target data. A common data transfer instruction is an instruction that sends a command to transfer the same common data to all high-speed circuits 202-1 to 202-n. A target data transfer instruction is an instruction that specifies one of the high-speed circuits 202-1 to 202-n and sends a command to transfer target data to the specified high-speed circuit 202. Arithmetic instructions are instructions that instruct the arithmetic unit 206 to perform various arithmetic processes. Furthermore, as described above, the instruction holding unit 501 may also hold arithmetic instructions for the high-speed arithmetic unit 302 in each high-speed circuit 202 and transmit them to each high-speed arithmetic unit 302.

[0032] Figure 7 shows an example of the configuration of the general-purpose data storage unit according to Embodiment 1. The general-purpose data storage unit 502 stores multiple common data, multiple target data related to each control target 130 (multiple target 1 data to target n data, respectively), and multiple CPU calculation data. The common data and target data are the same as the common data and target data held by the high-speed calculation data storage unit 301, as described in the explanation of Figure 4.

[0033] Common data is transferred to all high-speed circuits 202 and written to their respective high-speed calculation data storage units 301. Target data is transferred individually to the high-speed circuit 202 corresponding to the control target 130, depending on whether it pertains to one of the control targets 130-1 to 130-n, and written to its high-speed calculation data storage unit 301. CPU calculation data refers to the data input to the arithmetic unit 206 and used for calculations, as well as the calculation result data output by the arithmetic unit 206.

[0034] Figure 8 shows an example of the configuration of the instruction code for a data transfer instruction held by the instruction holding unit according to Embodiment 1. As shown in Figure 8, the instruction code for a data transfer instruction consists of the instruction type, destination circuit number, read start address, write start address, and number of data to be transferred.

[0035] The instruction type indicates the type of data transfer instruction. In the example shown in Figure 8, there are two types depending on the type of data being transferred: common data transfer and targeted data transfer. Common data transfer and targeted data transfer are as described in the explanation of Figure 6.

[0036] The destination circuit number specifies which of the acceleration circuits 202-1 to 202-n should receive the data when the instruction type indicates data transfer. In this embodiment, each acceleration circuit 202-1 to 202-n is pre-assigned a different circuit number from 1 to n, and one of these circuit numbers is specified as the destination circuit number.

[0037] The read start address indicates the address of the general-purpose data storage unit 502 in memory 207, and specifies the starting address of the storage location for the data to be transferred. The write start address indicates the address of the high-speed calculation data storage unit 301 in the high-speed circuit 202, and specifies the starting address of the storage location for the data to be transferred. Note that the write start address is a relative address indicating the position from the beginning of the high-speed calculation data storage unit 301, and can be used in common for each high-speed calculation data storage unit 301 of each high-speed circuit 202.

[0038] Regarding the number of data transfers, the size of data that can be transferred in one cycle (hereinafter referred to as the transferable data size) is predetermined for each operation (this operation is called a cycle) in which the data transfer circuit 205 reads the data from the memory 207 and transfers it to each data writing circuit 203-1 to 203-n. If the data size of the data to be transferred is larger than the transferable data size, the data transfer circuit 205 repeats the cycle multiple times in a row, that is, it performs the data transfer over multiple cycles. Therefore, in the example shown in Figure 8, one cycle of data transfer by the data transfer circuit 205 is represented as 1 data, and the number of data transfer cycles corresponding to the data size of the data to be transferred is specified as the number of data to be transferred.

[0039] For example, if the data size of the data to be transferred is less than or equal to the transferable data size, it can be transferred in one cycle, so the number of data transferred is "1". Similarly, if the data size of the data to be transferred is less than or equal to twice the transferable data size, two cycles are required for data transfer, so the number of data transferred is "2". If it is less than or equal to x times the transferable data size, the number of data transferred is "x".

[0040] In addition to the above, the number of data items to be transferred may also be specified by the data size of the data to be transferred in bytes or other units.

[0041] Figure 9 shows an example of a functional block diagram of the write destination determination circuit according to Embodiment 1. The write destination determination circuit 204 comprises a counter 901, a write signal generation unit 902, and a write signal output unit 903.

[0042] The counter 901 counts based on the number of data transfer cycles and outputs the counter value to the write signal output unit 903. First, the counter 901 calculates the number of data transfer cycles based on the information of the number of data to be transferred from the data transfer command transmitted from the command holding unit 501. For example, as shown in the example in Figure 8, if the number of data to be transferred is specified in a format that indicates the number of data transfer cycles based on the transferable data size, the counter 901 uses that value of the number of data to be transferred as the number of cycles. Also, if the number of data to be transferred is specified in a format that indicates the data size of the data to be transferred, such as the number of bytes, the counter 901 uses that number of data to be transferred, i.e., the data size, to calculate the number of cycles based on the transferable data size.

[0043] The counter 901 then sets an initial value for the count and starts counting. The counter 901 is, for example, an addition / subtraction counter, and can count down using the number of cycles calculated as described above as the initial value for the count, or conversely, it can count up using the initial value of "1". The counter 901 counts, i.e., counts up or counts down each time it outputs a counter value to the write signal output unit 903.

[0044] The write signal generation unit 902 takes a data transfer command as input, generates a write enable signal to enable or disable data writing by each data writing circuit 203, and outputs it to the write signal output unit 903.

[0045] The write signal output unit 903 takes the counter value from the counter 901 and the write activation signal from the write signal generation unit 902 as inputs, and sends write instruction signals to each data writing circuit 203-1 to 203-n, and also sends a transfer activation signal to the data transfer circuit 205.

[0046] Figure 10 shows an example of the configuration of a write-enable signal generated by the write signal generation unit according to Embodiment 1. Figure 10 also shows the data transfer command input to the write signal generation unit 902.

[0047] The write signal generation unit 902 takes the instruction type and destination circuit number of the data transfer instruction as input and generates a write enable signal. The write enable signal includes a 1-bit circuit write enable signal for each set of high-speed circuits 202 and each dedicated data write circuit 203 (for example, a set of high-speed circuit 202-1 and data write circuit 203-1), for a total of n sets. In Figure 10, for example, the circuit write enable signal for the set of high-speed circuit 202-1 and data write circuit 203-1 is represented as the circuit 1 write enable signal, and the write enable signal includes circuit 1 write enable signals to circuit n write enable signals.

[0048] The write signal generation unit 902 generates a write enable signal by setting all circuit write enable signals to "1" when the instruction type indicates common data transfer, regardless of the value of the destination circuit number. For example, in the first example of the write enable signal in Figure 10, since the instruction type indicates common data transfer, all of the circuit 1 write enable signals to circuit n write enable signals are set to "1".

[0049] If the instruction type indicates a target data transfer, the write signal generation unit 902 generates a write enable signal by setting the circuit write enable signal to "1" for the set corresponding to one of the high-speed circuits 202-1 to 202-n specified by the destination circuit number, and setting the other circuit write enable signals to "0".

[0050] For example, in the second example of the write enable signal in Figure 10, the instruction type indicates target data transfer and the destination circuit number is "1". Therefore, the circuit 1 write enable signal for the set of high-speed circuit 202-1 and data write circuit 203-1, whose circuit number is "1", is set to "1", while all other circuit 2 write enable signals ~ circuit n write enable signals are set to "0".

[0051] Figure 11 is a flowchart showing an example of signal output processing by the write signal output unit according to Embodiment 1. It should be noted that, as a prerequisite, the counter 901 sets the calculated number of cycles as the initial value for the count and then outputs the counter value and performs countdown.

[0052] In S1101, the write signal output unit 903 acquires the counter value output by the counter 901 and the write activation signal output by the write signal generation unit 902. In S1102, the write signal output unit 903 determines whether the counter value is "1" or greater. If the counter value is "1" or greater, in S1103, the write signal output unit 903 outputs the acquired write activation signal as a write instruction signal to each data writing circuit 203. Since the write instruction signal has the same configuration as the write activation signal shown in Figure 10, the write signal output unit 903 can use (output) the write activation signal as is as a write instruction signal.

[0053] In the subsequent S1104, the write signal output unit 903 sets the transfer enable signal to "1" and outputs it to the data transfer circuit 205. After that, the write signal output unit 903 returns to the process of S1101 and repeats the processes of S1101 to S1104 as long as the counter value is "1" or greater.

[0054] If, in S1102, the counter value is determined to be less than "1", then in S1105, the write signal output unit 903 sets all circuit write activation signals in the write instruction signal to "0" and outputs them to each data write circuit 203. Then, in S1106, the write signal output unit 903 sets the transfer activation signal to "0" and outputs it to the data transfer circuit 205, ending the signal output process.

[0055] Figure 12 is a flowchart showing an example of a data transfer process by the data transfer circuit according to Embodiment 1. It should be noted that, as a prerequisite, the data transfer circuit 205 includes at least a register for temporarily holding the data to be transferred, a register for counting the number of transferred data (or the amount of data), a register for setting the high-speed circuit write address, and a register for setting the memory read address.

[0056] In S1201, the data transfer circuit 205 determines whether the transfer activation signal transmitted from the write signal output unit 903 in the write destination determination circuit 204 is "1". If the transfer activation signal is "0", the data transfer circuit 205 terminates the transfer process. If the transfer activation signal is "1", in S1202, the data transfer circuit 205 initializes the number of transferred data, that is, sets the value of the register for counting the number of transferred data to "0". In S1203, the data transfer circuit 205 sets the speed-up circuit write address and the memory read address in the registers, respectively, based on the data transfer instruction transmitted from the instruction holding unit 501 in the memory 207. The speed-up circuit write address uses the write start address in the data transfer instruction. The memory read address uses the read start address in the data transfer instruction.

[0057] In S1204, the data transfer circuit 205 generates a memory read signal and sends it to memory 207 along with the memory read address. Memory 207 outputs the transfer data stored at the memory read address in response to the memory read signal. As a result, the data transfer circuit 205 retrieves the transfer data from memory 207 and stores it in a register. In S1205, the data transfer circuit 205 transfers the transfer data and the high-speed circuit write address to all data write circuits 203. At this time, since the data transfer circuit 205 is transferring the same data, it is not necessary to send the transfer data to each data write circuit 203 sequentially, but it may send it to all data write circuits 203 simultaneously. Note that S1205 is one cycle of data transfer, and in S1205, the data transfer circuit 205 transfers data up to the transferable data size of the transfer data.

[0058] When the transfer of data equal to the transferable data size is complete, in S1206, the data transfer circuit 205 increments the high-speed circuit write address set in the register by the transferable data size. Also, if the number of data to be transferred in the data transfer instruction sent from the instruction holding unit 501 is specified in a format that indicates the number of data transfer cycles, the data transfer circuit 205 increments the number of transferred data (+1). On the other hand, if the number of data to be transferred is specified in a format that indicates the data size of the data to be transferred, such as the number of bytes, the data transfer circuit 205 increments the number of transferred data by the transferable data size.

[0059] In the following step S1207, the data transfer circuit 205 compares the number of data to be transferred with the number of data already transferred to determine whether the number of data already transferred is greater than the number of data to be transferred. If the number of data already transferred is less than the number of data to be transferred, the data transfer circuit 205 returns to the process in S1205 and repeats the process in S1205 to S1207 as long as the number of data already transferred is less than the number of data to be transferred.

[0060] In S1207, if it is determined that the number of transferred data is greater than the number of data to be transferred, that is, if the transfer of data has been completed, the data transfer circuit 205 terminates the transfer process.

[0061] Figure 13 is a flowchart showing an example of the writing process by the data writing circuit according to Embodiment 1. All data writing circuits 203-1 to 203-n perform the writing process according to this flowchart.

[0062] In S1301, the data writing circuit 203 acquires the transfer data and the high-speed circuit write address transmitted from the data transfer circuit 205. Note that in S1301, the data writing circuit 203 acquires only the data portion of the original transfer data that corresponds to the transferable data size. In S1302, the data writing circuit 203 determines whether the circuit write activation signal for itself (the set of its own data writing circuit and the corresponding high-speed circuit) in the write instruction signal transmitted from the write signal output unit 903 in the write destination determination circuit 204 is "1". If the circuit write activation signal is "1", in S1303, the data writing circuit 203 uses the acquired high-speed circuit write address to write the acquired data portion of the transferable data size to the high-speed calculation data holding unit 301 in the corresponding high-speed circuit 202.

[0063] Subsequently, the data writing circuit 203 returns to the process of S1301 and repeats the processes of S1301 to S1303 as long as the circuit write enable signal for itself is "1". In S1302, when the circuit write enable signal becomes "0", that is, when the writing of the entire transfer data is completed, the data writing circuit 203 terminates the writing process.

[0064] As described above, the information processing device in Embodiment 1 includes a data transfer circuit and a write destination determination circuit. The data transfer circuit transfers the data to all data writing circuits, for example, simultaneously, and controls the writing of data to each acceleration circuit by each data writing circuit using a write instruction signal transmitted from the write destination determination circuit. This eliminates the need to sequentially transfer data between the CPU and multiple acceleration circuits, significantly reducing data transfer time and suppressing the increase in processing time caused by the movement of large amounts of data between the CPU and multiple acceleration circuits. Furthermore, it does not require multiple data transfer circuits for transferring data, thus suppressing an increase in the physical size of the information processing device. [Examples]

[0065] In Example 1, an example was described in which the write destination determination circuit and data transfer circuit in the information processing device transfer the same common data to all acceleration circuits in accordance with a common data transfer instruction. However, it is also possible to configure the information processing device to transfer the same common data to a group of at least two or more acceleration circuits, for example. Example 2 describes an example of an information processing device with such a configuration. The information processing device according to Example 2 has a similar configuration to the information processing device 110 according to Example 1 shown in Figure 2, but the configuration or content of the instructions and data held by the instruction holding unit and the general-purpose data holding unit are partially different, and the configuration or function of the write destination determination circuit is also partially different. Therefore, in Figures 14 to 20 described below, the same reference numerals are used for components that are the same as those in the information processing device 110 and its respective components shown in Figures 2 to 13, and in the following description, explanations of content that overlaps with Example 1 will be omitted, and only the differences will be explained.

[0066] Figure 14 shows an example of the configuration of the instruction holding unit according to Embodiment 2. In Embodiment 2, the instruction holding unit 501 holds multiple data transfer instructions, arithmetic instructions, and group management instructions. Although only data transfer instructions, arithmetic instructions, and group management instructions are shown in Figure 14, the instruction holding unit 501 may also hold various other instructions.

[0067] The data transfer instructions held by the instruction holding unit 501 include instructions for transferring general common data, instructions for transferring target data, and instructions for transferring group common data. The target data transfer instruction is the same instruction as the target data transfer instruction described in Example 1. The general common data transfer instruction is the same instruction as the common data transfer instruction described in Example 1, and is an instruction that instructs all high-speed circuits 202-1 to 202-n to transfer the same common data. On the other hand, the group common data transfer instruction specifies one group consisting of at least two (but not all) high-speed circuits 202, and is an instruction that transfers the same group common data to all high-speed circuits 202 included in the specified group.

[0068] The arithmetic instructions are the same as those described in Example 1, and the group management instructions are instructions that specify the group configuration of the high-speed circuits 202-1 to 202-n. The group management instructions will be described later with reference to Figure 17.

[0069] Figure 15 shows an example of the configuration of the general-purpose data storage unit according to Embodiment 2. In Embodiment 2, the general-purpose data storage unit 502 stores multiple general common data, target data, CPU calculation data, and group common data. The target data and CPU calculation data are the same as the target data and CPU calculation data described in Embodiment 1. The general common data is also the same as the common data described in Embodiment 1. On the other hand, group common data is data that is commonly used for calculation processing by two or more high-speed circuits included in the same group, and is, for example, common information about two or more control targets 130 that have the same attributes, such as type and location.

[0070] Figure 16 shows an example of the instruction code structure for a data transfer command according to Embodiment 2. The instruction code structure is substantially the same as that of the instruction code structure for Embodiment 1 shown in Figure 8. However, the destination circuit number shown in Figure 8 is the destination circuit / group number in Figure 16, and when the instruction type indicates group common data transfer, the destination group number is used instead of the destination circuit number, specifying which of the one or more groups set in the high-speed circuits 202-1 to 202-n should receive the group common data.

[0071] Figure 17 shows an example of the structure of the instruction code for a group management instruction according to Embodiment 2. The instruction code for a group management instruction consists of the instruction type, setting method, number of divisions, starting circuit number, ending circuit number, and group number.

[0072] The instruction type indicates the type of group management instruction. In the example shown in Figure 17, there are three types: group setting, group exclusion, and group addition. Group setting is an instruction that sets up a new group by specifying any two or more speed-up circuits 202. Group exclusion and group addition will be described later.

[0073] The setting method refers to how to specify two or more high-speed circuits 202 that make up a group, and there are two types of setting methods: specifying the number of divisions and specifying a range. The number of divisions refers to the specific number of divisions when the setting method is specifying the number of divisions, and is expressed as an integer of 2 or more.

[0074] The number of divisions and the number of divisions themselves will be explained in detail. When the setting method indicates specifying the number of divisions, each set of high-speed circuits 202 and each set of data writing circuits 203 (for example, the set of high-speed circuit 202-1 and data writing circuit 203-1, the set of high-speed circuit 202-2 and data writing circuit 203-2, etc., and hereafter the set of high-speed circuit 202-1 and data writing circuit 203-1 will be described as Circuit 1, the set of high-speed circuit 202-2 and data writing circuit 203-2 as Circuit 2, etc.) is grouped from the beginning according to the number of divisions. For example, if the number of divisions is 10, circuits 1 to 10 will be set as Group 1, circuits 11 to 20 as Group 2, circuits 21 to 30 as Group 3, and so on. If there is a fraction of a circuit that is less than the number of divisions, the remaining circuits with fewer than the number of divisions will be grouped together and set as one group. When the setting method indicates specifying the number of divisions, the start circuit number, end circuit number, and group number information included in the instruction code are not used in group setting.

[0075] Returning to the explanation of Figure 17, the start circuit number and end circuit number in the instruction code specify one of the circuit numbers assigned to each acceleration circuit 202. When the setting method indicates range specification, the start circuit number and end circuit number specify a range of two or more acceleration circuits 202 that form a group, that is, a range of two or more circuits from circuits 1 to n, which are sets of each acceleration circuit 202 and each data writing circuit 203.

[0076] In instruction codes, the group number indicates the number assigned to a group when the instruction type indicates group setting. Specifically, when the setting method indicates range specification, a group is set for two or more high-speed circuits 202 that fall within the range indicated by the start circuit number and end circuit number, and the number specified by the group number is assigned to that group.

[0077] For example, in the third example of the group management instruction in Figure 17, the instruction type is group setting, the setting method is range specification, and the start circuit number is specified as 1, the end circuit number as 10, and the group number as 1. Therefore, a group is set for circuits 1 to 10, which are a set of high-speed circuits 202-1 to 202-10 and data writing circuits 203-1 to 203-10, to which circuit numbers 1 to 10 are assigned, and group number 1 is assigned (circuits 1 to 10 will be treated as group 1). Similarly, in the fourth example of the group management instruction in Figure 17, the instruction type is group setting, the setting method is range specification, and the start circuit number is specified as 11, the end circuit number as 20, and the group number as 2. Therefore, a group is assigned to circuits 11-20, which are a set of high-speed circuits 202-11-202-20 and data writing circuits 203-11-203-20, and the group number 2 is assigned to them (circuits 11-20 will be treated as group 2).

[0078] Furthermore, each circuit 1 to n may belong to (or be included in) multiple groups. For example, in the fifth group management instruction example in Figure 17, the instruction type is group setting, the setting method is range specification, and the start circuit number is specified as 1, the end circuit number as 15, and the group number as 10. Therefore, a group is set for circuits 1 to 15, which are a set of high-speed circuits 202-1 to 202-15 and data writing circuits 203-1 to 203-15, to which circuit numbers 1 to 15 are assigned, and group number 10 is assigned (circuits 1 to 15 are treated as group 10). However, as mentioned above, since circuits 1 to 10 already belong to group 1 due to the third group management instruction in Figure 17, circuits 1 to 10 will belong to (be included in) both group 1 and group 10.

[0079] Furthermore, the third to fifth figures in Figure 17 show examples of group management commands that specify (group) high-speed circuits 202 with consecutive circuit numbers based on the start and end circuit numbers. However, it is also possible to set up groups by specifying high-speed circuits 202 with discontinuous circuit numbers. To specify high-speed circuits 202 with such discontinuous circuit numbers, commands are used, such as the seventh command in Figure 17, which specifies high-speed circuits 202 belonging to a group by excluding high-speed circuits 202 other than the specified circuit number from the existing group, and commands, such as the eighth and ninth commands in Figure 17, which specify the circuit numbers of high-speed circuits 202 to be added to an existing group while retaining the existing group settings.

[0080] Specifically, for example, in the seventh group management instruction example in Figure 17, the instruction type is group exclusion, the setting method is range specification, the start circuit number is specified as 1, the end circuit number as 2, and the group number as 1. Assuming that circuits 1 to 10 are set to group 1 in the third group management instruction in Figure 17, this group exclusion instruction excludes circuits 3 to 10 from group 1, excluding circuits 1 and 2, which are the set of high-speed circuits 202-1 and 202-2 and data writing circuits 203-1 and 203-2 to which the range-specified circuit numbers 1 and 2 are assigned, so that group 1 consists only of circuits 1 and 2.

[0081] Next, in the example of the eighth group management instruction in Figure 17, the instruction type is group addition, the setting method is range specification, the start circuit number is 5, the end circuit number is 5, and the group number is 1. As described above, assuming that group 1 consists only of circuits 1 and 2 due to the seventh group exclusion instruction, this group addition instruction adds circuit 5, which is a set of high-speed circuit 202-5 and data writing circuit 203-5 assigned the range-specified circuit number 5, to group 1, and group 1 will consist of circuits 1, 2, and 5. Similarly, for the ninth group management instruction, circuit 10, which is a set of high-speed circuit 202-10 and data writing circuit 203-10 assigned the range-specified circuit number 10, is added to group 1, and group 1 will consist of circuits 1, 2, 5, and 10.

[0082] In this way, by using group setting instructions, group exclusion instructions, and group addition instructions, it is possible to set up groups by specifying high-speed circuits 202 with discontinuous circuit numbers. Note that the above-mentioned group exclusion and group addition instructions are just examples; for example, a group exclusion instruction may be an instruction to exclude the high-speed circuit 202 of a specified circuit number from the group. Alternatively, a group exclusion instruction or group addition instruction may be an instruction to exclude or add high-speed circuits 202 of two circuit numbers individually specified by a start circuit number and an end circuit number. Or, other types of group management instructions besides the above-mentioned group exclusion and group addition may be provided.

[0083] Figure 18 shows an example of a functional block diagram of the write destination determination circuit according to Embodiment 2. In Figure 18, the write destination determination circuit 1800 includes a counter 901, a write signal generation unit 902, and a write signal output unit 903, similar to the write destination determination circuit 204 shown in Figure 9, and also includes a group management unit 1801. The group management unit 1801 generates, holds, and updates group configuration information (hereinafter referred to as group configuration information) set for circuits 1 to n, which are sets of each high-speed circuit 202 and each data writing circuit 203, in accordance with group management commands transmitted from the command holding unit 501.

[0084] Figure 19 shows an example of group configuration information held by the group management unit according to Embodiment 2. The group configuration information held by the group management unit 1801 indicates which of circuits 1 to n belong to (are included in) each group, and specifically includes a group number and 1 bit of data for each of circuits 1 to n. The 1 bit of data for each circuit is set to "1" if it belongs to the group indicated by the group number, and to "0" if it does not belong to the group, indicating whether each of circuits 1 to n belongs to each group. For example, in the example of the 7th group configuration information in Figure 19, the group number is 10, the 1 bit of data for circuits 1 to 11 is "1", and the 1 bit of data for the other circuits is "0", indicating that circuits 1 to 11 belong to group 10.

[0085] When a group management command is received from the command holding unit 501, the group management unit 1801 generates or updates group configuration information according to the content of the group management command. As described above, in the example of group configuration information shown in Figure 19, the management of one group requires the same number of 1-bit data points (a total of n bits of data) as the number of circuits 1 to n. However, if each group is set only for sets of high-speed circuits 202 and data writing circuits 203 with consecutive circuit numbers, the group configuration information may include only data indicating the start and end circuit numbers, as in the range specification in the instruction code of the group management command. This reduces the amount of data in the group configuration information, making it possible to reduce the amount of circuitry required by the group management unit 1801.

[0086] Figure 20 shows an example of the configuration of the write-enable signal generated by the write-signal generation unit according to Embodiment 2. Similar to Figure 10, Figure 20 also shows the data transfer instructions input to the write-signal generation unit 902. The write-signal generation unit 902 takes the instruction type and destination circuit / group number of the data transfer instructions as input and generates a write-enable signal. Similar to the write-enable signal according to Embodiment 1 shown in Figure 10, the write-enable signal includes 1-bit circuit write-enable signals (circuit 1 write-enable signal to circuit n write-enable signal) for each of the circuits 1 to n, which are sets of each speed-up circuit 202 and each data write circuit 203.

[0087] The write signal generation unit 902 generates a write enable signal as described in the explanation of Figure 10 when the instruction type indicates a general common data transfer or a target data transfer. When the instruction type indicates a group common data transfer, the write signal generation unit 902 obtains and refers to the configuration information of the group specified by the transfer destination group number from the group management unit 1801, and generates a write enable signal by setting all circuit write enable signals for two or more circuits belonging to that group to "1" and all other circuit write enable signals to "0".

[0088] Furthermore, if the group configuration information held by the group management unit 1801 consists of 1-bit data for each of the circuits 1 to n, as shown in Figure 19, the group configuration information will have the same configuration as the write-enable signal. Therefore, the write signal generation unit 902 can use (output) the group configuration information obtained from the group management unit 1801 as is for the write-enable signal. Also, if the group configuration information held by the group management unit 1801 is configured to specify a range of two or more circuits belonging to each group, that is, to include only data indicating the start circuit number and the end circuit number, the write signal generation unit 902 generates a write-enable signal by setting all circuit write-enable signals for two or more circuits included in the range specified by the start circuit number and the end circuit number to "1", and all other circuit write-enable signals to "0".

[0089] As explained above, the information processing device in Embodiment 2 allows for the arbitrary setting of one or more groups for all high-speed circuits provided by the information processing device using newly prepared group management instructions and a group management unit, and also allows for the transfer of the same common data by specifying a group using newly prepared group common data transfer instructions. As a result, in addition to the same effects as in Embodiment 1, the data transfer time between the CPU and some high-speed circuits can be significantly reduced even when some high-speed circuits corresponding to each control target perform calculation processing using common information about some control targets that have the same attributes, such as type and location.

[0090] Although embodiments of the present invention have been described in detail above, the present invention is not limited to the embodiments described above, and various design modifications can be made without departing from the spirit of the invention as described in the claims. For example, each of the embodiments described above is described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to having all of the described configurations. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace parts of the configuration of each embodiment with other configurations. [Explanation of Symbols]

[0091] 100...Control device 110... Information Processing Device 120...Communication device 130...Controlled object 140…Peripheral devices 201…CPU 202...High speed circuit 203...Data writing circuit 204, 1800...Writing destination determination circuit 205...Data transfer circuit 206...Arithmetic unit 207...Memory 301...High-speed calculation data storage unit 302...High-speed computing unit 501...Instruction holding section 502...General-purpose data storage unit 901... Counter 902...Write signal generation section 903...Write signal output section 1801... Group Management Department

Claims

1. An information processing device comprising: a plurality of high-speed circuits that perform specific arithmetic processing; and a CPU that holds a plurality of transfer data to be transferred to one or more of the high-speed circuits and a plurality of data transfer instructions that instruct the transfer of the transfer data to one or more of the high-speed circuits, Each of the aforementioned high-speed circuits is provided with a plurality of data writing circuits, each of which writes the transfer data to the high-speed circuit, A write destination determination circuit that outputs a write instruction signal to one or more data writing circuits instructing them to write the transfer data to the high-speed circuit in accordance with the data transfer instruction output from the CPU, A data transfer circuit that transfers the transfer data output from the CPU to each of the data writing circuits, An information processing device equipped with the following features.

2. An information processing apparatus according to claim 1, The transferred data includes common data used by all of the high-speed circuits for calculation processing. The data transfer instruction includes a common data transfer instruction that instructs the transfer of the common data to all of the high-speed circuits. Information processing device.

3. An information processing apparatus according to claim 2, The write destination determination circuit outputs a write instruction signal to all of the data write circuits instructing them to write, in accordance with the common data transfer command. Information processing device.

4. An information processing apparatus according to claim 1, The transferred data includes target data used individually by each of the aforementioned high-speed circuits for calculation processing. The data transfer command includes a target data transfer command that specifies one of the high-speed circuits and instructs it to transfer the target data. Information processing device.

5. The information processing apparatus according to claim 4, The write destination determination circuit outputs a write instruction signal that instructs the data write circuit corresponding to the designated high-speed circuit to write, in accordance with the target data transfer command. Information processing device.

6. An information processing apparatus according to claim 1 or claim 4, Each of the aforementioned high-speed circuits is assigned a different circuit number in advance. In the aforementioned data transfer command, the transfer of the data is instructed by specifying the high-speed circuit using the circuit number. Information processing device.

7. An information processing apparatus according to claim 1, The CPU further holds a group management instruction that sets up a group by specifying at least two or more of the aforementioned acceleration circuits. The system further includes a group management unit that generates and maintains group configuration information for each group configured according to the group management instruction output from the CPU, including information on at least two of the high-speed circuits constituting the group and a group number assigned to the group. Information processing device.

8. The information processing apparatus according to claim 7, The transferred data includes group common data used for arithmetic processing by at least two of the high-speed circuits constituting the group, The data transfer command includes a group common data transfer command that specifies the group by the group number and instructs the transfer of the group common data. Information processing device.

9. The information processing apparatus according to claim 8, The write destination determination circuit, in accordance with the group common data transfer command, refers to the group configuration information held by the group management unit, including the specified group number, and outputs a write instruction signal that instructs writing only to at least two of the data writing circuits corresponding to the at least two of the high-speed circuits constituting the group to which the group number has been assigned. Information processing device.

10. An information processing system, One or more controlled objects, A control device for controlling each of the aforementioned controlled objects, It has at least the following features: The control device is The information processing apparatus according to claim 1, A communication device that communicates with each of the one or more of the aforementioned controlled objects, Equipped with, Information processing system.

11. An information processing method in an information processing apparatus comprising: a plurality of acceleration circuits that perform specific arithmetic processing; a CPU that holds a plurality of instructions including a plurality of transfer data to be transferred to one or more of the acceleration circuits and a plurality of data transfer instructions that instruct the transfer of the transfer data to one or more of the acceleration circuits; and a plurality of data writing circuits provided for each of the acceleration circuits, each writing the transfer data to the acceleration circuit, wherein The transfer data output from the CPU is simultaneously transferred to each of the data writing circuits. In accordance with the data transfer command output from the CPU, one or more data writing circuits are instructed to write the transfer data to the high-speed circuit. Information processing methods.

12. The information processing method according to claim 11, The transferred data includes common data used by all of the high-speed circuits for calculation processing. The data transfer instruction includes a common data transfer instruction that instructs the transfer of the common data to all of the high-speed circuits, In accordance with the aforementioned common data transfer command, all of the data writing circuits are instructed to write. Information processing methods.

13. The information processing method according to claim 11, The transferred data includes target data used individually by each of the aforementioned high-speed circuits for calculation processing. The data transfer command includes a target data transfer command that specifies one of the high-speed circuits and instructs it to transfer the target data. In accordance with the aforementioned target data transfer command, write is instructed only to the data writing circuit corresponding to the designated high-speed circuit. Information processing methods.

14. The information processing method according to claim 11, The instruction further includes a group management instruction that specifies at least two of the aforementioned speed-up circuits to set up a group, The transferred data includes group common data used for arithmetic processing by at least two of the high-speed circuits constituting the group, The data transfer command includes a group common data transfer command that specifies the group and instructs the transfer of the group common data, In accordance with the group management instruction output from the CPU, group configuration information including information on at least two of the high-speed circuits constituting the group is generated and maintained for each group that is set up. In accordance with the group common data transfer command, the group configuration information of the specified group among the group configuration information is referenced, Write instructions are given only to at least two of the data writing circuits corresponding to at least two of the high-speed circuits that constitute the group. Information processing methods.

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