Low-noise amplification circuit

Abstract

This invention provides a low-noise amplification circuit that can improve the noise figure (NF). [Solution] The low-noise amplification circuit 1 comprises an input terminal 11 and an output terminal 12, an amplifier 20 connected between the input terminal 11 and the output terminal 12, a limiter circuit 30 including two diodes D1 and D2 connected in parallel in opposite directions between the path connecting the input terminal 11 and the input terminal of the amplifier 20 and ground, a matching circuit 40 including an inductor L1 connected between the path connecting the input terminal 11 and the input terminal of the amplifier 20 and ground, and a capacitor C1 connected between the limiter circuit 30 and ground, and also connected between the matching circuit 40 and ground.

Description

Technical Field

[0001] The present invention relates to a low-noise amplifier circuit.

Background Art

[0002] Patent Document 1 discloses a low-noise amplifier circuit including an input matching circuit and a limiter circuit connected to the input side of an amplifier.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the above conventional technique, improvement of NF (Noise Figure) in the low-noise amplifier circuit is desired.

[0005] Accordingly, the present invention provides a low-noise amplifier circuit capable of improving NF.

Means for Solving the Problems

[0006] A low-noise amplifier circuit according to one aspect of the present invention includes: an input terminal and an output terminal; an amplifier connected between the input terminal and the output terminal; a limiter circuit including two diodes connected in parallel in opposite directions between a path connecting the input terminal and an input end of the amplifier and a ground; a matching circuit including a first inductor connected between the path connecting the input terminal and the input end of the amplifier and the ground; and a first capacitor connected between the limiter circuit and the ground, and connected between the matching circuit and the ground.

Effects of the Invention

[0007] According to one aspect of the present invention, the noise figure (NF) in a low-noise amplifier circuit can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a circuit diagram of a low-noise amplifier circuit according to Embodiment 1. [Figure 2] Figure 2 is a layout diagram of the low-noise amplifier circuit according to Embodiment 1. [Figure 3] Figure 3 is a plan view of the first layer of the capacitor and matching circuit according to Embodiment 1. [Figure 4] Figure 4 is a plan view of the second layer of the matching circuit according to Embodiment 1. [Figure 5] Figure 5 is a plan view of the third layer of the matching circuit according to Embodiment 1. [Figure 6] Figure 6 is a layout diagram of the low-noise amplifier circuit according to Embodiment 2. [Figure 7] Figure 7 is a plan view of the first layer of the capacitor and matching circuit according to Embodiment 2. [Figure 8] Figure 8 is a plan view of the second layer of the matching circuit according to Embodiment 2. [Figure 9] Figure 9 is a plan view of the third layer of the matching circuit according to Embodiment 2. [Figure 10] Figure 10 is a circuit diagram of a low-noise amplifier circuit according to another embodiment. [Modes for carrying out the invention]

[0009] The embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below are all general or specific examples. The numerical values, shapes, materials, components, arrangement of components, and connection configurations shown in the following embodiments are examples only and are not intended to limit the present invention.

[0010] The figures are schematic diagrams that have been appropriately emphasized, omitted, or had their proportions adjusted to illustrate the present invention, and are not necessarily strictly accurate representations. Actual shapes, positional relationships, and proportions may differ. In each figure, substantially identical components are denoted by the same reference numerals, and redundant explanations may be omitted or simplified.

[0011] In the following figures, the x and y axes are mutually orthogonal axes on a plane parallel to the main surface of the substrate. The z axis is perpendicular to the main surface of the substrate, with its positive direction indicating upwards and its negative direction indicating downwards.

[0012] In the following explanation, "connected" includes not only direct connections via terminals and / or wiring conductors, but also electrical connections via other circuit elements. "A is switchably connected to B" means that the connection and disconnection between A and B are switchable, and that A is connected to B via a switch. Note that "A is connected to B" includes "A is switchably connected to B".

[0013] "C is connected between A and B" means that one end of C is connected to A and the other end of C is connected to B, meaning that C is in series connection to the path between A and B. "C is connected between the path between A and B and ground" means that one end of C is connected to the path between A and B and the other end of C is connected to ground, meaning that C is in shunt connection to the path between A and B. "The path between A and B" means a path consisting of conductors that electrically connect A to B.

[0014] The term "terminal" means the point at which a conductor in a circuit element terminates. When the impedance of the conductor between circuit elements is sufficiently low, a terminal is interpreted not only as a single point, but also as any point on the conductor between circuit elements or the entire conductor. The term "node" means a point between circuit elements. When the impedance of the conductor between circuit elements is sufficiently low, a node is interpreted not only as a single point, but also as any point on the conductor between circuit elements or the entire conductor.

[0015] The phrase "a component is arranged on a substrate" includes that the component is arranged on the main surface of the substrate, and that the component is arranged inside the substrate. The phrase "a component is arranged on the main surface of the substrate" includes, in addition to the component being arranged in contact with the main surface of the substrate, that the component is arranged above the main surface without being in contact with the main surface (for example, the component is stacked on another component arranged in contact with the main surface). Further, "a component is arranged on the main surface of the substrate" may include that the component is arranged in a recess formed in the main surface. The phrase "a component is arranged inside the substrate" includes, in addition to the component being encapsulated in the substrate, that the entire component is arranged between both main surfaces of the substrate but a part of the component is not covered by the substrate, and that only a part of the component is arranged inside the substrate.

[0016] The term "plan view of the substrate" means viewing an object by orthographic projection onto the xy plane in the negative direction of the z-axis. The phrase "A overlaps B in a plan view of the substrate" means that the region of A orthographically projected onto the xy plane overlaps the region of B orthographically projected onto the xy plane.

[0017] The phrase "A is directly connected to B" means that A is connected in physical contact with B. Note that "A is directly connected to B" also includes that A is connected to B via a bonding material. The term "bonding material" means a substance interposed between A and B for the physical connection (bonding) between A and B.

[0018] "The thickness of a wiring on a wiring layer of a semiconductor substrate" means the length of the wiring along the z-axis. When comparing the thicknesses of wirings on different wiring layers, the comparison is made based on the average thickness of the wirings. For the average thickness of the wiring, the average of the thicknesses at the center of the wiring sampled at equal intervals in the direction in which the wiring extends is used.

[0019] Terms indicating the relationship between elements such as "parallel" and "perpendicular", terms indicating the shape of elements such as "straight line", and numerical ranges do not represent only strict meanings, but mean that they also include a substantially equivalent range, for example, an error of about several percent.

[0020] (Embodiment 1) Embodiment 1 will be described.

[0021] [1.1. Circuit Configuration of Low Noise Amplifier Circuit 1] FIG. 1 is a circuit configuration diagram of the low noise amplifier circuit 1 according to the present embodiment. Note that FIG. 1 is an exemplary circuit configuration diagram, and the low noise amplifier circuit 1 may be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the low noise amplifier circuit 1 provided below should not be construed in a limited manner.

[0022] The low noise amplifier circuit 1 includes an input terminal 11 and an output terminal 12, an amplifier 20, a limiter circuit 30, a matching circuit 40, and capacitors C1 and C2.

[0023] The input terminal 11 is an external connection terminal of the low noise amplifier circuit 1, and is a terminal for receiving a high-frequency signal. The input terminal 11 is connected to, for example, an antenna (not shown) outside the low noise amplifier circuit 1, and is connected to the capacitor C2 inside the low noise amplifier circuit 1.

[0024] The output terminal 12 is an external connection terminal of the low noise amplifier circuit 1, and is a terminal for supplying a high-frequency signal. The output terminal 12 is connected to, for example, an RFIC (Radio Frequency Integrated Circuit) (not shown) outside the low noise amplifier circuit 1, and is connected to the output end of the amplifier 20 inside the low noise amplifier circuit 1.

[0025] Capacitor C1 is an example of a first capacitor, connected between the limiter circuit 30 and ground, and between the matching circuit 40 and ground. Specifically, one of the two electrodes of capacitor C1 is connected to the limiter circuit 30 and the matching circuit 40, and the other of the two electrodes of capacitor C1 is connected to ground. Capacitor C1 can block the DC component in the path between the limiter circuit 30 and the matching circuit 40 and ground.

[0026] Capacitor C2 is an example of a second capacitor and is connected between the input terminal 11 and the inductor L2 of the matching circuit 40. Specifically, one of the two electrodes of capacitor C2 is connected to the input terminal 11, and the other electrode of capacitor C2 is connected to one end of inductors L1 and L2. Capacitor C2 is a so-called coupling capacitor and can pass high-frequency components and block DC components in the path between the input terminal 11 and the amplifier 20.

[0027] [1.1.1. Circuit configuration of amplifier 20] Amplifier 20 receives a power supply voltage V from a power supply (not shown). DD High-frequency signals can be amplified using this. The amplifier 20 is connected between the input terminal 11 and the output terminal 12. Specifically, the input terminal of the amplifier 20 is connected to the input terminal 11 via the capacitor C2 and the matching circuit 40, and the output terminal of the amplifier 20 is connected to the output terminal 12.

[0028] The amplifier 20 includes cascode-connected transistors Tr1 and Tr2, inductors L3 and L4, and capacitors C3, C4 and C5.

[0029] The drain terminal of transistor Tr1 is connected to the source terminal of transistor Tr2. The source terminal of transistor Tr1 is connected to ground via inductor L4. The gate terminal of transistor Tr1 is connected to input terminal 11 via capacitor C2 and matching circuit 40.

[0030] The drain terminal of transistor Tr2 is connected to the power supply via inductor L3 and to output terminal 12 via capacitor C4. The source terminal of transistor Tr2 is connected to the drain terminal of transistor Tr1. The gate terminal of transistor Tr2 is connected to ground via capacitor C3.

[0031] Field-effect transistors (FETs) are used as transistors Tr1 and Tr2, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). However, transistors Tr1 and Tr2 are not limited to FETs. Transistors Tr1 and Tr2 may also be bipolar transistors.

[0032] Inductor L3 is a so-called choke inductor and is connected between the power supply and transistor Tr2. Specifically, one end of inductor L3 is connected to the drain terminal of transistor Tr2, and the other end of inductor L3 is connected to the power supply.

[0033] Inductor L4 is a so-called source inductor and is connected between transistor Tr1 and ground. Specifically, one end of inductor L4 is connected to the source terminal of transistor Tr1, and the other end of inductor L4 is connected to ground.

[0034] Capacitor C3 is connected between transistor Tr2 and ground. Specifically, one of the two electrodes of capacitor C3 is connected to the gate terminal of transistor Tr2, and the other electrode of capacitor C3 is connected to ground.

[0035] Capacitor C4 is connected between the path between transistor Tr2 and inductor L3 and the output terminal 12. Specifically, one of the two electrodes of capacitor C4 is connected to the path between the drain terminal of transistor Tr2 and one end of inductor L3, and the other of the two electrodes of capacitor C4 is connected to the output terminal 12.

[0036] Capacitor C5 is connected between the path between capacitor C4 and output terminal 12 and ground. Specifically, one of the two electrodes of capacitor C5 is connected to the path between capacitor C4 and output terminal 12, and the other of the two electrodes of capacitor C5 is connected to ground.

[0037] It should be noted that amplifier 20 is not limited to a common-source amplifier. For example, amplifier 20 may be a common-gate amplifier. Also, amplifier 20 does not have to include cascode-connected transistors Tr1 and Tr2. For example, amplifier 20 may include transistor Tr1 but not transistor Tr2. Furthermore, in the circuit configuration of amplifier 20, other circuit elements and wiring may be inserted between the paths connecting each circuit element and signal path disclosed in Figure 1. For example, a path may be provided connecting the drain terminal and gate terminal of transistor Tr2 via a capacitor.

[0038] [1.1.2. Circuit configuration of limiter circuit 30] The limiter circuit 30 is connected between the path connecting the matching circuit 40 and the amplifier 20 and ground. Specifically, one end of the limiter circuit 30 is connected to the path connecting the matching circuit 40 and the input terminals of the amplifier 20, and the other end of the limiter circuit 30 is connected to ground via capacitor C1.

[0039] The limiter circuit 30 includes two diodes D1 and D2 connected in parallel in opposite directions. The limiter circuit 30 can limit the signal voltage to a voltage amplitude defined by the forward voltages of diodes D1 and D2 (e.g., 0.4V to 0.7V). Specifically, a diode to which a forward voltage is applied becomes conductive, and can limit voltages exceeding the forward voltage. In other words, the limiting voltage of the limiter circuit 30 is the forward voltage of diodes D1 and D2. Note that other diodes may be connected in series with each of diodes D1 and D2, and the limiting voltage of the limiter circuit 30 may be adjusted according to the number of diodes connected in series. The limiter circuit 30 may also be implemented by diode-connected MOSFETs or diode-connected bipolar transistors.

[0040] [1.1.3. Circuit configuration of matching circuit 40] The matching circuit 40 is a transmission line transformer (TLT) capable of shifting the phase and converting the impedance. The matching circuit 40 is not limited to a TLT. The matching circuit 40 includes inductors L1 and L2.

[0041] Inductor L1 is an example of a first inductor and is a so-called secondary line. Inductor L1 is connected between the path between the input terminal 11 and the input terminal of the amplifier 20 and ground. Specifically, one end of inductor L1 is connected to the path between capacitor C2 and inductor L2, and the other end of inductor L1 is connected to ground via capacitor C1.

[0042] Inductor L2 is an example of a second inductor and is the so-called main line. Inductor L2 is connected between the input terminal 11 and the input terminal of the amplifier 20. Specifically, one end of inductor L2 is connected to the input terminal 11 via capacitor C2, and the other end of inductor L2 is connected to the input terminal of the amplifier 20.

[0043] These inductors L1 and L2 are configured to be connectable to each other. Furthermore, one end of inductors L1 and L2 are connected to each other, and the first direction from one end of inductor L1 to the other end and the second direction from one end of inductor L2 to the other end are configured to be in opposite directions.

[0044] [1.2. Implementation example of low-noise amplifier circuit 1] Next, an example of implementing the low-noise amplifier circuit 1 having the circuit configuration described above will be explained with reference to Figure 2. Figure 2 is a layout diagram of the low-noise amplifier circuit 1 according to this embodiment.

[0045] In Figure 2, each component is labeled to facilitate understanding of its relative positions. However, these labels are not necessarily required on the actual components.

[0046] Figure 2 shows an exemplary layout of the low-noise amplifier circuit 1, and the low-noise amplifier circuit 1 can be implemented using a wide variety of circuit implementations and circuit technologies. Therefore, the description of the low-noise amplifier circuit 1 provided below should not be interpreted as restrictive.

[0047] The low-noise amplifier circuit 1 is mounted as a semiconductor integrated circuit having multiple wiring layers on a semiconductor substrate 10. The multiple wiring layers include, in order from the semiconductor substrate 10 side, at least a first layer, a second layer, and a third layer. The second and third layers can form metal films that are thicker than those of the first layer. For example, the thickness of the metal films in the second and third layers is several micrometers, and the thickness of the metal film in the first layer is about 1 / 10th of that of the metal films in the second and third layers.

[0048] The semiconductor substrate 10 is a substrate made of semiconductor material, and is sometimes called a die or chip. The semiconductor material for the semiconductor substrate 10 can be, but is not limited to, silicon single crystal, gallium nitride (GaN), or silicon carbide (SiC).

[0049] The input terminal 11 (IN) is connected to one electrode of capacitor C2 (C) via wiring 51 formed in the second and / or third layer. The other electrode of capacitor C2 is directly connected to one end of inductors L1 and L2 of matching circuit 40 (TLT). The other end of inductor L2 of matching circuit 40 is connected to one end of limiter circuit 30 (LMT) and the input terminal of amplifier 20 (AMP) via wiring 53 formed in the second and / or third layer. The other end of inductor L1 of matching circuit 40 is connected to the other end of limiter circuit 30 (LMT) and one electrode of capacitor C1 (C) via wiring 54 formed in the second and / or third layer. The other electrode of capacitor C1 is connected to ground terminal 13 (GND) via wiring 55 formed in the second and / or third layer. The output terminal of amplifier 20 is connected to output terminal 12 (OUT) via wiring 56 formed in the second and / or third layer.

[0050] [1.3. Implementation example of capacitor C2 and matching circuit 40] The detailed configuration of capacitor C2 and matching circuit 40 will be described with reference to Figures 3, 4, and 5. Figures 3 to 5 are plan views of the first, second, and third layers of capacitor C2 and matching circuit 40 according to this embodiment. In Figures 3 to 5, elements and wiring in other layers are represented by dashed lines.

[0051] Figures 3 to 5 show exemplary configurations of capacitor C2 and matching circuit 40, and capacitor C2 and matching circuit 40 can be implemented using a wide variety of circuit implementations and circuit technologies. Therefore, the description of capacitor C2 and matching circuit 40 provided below should not be interpreted as restrictive.

[0052] Capacitor C2 is a MOM (Metal-Oxide-Metal) capacitor and is positioned to cross the matching circuit 40. Capacitor C2 includes two comb-shaped electrodes C21 and C22 formed by wiring on the first layer. The two comb-shaped electrodes C21 and C22 are positioned opposite each other so as to interlock, and an oxide film (e.g., SiO2) is placed between the two comb-shaped electrodes C21 and C22. Comb-shaped electrode C21 is an example of a first electrode and is connected to the input terminal 11 via wiring 51. Comb-shaped electrode C22 is an example of a second electrode and is directly connected to one end of the helical shape of inductors L1 and L2. Note that capacitor C2 is not limited to a MOM capacitor. For example, capacitor C2 may be a MIM (Metal-Insulator-Metal) capacitor.

[0053] The inductors L1 and L2 of the matching circuit 40 are formed by wiring on the second and third layers. Specifically, inductor L1 is formed by wiring that extends in a counterclockwise spiral shape from the inside to the outside. Inductor L2 is formed by wiring that extends in a clockwise spiral shape from the inside to the outside. One end of the inner spiral shape of inductors L1 and L2 is directly connected to the comb-shaped electrode C22 of capacitor C2. The other end of the outer spiral shape of inductors L1 and L2 is connected to wiring 54 and 53, respectively.

[0054] In a plan view of the semiconductor substrate 10, a portion L11 of inductor L1 overlaps with a portion L21 of inductor L2, and a portion L12 of inductor L1 overlaps with a portion L22 of inductor L2. Also, in a plan view of the semiconductor substrate 10, capacitor C2 overlaps at least partially with a portion L11 of inductor L1 and a portion L21 of inductor L2.

[0055] [1.4. Summary] As described above, the low-noise amplification circuit 1 according to this embodiment comprises an input terminal 11 and an output terminal 12, an amplifier 20 connected between the input terminal 11 and the output terminal 12, a limiter circuit 30 including two diodes D1 and D2 connected in parallel in opposite directions between the path connecting the input terminal 11 and the input terminal of the amplifier 20 and ground, a matching circuit 40 including an inductor L1 connected between the path connecting the input terminal 11 and the input terminal of the amplifier 20 and ground, and a capacitor C1 connected between the limiter circuit 30 and ground, and also connected between the matching circuit 40 and ground.

[0056] According to this, the capacitor connected between the limiter circuit 30 and ground and the capacitor connected between the matching circuit 40 and ground are made common. Therefore, the circuit area for the capacitor can be reduced, increasing the freedom of layout and shortening the wiring length. As a result, parasitic capacitance due to wiring can be reduced, and the noise figure (NF) of the low-noise amplifier circuit 1 can be improved.

[0057] Furthermore, in the low-noise amplification circuit 1 according to this embodiment, for example, the matching circuit 40 may be a transmission line transformer, and may also include an inductor L2 connected between the input terminal 11 and the input terminal of the amplifier 20.

[0058] According to this, even if the matching circuit 40 is a transmission line transformer, the noise figure (NF) of the low-noise amplifier circuit 1 can be improved.

[0059] For example, the low-noise amplification circuit 1 according to this embodiment may further include a semiconductor substrate 10 and a capacitor C2 connected between the input terminal 11 and the inductor L2. The inductors L1, L2, and capacitor C2 may be formed by wiring on the semiconductor substrate 10. In a plan view of the semiconductor substrate 10, a portion of the inductor L1 may overlap with a portion of the inductor L2, and in a plan view of the semiconductor substrate 10, the capacitor C2 may at least partially overlap with a portion of the inductor L1 and a portion of the inductor L2.

[0060] According to this, a capacitor C2 is placed over the overlapping portion of inductors L1 and L2. If ordinary wiring were placed over the overlapping portion of inductors L1 and L2, the thickness of the wiring would decrease, increasing the wiring resistance. In contrast, capacitor C2 experiences little degradation in characteristics even when the thickness of the wiring decreases. Therefore, by placing capacitor C2 over the overlapping portion of inductors L1 and L2, the increase in wiring resistance can be suppressed, and the noise figure (NF) of the low-noise amplifier circuit 1 can be improved.

[0061] Furthermore, for example, in the low-noise amplification circuit 1 according to this embodiment, the inductors L1 and L2 may be formed by wiring that extends in a spiral shape in opposite directions from the inside to the outside in a plan view of the semiconductor substrate 10, the input terminal 11 may be located outside the spiral shape, and the capacitor C2 may include a first electrode (e.g., a comb-shaped electrode C21) connected to the input terminal 11 and a second electrode (e.g., a comb-shaped electrode C22) connected to one end of the inside of the spiral shape of the inductors L1 and L2.

[0062] According to this, in inductors L1 and L2 formed by wiring extending in opposite directions in a spiral shape, the wiring that crosses from the outside to the inside of the spiral shape can be replaced with a capacitor C2, thereby suppressing the increase in wiring resistance and improving the NF of the low-noise amplifier circuit 1.

[0063] Furthermore, for example, in the low-noise amplifier circuit 1 according to this embodiment, the second electrode of the capacitor C2 (for example, the comb-shaped electrode C22) may be directly connected to one end of the inductors L1 and L2.

[0064] According to this, the wiring connecting inductors L1 and L2 and capacitor C2 can be omitted, reducing wiring resistance and improving the noise figure (NF) of the low-noise amplifier circuit 1.

[0065] Furthermore, for example, in the low-noise amplifier circuit 1 according to this embodiment, a plurality of wiring layers including at least a first layer, a second layer, and a third layer may be formed on the semiconductor substrate 10 in order from the semiconductor substrate 10 side, the inductors L1 and L2 may be formed by wiring on the second and third layers, the capacitor C2 may be formed by wiring on the first layer, and the thickness of the wiring on the first layer may be thinner than the thickness of the wiring on the second and third layers, respectively.

[0066] According to this, capacitor C2, which experiences less characteristic degradation due to the thinness of the wiring, is formed from wiring on the thinner first layer. Therefore, characteristic degradation of the low-noise amplifier circuit 1 can be suppressed.

[0067] For example, in the low-noise amplification circuit 1 according to this embodiment, the capacitor C2 may be a MOM capacitor.

[0068] This allows for the simplification of the manufacturing process and the reduction of circuit area.

[0069] (Embodiment 2) Next, Embodiment 2 will be described. In this embodiment, the main difference from Embodiment 1 is that, in the implementation of the low-noise amplification circuit 1, capacitor C1 overlaps with the transmission line transformer instead of capacitor C2. Below, this embodiment will be described with reference to the drawings, focusing on the differences from Embodiment 1.

[0070] The circuit configuration of the low-noise amplifier circuit 1A according to this embodiment is the same as that of the low-noise amplifier circuit 1 according to Embodiment 1, so its illustration and description are omitted. In this embodiment, the low-noise amplifier circuit 1A does not need to include the capacitor C2.

[0071] [2.1. Implementation example of low-noise amplifier circuit 1A] An example of implementing the low-noise amplifier circuit 1A will be described with reference to Figure 6. Figure 6 is a layout diagram of the low-noise amplifier circuit 1 according to this embodiment.

[0072] In Figure 6, each component is labeled to facilitate understanding of its relative positions. However, these labels are not necessarily required on the actual components.

[0073] Figure 6 shows an exemplary layout of the low-noise amplifier circuit 1A, and the low-noise amplifier circuit 1A can be implemented using a wide variety of circuit implementations and circuit technologies. Therefore, the description of the low-noise amplifier circuit 1A provided below should not be interpreted as restrictive.

[0074] The low-noise amplification circuit 1A is implemented as a semiconductor integrated circuit having multiple wiring layers on a semiconductor substrate 10, similar to the low-noise amplification circuit 1 according to Embodiment 1.

[0075] The input terminal 11 (IN) is connected to one electrode of capacitor C2 (C) via wiring 51A formed in the second and / or third layer. The other electrode of capacitor C2 is connected to one end of inductors L1 and L2 of matching circuit 40 (TLT) via wiring 52A formed in the second and / or third layer. The other end of inductor L2 of matching circuit 40 is directly connected to one end of limiter circuit 30 (LMT) and is also connected to the input terminal of amplifier 20 (AMP) via wiring 531A formed in the first layer and wiring 532A formed in the second and / or third layer. The other end of inductor L1 of matching circuit 40 is directly connected to the other end of limiter circuit 30 and is also directly connected to one electrode of capacitor C1 (C). The other electrode of capacitor C1 is connected to ground terminal 13 (GND) via wiring 55A formed in the second and / or third layer. The output terminal of the amplifier 20 is connected to the output terminal 12 (OUT) via wiring 56 formed in the second and / or third layer.

[0076] [2.2. Implementation example of capacitor C1 and matching circuit 40] The detailed configuration of capacitor C1 and matching circuit 40 will be described with reference to Figures 7, 8, and 9. Figures 7 to 9 are plan views of the first, second, and third layers of capacitor C1 and matching circuit 40 according to this embodiment. In Figures 7 to 9, elements and wiring in other layers are represented by dashed lines.

[0077] Figures 7 to 9 show exemplary configurations of capacitor C1 and matching circuit 40, and capacitor C1 and matching circuit 40 can be implemented using a wide variety of circuit implementations and circuit technologies. Therefore, the description of capacitor C1 and matching circuit 40 provided below should not be interpreted as restrictive.

[0078] Capacitor C1 is a MOM capacitor and is positioned to cross the matching circuit 40. Capacitor C1 includes two comb-shaped electrodes C11 and C12 formed by wiring on the first layer. The two comb-shaped electrodes C11 and C12 are positioned opposite each other so as to interlock, and an oxide film (e.g., SiO2) is placed between the two comb-shaped electrodes C11 and C12. Comb-shaped electrode C11 is an example of a first electrode and is directly connected to the other end inside the helical shape of inductor L1 and also directly connected to the other end of the limiter circuit 30. Comb-shaped electrode C12 is an example of a second electrode and is connected to wiring 55A.

[0079] The inductors L1 and L2 of the matching circuit 40 are formed by wiring on the second and third layers. Specifically, inductor L1 is formed by wiring extending in a counterclockwise spiral shape from the outside to the inside. Inductor L2 is formed by wiring extending in a clockwise spiral shape from the outside to the inside. One end of the outer spiral shape of inductors L1 and L2 is connected to wiring 52A. The other end of the inner spiral shape of inductor L1 is directly connected to the limiter circuit 30 and also directly connected to the comb-shaped electrode C11 of capacitor C1. The other end of the inner spiral shape of inductor L2 is directly connected to the limiter circuit 30 and also connected to wiring 531A.

[0080] In a plan view of the semiconductor substrate 10, a portion L11 of inductor L1 overlaps with a portion L21 of inductor L2, and a portion L12 of inductor L1 overlaps with a portion L22 of inductor L2. Also, in a plan view of the semiconductor substrate 10, capacitor C1 overlaps at least partially with a portion L12 of inductor L1 and a portion L22 of inductor L2.

[0081] [2.3. Summary] As described above, the low-noise amplification circuit 1A according to this embodiment may further include a semiconductor substrate 10, and the inductors L1 and L2 and the capacitor C1 may be formed by wiring on the semiconductor substrate 10, and in a plan view of the semiconductor substrate 10, a part of inductor L1 may overlap with a part of inductor L2, and in a plan view of the semiconductor substrate 10, the capacitor C1 may at least partially overlap with a part of inductor L1 and a part of inductor L2.

[0082] According to this, capacitor C1 is superimposed on the area where inductors L1 and L2 overlap. If ordinary wiring were superimposed on the area where inductors L1 and L2 overlap, the thickness of the wiring would decrease, increasing the wiring resistance. In contrast, capacitor C1 undergoes little characteristic degradation even when the thickness of the wiring decreases. Therefore, by superimposing capacitor C1 on the area where inductors L1 and L2 overlap, the increase in wiring resistance can be suppressed, and the NF of the low-noise amplifier circuit 1 can be improved.

[0083] For example, in the low-noise amplification circuit 1A according to this embodiment, the inductors L1 and L2 may be formed by wiring that extends in a spiral shape in opposite directions from the outside to the inside in a plan view of the semiconductor substrate 10, the input terminal 11 may be located outside the spiral shape and connected to one end of the spiral shape of the inductors L1 and L2, the low-noise amplification circuit 1A may further include a ground terminal 13 located outside the spiral shape, and the capacitor C1 may include a first electrode (e.g., a comb-shaped electrode C11) connected to the other end of the spiral shape of the inductor L1 and a second electrode (e.g., a comb-shaped electrode C12) connected to the ground terminal 13.

[0084] According to this, in inductors L1 and L2 formed by wiring extending in opposite directions in a spiral shape, the wiring that crosses from the inside to the outside of the spiral shape can be replaced with a capacitor C1, thereby suppressing the increase in wiring resistance and improving the NF of the low-noise amplifier circuit 1A.

[0085] Furthermore, for example, in the low-noise amplification circuit 1A according to this embodiment, the first electrode of the capacitor C1 (for example, the comb-shaped electrode C11) may be directly connected to the other end of the inductor L1.

[0086] According to this, the wiring connecting the inductor L1 and the capacitor C1 can be omitted, reducing the wiring resistance and improving the noise figure (NF) of the low-noise amplifier circuit 1A.

[0087] Furthermore, for example, in the low-noise amplifier circuit 1A according to this embodiment, a plurality of wiring layers including at least a first layer, a second layer, and a third layer may be formed on the semiconductor substrate 10 in order from the semiconductor substrate 10 side, the inductors L1 and L2 may be formed by wiring on the second and third layers, the capacitor C1 may be formed by wiring on the first layer, and the thickness of the wiring on the first layer may be thinner than the thickness of the wiring on the second and third layers, respectively.

[0088] According to this, capacitor C1, which experiences less characteristic degradation due to the thinness of the wiring, is formed with wiring on the thinner first layer. Therefore, characteristic degradation of the low-noise amplifier circuit 1A can be suppressed.

[0089] For example, in the low-noise amplification circuit 1A according to this embodiment, the capacitor C1 may be a MOM capacitor.

[0090] This allows for the simplification of the manufacturing process and the reduction of circuit area.

[0091] (Other embodiments) The low-noise amplification circuit according to the present invention has been described above based on embodiments, but the low-noise amplification circuit according to the present invention is not limited to the above embodiments. Other embodiments realized by combining any of the components in the above embodiments, modified versions obtained by applying various modifications to the above embodiments that a person skilled in the art can conceive of without departing from the spirit of the present invention, and various devices incorporating the above low-noise amplification circuit are also included in the present invention.

[0092] For example, in the circuit configuration of the low-noise amplifier circuit according to each of the above embodiments, other circuit elements and wiring may be inserted between the paths connecting each circuit element and signal path disclosed in the drawings. For example, the low-noise amplifier circuits 1 and 1A may include a bias circuit that applies a bias voltage to the transistor Tr1.

[0093] Furthermore, for example, the matching circuit 40 included in the low-noise amplification circuits 1 and 1A according to each of the above embodiments does not have to be a transmission line transformer. For example, the matching circuit 40 may have the circuit configuration shown in Figure 10.

[0094] Figure 10 is a circuit diagram of a low-noise amplifier circuit 1B according to another embodiment. As shown in Figure 10, the low-noise amplifier circuit 1B differs from the low-noise amplifier circuits 1 and 1A according to embodiments 1 and 2 above in that it includes a matching circuit 40B instead of a matching circuit 40. The matching circuit 40B includes an inductor L1B. Inductor L1B is an example of a first inductor and is connected between the path connecting the input terminal 11 and the input terminal of the amplifier 20 and ground. Specifically, one end of inductor L1B is connected to the path connecting capacitor C2 and the input terminal of the amplifier 20, and the other end of inductor L1B is connected to ground via capacitor C1. Even with the low-noise amplifier circuit 1B including the matching circuit 40B as described above, the capacitor connected between the limiter circuit 30 and ground and the capacitor connected between the matching circuit 40B and ground are common, similar to the low-noise amplifier circuits 1 and 1A. Therefore, the circuit area for the capacitor can be reduced, increasing the freedom of layout and shortening the wiring length. As a result, parasitic capacitance due to wiring can be reduced, and the noise figure (NF) of the low-noise amplifier circuit 1B can be improved.

[0095] In the embodiments described above, the plurality of wiring layers on the semiconductor substrate 10 included a first layer on which thinner metal wiring is formed and second and third layers on which thicker metal wiring is formed. However, the plurality of wiring layers are not limited to these. For example, the plurality of wiring layers do not necessarily include a second or third layer. Alternatively, for example, the plurality of wiring layers may include a fourth layer on which metal wiring of the same thickness as the second and third layers is formed.

[0096] In the embodiments described above, the low-noise amplification circuit was included in a semiconductor integrated circuit, but this is not limited to that. For example, part or all of the low-noise amplification circuit may not be included in a semiconductor integrated circuit. For example, the low-noise amplification circuit may be implemented using discrete components. [Industrial applicability]

[0097] This invention, as a low-noise amplification circuit placed in the front end, can be widely used in communication devices such as mobile phones. [Explanation of Symbols]

[0098] 1, 1A, 1B Low-noise amplifier circuits 10 Semiconductor substrates 11 input terminals 12 output terminals 13 Ground terminal 20 Amplifiers 30 Limiter Circuit 40, 40B matching circuit 51, 51A, 52A, 53, 531A, 532A, 54, 55, 55A, 56 Wiring C1, C2, C3, C4, C5 Capacitors C11, C12, C21, C22 comb-shaped electrodes D1, D2 diodes L1, L1B, L2, L3, L4 Inductors L11, L12, L21, L22 some Tr1, Tr2 Transistors

Claims

1. Input terminals and output terminals, An amplifier connected between the input terminal and the output terminal, A limiter circuit including two diodes connected in parallel in opposite directions between the path connecting the input terminal and the input terminal of the amplifier and ground, A matching circuit including a first inductor connected between the path connecting the input terminal and the input terminal of the amplifier and ground, The system comprises a first capacitor connected between the limiter circuit and ground, and also connected between the matching circuit and ground, Low-noise amplification circuit.

2. The matching circuit is a transmission line transformer and further includes a second inductor connected between the input terminal and the input terminal of the amplifier. The low-noise amplification circuit according to claim 1.

3. The low-noise amplification circuit further, Semiconductor substrate and A second capacitor connected between the input terminal and the second inductor is also included, The first inductor, the second inductor, and the second capacitor are formed by wiring on the semiconductor substrate. In a plan view of the semiconductor substrate, a portion of the first inductor overlaps with a portion of the second inductor. In a plan view of the semiconductor substrate, the second capacitor overlaps at least partially with the part of the first inductor and the part of the second inductor. The low-noise amplification circuit according to claim 2.

4. The first inductor and the second inductor are formed by wiring that extends in a spiral shape from the inside to the outside in opposite directions in a plan view of the semiconductor substrate. The input terminals are located on the outside of the spiral shape. The second capacitor includes a first electrode connected to the input terminal and a second electrode connected to one end of the helical shape of the first inductor and the second inductor. The low-noise amplification circuit according to claim 3.

5. The second electrode is directly connected to one end of the first inductor and the second inductor. The low-noise amplification circuit according to claim 4.

6. On the semiconductor substrate, a plurality of wiring layers are formed in order from the semiconductor substrate side, including at least a first layer, a second layer, and a third layer. The first inductor and the second inductor are formed by wiring on the second and third layers, The second capacitor is formed by wiring on the first layer, The thickness of the wiring on the first layer is thinner than the thickness of the wiring in the second and third layers, A low-noise amplifier circuit according to any one of claims 3 to 5.

7. The aforementioned second capacitor is a MOM (Metal-Oxide-Metal) capacitor. A low-noise amplifier circuit according to any one of claims 3 to 6.

8. The low-noise amplification circuit further comprises a semiconductor substrate, The first inductor, the second inductor, and the first capacitor are formed by wiring on the semiconductor substrate. In a plan view of the semiconductor substrate, a portion of the first inductor overlaps with a portion of the second inductor. In a plan view of the semiconductor substrate, the first capacitor overlaps at least partially with the portion of the first inductor and the portion of the second inductor. The low-noise amplification circuit according to claim 2.

9. The first inductor and the second inductor are formed by wiring that extends in a spiral shape in opposite directions from the outside to the inside when viewed in plan on the semiconductor substrate. The input terminal is located on the outside of the spiral shape and is connected to one end of the spiral shape of the first inductor and the second inductor. The low-noise amplification circuit further includes a ground terminal located on the outside of the helical shape, The first capacitor includes a first electrode connected to the other end of the helical shape of the first inductor and a second electrode connected to the ground terminal. The low-noise amplification circuit according to claim 8.

10. The first electrode is directly connected to the other end of the first inductor. The low-noise amplification circuit according to claim 9.

11. On the semiconductor substrate, a plurality of wiring layers are formed in order from the semiconductor substrate side, including at least a first layer, a second layer, and a third layer. The first inductor and the second inductor are formed by wiring on the second and third layers, The first capacitor is formed by wiring on the first layer, The thickness of the wiring on the first layer is thinner than the thickness of the wiring in the second and third layers, A low-noise amplifier circuit according to any one of claims 8 to 10.

12. The first capacitor is an MOM capacitor. A low-noise amplifier circuit according to any one of claims 8 to 11.

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