Semiconductor device and method for manufacturing a semiconductor device

Abstract

In a semiconductor device equipped with a MOS-type capacitor having a trench structure, the accumulation of signal charge at the bottom of the MOS-type capacitor is avoided. [Solution] The semiconductor device includes a semiconductor substrate having a first conductivity type, a photodiode provided on the semiconductor substrate, a MOS-type capacitor having a trench structure provided on the semiconductor substrate adjacent to the photodiode, a first well provided in the region containing the MOS-type capacitor and having a first conductivity type, a second well provided in the region containing the first well and the photodiode and having a second conductivity type opposite to the first conductivity type, and a third well provided in the region containing the first well and having a second conductivity type that extends deeper into the semiconductor substrate than the second well. The third well has a low-concentration region below the gate of the trench structure in which the concentration of impurities of the second conductivity type is lower than the surrounding area.

Description

Technical Field

[0001] The disclosed technology relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] The following technology is known as a technology related to a semiconductor device constituting a back-illuminated image sensor. Patent Document 1 describes a plurality of pixels each including a first conductivity type semiconductor substrate, a photodiode formed in the semiconductor substrate, a transistor formed in the semiconductor substrate, having a first conductivity type well region and amplifying charges generated in the photodiode, and a MOS capacitor portion formed in the semiconductor substrate, having a well region of the same first conductivity type as the semiconductor substrate, and accumulating and holding charges from the transistor; a first diffusion layer formed in the semiconductor substrate over the entire surface of the plurality of pixels so as to cover the well region of the transistor and the well region of the MOS capacitor portion, and implanted with an impurity for a second conductivity type different from the first conductivity type; and a plurality of second diffusion layers formed in the semiconductor substrate so as to respectively cover the well region of the transistor and the well region of the MOS capacitor portion of each pixel, and implanted with an impurity for the second conductivity type.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] A back-illuminated image sensor is known that includes, within one pixel, a photodiode that generates signal charges corresponding to incident light, a MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) capacitor that temporarily accumulates the signal charges, and a transistor that processes the signal charges. The signal charges are guided to the transfer gate by forming a potential gradient inside the semiconductor substrate.

[0005] MOS capacitors, which store signal charges, sometimes employ trench-structured gates to increase capacitance per unit area. However, forming a potential gradient to guide signal charges to the transfer gate is not easy at the bottom of a MOS capacitor with a trench-structured gate. If signal charges accumulate at the bottom of the MOS capacitor, crosstalk to adjacent pixels may occur. If signal charges are collected with a delay, ghosting may occur in the reconstructed image.

[0006] The disclosed technology has been made in view of the above points and aims to avoid the accumulation of signal charge at the bottom of a MOS type capacitor in a semiconductor device equipped with a MOS type capacitor having a trench structure.

[0007] A semiconductor device relating to the disclosed technology includes: a semiconductor substrate having a first conductivity type; a photodiode provided on the semiconductor substrate and generating a signal charge corresponding to incident light; a MOS-type capacitor provided on the semiconductor substrate adjacent to the photodiode and having a trench-structured gate for accumulating the signal charge; a first well provided in a region encompassing the MOS-type capacitor and having the first conductivity type; a second well provided in a region encompassing the first well and the photodiode and having a second conductivity type opposite to the first conductivity type; and a third well provided in a region encompassing the first well and having the second conductivity type, extending deeper into the semiconductor substrate than the second well. The third well has a low-concentration region below the trench-structured gate where the concentration of impurities of the second conductivity type is lower than the surrounding area.

[0008] A method for manufacturing a semiconductor device according to the disclosed technology is a method for manufacturing a semiconductor device as described above, comprising: a step of forming a trench in a semiconductor substrate; a step of forming an oxide film on the inner wall of the trench; a first impurity injection step of injecting an impurity of the first conductivity type into a region of the semiconductor substrate that encloses the trench; a step of embedding a gate member in the trench after the first impurity injection step; a second impurity injection step of injecting an impurity of the second conductivity type to form a second well; and a third impurity injection step of injecting an impurity of the second conductivity type to form a third well. The diffusion region of the impurity injected in the first impurity injection step is a low-concentration region in the third well where the concentration of the impurity of the second conductivity type is lower than that of the surrounding area. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a plan view showing an example of the configuration of a semiconductor device according to an embodiment of the disclosed technology. [Figure 2] Figure 2 is a cross-sectional view showing the configuration of one pixel in a semiconductor device. [Figure 3A] Figure 3A is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology. [Figure 3B] Figure 3B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology. [Figure 3C] Figure 3C is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology. [Figure 3D] Figure 3D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology. [Figure 3E] Figure 3E is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology. [Figure 3F] Figure 3F is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology. [Figure 3G] Figure 3G is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology. [Figure 3H] Figure 3H is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology. [Figure 4] Figure 4 is a cross-sectional view showing the configuration of a semiconductor device according to a comparative example. [Figure 5] Figure 5 is a graph showing the potential distribution along the path from the bottom of the MOS capacitor to the transfer gate. [Modes for carrying out the invention]

[0010] The embodiments of the disclosed technology will be described below with reference to the drawings. In each drawing, substantially identical or equivalent components or parts are given the same reference numerals.

[0011] Figure 1 is a plan view showing an example of the configuration of a semiconductor device 10 according to an embodiment of the disclosed technology. The semiconductor device 10 constitutes a back-illuminated image sensor. Figure 2 is a cross-sectional view showing the configuration of one pixel of the semiconductor device 10. The semiconductor device 10 has a plurality of pixels 15 provided on a semiconductor substrate 11. Each pixel 15 has one photodiode 20, one MOS capacitor 30, one transistor 40, and one transfer gate 60. These elements constituting the pixel 15 are provided on the surface side of the semiconductor substrate 11. The surface of the semiconductor substrate 11 is covered with an insulating film 70 including a wiring layer.

[0012] The semiconductor device 10 generates an image corresponding to the incident light L from the back surface of the semiconductor substrate 11. The incident light L may be, for example, soft X-rays. By using a back-illumination type, it becomes unnecessary to shield areas other than the photodiode 20, and almost all of the incident light L can be used as signal light.

[0013] When the incident light L is soft X-rays, the incident light L may pass through the semiconductor substrate 11 and reach the surface of the semiconductor substrate 11, which may cause malfunction of the transistor 40. In order to avoid the occurrence of malfunction, the thickness of the semiconductor substrate 11 is set to be relatively large, for example, about 50 μm. Thereby, most of the incident light L is absorbed in the semiconductor substrate 11, so that the risk of malfunction can be suppressed, and the utilization efficiency of the incident light L can be further improved.

[0014] The semiconductor substrate 11 is, for example, a P-type silicon substrate. The photodiode 20 generates signal charges corresponding to the incident light L. The photodiode 20 has an N-type diffusion region 21 provided on the surface side of the semiconductor substrate 11. By applying a reverse bias to the PN junction formed by the N-type diffusion region 21 and the P-type semiconductor substrate 11, a depletion layer extending from the photodiode 20 reaches the back surface of the semiconductor substrate 11 (full depletion). This facilitates the collection of signal charges, and achieves higher sensitivity, faster response, and lower noise in image sensing.

[0015] The MOS capacitor 30 is provided adjacent to the photodiode 20. The MOS capacitor 30 accumulates signal charges generated in response to the incident light L. The MOS capacitor 30 has a trench structure. The MOS capacitor 30 has an oxide film 32 and a gate 31 embedded in a trench formed in the semiconductor substrate 11. The member constituting the gate 31 is, for example, polysilicon. The oxide film 32 is a silicon oxide film (SiO₂ film) and functions as a gate oxide film. Around the gate 31, an N-type diffusion region 33 constituting a drain or a source is provided.

[0016] The MOS capacitor 30 is provided inside the P-type well 35. In other words, the P-type well 35 is provided in a region enclosing the MOS capacitor 30. In the P-type well 35, the portion extending directly under the gate 31 reaches a deeper position in the semiconductor substrate 11 than other portions. The P-type well 35 is an example of the "first well" in the disclosed technology. The MOS capacitor 30 is electrically isolated from other elements on the semiconductor substrate 11 by an STI (Shallow Trench Isolation) 50 surrounding its outer periphery.

[0017] The transistor 40 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) that processes collected signal charges, and has an N-type diffusion region 42 constituting a drain or a source, and a gate 41.

[0018] The transistor 40 is provided inside the P-type well 45. In other words, the P-type well 45 is provided in a region enclosing the transistor 40. The P-type well 45 is an example of the "fourth well" in the disclosed technology.

[0019] The transfer gate 60 is provided between the photodiode 20 and the transistor 40. The transfer gate 60 has a gate electrode provided between the N-type diffusion region 21 of the photodiode 20 and the N-type diffusion region 42 of the transistor 40. The transfer gate 60 transfers the collected signal charges to the transistor 40 by being turned on.

[0020] The semiconductor device 10 includes a P-type well 35 associated with the MOS capacitor 30, a P-type well 45 associated with the transistor 40, and an N-type well 12 provided in a region enclosing the photodiode 20. That is, each element constituting the pixel 15 is provided inside the N-type well 12. The N-type well 12 is an example of the "second well" in the disclosed technology.

[0021] The semiconductor device 10 has an N-type well 37 located in a region that encloses a P-type well 35 associated with a MOS-type capacitor 30. That is, the P-type well 35 enclosing the MOS-type capacitor 30 is located inside the N-type well 37. The N-type well 37 partially overlaps with the N-type well 12 and extends deeper into the semiconductor substrate 11 than the well 12. The N-type well 37 is an example of a “third well” in the disclosed art.

[0022] The N-type well 37 has a low-concentration N-type region 36 formed directly below the gate 31 of the MOS capacitor 30. The low-concentration region 36 is a region in which the concentration of N-type impurities is lower than in other regions within the well 37. In other words, a concentration gradient is formed in the lower part of the MOS capacitor 30, where the concentration of N-type impurities gradually increases from directly below the gate 31 toward its periphery.

[0023] The semiconductor device 10 has an N-type well 47 located in a region that encloses a P-type well 45 associated with the transistor 40. That is, the P-type well 45 enclosing the transistor 40 is located inside the N-type well 47. The N-type well 47 partially overlaps with the N-type well 12 and extends deeper into the semiconductor substrate 11 than the well 12. The N-type well 47 is an example of a “fifth well” in the disclosed art.

[0024] The manufacturing method of the semiconductor device 10 is described below. Figures 3A to 3H are cross-sectional views showing an example of the manufacturing method of the semiconductor device 10.

[0025] First, a semiconductor substrate 11 is prepared. The semiconductor substrate 11 may be, for example, a P-type silicon substrate. Next, an STI (Shallow Trench Isolation) 50 is formed at a predetermined position on the surface of the semiconductor substrate 11 (Figure 3A). The STI 50 is formed by creating shallow grooves on the surface of the semiconductor substrate 11 using photolithography and etching techniques, embedding a silicon oxide film (SiO2) in these grooves using the CVD (Chemical Vapor Deposition) method, and then removing the excess silicon oxide film by CMP (Chemical Mechanical Polishing).

[0026] Next, using photolithography and etching techniques, a trench 51 with a depth of approximately 1.5 μm to 3.0 μm is formed at the gate 31 formation position of the MOS type capacitor 30 (Figure 3B).

[0027] Next, an oxide film 32 is formed on the inner wall surface of the trench 51 using thermal oxidation and CVD methods (Figure 3C). The oxide film 32 is a silicon oxide film (SiO2) and functions as a gate oxide film.

[0028] Next, P-type impurities are implanted into the region containing the trench 51 using photolithography and ion implantation techniques. This forms a P-type diffusion region 36A, which will later become a low-concentration N-type region 36 (Figure 3D). This process is referred to as the first impurity implantation step. The impurities implanted in the first impurity implantation step are, for example, boron, with an implantation energy of, for example, 200 keV, and a dose of, for example, 2.0 × 10⁻⁶. 11 cm -2 In the first impurity injection step, the impurities are injected in layers into the trench 51, so the impurities reach deep into the lower part of the trench 51.

[0029] Next, gate members are embedded in the trench 51 using the CVD method, and then excess gate members are removed by etch-back. This forms the gate 31 of the trench structure (Figure 3E). The gate members are, for example, polysilicon. The embedding of gate members into the trench 51 is performed after the first impurity injection step described above.

[0030] Next, using photolithography and ion implantation techniques, N-type impurities are implanted into the region encompassing the entire pixel 15. This forms an N-type well 12 (Figure 3F). This process is referred to as the second impurity implantation process. The impurities implanted in the second impurity implantation process are, for example, phosphorus, with an implantation energy of, for example, 3000 keV and a dose of, for example, 1.0 × 10⁻⁶. 11 cm -2 That is the case.

[0031] Next, using photolithography and ion implantation techniques, N-type impurities are implanted into the region containing the MOS capacitor 30 and the region containing the transistor 40, respectively. This forms N-type wells 37 and 47 (Figure 3G). This process is referred to as the third impurity implantation step. The impurity implanted in the third impurity implantation step is, for example, phosphorus, with an implantation energy of, for example, 1600 keV and a dose of, for example, 1.0 × 10⁻⁶. 12 cm -2 In the third impurity injection step, an N-type impurity is injected over the P-type diffusion region 36A formed in the first impurity injection step.

[0032] Subsequently, an annealing process is performed, for example, at 1100°C for about 12 hours. This causes the impurities implanted in the first to third impurity implantation steps to diffuse. As a result, the P-type diffusion region 36A and the N-type wells 37 and 47 reach deeper into the semiconductor substrate 11 than the N-type well 12, respectively.

[0033] The P-type diffusion region 36A becomes a low-concentration N-type diffusion region due to the N-type impurities injected in the third impurity injection step. In other words, the P-type diffusion region 36A becomes a low-concentration region 36 within the well 37, where the concentration of N-type impurities is lower than that of the surrounding area. In order to form the N-type low-concentration region 36, the conditions in the first and third impurity injection steps are set so that the concentration of N-type impurities in the well 37 is higher than the concentration of P-type impurities in the diffusion region 36A.

[0034] Next, using photolithography and ion implantation techniques, P-type impurities are implanted into the region containing the MOS capacitor 30 and the region containing the transistor 40, respectively. This forms P-type wells 35 and 45 (Figure 3H).

[0035] Next, N-type impurities are implanted at the formation site of the photodiode 20 using photolithography and ion implantation techniques. This forms an N-type diffusion region 21 that constitutes the cathode of the photodiode 20 (Figure 3H).

[0036] Next, the gate 41 and transfer gate 60 of transistor 40 are formed. Subsequently, the diffusion region 33 of MOS capacitor 30 and the diffusion region 42 of transistor 40 are formed using photolithography and ion implantation techniques. Next, an insulating film 70 including a wiring layer is formed (Figure 3H).

[0037] As described above, the semiconductor device 10 according to the embodiment of the disclosed technology includes a P-type semiconductor substrate 11, a photodiode 20 provided on the semiconductor substrate 11 that generates a signal charge corresponding to incident light L, a trench-structured MOS-type capacitor 30 provided on the semiconductor substrate 11 adjacent to the photodiode 20 that stores signal charge, a P-type well 35 provided in the region encompassing the MOS-type capacitor 30, an N-type well 12 provided in the region encompassing the well 35 and the photodiode 20, and an N-type well 37 provided in the region encompassing the well 35 that extends deeper into the semiconductor substrate 11 than the well 12. The well 37 has a low-concentration region 36 below the gate of the trench structure of the MOS-type capacitor 30 where the concentration of N-type impurities is lower than the surrounding area.

[0038] Figure 4 is a cross-sectional view showing the configuration of the semiconductor device 10X according to the comparative example. The semiconductor device 10X according to the comparative example does not have a low-concentration region in well 37.

[0039] Figure 5 is a graph showing the potential distribution along the path from the bottom of the MOS capacitor 30 to the transfer gate 60 for semiconductor devices 10 and 10X, respectively. In the graphs shown in Figure 5, the horizontal axis represents the position on the path from the bottom of the MOS capacitor 30 to the transfer gate 60, and the vertical axis represents the potential. The solid line is a graph for semiconductor device 10 according to an embodiment of the disclosed technology, and the dotted line is a graph for semiconductor device 10X according to a comparative example.

[0040] In semiconductor devices 10 and 10X, it is necessary to guide signal charges to the transfer gate 60 by forming a potential gradient inside the semiconductor substrate 11. In the comparative example semiconductor device 10X, a concentration gradient of N-type impurities is not formed below the MOS capacitor 30, and a potential barrier is formed on the path from below the MOS capacitor 30 to the transfer gate 60. That is, a potential gradient for guiding the signal charges present below the MOS capacitor 30 to the transfer gate 60 is not formed. As a result, signal charges accumulate below the MOS capacitor 30. If signal charges accumulate below the MOS capacitor 30, crosstalk to adjacent pixels may occur. If the signal charges are collected with a delay, ghosting may occur in the reconstructed image.

[0041] On the other hand, according to the semiconductor device 10 according to an embodiment of the disclosed technology, the well 37 containing the MOS type capacitor 30 has a low-concentration region 36 at the bottom of the MOS type capacitor 30 where the concentration of N-type impurities is lower than the surrounding area. As a result, a concentration gradient is formed at the bottom of the MOS type capacitor 30 where the concentration of N-type impurities gradually increases from directly below the gate 31 toward its periphery. This forms a potential gradient for guiding the signal charge present at the bottom of the MOS type capacitor 30 to the transfer gate 60. As a result, the accumulation of signal charge at the bottom of the MOS type capacitor 30 is avoided, and the occurrence of defects such as crosstalk and ghosting can be prevented. The potential gradient for guiding the signal charge present at the bottom of the MOS type capacitor 30 to the transfer gate 60 means that the potential increases monotonically from the bottom of the MOS type capacitor 30 toward the transfer gate 60.

[0042] The following additional information is disclosed regarding the embodiments described above. (Note 1) A semiconductor substrate having a first conductivity type, A photodiode provided on the semiconductor substrate generates a signal charge corresponding to incident light, A MOS-type capacitor is provided on the semiconductor substrate adjacent to the photodiode and has a trench-structured gate for accumulating the signal charge. A region containing the MOS type capacitor is provided, and a first well having the first conductivity type is provided, A second well is provided in the region containing the first well and the photodiode, and has a second conductivity type opposite to that of the first conductivity type, A third well having the second conductivity type is provided in the region encompassing the first well and extends deeper into the semiconductor substrate than the second well, It has, The third well has a low-concentration region below the gate of the trench structure where the impurity concentration is lower than that of the surrounding area. Semiconductor equipment.

[0043] (Note 2) A transistor is provided on the semiconductor substrate adjacent to the photodiode and processes the signal charge, A fourth well having the first conductivity type is provided in the region containing the transistor, A fifth well having the second conductivity type is provided in the region encompassing the fourth well and extends deeper into the semiconductor substrate than the second well, It further possesses, The second well is located in the region encompassing the first well, the photodiode, and the fourth well. The semiconductor device described in Appendix 1.

[0044] (Note 3) The first conductivity type is P-type, and the second conductivity type is N-type. The semiconductor device described in Appendix 1 or Appendix 2.

[0045] (Note 4) A method for manufacturing a semiconductor device as described in any one of the appendices 1 to 3, The steps include forming trenches in the semiconductor substrate, The process of forming an oxide film on the inner wall of the trench, A first impurity implantation step of implanting the first conductivity type of impurity into the region of the semiconductor substrate that encloses the trench, The process involves embedding a gate member in the trench after the first impurity injection step, A second impurity injection step of injecting the second conductive type of impurity to form the second well, A third impurity injection step of injecting the second conductive type of impurity to form the third well, It has, The diffusion region of the impurities injected in the first impurity injection step is a low-concentration region within the third well where the concentration of the second conductive type of impurity is lower than that of the surrounding area. Manufacturing method. [Explanation of symbols]

[0046] 10, 10X Semiconductor 11 Semiconductor substrates 12, 35, 37, 45, 47 wells 15 pixels 20 Photodiodes 30 MOS type capacitors Gate 31 36 Low concentration area 40 transistors Gate 41 60 Transfer Gates

Claims

1. A semiconductor substrate having a first conductivity type, A photodiode provided on the semiconductor substrate generates a signal charge corresponding to incident light, A MOS-type capacitor is provided on the semiconductor substrate adjacent to the photodiode and has a trench-structured gate for accumulating the signal charge. A first well having the first conductivity type is provided in the region enclosing the MOS type capacitor, A second well is provided in the region containing the first well and the photodiode, and has a second conductivity type opposite to the first conductivity type, A third well having the second conductivity type is provided in the region encompassing the first well and extends deeper into the semiconductor substrate than the second well, It has, The third well has a low-concentration region below the gate of the trench structure in which the concentration of the second conductive type of impurity is lower than that of the surrounding area. Semiconductor equipment.

2. A transistor is provided on the semiconductor substrate adjacent to the photodiode and processes the signal charge, A fourth well having the first conductivity type is provided in the region enclosing the transistor, A fifth well having the second conductivity type is provided in the region encompassing the fourth well and extends deeper into the semiconductor substrate than the second well, It further possesses, The second well is provided in the region that encompasses the first well, the photodiode, and the fourth well. The semiconductor device according to claim 1.

3. The first conductivity type is P-type, and the second conductivity type is N-type. The semiconductor device according to claim 1.

4. A method for manufacturing a semiconductor device according to any one of claims 1 to 3, The steps include forming trenches in the semiconductor substrate, The process of forming an oxide film on the inner wall of the trench, A first impurity implantation step of implanting the first conductivity type of impurity into the region of the semiconductor substrate that encloses the trench, The first impurity injection step is followed by the step of embedding a gate member in the trench, A second impurity injection step of injecting the second conductive type of impurity to form the second well, A third impurity injection step of injecting the second conductive type of impurity to form the third well, It has, The diffusion region of the impurities injected in the first impurity injection step is a low-concentration region within the third well where the concentration of the second conductive type of impurity is lower than that of the surrounding area. Manufacturing method.

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