Multilayer ceramic electronic components

Abstract

To provide a multilayer ceramic electronic component with a low rate of crack occurrence in the end margin of the base material during external electrode formation. [Solution] The multilayer ceramic capacitor 100 has a base body including a capacitance section in which a dielectric layer 11 mainly composed of ceramic crystal particles and an internal electrode layer are alternately stacked along the Z axis, and a pair of external electrodes. The internal electrode layer is arranged in which a first internal electrode layer 12a and a second internal electrode layer 12b are alternately stacked in the capacitance section and are drawn out to the first side surface 10a and the second side surface, respectively, which are the external surfaces of the base body. The pair of external electrodes are formed on the external surface of the base body so as to be electrically connected to the internal electrode layer of the base body, with each electrode spaced apart. The base body has an end margin 15 between the capacitance section and the external electrodes, which includes a first end margin 15a that encloses only the first internal electrode layer and a second end margin that encloses only the second internal electrode layer. The end margin includes a secondary phase 41 that penetrates the internal electrode layer.

Description

[Technical Field]

[0001] This disclosure relates to multilayer ceramic electronic components. [Background technology]

[0002] Multilayer ceramic electronic components have a structure in which dielectric layers and internal electrode layers are alternately stacked. Examples of multilayer ceramic electronic components include multilayer ceramic capacitors (MLCCs).

[0003] Multilayer ceramic electronic components, such as multilayer ceramic capacitors, are used in various electronic devices, including high-frequency communication systems like mobile phones and in-vehicle electronic control devices. Therefore, there is a demand for various performance improvements in multilayer ceramic electronic components, and these have been studied for some time (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2023-158176 [Overview of the project] [Problems that the invention aims to solve]

[0005] As mentioned above, multilayer ceramic electronic components are mounted in various electronic devices, and there is a demand for various performance improvements. In particular, in recent years, there has been a demand for smaller size and higher capacity in multilayer ceramic electronic components, requiring miniaturization and thinning of each component. However, with multilayer ceramic electronic components, for example, when external electrodes are formed, cracks sometimes occur inside the base material called the end margin on the side where the internal electrodes are pulled out and connected to the external electrodes. Furthermore, the miniaturization and thinning of each component made cracks particularly likely to occur. For this reason, there is a demand for multilayer ceramic electronic components with a low crack occurrence rate in the end margin during external electrode formation.

[0006] This disclosure aims to provide a multilayer ceramic electronic component that has a low rate of crack occurrence in the end margin of the base material during external electrode formation. [Means for solving the problem]

[0007] The multilayer ceramic electronic components disclosed herein are The device comprises a substrate including a capacitance section in which multiple layers of dielectric layers mainly composed of ceramic crystal particles and internal electrode layers are alternately stacked along a first axis, and a pair of external electrodes. The internal electrode layer is formed by alternately stacking a first internal electrode layer and a second internal electrode layer in the capacitance portion, and each is brought out to the outer surface of the base body. The pair of external electrodes are formed on the outer surface of the base body so as to be spaced apart from each other, so as to be electrically connected to the internal electrode layer of the base body. The substrate has an end margin that includes a first end margin that encloses only the first internal electrode layer and a second end margin that encloses only the second internal electrode layer between the capacitance portion and the external electrode. The end margin includes a secondary phase that penetrates the internal electrode layer. [Effects of the Invention]

[0008] According to this disclosure, it is possible to provide a multilayer ceramic electronic component in which the crack occurrence rate of the end margin of the base material is low when external electrodes are formed. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a partial cross-sectional perspective view illustrating a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 2] Figure 2 is a cross-sectional view illustrating an example of a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 3] Figure 3 is a cross-sectional view illustrating an example of a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 4] Figure 4 is a cross-sectional view illustrating the details of the end margin in a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 5] Figure 5 is a flowchart of a method for manufacturing a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 6] Figure 6 is a diagram illustrating a method for manufacturing a multilayer ceramic capacitor according to one aspect of the present disclosure. [Modes for carrying out the invention]

[0010] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In the present specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to omit redundant descriptions. In the drawings, an X-axis, a Y-axis, and a Z-axis that are orthogonal to each other are appropriately shown. The X-axis, Y-axis, and Z-axis define a fixed coordinate system fixed to a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component. When the outer shape of the multilayer ceramic capacitor, which is an example of the multilayer ceramic electronic component, is a substantially rectangular parallelepiped, the X-axis, Y-axis, and Z-axis can correspond to the length, width, and height thereof. All the drawings are schematically illustrated for explaining the structure, and do not accurately depict the sizes, scales, and the like. In particular, since it is difficult to accurately depict the number of internal electrode layers and dielectric layers due to space limitations on the page, the number of internal electrode layers and dielectric layers may be larger or smaller than the number of layers shown in the drawings.

[0011] Hereinafter, the multilayer ceramic electronic component of the present embodiment will be described using a multilayer ceramic capacitor which is an example of the multilayer ceramic electronic component.

[0012] [Multilayer Ceramic Electronic Component] (1) Structure of Multilayer Ceramic Electronic Component Figure 1 is a partial cross-sectional perspective view illustrating a multilayer ceramic capacitor 100. Figures 2 and 3 are cross-sectional views illustrating a multilayer ceramic capacitor. Figure 2 is a cross-sectional view along line AA in Figure 1. Figure 3 is a cross-sectional view along line BB in Figure 1. As illustrated in Figures 1 to 3, the multilayer ceramic capacitor 100 comprises a body 10 having a substantially rectangular parallelepiped shape. In the body 10, two opposing surfaces are referred to as the top surface and the bottom surface, and the four surfaces connecting the top surface and the bottom surface are referred to as sides. Usually, the surface on the circuit board side when the multilayer ceramic capacitor is mounted on a circuit board is referred to as the bottom surface, but this is not limited to this. In the example of Figures 1 to 3, the body 10 has a first external electrode 20a and a second external electrode 20b provided on the two opposing sides, the first side 10a and the second side 10b (see Figure 2). The first external electrode 20a extends from the first side 10a to the four adjacent surfaces. The second external electrode 20b extends from the second side surface 10b to four adjacent surfaces. However, the first external electrode 20a and the second external electrode 20b are spaced apart from each other. The external electrodes may be provided on any surface of the base body 10, not limited to two opposing sides.

[0013] The stacking direction in which the dielectric layer 11 and the internal electrode layer 12 are stacked is the first axis. In Figures 1 to 3, the first axis, which is the stacking direction between the dielectric layer 11 and the internal electrode layer 12, is the Z axis, and is the direction in which each internal electrode layer faces the other.

[0014] The axis perpendicular to the first axis, which is the stacking direction, is the second axis. In Figures 1 to 3, the second axis, which is perpendicular to the first axis, which is the stacking direction, is the X-axis. The second axis runs along the length of the base body 10 and is the axis that runs along the direction in which the first side surface 10a and the second side surface 10b of the base body 10 face each other, and the direction in which the first external electrode 20a and the second external electrode 20b face each other.

[0015] The axis perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis is the third axis. The third axis is the axis along the width of the internal electrode layer 12. In Figures 1 to 3, the third axis, which is perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis, is the Y axis. The third axis is the axis along the direction in which the third side 10c and the fourth side 10d, which are two of the four sides of the base body 10 other than the first side 10a and the second side 10b, face each other (see Figure 3). The X axis, Y axis, and Z axis are orthogonal to each other.

[0016] The stacking direction is not limited to the Z direction, but can be any direction. For example, the first axis, which is the stacking direction, may be the X-axis in the X direction, or the Y-axis in the Y direction.

[0017] In this specification, for the purpose of describing general embodiments, figures illustrating a specific embodiment may be used. However, the coordinate system described in one embodiment should be interpreted and applied in general embodiments as a general coordinate system with the stacking direction as the first axis. For example, what is described as the X-axis, Y-axis, and Z-axis in Figures 1 to 3, which are used in a specific embodiment where the stacking direction coincides with the Z-axis, can be interpreted and applied in general embodiments as the second axis, third axis, and first axis.

[0018] The base body 10 has a structure in which dielectric layers 11 containing a ceramic material that functions as a dielectric as its main component and internal electrode layers 12 are alternately stacked. The dielectric layer 11 may contain ceramic crystal particles as the ceramic material, and may also contain secondary phases. The internal electrode layer 12 comprises a plurality of first internal electrode layers 12a and a plurality of second internal electrode layers 12b. The first internal electrode layers 12a and the second internal electrode layers 12b are alternately stacked. The edge of the first internal electrode layer 12a is drawn out to the surface of the base body 10 on which the first external electrode 20a is provided, in the example of Figures 1 to 3, to the first side surface 10a. The edge of the second internal electrode layer 12b is drawn out to the surface of the base body 10 on which the second external electrode 20b is provided, in the example of Figures 1 to 3, to the second side surface 10b. In other words, the internal electrode layer 12 is drawn out from both ends along the second axis, the X axis. As a result, the first internal electrode layer 12a and the second internal electrode layer 12b are alternately conductive to the first external electrode 20a and the second external electrode 20b. Therefore, the multilayer ceramic capacitor 100 has a structure in which capacitor units are stacked. In addition, in the laminate of the dielectric layer 11 and the internal electrode layer 12, the internal electrode layer 12 is arranged as the outermost layer in the stacking direction, and the outer surface of the laminate in the stacking direction, in the example of Figures 1 to 3, the top and bottom surfaces are covered by a cover layer 13. The cover layer 13 mainly consists of a ceramic material. For example, the composition of the cover layer 13 may be the same as or different from that of the dielectric layer 11. Note that the configuration is not limited to that shown in Figures 1 to 3, as long as the first internal electrode layer 12a and the second internal electrode layer 12b are exposed in different regions of the surface of the laminate and are conductive to different external electrodes. Different regions on the surface of the laminate may be the respective surface regions of opposing faces of the laminate, the respective surface regions of adjacent faces of the laminate, or different surface regions of the same face of the laminate. If the different external electrodes are spaced apart from each other, the first internal electrode layer 12a and the second internal electrode layer 12b may extend from the surface exposed to the surface region of the laminate to other surfaces.

[0019] As illustrated in Figure 2, the region where the first internal electrode layer 12a connected to the first external electrode 20a and the second internal electrode layer 12b connected to the second external electrode 20b face each other is a region in the multilayer ceramic capacitor 100 where capacitance is generated. Therefore, the region where capacitance is generated is referred to as the capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers face each other across a dielectric layer 11 connected to different external electrodes.

[0020] The region in which the first internal electrode layers 12a connected to the first external electrode 20a face each other in the stacking direction without passing through the second internal electrode layer 12b connected to the second external electrode 20b is referred to as the first end margin 15a (see Figure 2). Similarly, the region in which the second internal electrode layers 12b connected to the second external electrode 20b face each other in the stacking direction without passing through the first internal electrode layer 12a connected to the first external electrode 20a is referred to as the second end margin 15b. In the following explanation, the first end margin 15a and the second end margin 15b will be collectively referred to as the end margin 15.

[0021] The end margin 15 is the region of the outer element adjacent to the capacitance section 14 in the second axis perpendicular to the first axis which is the stacking direction, and in the example of Figure 2, in the direction along the X axis. It is the region of the outer element adjacent to the capacitance section 14 on the side where the internal electrode layer 12 is pulled out and connected to the external electrode 20. Since the end margin 15 is the region of the outer element adjacent to the capacitance section 14 where the internal electrode layer is connected to the external electrode, the configuration is not limited to those shown in Figures 1 to 3, depending on the position of the external electrode.

[0022] In other words, the end margins 15 may be arranged such that the first end margin 15a and the second end margin 15b face each other, and each is located in a region outside the capacity portion 14 adjacent to the capacity portion 14 within the base body. The end margins 15 may be arranged such that the first end margin 15a and the second end margin 15b are adjacent to each other, and each is located in a region outside the capacity portion 14 adjacent to the capacity portion 14 within the base body. The end margins 15 may be arranged such that the first end margin 15a and the second end margin 15b are on the same surface outside the capacity portion 14 adjacent to the capacity portion 14 within the base body, and each is located in a different surface region on that same surface.

[0023] The different surface regions on the same plane refer to a configuration in which a region on the same plane of the base body is divided into two regions, which are adjacent to each other as the first end margin 15a and the second end margin 15b.

[0024] The end margin 15 includes a first end margin 15a that contains only the first internal electrode layer 12a, and a second end margin 15b that contains only the second internal electrode layer 12b. Therefore, each end margin region contains only one of either the first internal electrode layer 12a or the second internal electrode layer 12b.

[0025] Each end margin 15 can also be described as a region where internal electrode layers connected to the same external electrode face each other in the stacking direction without being connected to internal electrode layers connected to different external electrodes. The first end margin 15a and the second end margin 15b are regions where internal electrodes with equal potential face each other and are regions where no substantial capacitance is generated. The end margin 15 can mainly contain ceramic material. For example, the end margin 15 may have the same or different composition as the dielectric layer 11. Furthermore, as will be described later, the end margin 15 may contain secondary phases with a different composition from the dielectric material in addition to the dielectric material.

[0026] The side margin 16 is a region located outside the capacitance portion 14 in the third axis perpendicular to the stacking direction and the second axis, and in the example of Figure 3, in the direction along the Y axis. That is, the side margin 16 is the outer region adjacent to the capacitance portion 14 as viewed from the stacking direction, and the outer region adjacent to the capacitance portion 14 on the side from which the internal electrode layer 12 is not drawn out. The side margin 16 is also a region that does not generate capacitance. The side margin 16 can contain ceramic material as its main component. For example, the composition of the side margin 16 may be the same as or different from that of the dielectric layer 11.

[0027] The size of the multilayer ceramic capacitor 100 is not particularly limited, but for example, it may be 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height; 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height; 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height; 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height; 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height; or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height. However, the sizes listed above for the multilayer ceramic capacitor 100 are merely examples, and the multilayer ceramic capacitor is not limited to the above sizes. The size of the multilayer ceramic capacitor 100 may be, for example, length > width ≥ height, width > length ≥ height, height > length ≥ width, or height > width ≥ length. For example, length represents the size in the X-axis direction, width represents the size in the Y-axis direction, and height represents the size in the Z-axis direction.

[0028] As described above, one form of the multilayer ceramic capacitor 100 of this embodiment has a base body 10 and a pair of external electrodes. The base body 10 includes a capacitance section 14 in which a dielectric layer 11 mainly composed of ceramic crystal particles and an internal electrode layer 12 are alternately stacked in multiple layers along the first axis, the Z axis.

[0029] Furthermore, the internal electrode layer 12 is arranged in which a first internal electrode layer 12a and a second internal electrode layer 12b are alternately stacked in the capacitance section 14. The internal electrode layers 12 are each drawn out to the outer surface of the base body 10, and in one embodiment, they can be drawn out to the outside of the base body 10 from both ends along the X-axis, which is the second axis perpendicular to the first axis of the base body 10, i.e., from the first side surface 10a and the second side surface 10b.

[0030] A pair of external electrodes, the first external electrode 20a and the second external electrode 20b, are formed such that they are spaced apart from the outer surface of the body from which the first internal electrode layer 12a and the second internal electrode layer 12b are drawn, so that they are electrically connected to the internal electrode layer 12 of the body 10. In one embodiment, the external electrodes can be formed to cover the first side surface 10a and the second side surface 10b, which are the surfaces (outer surfaces) at both ends of the body 10 along the second axis, the X axis.

[0031] The base body 10 has an end margin 15 between the capacitance section 14 and the first external electrode 20a and the second external electrode 20b. In one embodiment, the end margin 15 is located at both ends of the capacitance section 14 along the second axis, which is the X-axis. The end margin 15 can contain only one of the first internal electrode layer 12a and the second internal electrode layer 12b. Specifically, the end margin 15 can include a first end margin 15a and a second end margin 15b. The first end margin 15a contains only the first internal electrode layer 12a as an internal electrode layer. The second end margin 15b contains only the second internal electrode layer 12b as an internal electrode layer.

[0032] The following explanation will describe each part based on the embodiment shown in Figures 1 to 3.

[0033] In this specification, component names may be given numbers such as "1st internal electrode layer" and "2nd internal electrode layer." However, these numbers are added solely to identify the component being described and to avoid confusion; they do not indicate priority or arrangement. Therefore, when there is no risk of confusion or when referring to them collectively, they may simply be written as "internal electrode layer." (2) Regarding the dielectric layer The dielectric layer 11 may contain a dielectric material. The dielectric layer 11 may mainly consist of ceramic crystal particles, which are the dielectric material, i.e., it may contain the largest amount of ceramic crystal particles in terms of substance. In addition to the ceramic crystal particles, the dielectric layer 11 may also contain additive compounds described later, or secondary phases formed by their reactants. The dielectric layer 11 may contain, for example, elements A and B as the dielectric material, and the general formula may be ABO 3-α The compound may contain a perovskite structure represented by (0 ≤ α ≤ 1). In the general formula, A and B represent the elements located at the A site and B site, respectively. (2-1) Regarding components having a perovskite structure For compounds having a perovskite structure, in the case of a stoichiometric composition, α, which represents the amount deviating from the stoichiometric composition, is 0, and the compound is represented by the general formula ABO3. For compounds having a perovskite structure represented by the above general formula, α may be greater than 0 and less than or equal to 1. In other words, for compounds having a perovskite structure represented by the above general formula, oxygen may be deficient in a proportion greater than the stoichiometric composition.

[0034] Compounds having a perovskite structure include barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), magnesium titanate (MgTiO3), and Ba, which form a perovskite-type structure. 1-x-y Ca x Sr y Ti 1-z Zr z One or more types selected from O3 (0≦x≦1, 0≦y≦1, 0≦z≦1), etc., can be used.

[0035] Ba 1-x-y Ca x Sr y Ti 1-z Zr z O3 is, for example, barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, and barium calcium titanate zirconate. The compound having a perovskite structure may contain oxygen deficiency regardless of the type of material.

[0036] The dielectric layer 11 is particularly excellent in dielectric properties, and thus preferably contains barium titanate as the compound having a perovskite structure, may contain barium titanate as a main component, or may be composed solely of barium titanate. Barium titanate is excellent in dielectric properties, such as an extremely high dielectric constant and low dielectric loss. Therefore, when the dielectric layer 11 contains barium titanate as the compound having a perovskite structure, the capacitance of the multilayer ceramic capacitor 100 can be increased. As used herein, "contained as a main component" means that the component is contained in the largest proportion by the amount of substance among the contained components.

[0037] Further, in the dielectric layer 11, the compound having a perovskite structure may be contained as a main component. The dielectric layer 11 may contain, for example, 50 mol% or more, or 90 mol% or more of the compound having a perovskite structure. (Additive Compound) The dielectric layer 11 can also contain an additive compound as an optional component.

[0038] The additive compounds that the dielectric layer 11 can contain are not particularly limited, but examples include oxides, carbonates, or nitrides containing one or more elements selected from zirconium (Zr), magnesium (Mg), molybdenum (Mo), vanadium (V), chromium (Cr), and rare earth elements; or oxides, carbonates, or nitrides containing one or more elements selected from cobalt (Co), nickel (Ni), copper (Cu), lithium (Li), boron (B), sodium (Na), potassium (K), calcium (Ca), manganese (Mn), molybdenum (Mo), silicon (Si), and aluminum (Al); or glass containing one or more elements selected from cobalt, nickel, copper, lithium, boron, sodium, potassium, calcium, magnesium, manganese, molybdenum, silicon, and aluminum.

[0039] The rare earth elements are not particularly limited, and one or more selected from scandium (Sc), cerium (Ce), neodymium (Nd), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb) may be used. (2-2) Regarding the thickness of the dielectric layer The thickness of the dielectric layer 11 is not particularly limited. From the viewpoint of miniaturizing the multilayer ceramic capacitor 100 while increasing the number of layers to increase capacitance, the thickness of the dielectric layer 11 may be, for example, 1.0 μm or less, 0.8 μm or less, 0.5 μm or less, or 0.4 μm or less.

[0040] The minimum thickness of the dielectric layer 11 is not particularly limited, but from the viewpoint of improving productivity and yield, it can be set to a minimum of 2 to 4 times the average diameter of the dielectric material particles (ceramic crystal particles) used. For example, if the average diameter of the dielectric material particles used is 0.1 μm, the minimum thickness of the dielectric layer 11 can be 0.2 μm or more and 0.4 μm or less, and the thickness of the dielectric layer 11 may be, for example, 0.2 μm or more, or 0.4 μm or more.

[0041] The average diameter of dielectric material particles can be determined by measuring the particle size of each dielectric material particle in a cross-section of the multilayer ceramic capacitor 100 that includes a first axis equal to the stacking direction, and taking the average of these measurements. Optical microscopes, microscopes, scanning electron microscopes (SEMs), etc., can be used as appropriate to measure the particle size of dielectric material particles. The particle size of dielectric material particles can be defined as the Heywood diameter (the diameter of a circle with an area equal to the area of ​​the dielectric material particle being evaluated) at the observed cross-section. The average diameter, which is the average value of the dielectric material particle size, can be the arithmetic mean of the particle sizes of 50 to 200 arbitrarily selected dielectric material particles. In this specification, unless otherwise specified, "average value" refers to the arithmetic mean.

[0042] When evaluating the thickness of the dielectric layer 11, the evaluation is performed in a cross-section that includes a first axis equal to the stacking direction. For example, it is preferable to evaluate in a cross-section that further includes a second axis set perpendicular to the stacking direction, or a cross-section that further includes a third axis set perpendicular to both the stacking direction and the second axis, due to the ease of polishing and measurement. In the former case, the multilayer ceramic capacitor 100 is polished in the third axis direction, and in the latter case, in the second axis direction. Five layers are selected from the central part, upper end, and lower end of the exposed dielectric layer 11 in the first axis direction. If the number of dielectric layers 11 is even, six layers are selected from the central part. Then, the thickness of each selected dielectric layer is measured at three locations: the central part, the left end, and the right end, and the average of the measured thicknesses is taken as the thickness of each dielectric layer 11. Furthermore, the average of the thicknesses of all selected and evaluated dielectric layers 11 can be taken as the thickness of the dielectric layer 11 in the multilayer ceramic capacitor 100.

[0043] In the examples shown in Figures 1 and 2, the first axis, which is the stacking direction, is the Z-axis direction. Therefore, the multilayer ceramic capacitor 100 is polished along the third axis, the Y-axis, to expose the XZ plane where the dielectric layer 11 and the internal electrode layer 12 are stacked.

[0044] In this case, five dielectric layers 11 located in the center along the first axis (Z axis) of the exposed XZ plane are selected, and five dielectric layers 11 each are selected at the upper and lower ends along the first axis (Z axis). If the number of dielectric layers 11 is even, six layers may be selected for the central part. In this case, the dielectric layers 11 to be selected are selected from within the capacitance section 14.

[0045] Then, for each of the selected dielectric layers 11, the thickness is measured at three points along the second axis, the X-axis, at distances of 1 / 4, 1 / 2, and 3 / 4 of the length of the dielectric layer 11 along the X-axis from the edge, and the average value of these measurements is taken as the thickness of the dielectric layer 11. By the same procedure, the thickness of all the selected dielectric layers 11 is measured, and the average value of the thicknesses of all the selected and evaluated dielectric layers 11 can be taken as the thickness of the dielectric layers 11 in the evaluated multilayer ceramic capacitor 100. (3) Regarding the internal electrode layer (3-1) Components contained in the internal electrode layer The internal electrode layer 12 can contain base metal elements as its main component.

[0046] The internal electrode layer 12 may contain components used in the internal electrode layer of a multilayer ceramic capacitor. In particular, the internal electrode layer 12 may mainly consist of a base metal such as nickel (Ni), tin (Sn), or tungsten (W), or an alloy containing one or more selected from the group of base metals, that is, it may contain the largest amount in terms of molar volume.

[0047] Because it offers excellent electrical properties and reduces costs, the internal electrode layer 12 may contain nickel as a base metal element, or it may contain nickel as the main component.

[0048] The main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same or different. For example, the main components of both the first internal electrode layer 12a and the second internal electrode layer 12b may be the same, namely nickel. (3-2) Regarding the thickness of the internal electrode layer The thickness of the internal electrode layer 12 is not particularly limited, but from the viewpoint of miniaturizing the multilayer ceramic capacitor 100 while increasing the number of layers to increase capacitance, it is preferably 0.8 μm or less, and more preferably 0.6 μm or less.

[0049] The lower limit of the thickness of the internal electrode layer 12 is not particularly limited, but for example, when it is formed by printing a metal conductive paste using a printing method such as screen printing or gravure printing, it can be 0.4 μm or more. For example, when it is formed by a thin-film process such as sputtering or vapor deposition, it can be thinner than that of the printing method, 0.1 μm or more.

[0050] When evaluating the thickness of the internal electrode layer 12, the evaluation is performed in a cross-section that includes a first axis equal to the stacking direction, similar to the evaluation of the thickness of the dielectric layer 11. For example, it is preferable to evaluate in a cross-section that further includes a second axis set perpendicular to the stacking direction, or a cross-section that further includes a third axis set perpendicular to both the stacking direction and the second axis, due to the ease of polishing and measurement.

[0051] Five layers are selected from the central part, upper end, and lower end of the exposed internal electrode layer 12 in the first axial direction. If the number of layers in the internal electrode layer 12 is even, six layers are selected from the central part. Then, the thickness of each selected internal electrode layer 12 is measured at three locations: the central part, the left end, and the right end, and the average of the measured thicknesses is taken as the thickness of each internal electrode layer 12. Furthermore, the average of the thicknesses of all the selected and evaluated internal electrode layers 12 can be taken as the thickness of the internal electrode layer 12 in the multilayer ceramic capacitor 100.

[0052] In the examples shown in Figures 1 and 2, the first axis, which is the stacking direction, is the Z-axis direction. Therefore, the multilayer ceramic capacitor 100 is polished along the third axis, the Y-axis, to expose the XZ plane where the dielectric layer 11 and the internal electrode layer 12 are stacked.

[0053] In this case, of the exposed XZ plane, five internal electrode layers 12 located in the center along the first axis (Z axis) are selected, and five internal electrode layers 12 located at the upper and lower ends along the first axis (Z axis) are selected. If the number of internal electrode layers 12 is even, six layers may be selected for the central part. In this case, the selected internal electrode layers 12 are selected from within the capacitance section 14.

[0054] Then, for each selected internal electrode layer 12, the thickness is measured at three points along the second axis, the X-axis, at distances of 1 / 4, 1 / 2, and 3 / 4 of the length of the internal electrode layer 12 along the X-axis from the edge, and the average value of these measurements is taken as the thickness of the internal electrode layer 12. By the same procedure, the thickness of all selected internal electrode layers 12 is measured, and the average value of the thicknesses of all selected and evaluated internal electrode layers 12 can be taken as the thickness of the internal electrode layers 12 in the evaluated multilayer ceramic capacitor 100. (4) End margin (4-1) Regarding the secondary phase As shown in Figure 4, the end margin 15 may include a secondary phase 41 that penetrates the internal electrode layer 12. Figure 4 corresponds to an enlarged view of region C in Figure 2 and is a partial enlarged view of the end margin 15. As shown in Figure 4, even though the internal electrode layer 12 is partially penetrated by the secondary phase 41, the electrical continuity between the internal and external electrodes is ensured overall because the secondary phase 41 has a non-penetrating portion in the depth on the Y-axis side, which is the third axis.

[0055] The inventors of the present invention investigated multilayer ceramic electronic components that have a low rate of crack occurrence in the end margin of the base body 10 during external electrode formation. As a result, they found that the end margin 15 includes a secondary phase 41 that penetrates the internal electrode layer 12, thereby reducing the occurrence of cracks in the end margin during external electrode formation, and thus completed the present invention.

[0056] In this specification, a low rate of crack occurrence in the end margin of the substrate during external electrode formation means that the crack occurrence rate of the end margin, as explained in the evaluation method of the examples described later, is smaller than that of Comparative Example 1, which is a conventional example. In other words, it means that the crack occurrence rate of the end margin is less than 4.50%.

[0057] The secondary phase 41 has a composition different from that of the dielectric material mainly contained in the end margin 15. The secondary phase 41 may be, for example, an additive compound added along with the dielectric material and the material of the internal electrode layer, which are the raw materials, during the firing of the end margin 15, or a reaction product of the additive compound and ceramic particles.

[0058] The secondary phase 41 may contain, for example, copper (Cu). By including copper in the secondary phase 41, mutual diffusion between the components contained in the external electrode and the base metal elements and other components contained in the internal electrode layer 12 can be reduced when forming the external electrode.

[0059] The secondary phase 41 may contain one or more elements selected from silicon (Si), lithium (Li), and boron (B) in addition to copper. The secondary phase 41 may further contain aluminum (Al).

[0060] The inclusion of the secondary phase 41 in the end margin 15 allows the secondary phase 41 to fill the voids in the dielectric layer 11 and the internal electrode layer 12 of the end margin 15, thereby increasing the mechanical strength of the end margin 15. Filling here includes cases where the secondary phase fills voids that would have otherwise been present if the secondary phase were not present. Furthermore, the inclusion of the secondary phase 41 penetrating the internal electrode layer 12 in the end margin 15 can increase the adhesion strength between the internal electrode layer 12 and the dielectric layer 11, for example, through an anchoring effect, and from this perspective as well, the mechanical strength of the end margin 15 can be increased.

[0061] Furthermore, the solid solution of copper (Cu) in the secondary phase 41 prevents alloying due to mutual diffusion between the main metal component contained in the external electrode and the base metal element component contained in the internal electrode layer 12. This prevents volume expansion associated with alloying, which causes cracks, thus reducing the occurrence of cracks in the end margin. The end margin 15 also enhances the moisture resistance of the multilayer ceramic capacitor while preventing cracks from forming in the base body 10 and causing short circuits during external electrode formation. Therefore, increasing the mechanical strength of the end margin 15 reduces the occurrence of cracks in the end margin 15 of the base body 10 during external electrode formation.

[0062] The secondary phase 41 that penetrates the internal electrode layer 12 means that the secondary phase 41 is arranged to be in contact with the first dielectric layer 11a and the second dielectric layer 11b, which have the internal electrode layer 12 in between.

[0063] The end margin 15 may further include a secondary phase 41a that does not penetrate the internal electrode layer 12, i.e., is disposed between the internal electrode layers 12, in addition to the secondary phase 41 that penetrates the internal electrode layer 12.

[0064] The presence of a secondary phase penetrating the internal electrode layer 12 reduces the occurrence of cracks in the end margin 15. For this reason, the content ratio of the secondary phase 41 is not particularly limited. Preferably, for example, the end margin 15 may contain an average of 1 or more secondary phases penetrating the internal electrode layer 12 per 10 internal electrode layers 12 along the first axis, the Z-axis, which may be 2 or more, 3 or more, or 4 or more. By setting the average number of secondary phases penetrating the internal electrode layer 12 per 10 internal electrode layers 12 along the first axis, the Z-axis, of the end margin 15 to 1 or more, the occurrence rate of cracks in the end margin during external electrode formation can be particularly reduced. Furthermore, as the average number of secondary phases penetrating the internal electrode layer 12 increases, the occurrence rate of cracks in the end margin during external electrode formation can be further reduced.

[0065] There is no particular upper limit to the average number of secondary phases penetrating the internal electrode layers 12 included per 10 internal electrode layers 12 along the Z-axis, which is the first axis of the end margin 15. However, placing an excessive number of secondary phases may reduce productivity. For this reason, the average number of secondary phases penetrating the internal electrode layers 12 included per 10 internal electrode layers 12 along the Z-axis, which is the first axis of the end margin 15 may be 20 or less, 15 or less, or 10 or less. (4-2) Regarding the thickness of the end margin In recent years, there has been a demand for improved capacitance in multilayer ceramic electronic components, and consequently, a demand for reducing the thickness of the end margin 15.

[0066] However, reducing the thickness of the end margin 15 resulted in a decrease in the mechanical strength of the multilayer ceramic electronic component, and increased the likelihood of cracks occurring in the end margin of the base material during external electrode formation.

[0067] In contrast, in the multilayer ceramic electronic component of this embodiment, the mechanical strength of the multilayer ceramic electronic component can be increased by including a predetermined secondary phase 41 in the end margin 15. Since this effect is particularly pronounced when the thickness of the end margin 15 is reduced, it is preferable that the thickness of the end margin 15 is reduced in the multilayer ceramic electronic component of this embodiment. The thickness T15 of the end margin 15 may be less than 50 μm, 40 μm or less, or 30 μm or less.

[0068] The lower limit of the thickness T15 of the end margin 15 is not particularly limited, but may be, for example, 10 μm or more, or 15 μm or more.

[0069] The thickness of the end margin 15 can be evaluated in a cross-section including the first axis and the second axis, which are the stacking directions.

[0070] For each of the first internal electrode layer 12a and the second internal electrode layer 12b in the exposed cross-section, five layers are selected from the central part in the first axial direction, as well as from the upper and lower ends. If the number of layers in the first internal electrode layer 12a and the second internal electrode layer 12b is even, six layers are selected from the central part.

[0071] Then, in the case of the first end margin 15a, the distance between the edge of the selected second internal electrode layer 12b and the first side surface 10a is measured as the thickness T15a of the first end margin 15a. Similarly, in the case of the second end margin 15b, the distance between the edge of the selected first internal electrode layer 12a and the second side surface 10b is measured as the thickness of the second end margin 15b. Furthermore, the distance between the edge of each selected and evaluated internal electrode layer 12 and the first side surface 10a or the second side surface 10b, which is the outer surface of the end margin 15, is measured. The distance between the edge of the internal electrode layer 12 and the outer surface of the end margin 15 represents the shortest distance between the edge of the internal electrode layer 12 and the outer surface of the end margin 15.

[0072] In the case of the first end margin 15a, the average value of the distance between the measured edge of the second internal electrode layer 12b and the first side surface 10a can be used as the thickness of the first end margin 15a in the multilayer ceramic capacitor 100.

[0073] In the case of the second end margin 15b, the average value of the measured distance between the end of the first internal electrode layer 12a and the second side surface 10b can be used as the thickness of the second end margin 15b in the multilayer ceramic capacitor 100.

[0074] It is preferable that the measured and calculated thicknesses of the first end margin 15a and the second end margin 15b satisfy the above range. The thicknesses of the first end margin 15a and the second end margin 15b may be the same or different.

[0075] In the examples shown in Figures 1 and 2, the first axis, which is the stacking direction, is the Z-axis direction. Therefore, the multilayer ceramic capacitor 100 is polished along the third axis, the Y-axis, to expose the XZ plane where the dielectric layer 11 and the internal electrode layer 12 are stacked.

[0076] In this case, of the exposed XZ plane, five layers of the second internal electrode layer 12b located in the center along the first axis (Z axis) are selected, and five layers each of the second internal electrode layer 12b located at the upper and lower ends along the first axis (Z axis) are selected. If the number of layers of the second internal electrode layer 12b is even, six layers may be selected for the central part.

[0077] Then, for each selected second internal electrode layer 12b, the distance between the edge of the second internal electrode layer 12b and the first side surface 10a, which is the outer surface of the first end margin 15a, is measured along the second axis, the X-axis. The same procedure is used to measure the distance between the edge of each selected second internal electrode layer 12b and the first side surface 10a, which is the outer surface of the first end margin 15a, and the average value of these distances can be used as the thickness T15a of the first end margin 15a.

[0078] The thickness of the second end margin 15b can also be measured and calculated using the same procedure as the first end margin 15a, except that the second internal electrode layer 12b is replaced with the first internal electrode layer 12a, and the first side surface 10a is replaced with the second side surface 10b.

[0079] [Manufacturing method for multilayer ceramic capacitors] Next, the manufacturing method of the multilayer ceramic capacitor 100 will be described. Figure 5 is a flowchart 50 illustrating the manufacturing method of the multilayer ceramic capacitor 100. Figure 6 is a diagram illustrating the manufacturing method of the multilayer ceramic capacitor 100.

[0080] The manufacturing method for the multilayer ceramic capacitor of this embodiment may include a dielectric green sheet formation step, an internal electrode layer pattern formation step, and a firing step. The manufacturing method for the multilayer ceramic capacitor of this embodiment will be described below, including any other steps besides those mentioned above. (1) Raw material powder preparation process (S1) In the raw material powder preparation process, raw material powder for forming the dielectric layer 11 can be prepared.

[0081] The dielectric layer 11 of the multilayer ceramic capacitor 100 manufactured by the manufacturing method of the multilayer ceramic capacitor of this embodiment is of the general formula ABO 3-α It can contain dielectric materials that are compounds having a perovskite structure represented by (0≦α≦1). General formula ABO 3-α Since dielectric materials, which are compounds having a perovskite structure represented by (0 ≤ α ≤ 1), have already been explained, we will omit further explanation.

[0082] The dielectric material contained in the dielectric layer 11 contains A-site elements (element A) and B-site elements (element B), which are usually ABO. 3-α The dielectric layer 11 is contained in the form of a sintered body of particles with (0≦α≦1). For example, barium titanate is a tetragonal compound having a perovskite structure and exhibiting a high dielectric constant. Barium titanate can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been conventionally known for synthesizing dielectric materials that can be used as the main component of the dielectric layer 11, such as the solid-phase method, the sol-gel method, and the hydrothermal method. In this embodiment, any of these can be employed.

[0083] In the raw material powder preparation process, predetermined additive compounds can be added to the dielectric material according to the purpose. These additive compounds also serve as raw materials for the secondary phase. Therefore, additive compounds corresponding to the desired composition of the secondary phase can be added to the dielectric material. Since the secondary phase only needs to be contained in the end margin 15, the additive compound corresponding to the desired composition of the secondary phase may be added only to the raw material powder used in the end margin 15 portion. The secondary phase may be contained in dielectric layers other than the end margin, but if it is contained in the capacitance portion, it can cause deterioration of electrical properties such as dielectric constant, so it is better to have a small amount of secondary phase in the capacitance portion. For this reason, when comparing the amount of secondary phase in the capacitance portion and the end margin, the amount of secondary phase in the end margin may be larger. When comparing the amount of secondary phase in the capacitance portion and the end margin, the amount of secondary phase contained in each portion can be compared by the sum of the areas of the secondary phase contained in the capacitance portion and the end margin in a single cross-section including the first axis and the second axis. That is, the sum of the areas of the secondary phase contained in the end margin may be larger than the area of ​​the secondary phase contained in the capacitance portion.

[0084] Examples of additive compounds include oxides, carbonates, or nitrides containing one or more elements selected from zirconium (Zr), magnesium (Mg), molybdenum (Mo), vanadium (V), chromium (Cr), and rare earth elements; oxides, carbonates, or nitrides containing one or more elements selected from cobalt (Co), nickel (Ni), copper (Cu), lithium (Li), boron (B), sodium (Na), potassium (K), calcium (Ca), manganese (Mn), molybdenum (Mo), silicon (Si), and aluminum (Al); and glasses containing one or more elements selected from cobalt, nickel, copper, lithium, boron, sodium, potassium, calcium, magnesium, manganese, molybdenum, silicon, and aluminum.

[0085] Examples of the rare earth elements mentioned above include one or more selected from scandium (Sc), cerium (Ce), neodymium (Nd), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb).

[0086] The raw material powder can be prepared, for example, by wet-mixing an additive compound with a dielectric material, followed by drying and pulverization. The raw material powder will also be referred to as the dielectric pattern material in the following description. For example, the raw material powder obtained as described above may be subjected to pulverization to adjust the particle size, or the particle size may be adjusted by combining this with a classification process as needed. Through the above steps, a raw material powder that is a ceramic material is obtained. (2) Dielectric green sheet formation process (S2) The dielectric green sheet formation process can be carried out by wet mixing the raw material powder obtained in the raw material powder preparation process with a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer to form a slurry. Alternatively, the binder may be added at the same time as mixing the raw material powder in the raw material powder preparation process (S1), and the slurry may be formed by wet mixing.

[0087] In the dielectric green sheet formation process, the obtained slurry can be used to coat a substrate with the slurry, for example, by a die coater or doctor blade method, and then dried to form a dielectric green sheet 61. For example, polyethylene terephthalate (PET) film can be used as the substrate. A diagram illustrating the dielectric green sheet formation process has been omitted.

[0088] Therefore, in the dielectric green sheet formation process (S2), the general formula ABO 3-α A dielectric green sheet can be formed containing a compound having a perovskite structure represented by (0≦α≦1) or an additive compound. In addition to the dielectric with a perovskite structure represented by the above general formula, the dielectric green sheet can also contain the additive compound as described above. (3) Internal electrode layer formation process (S3) The first internal electrode layer 12a and the second internal electrode layer 12b may be primarily composed of one or more base metals selected from nickel (Ni), tin (Sn), tungsten (W), and alloys containing these metals.

[0089] The main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same or different. For example, the main components of both the first internal electrode layer 12a and the second internal electrode layer 12b may be the same, namely nickel.

[0090] A metal conductive paste for forming the precursors of the first internal electrode layer 12a and the second internal electrode layer 12b can be prepared by kneading a selected main component, an organic binder, and a solvent.

[0091] In the internal electrode layer formation process, as illustrated in Figure 6(A), a metal conductive paste for forming the internal electrode layer, containing an organic binder, can be printed onto the surface of the dielectric green sheet 61 by screen printing, gravure printing, or the like. Examples of organic binders include ethyl cellulose (EC) and polyvinyl butyral (PVB) resin. This arranges a first internal electrode layer pattern 62a for the first internal electrode layer 12a or a second internal electrode layer pattern 62b for the second internal electrode layer 12b on the surface of the dielectric green sheet 61. Various auxiliary agents, such as dispersants, and ceramic particles as co-materials can also be added to the metal conductive paste. The main component of the ceramic particles is not particularly limited, but it is preferable that it be the same as the main ceramic component of the dielectric layer 11. When ceramic particles are added as co-materials, they can be added during the mixing of the metal conductive paste. The method for forming the internal electrode layer is not limited to printing; plating, vacuum deposition, sputtering, and CVD methods may also be used.

[0092] Alternatively, a dielectric pattern paste for an inverse pattern dielectric layer can be obtained by adding a binder such as ethyl cellulose and an organic solvent such as terpineol to the dielectric pattern material obtained in the raw material powder preparation process and kneading it in a roll mill. Then, as illustrated in Figure 6(A), the dielectric pattern 63 may be arranged on the dielectric green sheet 61 by printing the dielectric pattern paste in the peripheral area where the internal electrode layer pattern is not printed, thereby filling the step difference with the internal electrode layer pattern. The dielectric pattern 63 can also be described as an inverse pattern dielectric layer, and the process of forming the above inverse pattern dielectric layer may be described as an inverse pattern dielectric layer formation process. A portion of the dielectric pattern 63 becomes the end margin 15. For this reason, components that will be the raw materials for the secondary phase contained in the end margin 15 of the dielectric pattern 63 may be added. The dielectric pattern 63 may be formed by separating the portion that becomes the end margin 15 from the other portion. In this case, the composition of the other portion may be the same as or different from the composition of the portion that becomes the end margin 15. By varying the composition, it is easy to obtain an amount of secondary phase suitable for the end margin 15. The dielectric pattern 63 may contain, for example, the additive compound described in the section on the dielectric layer material. The inclusion of the additive compound in the dielectric pattern 63 allows for the deposition of a secondary phase within the end margin 15 during or after the firing process, as described later. Alternatively, particles corresponding to the secondary phase can be added to the dielectric pattern 63.

[0093] A dielectric green sheet 61 on which an internal electrode layer pattern and a dielectric pattern 63 are printed is referred to as a laminated unit. (4) Lamination process (S4) In the lamination process, as illustrated in Figure 6(B), the lamination units can be stacked such that the internal electrode layers and dielectric layers are staggered, and the edges of the internal electrode layers are alternately exposed on both ends of the dielectric layer in the longitudinal direction, alternately leading out to a pair of external electrodes. Specifically, a dielectric green sheet 61 printed with a first internal electrode layer pattern 62a and a dielectric pattern 63 is stacked in sequence with a dielectric green sheet 61 printed with a second internal electrode layer pattern 62b and a dielectric pattern 63. For example, the number of layers in the lamination unit can be 100 to 500. (5) Crimping process (S5) In the heat-sealing process, a predetermined number of cover sheets, for example, 2 to 10 layers, can be heat-sealed to the top and bottom of the laminated body in which the laminated units are stacked. (6) Singulation process (S6) In the individualization process, the crimped body is separated into individual pieces, and a laminate of individual pieces can be obtained. Existing methods such as dicing with a dicer or laser cutting can be used as appropriate for individualization. (7) Firing process (S7) In the firing process, the individual laminated pieces can be degreased and then fired. The degreasing and firing processes may be performed consecutively or separately. The conditions for degreasing and firing are not particularly limited. For example, degreasing may be performed in a nitrogen atmosphere at a temperature between 250°C and 500°C.

[0094] For firing, for example, if the oxygen partial pressure is 10 -12 atm over 10 -8 The firing may be carried out in a weakly oxidizing atmosphere or a reducing atmosphere with a temperature range of 1100°C to 1350°C, below atm, for 5 minutes to 10 hours. The oxygen partial pressure is preferably 10 -12 atm over 10 -10 It may also be set to atm or less.

[0095] When creating a reducing atmosphere, one or more reducing gases selected from hydrogen and carbon monoxide can be used. The reducing gas may also be an inert gas, such as nitrogen, or a mixture with a noble gas. Examples of noble gases include helium and argon.

[0096] The firing temperature range may preferably be 1150°C to 1350°C. The firing time may preferably be 5 minutes to less than 15 minutes. (8) External electrode formation process (S8) In the external electrode formation process, a metal conductive paste for forming an external electrode layer, containing a base metal such as nickel as a main component, a metal such as copper, and an organic binder, is formed by screen printing, dipping, etc., and then baked to form the external electrode. The method of forming the external electrode is not limited to printing or dipping; plating, vacuum deposition, sputtering, or CVD methods may also be used. Alternatively, the external electrode may be formed by printing or coating a conductive resin paste by screen printing, dipping, etc., and then curing the resin. If necessary, layers of copper, nickel, or tin may be formed by plating or other treatments. This allows for the formation of the first external electrode 20a and the second external electrode 20b. Through the above process, a multilayer ceramic capacitor 100 can be manufactured.

[0097] The above process is merely an example, and the manufacturing method of the multilayer ceramic capacitor of this embodiment is not limited to the above configuration. For example, the base layer for the external electrodes can be provided on the surface of the fragmented laminate, and the base layer can be formed by firing the ceramic simultaneously with firing the base layer for the external electrodes. In this case, in the external electrode formation process after firing, the external electrodes are formed by forming layers of copper, nickel, or tin on top of this base layer through a plating process.

[0098] [Other embodiments] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims.

[0099] For example, although the above embodiment is applied to a multilayer ceramic capacitor with two terminal electrodes, it may also be applied to a multilayer ceramic capacitor with three or more terminals. [Examples]

[0100] The present invention will be described with specific examples below, but it is not limited to these examples. (1) Evaluation method (1-1) Presence or absence of a secondary phase penetrating the internal electrode layer For each example and comparative example, a cross-section of the multilayer ceramic capacitor fabricated along line AA in Figure 1 was exposed, and the end margin 15 of the exposed cross-section was observed using SEM to observe a secondary phase different from the dielectric material. If a secondary phase was found, the presence or absence of a secondary phase penetrating the internal electrode layer was checked, and if confirmed, it was marked as "present". If no secondary phase was confirmed in the end margin 15, or if no secondary phase penetrating the internal electrode layer was confirmed, it was marked as "absent". (1-2) Composition of the secondary phase If the evaluation of "(1-1) Presence or absence of a secondary phase penetrating the internal electrode layer" was evaluated as "Present," the composition of the secondary phase was analyzed using EDX (Energy Dispersive X-ray Spectroscopy).

[0101] Based on the evaluation results, if the secondary phase within the observation field contained a secondary phase in which copper was detected, the "Presence or Absence of Copper Solid Solution in Secondary Phase" column was marked "Yes." If the observation field did not contain a secondary phase, or if copper was not detected in the composition of the secondary phase, it was marked "No." (1-3) The average number of secondary phases penetrating the internal electrode layers contained in each of the 10 internal electrode layers along the first axis. If the evaluation of "(1-1) Presence or absence of secondary phases penetrating the internal electrode layers" was evaluated as "Present," the number of secondary phases penetrating the internal electrode layers contained in each of the 10 internal electrode layers 12 along the first axis was counted, and the average was calculated.

[0102] Specifically, from the cross-sections observed using SEM, six evaluation regions were selected within the end margin 15, containing 10 continuous internal electrode layers 12 along the first axis, ensuring no overlap. The number of secondary phases penetrating the internal electrode layers was counted in each evaluation region. The arithmetic mean of the number of secondary phases measured in each evaluation region was then taken as the average number of secondary phases penetrating the internal electrode layers contained per 10 internal electrode layers along the first axis in the multilayer ceramic capacitor. (1-4) Crack occurrence rate and determination at the end margin In each example and comparative example, 400 multilayer ceramic capacitors fabricated under the same conditions had one cross-section exposed along line AA in Figure 1. The exposed cross-section near the external electrode, i.e., the end margin, was observed using an optical microscope or SEM to evaluate whether or not cracks had formed.

[0103] Out of 400 multilayer ceramic capacitors, the percentage of those in which cracks were observed was determined, and this was defined as the crack occurrence rate at the end margin.

[0104] A crack occurrence rate in the end margin was judged as ◎ if it was between 0% and 0.5%, ○ if it was between 0.5% and 2%, △ if it was between 2% and less than 4.50% (i.e., between 2% and 4.50%), and × if it was greater than or equal to the conventional example, Comparative Example 1.

[0105] A rating of ◎ indicates the greatest reduction in crack occurrence rate, while ratings of ○, △, and × indicate increasing crack occurrence rates in that order. ◎, ○, or △ indicate a multilayer ceramic capacitor with a lower end-margin crack occurrence rate than conventional capacitors. (2) Conditions for preparing the sample [Example 1] (2-1) Raw material powder preparation process A multilayer ceramic capacitor was manufactured according to the flowchart 50 shown in Figure 5.

[0106] Specifically, a slurry was obtained by wet mixing barium titanate powder with the additive compounds holmium oxide (Ho2O3), magnesium oxide (MgO), manganese carbonate (MnCO3), silicon dioxide (SiO2), polyvinyl butyral (PVB) resin, a solvent, a plasticizer, and a dispersant. (2-2) Dielectric Green Sheet Formation Process The obtained slurry was coated onto a base film, and the slurry coated onto the base film was dried to obtain a dielectric green sheet. (2-3) Internal electrode layer formation process Next, nickel powder, the main component metal element, was wet-mixed with a binder such as ethyl cellulose (EC) or polyvinyl butyral (PVB) resin, a solvent, and a plasticizer to obtain a metal conductive paste for forming the internal electrode layer. Then, the metal conductive paste was printed onto a portion of the surface of a dielectric green sheet to form an internal electrode layer pattern containing nickel, a base metal element, as the main component on each dielectric green sheet. (2-4) Reverse pattern dielectric layer formation process Next, copper oxide (Cu2O), silicon oxide (SiO2), aluminum oxide (Al2O3), calcium carbonate (CaCO3), and binders such as ethylcellulose, along with organic solvents such as terpineol, were added to the dielectric pattern material obtained in the raw material powder preparation step, and the mixture was kneaded in a roll mill. By kneading the above material, a dielectric pattern paste for the inverse pattern dielectric layer was obtained. Then, as illustrated in Figure 6(A), the dielectric pattern paste for the inverse pattern dielectric layer was printed on the dielectric green sheet 61 in the peripheral area where the internal electrode layer pattern was not printed, thereby arranging the dielectric pattern 63 and forming the inverse pattern dielectric layer.

[0107] A laminated unit was fabricated by the dielectric green sheet formation process, the internal electrode layer formation process, and the reverse pattern dielectric layer formation process described above. The obtained laminated unit comprises a dielectric green sheet, an internal electrode layer pattern formed on the surface of the dielectric green sheet, and a reverse pattern dielectric layer. (2-5) Lamination process Next, 500 stacking units were stacked to form a laminate. (2-6) Crimping process, individual piece formation process Then, after the laminate was compressed, it was separated into individual pieces to obtain chip-shaped green laminates. (2-7) Firing process Next, this chip-shaped green laminate was degreased in a nitrogen atmosphere at 500°C.

[0108] After degreasing, a metal conductive paste containing nickel-based metal fillers, a binder, and a solvent was applied to the green laminate from both ends to each side as a base layer, and then dried. Subsequently, the green laminate with the base layer for the external electrodes was placed in a firing furnace and fired.

[0109] During the firing process, the oxygen partial pressure is 1.0 × 10⁻⁶. -10 The material was kept at a reducing atmosphere of atm (atm) and a mixed atmosphere of hydrogen and nitrogen, and maintained at the firing temperature of 1220°C for 300 seconds. During the heating process, the supply rate of the green laminate and the oxygen partial pressure were adjusted to prevent abrupt changes in the firing atmosphere due to gases generated from the green laminate and to prevent cracking of the fired product. (2-8) External electrode formation process A first external electrode 20a and a second external electrode 20b were formed on the laminated body after firing by plating.

[0110] The resulting multilayer ceramic capacitor had a chip shape of 1.0 mm × 0.5 mm × 0.5 mm, a dielectric layer 11 thickness of 0.8 μm, an internal electrode layer 12 thickness of 0.6 μm, and 500 layers. The thicknesses of the dielectric layer 11 and the internal electrode layer 12 were evaluated using the procedure already described.

[0111] The obtained multilayer ceramic capacitors were evaluated as described above. The evaluation results are shown in Table 1. [Examples 2-8] In the reverse pattern dielectric layer formation process, the ratios of copper oxide (Cu2O), silicon oxide (SiO2), aluminum oxide (Al2O3), and calcium carbonate (CaCO3) added to the dielectric pattern material obtained in the raw material powder preparation process were the same as in Example 1, but the total amount was changed from that of Example 1, so that the average number of secondary phases penetrating the internal electrode layer was 2, 3, 4, 5, 6, 8, and 10. A binder such as ethyl cellulose and an organic solvent such as terpineol were added to these, and the mixture was kneaded in a roll mill to obtain a dielectric pattern paste for the reverse pattern layer. All other conditions were the same as in Example 1.

[0112] Except for the points mentioned above, multilayer ceramic capacitors were fabricated and evaluated using the same procedure as in Example 1. The evaluation results are shown in Table 1. [Examples 9 to 13] In the reverse pattern dielectric layer formation process, multilayer ceramic capacitors were manufactured under the same conditions and procedures as in Examples 1 to 8, except that the dielectric pattern material obtained in the raw material powder preparation process did not contain copper oxide (Cu2O). Specifically, the ratios of silicon dioxide (SiO2), aluminum oxide (Al2O3), and calcium carbonate (CaCO3) added to the dielectric pattern material obtained in the raw material powder preparation process were the same as in Example 1, excluding copper oxide (Cu2O), but the total amount was changed from Example 1, resulting in an amount such that the average number of secondary phases penetrating the internal electrode layer was 1, 2, 3, 4, and 5. A binder such as ethyl cellulose and an organic solvent such as terpineol were added to these, and the mixture was kneaded in a roll mill to obtain a dielectric pattern paste for the reverse pattern layer. All other conditions were the same as in Example 1.

[0113] Except for the points mentioned above, multilayer ceramic capacitors were fabricated and evaluated using the same procedure as in Example 1. The evaluation results are shown in Table 1. [Comparative Example 1] In the raw material powder preparation process, no additive compounds were added. Except for the above, a multilayer ceramic capacitor was fabricated and evaluated using the same procedure as in Example 1. The evaluation results are shown in Table 1.

[0114] [Table 1] According to Table 1, in Examples 1 to 13, where secondary phases penetrating the internal electrode layer were confirmed in the end margin, the crack occurrence rate in the end margin was improved compared to Comparative Example 1, where secondary phases penetrating the internal electrode layer were not confirmed. In particular, in Examples 2 to 8 and 10 to 13, where the average number of secondary phases penetrating the internal electrode layer was 2 or more, the crack occurrence rate in the end margin was 2% or less, confirming that multilayer ceramic capacitors with a low crack occurrence rate in the end margin during external electrode formation were obtained. In Examples 5 to 8 and 13, where the average number of secondary phases penetrating the internal electrode layer was 5 or more, the crack occurrence rate in the end margin was 0.5% or less, confirming that this was even more desirable.

[0115] When comparing examples with the same average number of secondary phases penetrating the internal electrode layer, it can be confirmed that the crack occurrence rate of the end margin in the example with copper solid solution to the secondary phase is lower than that of the example without copper solid solution to the secondary phase. Therefore, it was confirmed that copper solid solution to the secondary phase is effective. The comparison of the above examples refers to a comparison between Example 2 and Example 10, where the average number of secondary phases penetrating the internal electrode layer is approximately 2; Example 3 and Example 11, where the average number of secondary phases penetrating the internal electrode layer is approximately 3; Example 4 and Example 12, where the average number of secondary phases penetrating the internal electrode layer is approximately 4; and Example 5 and Example 13, where the average number of secondary phases penetrating the internal electrode layer is approximately 5.

[0116] The aspects of this disclosure are, for example, as follows:

[0117] <1> The device comprises a substrate including a capacitance section in which multiple layers of dielectric layers mainly composed of ceramic crystal particles and internal electrode layers are alternately stacked along a first axis, and a pair of external electrodes. The internal electrode layer is formed by alternately stacking a first internal electrode layer and a second internal electrode layer in the capacitance portion, and each is brought out to the outer surface of the base body. The pair of external electrodes are formed on the outer surface of the base body so as to be spaced apart from each other, so as to be electrically connected to the internal electrode layer of the base body. The substrate has an end margin that includes a first end margin that encloses only the first internal electrode layer and a second end margin that encloses only the second internal electrode layer between the capacitance portion and the external electrode. The end margin includes a secondary phase penetrating the internal electrode layer, in a multilayer ceramic electronic component.

[0118] <2> The secondary phase contains copper. <1> Multilayer ceramic electronic components as described above.

[0119] <3> The end margin is such that the average number of secondary phases penetrating the internal electrode layers is 2 or more per 10 internal electrode layers along the first axis. <1> or <2> Multilayer ceramic electronic components as described above.

[0120] <4> The dielectric layer contains elements A and B, and the general formula is ABO 3-α It is represented as (0≦α≦1) and contains a compound having a perovskite structure, The internal electrode layer contains base metal elements as its main component. <1> from <3> A multilayer ceramic electronic component as described in any of the following. [Explanation of Symbols]

[0121] 100 Multilayer Ceramic Capacitors 10 Base Body 10a First side 10b Second side 11 Dielectric layer 11a First dielectric layer 11b Second dielectric layer 12 Internal electrode layer 12a 1st internal electrode layer 12b Second internal electrode layer 13. Cover layer 14 Capacity part 15 End margin 15a First end margin 15b Second End Margin T15 Thickness T15a Thickness 16 Side margins 20a 1st external electrode 20b 2nd external electrode C area 41 Secondary phase 41a Secondary phase 50 Flowcharts S1 Raw material powder preparation process S2 Dielectric Green Sheet Formation Process S3 Internal electrode layer formation process S4 Lamination process S5 Crimping process S6 singulation process S7 Firing Process S8 External electrode formation process 61 Dielectric Green Sheet 62a First internal electrode layer pattern 62b Second internal electrode layer pattern

Claims

1. The device comprises a substrate including a capacitance section in which multiple layers of dielectric layers mainly composed of ceramic crystal particles and internal electrode layers are alternately stacked along a first axis, and a pair of external electrodes. The internal electrode layer is formed by alternately stacking a first internal electrode layer and a second internal electrode layer in the capacitance portion, and each is brought out to the outer surface of the base body. The pair of external electrodes are formed on the outer surface of the base body so as to be spaced apart from each other, so as to be electrically connected to the internal electrode layer of the base body. The substrate has an end margin that includes a first end margin that encloses only the first internal electrode layer and a second end margin that encloses only the second internal electrode layer between the capacitance portion and the external electrode. The end margin includes a secondary phase penetrating the internal electrode layer, in a multilayer ceramic electronic component.

2. The multilayer ceramic electronic component according to claim 1, wherein the secondary phase contains copper.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein the end margin is such that the average number of secondary phases penetrating the internal electrode layers is two or more per 10 internal electrode layers along the first axis.

4. The dielectric layer contains elements A and B, and the general formula is ABO ３－α It is represented as (0 ≤ α ≤ 1) and contains a compound having a perovskite structure, The multilayer ceramic electronic component according to claim 1 or claim 2, wherein the internal electrode layer contains a base metal element as a main component.

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