Multilayer ceramic electronic components

Abstract

We provide multilayer ceramic electronic components with excellent moisture resistance. [Solution] The multilayer ceramic capacitor 100 has a base body in which dielectric layers and internal electrode layers are alternately stacked in multiple layers along the Z axis, the internal electrode layers are drawn out from both ends along the X axis perpendicular to the Z axis, and the base body has side margins 16 at both ends along the Y axis perpendicular to the Z axis and the X axis, and in a cross-sectional observation image including the Z axis, the side margins contain secondary phase particles with a surface length of 2 μm or more, the average number of dielectric material particles in contact per 1 μm of the surface of the secondary phase particles is 0.5 or more and 5 or less, the average particle size of the dielectric material particles contained in the side margins is 0.8 μm or more and 1.2 μm or less, the average major axis diameter of the secondary phase particles is 2 μm or more and 4 μm or less, and the porosity of the side margins is 2% or less.

Description

[Technical Field]

[0001] This disclosure relates to multilayer ceramic electronic components. [Background technology]

[0002] Multilayer ceramic electronic components have a structure in which dielectric layers and internal electrode layers are alternately stacked. Examples of multilayer ceramic electronic components include multilayer ceramic capacitors (MLCCs).

[0003] Multilayer ceramic electronic components, such as multilayer ceramic capacitors, are used in various electronic devices, including high-frequency communication systems like mobile phones and in-vehicle electronic control devices. Therefore, there is a demand for various performance improvements in multilayer ceramic electronic components, and these have been studied for some time (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 8-45768 [Overview of the project] [Problems that the invention aims to solve]

[0005] As mentioned above, multilayer ceramic electronic components are used in various electronic devices, and there is a demand for various performance improvements. Multilayer ceramic electronic components can sometimes fail due to the effects of humidity in the air, depending on the installation environment. For this reason, there is a growing need for multilayer ceramic electronic components with excellent moisture resistance.

[0006] This disclosure aims to provide multilayer ceramic electronic components with excellent moisture resistance. [Means for solving the problem]

[0007] The multilayer ceramic electronic components disclosed herein are The substrate has multiple layers of dielectric layers and internal electrode layers stacked alternately along the first axis. The internal electrode layer is drawn outwards from both ends along a second axis perpendicular to the first axis, The aforementioned body has side margins at both ends along a third axis perpendicular to the first and second axes, In the cross-sectional observation image including the first axis, the side margin includes secondary phase particles with a surface length of 2 μm or more, and the average number of dielectric material particles in contact with the surface of the secondary phase particles per 1 μm is 0.5 or more and 5 or less. [Effects of the Invention]

[0008] According to this disclosure, it is possible to provide multilayer ceramic electronic components with excellent moisture resistance. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a partial cross-sectional perspective view illustrating a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 2] Figure 2 is a cross-sectional view illustrating an example of a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 3] Figure 3 is a cross-sectional view illustrating an example of a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 4] Figure 4 is a cross-sectional view illustrating the details of the side margin in a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 5] Figure 5 is a flowchart of a method for manufacturing a multilayer ceramic capacitor according to one aspect of the present disclosure. [Figure 6] Figure 6 is a diagram illustrating a method for manufacturing a multilayer ceramic capacitor according to one aspect of the present disclosure. [Modes for carrying out the invention]

[0010] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In the present specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to omit redundant descriptions. In addition, the drawings appropriately show an X-axis, a Y-axis, and a Z-axis that are orthogonal to each other. The X-axis, Y-axis, and Z-axis define a fixed coordinate system fixed with respect to a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component. The X-axis, Y-axis, and Z-axis can correspond to the length, width, and height of the multilayer ceramic capacitor, which is an example of the multilayer ceramic electronic component, when the outer shape thereof is a substantially rectangular parallelepiped. All of the drawings are schematically illustrated to explain the structure, and do not accurately depict sizes, scales, and the like. In particular, since it is difficult to accurately illustrate the number of internal electrode layers and dielectric layers due to space limitations on the page, the number of internal electrode layers and dielectric layers may be larger or smaller than the number of layers shown in the drawings.

[0011] Hereinafter, the multilayer ceramic electronic component of the present embodiment will be described using a multilayer ceramic capacitor which is an example of the multilayer ceramic electronic component.

[0012] [Multilayer Ceramic Electronic Component] (1) Structure of Multilayer Ceramic Electronic Component FIG. 1 is a partial cross-sectional perspective view illustrating a multilayer ceramic capacitor 100. FIG. 2 and FIG. 3 are cross-sectional views illustrating the multilayer ceramic capacitor. FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1. FIG. 3 is a cross-sectional view taken along line B-B in FIG. 1. As illustrated in FIG. 1 to FIG. 3, the multilayer ceramic capacitor 100 includes a base body 10 having a substantially rectangular parallelepiped shape. In the base body 10, two opposing surfaces on the surface thereof are referred to as an upper surface and a lower surface, and four surfaces connecting the upper surface and the lower surface are each referred to as side surfaces. Normally, when the multilayer ceramic capacitor is mounted on a circuit board, the surface on the board side is defined as the lower surface, but this is not necessarily a limitation. In the examples of FIG. 1 to FIG. 3, a first external electrode 20a and a second external electrode 20b are respectively provided on a first side surface 10a and a second side surface 10b (see FIG. 2), which are two opposing side surfaces of the base body 10. The first external electrode 20a extends from the first side surface 10a to four adjacent surfaces. The second external electrode 20b extends from the second side surface 10b to four adjacent surfaces. However, the first external electrode 20a and the second external electrode 20b are spaced apart from each other. The external electrodes are not limited to the two opposing side surfaces and may be provided on any surface of the base body 10 as long as it is the surface of the base body 10.

[0013] The lamination direction in which the dielectric layers 11 and the internal electrode layers 12 are laminated is a first axis. In FIG. 1 to FIG. 3, the first axis, which is the lamination direction of the dielectric layers 11 and the internal electrode layers 12, is the Z-axis, and is the direction in which the respective internal electrode layers face each other.

[0014] The axis perpendicular to the first axis that is the lamination direction is a second axis. In FIG. 1 to FIG. 3, the second axis, which is an axis perpendicular to the first axis that is the lamination direction, is the X-axis. The second axis extends along the length direction of the base body 10, and is an axis along the direction in which the first side surface 10a and the second side surface 10b of the base body 10 face each other, and along the direction in which the first external electrode 20a and the second external electrode 20b face each other.

[0015] The axis perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis is the third axis. The third axis is the axis along the width of the internal electrode layer 12. In Figures 1 to 3, the third axis, which is perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis, is the Y axis. The third axis is the axis along the direction in which the third side 10c and the fourth side 10d, which are two of the four sides of the base body 10 other than the first side 10a and the second side 10b, face each other (see Figure 3). The X axis, Y axis, and Z axis are orthogonal to each other.

[0016] The stacking direction is not limited to the Z direction, but can be any direction. For example, the first axis, which is the stacking direction, may be the X-axis in the X direction, or the Y-axis in the Y direction.

[0017] In this specification, for the purpose of describing general embodiments, figures illustrating a specific embodiment may be used. However, the coordinate system described in one embodiment should be interpreted and applied in general embodiments as a general coordinate system with the stacking direction as the first axis. For example, what is described as the X-axis, Y-axis, and Z-axis in Figures 1 to 3, which are used in a specific embodiment where the stacking direction coincides with the Z-axis, can be interpreted and applied in general embodiments as the second axis, third axis, and first axis.

[0018] The base body 10 has a structure in which dielectric layers 11 containing a ceramic material that functions as a dielectric as its main component and internal electrode layers 12 are alternately stacked. The dielectric layer 11 may contain particles of the dielectric material as the ceramic material, and may also contain secondary phases. The internal electrode layer 12 comprises a plurality of first internal electrode layers 12a and a plurality of second internal electrode layers 12b. The first internal electrode layers 12a and the second internal electrode layers 12b are alternately stacked. The edge of the first internal electrode layer 12a is drawn out to the surface of the base body 10 on which the first external electrode 20a is provided, in the example of Figures 1 to 3, to the first side surface 10a. The edge of the second internal electrode layer 12b is drawn out to the surface of the base body 10 on which the second external electrode 20b is provided, in the example of Figures 1 to 3, to the second side surface 10b. In other words, the internal electrode layer 12 is drawn out from both ends along the second axis, the X axis. As a result, the first internal electrode layer 12a and the second internal electrode layer 12b are alternately conductive to the first external electrode 20a and the second external electrode 20b. Therefore, the multilayer ceramic capacitor 100 has a structure in which capacitor units are stacked. In addition, in the laminate of the dielectric layer 11 and the internal electrode layer 12, the internal electrode layer 12 is arranged as the outermost layer in the stacking direction, and the outer surface of the laminate in the stacking direction, in the example of Figures 1 to 3, the top and bottom surfaces are covered by a cover layer 13. The cover layer 13 mainly consists of a ceramic material. For example, the composition of the cover layer 13 may be the same as or different from that of the dielectric layer 11. Note that the configuration is not limited to that shown in Figures 1 to 3, as long as the first internal electrode layer 12a and the second internal electrode layer 12b are exposed in different regions of the surface of the laminate and are conductive to different external electrodes. Different regions on the surface of the laminate may be the respective surface regions of opposing faces of the laminate, the respective surface regions of adjacent faces of the laminate, or different surface regions of the same face of the laminate. If the different external electrodes are spaced apart from each other, the first internal electrode layer 12a and the second internal electrode layer 12b may extend from the surface exposed to the surface region of the laminate to other surfaces.

[0019] As illustrated in Figure 2, the region where the first internal electrode layer 12a connected to the first external electrode 20a and the second internal electrode layer 12b connected to the second external electrode 20b face each other is a region in the multilayer ceramic capacitor 100 where capacitance is generated. Therefore, the region where capacitance is generated is referred to as the capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers face each other across a dielectric layer 11 connected to different external electrodes.

[0020] The region in which the first internal electrode layers 12a connected to the first external electrode 20a face each other in the stacking direction without passing through the second internal electrode layer 12b connected to the second external electrode 20b is referred to as the first end margin 15a (see Figure 2). Similarly, the region in which the second internal electrode layers 12b connected to the second external electrode 20b face each other in the stacking direction without passing through the first internal electrode layer 12a connected to the first external electrode 20a is referred to as the second end margin 15b.

[0021] Each end margin can also be described as a region where internal electrode layers connected to the same external electrode face each other in the stacking direction without being connected to different external electrodes. The first end margin 15a and the second end margin 15b are regions where internal electrodes with equal potential face each other and are regions that do not generate substantial capacitance. The end margins can contain ceramic material as the main component. For example, the composition of the end margins may be the same as or different from that of the dielectric layer 11.

[0022] The side margin 16 is a region located outside the capacitance portion 14 in the third axis perpendicular to the stacking direction and the second axis, and in the example of Figure 3, in the direction along the Y axis. That is, the side margin 16 is the outer region adjacent to the capacitance portion 14 as viewed from the stacking direction, and the outer region adjacent to the capacitance portion 14 on the side from which the internal electrode layer 12 is not drawn. The side margin 16 is also a region that does not generate capacitance. The side margin 16 can mainly contain ceramic material. For example, the side margin 16 may have the same composition as the dielectric layer 11 or a different composition. Furthermore, as will be described later, the side margin 16 may contain secondary phases with different compositions from the dielectric material in addition to the dielectric material.

[0023] The size of the multilayer ceramic capacitor 100 is not particularly limited, but for example, it may be 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height; 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height; 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height; 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height; 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height; or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height. However, the sizes listed above for the multilayer ceramic capacitor 100 are merely examples, and the multilayer ceramic capacitor is not limited to the above sizes. The size of the multilayer ceramic capacitor 100 may be, for example, length > width ≥ height, width > length ≥ height, height > length ≥ width, or height > width ≥ length. For example, length represents the size in the X-axis direction, width represents the size in the Y-axis direction, and height represents the size in the Z-axis direction.

[0024] As described above, the multilayer ceramic capacitor 100 of this embodiment has a base body 10 in which a dielectric layer 11 and an internal electrode layer 12 are alternately stacked in multiple layers along the first axis, the Z axis.

[0025] Furthermore, the internal electrode layer 12 can be extended to the outside of the body 10 from both ends along the X-axis, which is the second axis perpendicular to the first axis, namely the first side surface 10a and the second side surface 10b.

[0026] Furthermore, the base body 10 has side margins 16 at both ends along the Y-axis, which is the third axis perpendicular to the first and second axes.

[0027] The following is a description of each part.

[0028] In this specification, component names may be given numbers such as "1st internal electrode layer" and "2nd internal electrode layer." However, these numbers are added solely to identify the component being described and to avoid confusion; they do not indicate priority or arrangement. Therefore, when there is no risk of confusion or when referring to them collectively, they may simply be written as "internal electrode layer." (2) Regarding the dielectric layer The dielectric layer 11 may contain dielectric material. The dielectric layer 11 may mainly consist of particles of the dielectric material, i.e., it may contain the largest amount of dielectric material in terms of substance. In addition to the dielectric material particles, the dielectric layer 11 may also contain additive compounds described later, and secondary phases formed by their reactants. The dielectric layer 11 may contain, for example, elements A and B as the dielectric material, and the general formula may be ABO 3-α The compound may contain a perovskite structure represented by (0 ≤ α ≤ 1). In the general formula, A and B represent the elements located at the A site and B site, respectively. (2-1) Regarding components having a perovskite structure For compounds having a perovskite structure, in the case of a stoichiometric composition, α, which represents the amount deviating from the stoichiometric composition, is 0, and the compound is represented by the general formula ABO3. For compounds having a perovskite structure represented by the above general formula, α may be greater than 0 and less than or equal to 1. In other words, for compounds having a perovskite structure represented by the above general formula, oxygen may be deficient in a proportion greater than the stoichiometric composition.

[0029] As the compound having a perovskite structure, barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), magnesium titanate (MgTiO3), Ba forming a perovskite-type structure 1-x-y Ca x Sr y Ti 1-z Zr z One or more selected from O3 (0≦x≦1, 0≦y≦1, 0≦z≦1) and the like can be used.

[0030] Ba 1-x-y Ca x Sr y Ti 1-z Zr z O3 includes barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, barium calcium titanate zirconate, and the like. Note that the compound having a perovskite structure may contain oxygen vacancies in any of the materials.

[0031] Since the dielectric layer 11 is particularly excellent in dielectric properties, it preferably contains barium titanate as the compound having a perovskite structure, may contain barium titanate as a main component, or may be composed of barium titanate alone. Barium titanate is excellent in dielectric properties such as an extremely high dielectric constant and low dielectric loss. For this reason, the capacitance of the multilayer ceramic capacitor 100 can be increased by the dielectric layer 11 containing barium titanate as the compound having a perovskite structure. In the present specification, "contained as a main component" means that the component is contained in the largest proportion in terms of substance amount among the contained components.

[0032] Further, in the dielectric layer 11, the compound having a perovskite structure may be contained as a main component. The dielectric layer 11 may contain, for example, 50 mol% or more, or 90 mol% or more of the compound having a perovskite structure. (Additive Compound) The dielectric layer 11 may also contain an additive compound as an optional component.

[0033] The additive compounds that the dielectric layer 11 can contain are not particularly limited, but examples include oxides, carbonates, or nitrides containing one or more elements selected from zirconium (Zr), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), aluminum (Al), titanium (Ti), calcium (Ca), and rare earth elements; or oxides, carbonates, or nitrides containing one or more elements selected from cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), and silicon (Si); or glass containing one or more elements selected from cobalt, nickel, lithium, boron, sodium, potassium, and silicon.

[0034] The rare earth elements are not particularly limited, and one or more selected from scandium (Sc), cerium (Ce), neodymium (Nd), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb) may be used. (2-2) Regarding the thickness of the dielectric layer The thickness of the dielectric layer 11 is not particularly limited. From the viewpoint of miniaturizing the multilayer ceramic capacitor 100 while increasing the number of layers to increase capacitance, the thickness of the dielectric layer 11 may be, for example, 1.0 μm or less, 0.8 μm or less, 0.5 μm or less, or 0.4 μm or less.

[0035] The minimum thickness of the dielectric layer 11 is not particularly limited, but from the viewpoint of improving productivity and yield, it can be set to a minimum of 2 to 4 times the average diameter of the particles of the dielectric material used. For example, if the average diameter of the particles of the dielectric material used is 0.1 μm, the minimum thickness of the dielectric layer 11 can be 0.2 μm or more and 0.4 μm or less, and the thickness of the dielectric layer 11 may be, for example, 0.2 μm or more, or 0.4 μm or more.

[0036] The average diameter of dielectric material particles can be determined by measuring the particle size of each dielectric material particle in a cross-section of the multilayer ceramic capacitor 100 that includes a first axis equal to the stacking direction, and taking the average of these measurements. Optical microscopes, microscopes, scanning electron microscopes (SEMs), etc., can be used as appropriate to measure the particle size of dielectric material particles. The particle size of dielectric material particles can be defined as the Heywood diameter (the diameter of a circle with an area equal to the area of ​​the dielectric material particle being evaluated) at the observed cross-section. The average diameter, which is the average value of the dielectric material particle size, can be the arithmetic mean of the particle sizes of 50 to 200 arbitrarily selected dielectric material particles. In this specification, unless otherwise specified, "average value" refers to the arithmetic mean.

[0037] When evaluating the thickness of the dielectric layer 11, the evaluation is performed in a cross-section that includes a first axis equal to the stacking direction. For example, it is preferable to evaluate in a cross-section that further includes a second axis set perpendicular to the stacking direction, or a cross-section that further includes a third axis set perpendicular to both the stacking direction and the second axis, due to the ease of polishing and measurement. In the former case, the multilayer ceramic capacitor 100 is polished in the third axis direction, and in the latter case, in the second axis direction. Five layers are selected from the central part, upper end, and lower end of the exposed dielectric layer 11 in the first axis direction. If the number of dielectric layers 11 is even, six layers are selected from the central part. Then, the thickness of each selected dielectric layer is measured at three locations: the central part, the left end, and the right end, and the average of the measured thicknesses is taken as the thickness of each dielectric layer 11. Furthermore, the average of the thicknesses of all selected and evaluated dielectric layers 11 can be taken as the thickness of the dielectric layer 11 in the multilayer ceramic capacitor 100.

[0038] In the examples shown in Figures 1 and 2, the first axis, which is the stacking direction, is the Z-axis direction. Therefore, the multilayer ceramic capacitor 100 is polished along the third axis, the Y-axis, to expose the XZ plane where the dielectric layer 11 and the internal electrode layer 12 are stacked.

[0039] In this case, five dielectric layers 11 located in the center along the first axis (Z axis) of the exposed XZ plane are selected, and five dielectric layers 11 each are selected at the upper and lower ends along the first axis (Z axis). If the number of dielectric layers 11 is even, six layers may be selected for the central part. In this case, the dielectric layers 11 to be selected are selected from within the capacitance section 14.

[0040] Then, for each of the selected dielectric layers 11, the thickness is measured at three points along the second axis, the X-axis, at distances of 1 / 4, 1 / 2, and 3 / 4 of the length of the dielectric layer 11 along the X-axis from the edge, and the average value of these measurements is taken as the thickness of the dielectric layer 11. By the same procedure, the thickness of all the selected dielectric layers 11 is measured, and the average value of the thicknesses of all the selected and evaluated dielectric layers 11 can be taken as the thickness of the dielectric layers 11 in the evaluated multilayer ceramic capacitor 100. (3) Regarding the internal electrode layer (3-1) Components contained in the internal electrode layer The internal electrode layer 12 may contain base metal elements as its main component. In addition to the base metal elements that are the main component, the internal electrode layer 12 may also contain additive metal elements.

[0041] The internal electrode layer 12 may contain components used in the internal electrode layer of a multilayer ceramic capacitor. In particular, the internal electrode layer 12 may mainly consist of a base metal such as nickel (Ni), tin (Sn), or tungsten (W), or an alloy containing one or more selected from the group of base metals, that is, it may contain the largest amount in terms of molar volume.

[0042] Because it offers excellent electrical properties and reduces costs, the internal electrode layer 12 may contain nickel as a base metal element, or it may contain nickel as the main component.

[0043] The main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same or different. For example, the main components of both the first internal electrode layer 12a and the second internal electrode layer 12b may be the same, namely nickel. (3-2) Regarding the thickness of the internal electrode layer The thickness of the internal electrode layer 12 is not particularly limited, but from the viewpoint of miniaturizing the multilayer ceramic capacitor 100 while increasing the number of layers to increase capacitance, it is preferably 0.8 μm or less, and more preferably 0.6 μm or less.

[0044] The lower limit of the thickness of the internal electrode layer 12 is not particularly limited, but for example, when it is formed by printing a metal conductive paste using a printing method such as screen printing or gravure printing, it can be 0.4 μm or more. For example, when it is formed by a thin-film process such as sputtering or vapor deposition, it can be thinner than that of the printing method, 0.1 μm or more.

[0045] When evaluating the thickness of the internal electrode layer 12, the evaluation is performed in a cross-section that includes a first axis equal to the stacking direction, similar to the evaluation of the thickness of the dielectric layer 11. For example, it is preferable to evaluate in a cross-section that further includes a second axis set perpendicular to the stacking direction, or a cross-section that further includes a third axis set perpendicular to both the stacking direction and the second axis, due to the ease of polishing and measurement.

[0046] Five layers are selected from the central part, upper end, and lower end of the exposed internal electrode layer 12 in the first axial direction. If the number of layers in the internal electrode layer 12 is even, six layers are selected from the central part. Then, the thickness of each selected internal electrode layer 12 is measured at three locations: the central part, the left end, and the right end, and the average of the measured thicknesses is taken as the thickness of each internal electrode layer 12. Furthermore, the average of the thicknesses of all the selected and evaluated internal electrode layers 12 can be taken as the thickness of the internal electrode layer 12 in the multilayer ceramic capacitor 100.

[0047] In the examples shown in Figures 1 and 2, the first axis, which is the stacking direction, is the Z-axis direction. Therefore, the multilayer ceramic capacitor 100 is polished along the third axis, the Y-axis, to expose the XZ plane where the dielectric layer 11 and the internal electrode layer 12 are stacked.

[0048] In this case, of the exposed XZ plane, five internal electrode layers 12 located in the center along the first axis (Z axis) are selected, and five internal electrode layers 12 located at the upper and lower ends along the first axis (Z axis) are selected. If the number of internal electrode layers 12 is even, six layers may be selected for the central part. In this case, the selected internal electrode layers 12 are selected from within the capacitance section 14.

[0049] Then, for each selected internal electrode layer 12, the thickness is measured at three points along the second axis, the X-axis, at distances of 1 / 4, 1 / 2, and 3 / 4 of the length of the internal electrode layer 12 along the X-axis from the edge, and the average value of these measurements is taken as the thickness of the internal electrode layer 12. By the same procedure, the thickness of all selected internal electrode layers 12 is measured, and the average value of the thicknesses of all selected and evaluated internal electrode layers 12 can be taken as the thickness of the internal electrode layers 12 in the evaluated multilayer ceramic capacitor 100. (3) Regarding side margins (3-1) Regarding the secondary phase As shown in Figures 4(A) and 4(B), the side margin 16 can include the dielectric material 42 and the secondary phase 41. Figure 4(A) corresponds to an enlarged view of region C in Figure 3 and is a partial enlarged view of the side margin 16. Figure 4(B) is a schematic diagram of the arrangement of the secondary phase 41 and the particles of the dielectric material 42 arranged around the secondary phase 41.

[0050] The inventors of the present invention conducted research on multilayer ceramic electronic components with excellent moisture resistance. They discovered that moisture resistance can be improved by including particles of the secondary phase 41 in the side margin 16, and by keeping the average number of dielectric material particles in contact per 1 μm of the surface of the secondary phase 41 particles contained in the side margin 16 within a predetermined range, thereby completing the present invention.

[0051] In this specification, "excellent moisture resistance" means that the failure rate in the moisture resistance test described in the evaluation method of the examples is 2% or less.

[0052] The secondary phase 41 is formed from a material different from the dielectric material, etc., that is mainly included in the side margin 16. The secondary phase 41 may be, for example, an additive added together with the dielectric material, etc., which is the raw material, during the firing of the side margin 16, or a reaction product between the additive and ceramic particles.

[0053] The secondary phase 41 may contain, for example, silicon (Si). In addition to silicon (Si), the secondary phase 41 may contain one or more elements selected from lithium (Li), boron (B), and calcium (Ca). The secondary phase 41 may further contain aluminum (Al). (Plant arrangement with secondary phase particles) The particles of the dielectric material 42 can be arranged to surround the particles of the secondary phase 41. For example, in a cross-sectional observation image including the first axis, the side margin 16 can include particles of the secondary phase 41 having a surface length of 2 μm or more. Furthermore, the average number of dielectric material 42 particles in contact with the surface of the secondary phase 41 particles per 1 μm may be between 0.5 and 5.

[0054] For example, as shown in Figure 4(B), dielectric material 42 particles are arranged around the secondary phase 41 particles. By setting the average number of dielectric material 42 particles in contact with the surface of the secondary phase 41 particles per 1 μm to 0.5 or more, the dielectric material 42 particles can be densely arranged around the secondary phase 41 particles. As a result, the amount of moisture that previously reached the capacitance portion 14 by passing between the dielectric material 42 particles and between the secondary phase 41 particles and the dielectric material 42 particles can be reduced, and the moisture resistance of the multilayer ceramic electronic component can be improved.

[0055] By setting the average number of dielectric material 42 particles in contact with the surface of secondary phase 41 particles per 1 μm to 5 or less, the productivity of multilayer ceramic electronic components can be increased.

[0056] The number of dielectric material 42 particles in contact with the surface of the secondary phase 41 particles per 1 μm can be evaluated in a cross-section that includes the first axis and further includes a third axis set perpendicular to both the stacking direction and the second axis, and can be measured and calculated, for example, by the following procedure.

[0057] For evaluation, the multilayer ceramic electronic component is polished, for example, along the second axis to expose the YZ plane shown in Figure 3.

[0058] Next, the side margins 16 of the exposed cross-section are observed. As shown in Figure 3, there are two side margins 16 on the exposed cross-section, flanking the volumetric section 14, so both side margins 16 are observed.

[0059] By comparing the contrast and, if necessary, performing compositional analysis using EDX, the secondary phase 41 and the dielectric material 42 are identified.

[0060] Ten to fifty particles of the secondary phase 41, whose surface length within the side margin 16 is 2 μm or more, are selected. Then, for the selected particles of the secondary phase 41, two measurement areas are set: a first measurement area 43A and a second measurement area 43B. The first measurement area 43A and the second measurement area 43B are located on both sides of the particles of the secondary phase 41 along their short axes.

[0061] The length L43A along the surface of the secondary phase 41 particles in the first measurement area 43A and the length L43B along the surface of the secondary phase 41 particles in the second measurement area 43B are both 1 μm. Each measurement area is set up so that the center of the first measurement area 43A and the center of the second measurement area 43B coincide with the center line CL that passes through the center of the major axis diameter of the secondary phase 41 particles.

[0062] Then, the number of dielectric material 42 particles in contact with each measurement area on the surface of the set secondary phase 41 particles is counted. Note that at the boundary of each measurement area, there may be dielectric material 42 particles 42A located on the boundary. In this case, particles 42A located on the boundary and not entirely within the above range can be not counted. That is, in the case of the first measurement area 43A in Figure 4(B), if there are two dielectric material 42 particles 42B in contact with a region of length L43A of 1 μm set on the surface 41A of the secondary phase 41, they will be counted. For the selected secondary phase 41 particles, the arithmetic mean of the number of dielectric material 42 particles in contact with the surface of the secondary phase 41 particles per 1 μm, measured in the first measurement area 43A and the second measurement area 43B, respectively, is calculated. Then, the calculated arithmetic mean can be used as the number of dielectric material 42 particles in contact with the surface of the secondary phase 41 particles per 1 μm for the selected secondary phase 41 particles.

[0063] Using the same procedure, the number of dielectric material 42 particles in contact with the surface of all selected and measured secondary phase 41 particles per 1 μm can be determined, and their arithmetic mean can be calculated. The calculated arithmetic mean can be used as the average number of dielectric material 42 particles in contact with the surface of the secondary phase 41 particles per 1 μm in the evaluated multilayer ceramic electronic component.

[0064] The secondary phase 41 is distributed to fill the gaps between the particles of the dielectric material 42. By keeping the average particle size of the dielectric material particles and the average particle size (average major axis diameter) of the secondary phase 41 within a predetermined range, the gaps contained in the side margin 16 can be reduced. As a result, the amount of moisture that previously reached the capacitance portion 14 through the gaps between the particles of the dielectric material 42 can be reduced, and the moisture resistance of the multilayer ceramic electronic component can be particularly improved.

[0065] Therefore, the average major axis diameter of the particles of the secondary phase 41 contained in the side margin 16 may be 2 μm or more and 4 μm or less, 2.1 μm or more and 3.9 μm or less, or 2.5 μm or more and 3.9 μm or less.

[0066] The average major axis diameter of the particles in the secondary phase 41 can be evaluated in a cross-section that includes the first axis and a third axis set perpendicular to both the stacking direction and the second axis, and can be measured and calculated, for example, by the following procedure.

[0067] For evaluation, the multilayer ceramic electronic component is polished, for example, along the second axis to expose the YZ plane shown in Figure 3.

[0068] Next, the side margins 16 of the exposed cross-section are observed. As shown in Figure 3, there are two side margins 16 on the exposed cross-section, flanking the volumetric section 14, so both side margins 16 are observed.

[0069] By comparing the contrast and, if necessary, performing compositional analysis using EDX (Energy Dispersive X-ray Spectroscopy), the secondary phase 41 and the dielectric material 42 are identified.

[0070] Ten to fifty particles of the secondary phase 41 contained in the side margin 16 are selected, and the major axis diameter L41 and minor axis diameter W41 (see Figure 4(B)) of the selected secondary phase 41 particles are measured. It is preferable to select the same number of secondary phase 41 particles from the two side margins 16.

[0071] Then, the arithmetic mean values ​​of the major axis diameter and minor axis diameter of all selected and measured secondary phase 41 particles can be used as the average major axis diameter and average minor axis diameter of the secondary phase 41 contained in the side margin 16 of the evaluated multilayer ceramic electronic component. The ratio of the major axis diameter to the minor axis diameter can be calculated using the average of the major axis diameter and minor axis diameter (average major axis diameter:average minor axis diameter) and used as the aspect ratio of the secondary phase 41 particles. Specifically, the aspect ratio of the secondary phase 41 particles can be determined by dividing the average major axis diameter by the average minor axis diameter.

[0072] The aspect ratio may be, for example, between 4 and 6. (3-2) Dielectric materials The side margin 16 may also include the dielectric material 42.

[0073] The dielectric material may include compounds having a perovskite structure as described in "(2) Dielectric Layer". The dielectric material contained in the dielectric layer 11 and the dielectric material contained in the side margin 16 may be the same or different. (Average particle size) The average particle size of the dielectric material 42 contained in the side margin 16 may be 0.15 μm or more and 1.6 μm or less, 0.4 μm or more and 1.1 μm or less, or 0.6 μm or more and 0.9 μm or less.

[0074] The average particle size of the dielectric material 42 can be evaluated in a cross-section that includes a first axis and a third axis set perpendicular to both the stacking direction and the second axis, and can be measured and calculated, for example, by the following procedure.

[0075] For evaluation, the multilayer ceramic electronic component is polished, for example, along the second axis to expose the YZ plane shown in Figure 3.

[0076] Next, the side margins 16 of the exposed cross-section are observed. As shown in Figure 3, there are two side margins 16 on the exposed cross-section, flanking the volumetric section 14, so both side margins 16 are observed.

[0077] By comparing the contrast and, if necessary, performing compositional analysis using EDX, the secondary phase 41 and the dielectric material 42 are identified.

[0078] Ten to fifty particles of dielectric material 42 are selected from the side margin 16, and the Heywood diameter (the diameter of a circle with an area equal to the area of ​​the dielectric material particles being evaluated) of the selected dielectric material 42 particles is measured and calculated. It is preferable to select the same number of dielectric material 42 particles from the two side margins 16.

[0079] Then, the arithmetic mean of the particle sizes of all the dielectric material 42 particles selected and measured can be used as the average particle size of the dielectric material 42 particles contained in the side margin 16 of the evaluated multilayer ceramic electronic component. (3-3) Porosity Regarding the side margin 16, it is preferable that the porosity is small, and the porosity may be, for example, 2% or less, 1.9% or less, or 1.3% or less.

[0080] The method for determining the porosity of the side margin 16 is not particularly limited, but it can be measured and calculated by, for example, the following procedure.

[0081] The void ratio of the side margin 16 can be evaluated in a cross-section that includes a third axis set perpendicular to both the stacking direction and the second axis, and can be measured and calculated, for example, by the following procedure.

[0082] For evaluation, the multilayer ceramic electronic component is polished, for example, along the second axis to expose the YZ plane shown in Figure 3.

[0083] Next, the side margins 16 of the exposed cross-section are observed. As shown in Figure 3, there are two side margins 16 on the exposed cross-section, flanking the volumetric section 14, so both side margins 16 are observed.

[0084] The area ratio of the voids contained in the side margin 16 in the observed cross-section can be defined as the porosity of the side margin 16. (3-4) Regarding the thickness of the side margin In recent years, there has been a demand for improved capacitance in multilayer ceramic electronic components, and consequently, a demand to reduce the thickness of the side margin 16.

[0085] However, reducing the thickness of the side margin 16 presented a problem: it reduced the moisture resistance of the multilayer ceramic electronic component.

[0086] In contrast, the multilayer ceramic electronic component of this embodiment can improve the moisture resistance of the multilayer ceramic electronic component. This effect is particularly pronounced when the thickness of the side margin 16 is reduced. For this reason, in the multilayer ceramic electronic component of this embodiment, the thickness of the side margin 16 may be equal to or less than the thinnest side margin thickness of 15 μm in conventional multilayer ceramic electronic components, or it may be thinner than 15 μm. The thickness T16 of the side margin 16 may be 15 μm or less, less than 15 μm, 12 μm or less, or 10 μm or less.

[0087] The lower limit of the thickness T16 of the side margin 16 is not particularly limited, but may be, for example, 5 μm or more, or 7 μm or more.

[0088] The thickness of the side margin 16 can be evaluated in a cross-section that includes the first axis and further includes a third axis that is perpendicular to both the stacking direction and the second axis.

[0089] Five layers are selected from the central part, upper end, and lower end of the internal electrode layer 12 in the first axial direction within the exposed cross-section. If the number of layers in the internal electrode layer 12 is even, six layers are selected from the central part. The distance between the edge of each selected internal electrode layer 12 and the third side surface 10c and fourth side surface 10d, which are the outer surfaces of the side margin 16, is measured as the thickness T16 of the side margin 16. The distance between the edge of the internal electrode layer 12 and the outer surface of the side margin 16 represents the shortest distance between the edge of the internal electrode layer 12 and the outer surface of the side margin 16.

[0090] The average distance between the edges of all measured internal electrode layers 12 and the third side surface 10c and fourth side surface 10d, which are the outer surfaces of the side margin 16, can be used as the thickness of the side margin 16 in the multilayer ceramic capacitor 100.

[0091] In the examples shown in Figures 1 and 3, the first axis, which is the stacking direction, is the Z-axis direction. Therefore, the multilayer ceramic capacitor 100 is polished along the second axis, the X-axis, to expose the YZ plane where the dielectric layer 11 and the internal electrode layer 12 are stacked.

[0092] In this case, of the exposed YZ plane, five internal electrode layers 12 located in the center along the first axis (Z axis) are selected, and five internal electrode layers 12 located at the upper and lower ends along the first axis (Z axis) are selected. If the number of internal electrode layers 12 is even, six layers may be selected for the central part. In this case, the selected internal electrode layers 12 are selected from within the capacitance section 14.

[0093] Then, for each selected internal electrode layer 12, the distance between the edge of each internal electrode layer 12 and the third side surface 10c and the fourth side surface 10d, which are the outer surfaces of the side margin 16, is measured along the third axis, the Y axis. The average value of these measurements can then be used as the thickness T16 of the side margin 16.

[0094] [Manufacturing method for multilayer ceramic capacitors] Next, the manufacturing method of the multilayer ceramic capacitor 100 will be described. Figure 5 is a flowchart 50 illustrating the manufacturing method of the multilayer ceramic capacitor 100. Figure 6 is a diagram illustrating the manufacturing method of the multilayer ceramic capacitor 100.

[0095] The manufacturing method for the multilayer ceramic capacitor of this embodiment may include a dielectric green sheet formation step, an internal electrode layer pattern formation step, and a firing step. The manufacturing method for the multilayer ceramic capacitor of this embodiment will be described below, including any other steps besides those mentioned above. (1) Raw material powder preparation process (S1) In the raw material powder preparation process, raw material powder for forming the dielectric layer 11 can be prepared.

[0096] The dielectric layer 11 of the multilayer ceramic capacitor 100 manufactured by the manufacturing method of the multilayer ceramic capacitor of this embodiment is of the general formula ABO 3-αIt can contain dielectric materials that are compounds having a perovskite structure represented by (0≦α≦1). General formula ABO 3-α Since dielectric materials, which are compounds having a perovskite structure represented by (0 ≤ α ≤ 1), have already been explained, we will omit further explanation.

[0097] The dielectric material contained in the dielectric layer 11 contains A-site elements (element A) and B-site elements (element B), which are usually ABO. 3-α The dielectric layer 11 is contained in the form of a sintered body of particles with (0≦α≦1). For example, barium titanate is a tetragonal compound having a perovskite structure and exhibiting a high dielectric constant. Barium titanate can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been conventionally known for synthesizing dielectric materials that can be used as the main component of the dielectric layer 11, such as the solid-phase method, the sol-gel method, and the hydrothermal method. In this embodiment, any of these can be employed.

[0098] In the raw material powder preparation process, predetermined additive compounds can be added to the dielectric material according to the purpose. These additive compounds also serve as raw materials for the secondary phase. Therefore, additive compounds corresponding to the desired composition of the secondary phase can be added to the dielectric material. Since the secondary phase only needs to be contained in the side margin 16, additive compounds corresponding to the desired composition of the secondary phase may be added only to the raw material powder used in the side margin 16 portion.

[0099] Examples of additive compounds include oxides, carbonates, or nitrides containing one or more elements selected from zirconium (Zr), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), aluminum (Al), titanium (Ti), calcium (Ca), and rare earth elements; oxides, carbonates, or nitrides containing one or more elements selected from cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), and silicon (Si); and glasses containing one or more elements selected from cobalt, nickel, lithium, boron, sodium, potassium, and silicon.

[0100] Examples of the rare earth elements mentioned above include one or more selected from scandium (Sc), cerium (Ce), neodymium (Nd), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb).

[0101] The raw material powder can be prepared, for example, by wet-mixing an additive compound with a dielectric material, followed by drying and pulverization. The raw material powder will also be referred to as the dielectric pattern material in the following description. For example, the raw material powder obtained as described above may be subjected to pulverization to adjust the particle size, or the particle size may be adjusted by combining this with a classification process as needed. Through the above steps, a raw material powder that is a ceramic material is obtained. (2) Dielectric green sheet formation process (S2) The dielectric green sheet formation process can be carried out by wet mixing the raw material powder obtained in the raw material powder preparation process with a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer to form a slurry. Alternatively, the binder may be added at the same time as mixing the raw material powder in the raw material powder preparation process (S1), and the slurry may be formed by wet mixing.

[0102] In the dielectric green sheet formation process, the obtained slurry can be used to coat a substrate with the slurry, for example, by a die coater or doctor blade method, and then dried to form a dielectric green sheet 61. For example, polyethylene terephthalate (PET) film can be used as the substrate. A diagram illustrating the dielectric green sheet formation process has been omitted.

[0103] Therefore, in the dielectric green sheet formation process (S2), the general formula ABO 3-α A dielectric green sheet can be formed containing a compound having a perovskite structure represented by (0≦α≦1) or an additive compound. In addition to the dielectric with a perovskite structure represented by the above general formula, the dielectric green sheet can also contain the additive compound as described above. (3) Internal electrode layer formation process (S3) The first internal electrode layer 12a and the second internal electrode layer 12b may be primarily composed of one or more base metals selected from nickel (Ni), tin (Sn), tungsten (W), and alloys containing these metals.

[0104] The main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same or different. For example, the main components of both the first internal electrode layer 12a and the second internal electrode layer 12b may be the same, namely nickel.

[0105] A metal conductive paste for forming the precursors of the first internal electrode layer 12a and the second internal electrode layer 12b can be prepared by kneading a selected main component, an organic binder, and a solvent.

[0106] In the internal electrode layer formation process, as illustrated in Figure 6(A), a metal conductive paste for forming the internal electrode layer, containing an organic binder, can be printed onto the surface of the dielectric green sheet 61 by screen printing, gravure printing, or the like. Examples of organic binders include ethyl cellulose (EC) and polyvinyl butyral (PVB) resin. This arranges a first internal electrode layer pattern 62a for the first internal electrode layer 12a or a second internal electrode layer pattern 62b for the second internal electrode layer 12b on the surface of the dielectric green sheet 61. Various auxiliary agents, such as dispersants, and ceramic particles as co-materials can also be added to the metal conductive paste. The main component of the ceramic particles is not particularly limited, but it is preferable that it be the same as the main ceramic component of the dielectric layer 11. When ceramic particles are added as co-materials, they can be added during the mixing of the metal conductive paste. The method for forming the internal electrode layer is not limited to printing; plating, vacuum deposition, sputtering, and CVD methods may also be used.

[0107] Alternatively, a dielectric pattern paste for an inverse pattern dielectric layer can be obtained by adding a binder such as ethyl cellulose and an organic solvent such as terpineol to the dielectric pattern material obtained in the raw material powder preparation process and kneading it in a roll mill. Then, as illustrated in Figure 6(A), the dielectric pattern 63 may be arranged on the dielectric green sheet 61 by printing the dielectric pattern paste in the peripheral area where the internal electrode layer pattern is not printed, thereby filling the step difference with the internal electrode layer pattern. The dielectric pattern 63 can also be described as an inverse pattern dielectric layer, and the process of forming the inverse pattern dielectric layer may be described as an inverse pattern dielectric layer formation process. A part of the dielectric pattern 63 becomes the side margin 16. For this reason, components that serve as raw materials for the secondary phase contained in the side margin 16 of the dielectric pattern 63 may be added. The dielectric pattern 63 may contain, for example, the additive compounds described in the section on dielectric layer materials. By containing the additive compounds in the dielectric pattern 63, the secondary phase can be deposited in the side margin 16 during or after the firing process described later. In addition, particles corresponding to the secondary phase can be added to the dielectric pattern 63.

[0108] As will be described later, the side margin 16 can also be formed after or before the firing process.

[0109] A dielectric green sheet 61 on which an internal electrode layer pattern and a dielectric pattern 63 are printed is referred to as a laminated unit. (4) Lamination process (S4) In the lamination process, as illustrated in Figure 6(B), the lamination units can be stacked such that the internal electrode layers and dielectric layers are staggered, and the edges of the internal electrode layers are alternately exposed on both ends of the dielectric layer in the longitudinal direction, alternately leading out to a pair of external electrodes. Specifically, a dielectric green sheet 61 printed with a first internal electrode layer pattern 62a and a dielectric pattern 63 is stacked in sequence with a dielectric green sheet 61 printed with a second internal electrode layer pattern 62b and a dielectric pattern 63. For example, the number of layers in the lamination unit can be 100 to 500. (5) Crimping process (S5) In the heat-sealing process, a predetermined number of cover sheets, for example, 2 to 10 layers, can be heat-sealed to the top and bottom of the laminated body in which the laminated units are stacked. (6) Singulation process (S6) In the individualization process, the crimped body is separated into individual pieces, and a laminate of individual pieces can be obtained. Existing methods such as dicing with a dicer or laser cutting can be used as appropriate for individualization. (7) Firing process (S7) In the firing process, the individual laminated pieces can be degreased and then fired. The degreasing and firing processes may be performed consecutively or separately. The conditions for degreasing and firing are not particularly limited. For example, degreasing may be performed in a nitrogen atmosphere at a temperature between 250°C and 500°C.

[0110] For firing, for example, if the oxygen partial pressure is 10 -12 atm over 10 -8 The firing may be carried out in a weakly oxidizing atmosphere or a reducing atmosphere with a temperature range of 1100°C to 1350°C, below atm, for 5 minutes to 10 hours. The oxygen partial pressure is preferably 10-12 atm over 10 -10 It may also be set to atm or less.

[0111] When creating a reducing atmosphere, one or more reducing gases selected from hydrogen and carbon monoxide can be used. The reducing gas may also be an inert gas, such as nitrogen, or a mixture with a noble gas. Examples of noble gases include helium and argon.

[0112] The firing temperature range may preferably be 1150°C to 1350°C. The firing time may preferably be 5 minutes to less than 15 minutes. (8) External electrode formation process (S8) In the external electrode formation process, a metal conductive paste for forming an external electrode layer, containing a base metal such as nickel as a main component, a metal such as copper, and an organic binder, is formed by screen printing, dipping, etc., and then baked to form the external electrode. The method of forming the external electrode is not limited to printing or dipping; plating, vacuum deposition, sputtering, or CVD methods may also be used. Alternatively, the external electrode may be formed by printing or coating a conductive resin paste by screen printing, dipping, etc., and then curing the resin. If necessary, layers of copper, nickel, or tin may be formed by plating or other treatments. This allows for the formation of the first external electrode 20a and the second external electrode 20b. Through the above process, a multilayer ceramic capacitor 100 can be manufactured. (9) Side margin formation process As an optional step, the manufacturing method of the multilayer ceramic electronic component of this embodiment may also include a side margin formation step. In this case, it is preferable to form each component while excluding a portion of the dielectric green sheet and portions that will become side margins, such as the dielectric pattern 63, during the dielectric green sheet formation step (S2) and the internal electrode layer formation step (S3).

[0113] In the side margin formation process, a slurry for side margin formation can be prepared by adding a binder such as ethyl cellulose and an organic solvent such as terpineol to the dielectric pattern material obtained in the raw material powder preparation process. The slurry for side margin formation may contain additive compounds that serve as raw materials for the secondary phase, in addition to the dielectric pattern material. Using the obtained slurry, a dielectric green sheet for side margin formation can be formed by coating it onto a substrate using, for example, a die coater method or a doctor blade method and drying it. As the substrate, for example, polyethylene terephthalate (PET) film can be used. Then, the side margin can be formed by joining the dielectric green sheet for side margin formation to the portion of the laminate that corresponds to the side margin in the piece formation process (S6). After the side margin formation process, the laminate can be subjected to a firing process.

[0114] Alternatively, a paste for forming side margins can be applied to the portion of the laminate corresponding to the side margin after the firing process, and then fired as needed to form the side margins.

[0115] Furthermore, when additive compounds are added to the side margin portion to form a secondary phase during the calcination process, the average major axis diameter of the particles forming the secondary phase in the side margin can be adjusted by selecting the type and amount of additive compound, the calcination conditions during the calcination process, etc.

[0116] The above process is merely an example, and the manufacturing method of the multilayer ceramic capacitor of this embodiment is not limited to the above configuration. For example, the base layer for the external electrodes can be provided on the surface of the fragmented laminate, and the base layer can be formed by firing the ceramic simultaneously with firing the base layer for the external electrodes. In this case, in the external electrode formation process after firing, the external electrodes are formed by forming layers of copper, nickel, or tin on top of this base layer through a plating process.

[0117] [Other embodiments] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims.

[0118] For example, although the above embodiment is applied to a multilayer ceramic capacitor with two terminal electrodes, it may also be applied to a multilayer ceramic capacitor with three or more terminals. [Examples]

[0119] The present invention will be described with specific examples below, but it is not limited to these examples. (1) Evaluation method (1-1) Number of dielectric material particles in contact with the surface of secondary phase particles per 1 μm The number of dielectric material 42 particles in contact with the surface of the secondary phase 41 particles per 1 μm was evaluated in a cross-section that includes the first axis and further includes a third axis set perpendicular to both the stacking direction and the second axis.

[0120] For the evaluation, the multilayer ceramic capacitor was polished along the second axis to expose the YZ plane shown in Figure 3.

[0121] Next, we observed the side margins 16 of the exposed cross-section. As shown in Figure 3, there are two side margins 16 in the exposed cross-section, flanking the volumetric section 14, so we observed both side margins 16.

[0122] By comparing the contrast and performing compositional analysis using EDX as needed, the secondary phase 41 and the dielectric material 42 were identified.

[0123] Thirty particles of the secondary phase 41 with a surface length of 2 μm or more within the side margin 16 were selected.

[0124] Then, as shown in Figure 4(B), two measurement areas were set for the selected secondary phase 41 particles: a first measurement area 43A and a second measurement area 43B. The first measurement area 43A and the second measurement area 43B are located on both sides along the short axis of the secondary phase 41 particles.

[0125] The length L43A along the surface of the secondary phase 41 particles in the first measurement area 43A and the length L43B along the surface of the secondary phase 41 particles in the second measurement area 43B are both 1 μm. Each measurement area was set up so that the center of the first measurement area 43A and the center of the second measurement area 43B coincide with the center line CL that passes through the center of the major axis diameter of the secondary phase 41 particles.

[0126] Then, the number of dielectric material 42 particles in contact with each measurement region on the surface of the set secondary phase 41 particles was counted. Note that at the boundary of each measurement region, there may be dielectric material 42 particles 42A located on the boundary. In this case, particles 42A located on the boundary and not entirely within the above range were not counted.

[0127] For the selected secondary phase 41 particles, the arithmetic mean of the number of dielectric material 42 particles in contact with the surface of the secondary phase 41 particles per 1 μm was calculated in the first measurement area 43A and the second measurement area 43B, respectively. The calculated arithmetic mean was then used as the number of dielectric material 42 particles in contact with the surface of the secondary phase 41 particles per 1 μm for the selected secondary phase 41 particles.

[0128] Using the same procedure, the number of dielectric material 42 particles in contact with the surface of all selected and measured secondary phase 41 particles per 1 μm was determined, and the arithmetic mean was calculated. The calculated arithmetic mean was taken as the average number of dielectric material 42 particles in contact with the surface of the secondary phase 41 particles per 1 μm in the evaluated multilayer ceramic capacitor. (1-2) Average major axis diameter and average minor axis diameter of secondary phase particles, average particle size of dielectric material particles The average major axis diameter and average minor axis diameter of the particles of the secondary phase 41, and the average particle size of the particles of the dielectric material 42 were evaluated in a cross-section that includes the first axis and further includes a third axis set perpendicular to the stacking direction and also perpendicular to the second axis.

[0129] For the evaluation, the multilayer ceramic capacitor was polished along the second axis to expose the YZ plane shown in Figure 3.

[0130] Next, we observed the side margins 16 of the exposed cross-section. As shown in Figure 3, there are two side margins 16 in the exposed cross-section, flanking the volumetric section 14, so we observed both side margins 16.

[0131] By comparing the contrast and performing compositional analysis using EDX, the particles of the secondary phase 41 and the particles of the dielectric material 42 were distinguished.

[0132] Thirty particles of the secondary phase 41 and thirty particles of the dielectric material 42 were selected from the side margin 16. The same number of particles of the secondary phase 41 and dielectric material were selected from two side margins 16.

[0133] For the selected secondary phase 41 particles, the major axis diameter L41 and minor axis diameter W41 (see Figure 4(B)) were measured. The arithmetic mean values ​​of the major axis diameter and minor axis diameter of all selected and measured secondary phase 41 particles were then used as the average major axis diameter and average minor axis diameter of the secondary phase 41 particles in the evaluated multilayer ceramic capacitor.

[0134] The aspect ratio of the secondary phase particles was calculated from the average major axis diameter and average minor axis diameter. Specifically, the aspect ratio was calculated as: Aspect Ratio = Average Major Axis Diameter ÷ Average Minor Axis Diameter.

[0135] For the selected dielectric material 42 particles, the Heywood diameter was measured and calculated, and the arithmetic mean of the Heywood diameters of all selected and measured dielectric material 42 particles was used as the average particle size of the dielectric material 42 in the evaluated multilayer ceramic capacitor. (1-3) Void ratio, side margin thickness The void ratio of the side margin 16 can be evaluated in a cross-section that includes the first axis and further includes a third axis that is perpendicular to both the stacking direction and the second axis, and was measured and calculated using the following procedure.

[0136] For the evaluation, the multilayer ceramic electronic components were polished along the second axis to expose the YZ plane shown in Figure 3.

[0137] Next, we observed the side margins 16 of the exposed cross-section. As shown in Figure 3, there are two side margins 16 in the exposed cross-section, flanking the volumetric section 14, so we observed both side margins 16.

[0138] The area ratio of voids contained within the side margin 16 of the observed cross-section was calculated as the porosity of the side margin 16.

[0139] Furthermore, the thickness of the side margin 16 was evaluated using the procedure already described. (1-3) Evaluation and determination of moisture resistance In each example and comparative example, 1000 multilayer ceramic capacitors manufactured under the same conditions were subjected to a humidity load test.

[0140] Specifically, the multilayer ceramic capacitors fabricated in each example and comparative example were placed in a humidity-resistant chamber, and a humidity load test was performed under the following conditions: test temperature of 85°C, relative humidity of 85%RH, applied voltage of 10Vdc (direct current), and duration of 1000h.

[0141] After the humidity resistance load test, the samples were immediately removed from the humidity-resistant chamber and their resistance was measured once they had returned to room temperature. Samples with a resistance of less than 25 MΩ were judged to be unsuitable for humidity resistance, and the failure rate was investigated.

[0142] The defect rate obtained from the humidity load test is shown in the "Defect Rate in Humidity Load Test" column of Table 1.

[0143] A rating of ◎ was given if the defect rate in the humidity load test was between 0% and 0.5%, ○ if it was between 0.5% and 2%, and × if it was above 2%.

[0144] A rating of ◎ indicates the best moisture resistance, with the resistance decreasing in the order of ○ and ×. A rating of ◎ or ○ indicates a multilayer ceramic capacitor with excellent moisture resistance. (2) Conditions for preparing the sample [Example 1] (2-1) Raw material powder preparation process A multilayer ceramic capacitor was manufactured according to the flowchart 50 shown in Figure 5.

[0145] Specifically, a slurry was obtained by wet mixing barium titanate powder with the additive compounds holmium oxide (Ho2O3), magnesium oxide (MgO), manganese carbonate (MnCO3), silicon dioxide (SiO2), polyvinyl butyral (PVB) resin, a solvent, a plasticizer, and a dispersant. (2-2) Dielectric Green Sheet Formation Process The obtained slurry was coated onto a base film, and the slurry coated onto the base film was dried to obtain a dielectric green sheet. (2-3) Internal electrode layer formation process Next, nickel powder, the main component metal element, was wet-mixed with a binder such as ethyl cellulose (EC) or polyvinyl butyral (PVB) resin, a solvent, and a plasticizer to obtain a metal conductive paste for forming the internal electrode layer. Then, the metal conductive paste was printed onto a portion of the surface of a dielectric green sheet to form an internal electrode layer pattern containing nickel, a base metal element, as the main component on each dielectric green sheet. (2-4) Reverse pattern dielectric layer formation process Next, silicon dioxide (SiO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), ethylcellulose-based binders, and terpineol-based organic solvents were added to the dielectric pattern material obtained in the raw material powder preparation step, and the mixture was kneaded in a roll mill. By kneading the above material, a dielectric pattern paste for the inverse pattern dielectric layer was obtained. Then, as illustrated in Figure 6(A), the dielectric pattern paste for the inverse pattern dielectric layer was printed on the dielectric green sheet 61 in the peripheral area where the internal electrode layer pattern was not printed, thereby arranging the dielectric pattern 63 and forming the inverse pattern dielectric layer.

[0146] A laminated unit was fabricated by the dielectric green sheet formation process, the internal electrode layer formation process, and the reverse pattern dielectric layer formation process described above. The obtained laminated unit comprises a dielectric green sheet, an internal electrode layer pattern formed on the surface of the dielectric green sheet, and a reverse pattern dielectric layer. (2-5) Lamination process Next, 500 stacking units were stacked to form a laminate. (2-6) Crimping process, individual piece formation process Then, after the laminate was compressed, it was separated into individual pieces to obtain chip-shaped green laminates. (2-7) Firing process Next, this chip-shaped green laminate was degreased in a nitrogen atmosphere at 500°C.

[0147] After degreasing, a metal conductive paste containing nickel-based metal fillers, a binder, and a solvent was applied to the green laminate from both ends to each side as a base layer, and then dried. Subsequently, the green laminate with the base layer for the external electrodes was placed in a firing furnace and fired.

[0148] During the firing process, the oxygen partial pressure is 1.0 × 10⁻⁶. -10The material was heated to 1220°C for 300 seconds under a reducing atmosphere, which is a mixture of hydrogen and nitrogen. During the heating process, the supply rate of the green laminate and the oxygen partial pressure were adjusted to prevent abrupt changes in the firing atmosphere due to gases generated from the green laminate and to prevent cracking of the fired product. (2-7) External electrode formation process A first external electrode 20a and a second external electrode 20b were formed on the laminated body after firing by plating.

[0149] The resulting multilayer ceramic capacitor had a chip shape of 1.0 mm × 0.5 mm × 0.5 mm, a dielectric layer 11 thickness of 0.8 μm, an internal electrode layer 12 thickness of 0.6 μm, and 500 layers. The thicknesses of the dielectric layer 11 and the internal electrode layer 12 were evaluated using the procedure already described.

[0150] The obtained multilayer ceramic capacitors were evaluated as described above. The evaluation results are shown in Table 2. [Example 2] In the reverse pattern dielectric layer formation process, silicon dioxide (SiO2), aluminum oxide (Al2O3), calcium carbonate (CaCO3), titanium dioxide (TiO2), ethylcellulose-based binders, and terpineol-based organic solvents were added to the dielectric pattern material obtained in the raw material powder preparation process and kneaded in a roll mill. By kneading the above material, a dielectric pattern paste for the reverse pattern dielectric layer was obtained. Then, as illustrated in Figure 6(A), the dielectric pattern paste for the reverse pattern dielectric layer was printed on the dielectric green sheet 61 in the peripheral region where the internal electrode layer pattern was not printed, thereby arranging the dielectric pattern 63 and forming the reverse pattern dielectric layer.

[0151] Except for the points mentioned above, multilayer ceramic capacitors were fabricated and evaluated using the same procedure as in Example 1. The evaluation results are shown in Table 1. [Example 3] In the reverse pattern dielectric layer formation process, silicon dioxide (SiO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), manganese carbonate (MnCO3), ethylcellulose-based binders, and terpineol-based organic solvents were added to the dielectric pattern material obtained in the raw material powder preparation process, and the mixture was kneaded in a roll mill. By kneading the above material, a dielectric pattern paste for the reverse pattern dielectric layer was obtained. Then, as illustrated in Figure 6(A), the dielectric pattern paste for the reverse pattern dielectric layer was printed on the dielectric green sheet 61 in the peripheral region where the internal electrode layer pattern was not printed, thereby arranging the dielectric pattern 63 and forming the reverse pattern dielectric layer.

[0152] Except for the points mentioned above, multilayer ceramic capacitors were fabricated and evaluated using the same procedure as in Example 1. The evaluation results are shown in Table 1. [Example 4] In the reverse pattern dielectric layer formation process, silicon dioxide (SiO2), aluminum oxide (Al2O3), magnesium oxide (MgO), titanium dioxide (TiO2), an ethylcellulose-based binder, and an organic solvent such as terpineol were added to the dielectric pattern material obtained in the raw material powder preparation process and kneaded in a roll mill. By kneading the above material, a dielectric pattern paste for the reverse pattern dielectric layer was obtained. Then, as illustrated in Figure 6(A), the dielectric pattern paste for the reverse pattern dielectric layer was printed on the dielectric green sheet 61 in the peripheral region where the internal electrode layer pattern was not printed, thereby arranging the dielectric pattern 63 and forming the reverse pattern dielectric layer.

[0153] Except for the points mentioned above, multilayer ceramic capacitors were fabricated and evaluated using the same procedure as in Example 1. The evaluation results are shown in Table 1. [Example 5] In the reverse pattern dielectric layer formation process, silicon dioxide (SiO2), aluminum oxide (Al2O3), lithium carbonate (Li2CO3), titanium dioxide (TiO2), an ethylcellulose-based binder, and an organic solvent such as terpineol were added to the dielectric pattern material obtained in the raw material powder preparation process and kneaded in a roll mill. By kneading the above material, a dielectric pattern paste for the reverse pattern dielectric layer was obtained. Then, as illustrated in Figure 6(A), the dielectric pattern paste for the reverse pattern dielectric layer was printed on the dielectric green sheet 61 in the peripheral region where the internal electrode layer pattern was not printed, thereby arranging the dielectric pattern 63 and forming the reverse pattern dielectric layer.

[0154] Except for the points mentioned above, multilayer ceramic capacitors were fabricated and evaluated using the same procedure as in Example 1. The evaluation results are shown in Table 1. [Example 6] In the reverse pattern dielectric layer formation process, silicon dioxide (SiO2), aluminum oxide (Al2O3), boron nitride (BN), titanium dioxide (TiO2), an ethylcellulose-based binder, and an organic solvent such as terpineol were added to the dielectric pattern material obtained in the raw material powder preparation process and kneaded in a roll mill. By kneading the above material, a dielectric pattern paste for the reverse pattern dielectric layer was obtained. Then, as illustrated in Figure 6(A), the dielectric pattern paste for the reverse pattern dielectric layer was printed on the dielectric green sheet 61 in the peripheral region where the internal electrode layer pattern was not printed, thereby arranging the dielectric pattern 63 and forming the reverse pattern dielectric layer.

[0155] Except for the points mentioned above, multilayer ceramic capacitors were fabricated and evaluated using the same procedure as in Example 1. The evaluation results are shown in Table 1. [Example 7] In the reverse pattern dielectric layer formation process, silicon dioxide (SiO2), aluminum oxide (Al2O3), magnesium oxide (MgO), titanium dioxide (TiO2), manganese carbonate (MnCO3), ethylcellulose-based binders, and terpineol-based organic solvents were added to the dielectric pattern material obtained in the raw material powder preparation process and kneaded in a roll mill. By kneading the above material, a dielectric pattern paste for the reverse pattern dielectric layer was obtained. Then, as illustrated in Figure 6(A), the dielectric pattern paste for the reverse pattern dielectric layer was printed on the dielectric green sheet 61 in the peripheral region where the internal electrode layer pattern was not printed, thereby arranging the dielectric pattern 63 and forming the reverse pattern dielectric layer.

[0156] Except for the points mentioned above, multilayer ceramic capacitors were fabricated and evaluated using the same procedure as in Example 1. The evaluation results are shown in Table 1. [Example 8] In the reverse pattern dielectric layer formation process, silicon dioxide (SiO2), aluminum oxide (Al2O3), boron nitride (BN), titanium dioxide (TiO2), manganese carbonate (MnCO3), ethylcellulose-based binders, and terpineol-based organic solvents were added to the dielectric pattern material obtained in the raw material powder preparation process, and the mixture was kneaded in a roll mill. By kneading the above material, a dielectric pattern paste for the reverse pattern dielectric layer was obtained. Then, as illustrated in Figure 6(A), the dielectric pattern paste was printed on the dielectric green sheet 61 in the peripheral region where the internal electrode layer pattern was not printed, thereby arranging the dielectric pattern 63 and forming the reverse pattern dielectric layer.

[0157] Except for the points mentioned above, multilayer ceramic capacitors were fabricated and evaluated using the same procedure as in Example 1. The evaluation results are shown in Table 1. [Comparative Example 1] In the reverse pattern dielectric layer formation process, silicon dioxide (SiO2), titanium dioxide (TiO2), a binder such as ethylcellulose, and an organic solvent such as terpineol were added to the dielectric pattern material obtained in the raw material powder preparation process, and the mixture was kneaded in a roll mill. By kneading the above material, a dielectric pattern paste for the reverse pattern dielectric layer was obtained. Then, as illustrated in Figure 6(A), the dielectric pattern paste for the reverse pattern dielectric layer was printed on the dielectric green sheet 61 in the peripheral area where the internal electrode layer pattern was not printed, thereby arranging the dielectric pattern 63 and forming the reverse pattern dielectric layer.

[0158] Except for the points mentioned above, multilayer ceramic capacitors were fabricated and evaluated using the same procedure as in Example 1. The evaluation results are shown in Table 1. [Comparative Example 2] In the reverse pattern dielectric layer formation process, silicon dioxide (SiO2), aluminum oxide (Al2O3), calcium carbonate (CaCO3), lithium carbonate (Li2CO3), boron nitride (BN), titanium dioxide (TiO2), ethylcellulose-based binders, and terpineol-based organic solvents were added to the dielectric pattern material obtained in the raw material powder preparation process and kneaded in a roll mill. By kneading the above material, a dielectric pattern paste for the reverse pattern dielectric layer was obtained. Then, as illustrated in Figure 6(A), the dielectric pattern paste for the reverse pattern dielectric layer was printed on the dielectric green sheet 61 in the peripheral region where the internal electrode layer pattern was not printed, thereby arranging the dielectric pattern 63 and forming the reverse pattern dielectric layer.

[0159] Except for the points mentioned above, multilayer ceramic capacitors were fabricated and evaluated using the same procedure as in Example 1. The evaluation results are shown in Table 1.

[0160] [Table 1] According to Table 1, in Examples 1 to 8, where the average number of dielectric material particles in contact with the surface of the secondary phase particles contained in the side margin 16 is within the predetermined range of 0.5 to 5 particles, it was confirmed that multilayer ceramic capacitors with excellent moisture resistance were obtained. In particular, it was confirmed that multilayer ceramic capacitors with especially excellent moisture resistance were obtained when the average number of dielectric material particles in contact with the surface of the secondary phase particles is in the range of 1 to 4 particles.

[0161] Furthermore, focusing on the average major axis diameter of the secondary phase particles, it was confirmed that when the average major axis diameter is between 2 μm and 4 μm, a multilayer ceramic capacitor with excellent moisture resistance can be obtained. In addition, it was confirmed that a multilayer ceramic capacitor with excellent moisture resistance can be obtained when the aspect ratio is between 4 and 6.

[0162] The aspects of this disclosure are, for example, as follows:

[0163] <1> The substrate has multiple layers of dielectric layers and internal electrode layers stacked alternately along the first axis. The internal electrode layer is drawn outwards from both ends along a second axis perpendicular to the first axis, The aforementioned body has side margins at both ends along a third axis perpendicular to the first and second axes, A multilayer ceramic electronic component in which, in a cross-sectional observation image including the first axis, the side margin includes secondary phase particles with a surface length of 2 μm or more, and the average number of dielectric material particles in contact per 1 μm of the surface of the secondary phase particles is 0.5 or more and 5 or less.

[0164] <2> The side margin contains particles of the dielectric material with an average particle size of 0.15 μm or more and 1.6 μm or less, and particles of the secondary phase with an average major axis diameter of 2 μm or more and 4 μm or less. The porosity of the side margin is 2% or less. <1> Multilayer ceramic electronic components as described above.

[0165] <3> The thickness of the side margin is 15 μm or less. <1> or <2> Multilayer ceramic electronic components as described above.

[0166] <4> The dielectric layer contains elements A and B, and the general formula is ABO 3-α It is represented as (0≦α≦1) and contains a compound having a perovskite structure, The internal electrode layer contains base metal elements as its main component. <1> from <3> A multilayer ceramic electronic component as described in any of the following. [Explanation of Symbols]

[0167] 100 Multilayer Ceramic Capacitors 10 Base Body 10a First side 10b Second side 10c 3rd side 10d 4th side 11 Dielectric layer 11a First dielectric layer 11b Second dielectric layer 12 Internal electrode layer 12a 1st internal electrode layer 12b Second internal electrode layer 13. Cover layer 14 Capacity part 15a First end margin 15b Second End Margin 16 Side margins T16 Thickness 20a 1st external electrode 20b 2nd external electrode C area 41 Secondary phase 41A surface L41 Long axis diameter W41 Short shaft diameter 42 Dielectric Materials 42A particles 42B particles 43A 1st measurement area 43B 2nd measurement area L43A Length L43B Length 50 Flowcharts S1 Raw material powder preparation process S2 Dielectric Green Sheet Formation Process S3 Internal electrode layer formation process S4 Lamination process S5 Crimping process S6 singulation process S7 Firing Process S8 External electrode formation process 61 Dielectric Green Sheet 62a First internal electrode layer pattern 62b Second internal electrode layer pattern

Claims

1. The substrate has multiple layers of dielectric layers and internal electrode layers stacked alternately along a first axis. The internal electrode layer is drawn outwards from both ends along a second axis perpendicular to the first axis, The aforementioned body has side margins at both ends along a third axis perpendicular to the first and second axes, A multilayer ceramic electronic component in which, in a cross-sectional observation image including the first axis, the side margin includes secondary phase particles with a surface length of 2 μm or more, and the average number of dielectric material particles in contact per 1 μm of the surface of the secondary phase particles is 0.5 or more and 5 or less.

2. The side margin contains particles of the dielectric material with an average particle size of 0.15 μm or more and 1.6 μm or less, and particles of the secondary phase with an average major axis diameter of 2 μm or more and 4 μm or less. The multilayer ceramic electronic component according to claim 1, wherein the porosity of the side margin is 2% or less.

3. The multilayer ceramic electronic component according to claim 1 or claim 2, wherein the thickness of the side margin is 15 μm or less.

4. The dielectric layer contains elements A and B, and the general formula is ABO ３－α It is represented as (0 ≤ α ≤ 1) and contains a compound having a perovskite structure, The multilayer ceramic electronic component according to claim 1 or claim 2, wherein the internal electrode layer contains a base metal element as a main component.

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