Display device, method for driving a display device, and electronic device.

Abstract

This technology provides a way to suppress burn-in and flicker even when displaying at multiple refresh rates. [Solution] The source drive circuit (22) drives the polarity of the source signal supplied to the source bus line with AC. The control circuit (11) controls the gate drive circuit (21) and the source drive circuit (22) so that the pixel voltage is supplied at a first refresh rate in a partial area, and at a second refresh rate that is lower than the first refresh rate and has a frequency of one odd number of the first refresh rate in areas other than the partial area.

Description

Technical Field

[0001] The present disclosure relates to a display device, a driving method for the display device, and an electronic apparatus.

Background Art

[0002] In the configuration for driving display of a liquid crystal display panel described in Patent Document 1 below, during partial driving in which a partial region of the liquid crystal display panel is set as a non-display region and the remaining region is set as a display region, a refresh operation of the non-display region is performed every plural frame periods, and in a frame period in which the refresh operation of the non-display region is not performed, only a period for scanning the display region is provided while maintaining one frame period at a fixed time, and correspondingly, the number of polarity inversions of the common electrode drive signal VCOM is reduced from the number of times in the frame period in which the refresh operation of the non-display region is performed, to reduce power consumption.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The above Patent Document 1 is specialized for low power consumption technology in a liquid crystal panel in which polarity inversion is a line inversion technique, and does not mention the relationship between the input frequency of input video data and the actual panel refresh rate.

[0005] In a display device in which a plurality of refresh rates are spatially and temporally mixed, when polarity inversion driving corresponding to the refresh rates is performed, a phenomenon occurs in which a voltage is continuously applied to the liquid crystal only with a biased polarity, which causes burn-in and flicker. Such a problem cannot be solved even by using the technique disclosed in the above Patent Document 1.

[0006] One aspect of this disclosure aims to provide a technology that suppresses burn-in and flicker even when displaying at multiple refresh rates. [Means for solving the problem]

[0007] To solve the above problems, a display device according to one aspect of the present disclosure includes a display panel including pixel electrodes and a common electrode that forms an electric field between itself and the pixel electrodes; a gate drive circuit that supplies a gate signal to the gate bus line of the display panel; a source drive circuit that supplies a pixel voltage to the pixel electrodes by sequentially supplying a source signal to the source bus line of the display panel; and a control circuit that controls a refresh rate, which is the frequency at which the image displayed on the display panel is rewritten. The source drive circuit drives the polarity of the source signal supplied to the source bus line with alternating current, and the control circuit controls the gate drive circuit and the source drive circuit so that in a partial area the pixel voltage is supplied at a first refresh rate, and in areas other than the partial area the pixel voltage is supplied at a second refresh rate, which is lower than the first refresh rate and has a frequency of one odd number of the first refresh rate.

[0008] To solve the above problems, a display device according to one aspect of the present disclosure includes a display panel including pixel electrodes and a common electrode that forms an electric field with the pixel electrodes; a gate drive circuit that supplies a gate signal to the gate bus line of the display panel; a source drive circuit that supplies a pixel voltage to the pixel electrodes by sequentially supplying source signals to the source bus line of the display panel; and a control circuit that controls the refresh rate, which is the frequency at which the image displayed on the display panel is rewritten. The source drive circuit drives the polarity of the source signal supplied to the source bus line with alternating current, and the control circuit controls the gate drive circuit and the source drive circuit so that in a partial area the pixel voltage is supplied at a first refresh rate, and in areas other than the partial area the pixel voltage is supplied at a second refresh rate, which is at a frequency lower than the first refresh rate and in which the polarity of the source signal is driven with alternating current. [Effects of the Invention]

[0009] According to one aspect of this disclosure, it is possible to suppress burn-in and flicker even when displaying at multiple refresh rates. [Brief explanation of the drawing]

[0010] [Figure 1] This diagram illustrates the principle of display methods in a display device that uses multiple refresh rates. [Figure 2] This diagram illustrates the principle of display methods in a display device that uses multiple refresh rates. [Figure 3] This figure shows an example configuration of a display device according to one embodiment of the present disclosure. [Figure 4] This is a circuit diagram showing the pixel configuration. [Figure 5] This is a block diagram showing an example of the configuration of a control circuit for a display device according to one embodiment of the present disclosure. [Figure 6] This diagram illustrates the changes in RAM-stored data. [Figure 7] This figure illustrates a polarity reversal driving method for a display device according to one embodiment of the present disclosure. [Figure 8] This is a block diagram showing an example of the configuration of a control circuit for a display device according to one embodiment of the present disclosure. [Figure 9] This figure illustrates a polarity reversal driving method for a display device according to one embodiment of the present disclosure. [Figure 10] This is a block diagram showing an example of the configuration of a control circuit for a display device according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0011] Hereinafter, one embodiment of the present disclosure will be described in detail with reference to the drawings. In the drawings, identical or substantially identical components will be denoted by the same reference numerals, and detailed descriptions will not be repeated.

[0012] (First embodiment) On laptops and other personal computers, it's very common to use windowed mode, displaying video content in only a portion of the screen while displaying still images in the rest, rather than just full-screen mode. This isn't limited to video content display; in business settings, it's common to refresh a portion of the screen while displaying almost the same content in word processing or spreadsheet software.

[0013] In laptops and other devices frequently used in this way, traditionally, even a partial update in the display would trigger a full update (scanning the panel / gate bus lines), limiting power consumption. However, recently, power consumption has been reduced by creating areas with different refresh rates within the screen.

[0014] However, in the case of liquid crystal displays, it is necessary to perform AC drive that inverts the positive polarity and negative polarity of the voltage applied to the liquid crystal. Accordingly, the present disclosure aims to provide a liquid crystal display that achieves AC drive for all areas by controlling the frequency of the input partial area data such that the other areas are controlled at 1 over an odd number of that frequency.

[0015] <Principle of Display Method in Display Device with Multiple Mixed Refresh Rates> First, the principle of the display method in a display device with multiple mixed refresh rates will be described. Figure 1 and Figure 2 are diagrams for explaining the principle of the display method in a display device with multiple mixed refresh rates.

[0016] As shown in Figure 1, for example, the display area is divided into three areas. The upper area is a still image area, which is refreshed at a low refresh rate of 8Hz, for example. Since the refresh rate frequency is low, display with low power consumption (Power Save) is possible. Note that in the present embodiment, among the display areas, an area with a relatively high refresh rate frequency is referred to as a partial area, and an area with a lower refresh rate than the partial area is referred to as the other areas.

[0017] The central area is a movie area, which is refreshed at a high refresh rate of 120Hz, for example. Since the refresh rate frequency is high, display performance can be maintained (Keep Performance).

[0018] The lower area is a still image area, which is refreshed at a low refresh rate of 8Hz, for example. Since the refresh rate frequency is low, display with low power consumption (Power Save) is possible.

[0019] As shown in Figure 2, the refresh rate is controlled by a control circuit (Tcon (Timing Controller)). As shown in the upper left of Figure 2, the image of the entire area is refreshed only once every 15 frames. As shown in the lower part of Figure 2, the image of the entire area is refreshed at frames #1, #16, #31, ... As a result, the entire area is refreshed at a low refresh rate of 8Hz.

[0020] Furthermore, as shown in the upper right of Figure 2, the image in the video area is refreshed 14 times every 15 frames. As shown in the lower part of Figure 2, the image in the video area is refreshed in frames #2-#15, #17-#30, #32-#45, ... As a result, the video area is refreshed at a high refresh rate of 120Hz.

[0021] <Example of display device configuration> Figure 3 is a diagram showing an example configuration of a display device according to one embodiment of the present disclosure. As shown in Figure 3, the display device 100 comprises a drive board 1, a display panel 2, and an FPC 4. A device comprising the display device 100 and a PC system-side motherboard 3 will be referred to as an electronic device.

[0022] The display device 100 is, for example, a display monitor, a personal computer, a tablet terminal, a smartphone, a smartwatch, or a television device. Alternatively, the display device 100 may be, for example, a liquid crystal display. The drive board 1 may be configured as an integrated device with the display device 100, or as a separate device from the display device 100.

[0023] Furthermore, the display device 100 may employ any of the following driving methods, such as FFS (Fringe Field Switching), IPS (In-Plane-Switching), TN (Twisted Nematic), or VA (Vertical Alignment). The following description will focus on the case where the display device 100 is a liquid crystal display device, but it is not limited to this.

[0024] The display panel 2 includes a gate drive circuit 21, a source drive circuit 22, a plurality of gate lines, and a plurality of source lines. The gate drive circuit 21 supplies gate signals to the gate bus line of the display panel 2. The source drive circuit 22 supplies pixel voltage to the pixel electrodes by sequentially supplying source signals to the source bus line of the display panel 2.

[0025] The number of gate lines is a natural number m. The number of source lines is a natural number n. The gate lines are arranged to intersect with the source lines. As an example, the display panel 2 will be described in the case where AC drive is employed, with the polarity of which reverses every frame period. Therefore, the source drive circuit 22 reverses the polarity of the source signal supplied to the source bus line.

[0026] Reversing positive and negative polarity does not necessarily have to be done alternately every frame. It is also acceptable to reverse it every few frames, or to write the same polarity consecutively to correct for polarity bias. In that case, the full screen area should be updated every odd number of frames.

[0027] The reversal of positive and negative polarity does not necessarily occur at regular intervals. This is because, in laptops, input video data is frequently not received at regular intervals. Even in this case, the partial area and the rest of the area are basically driven at an odd number of times (1).

[0028] Figure 4 is a circuit diagram showing the configuration of a pixel. The display panel 2 includes a pixel electrode 54 and a common electrode that forms an electric field between itself and the pixel electrode 54. As shown in Figure 4, thin-film transistors 53 and pixel electrodes 54 are arranged in regions (pixels) demarcated by a plurality of gate bus lines 51 and a plurality of source bus lines 52. The gate bus line 51 is connected to the gate electrode of the thin-film transistor 53. The source bus line 52 is connected to the source electrode of the thin-film transistor 53.

[0029] A pixel electrode 54 is connected to the drain electrode of a thin-film transistor 53. The display panel 2 is provided with a common electrode 55 that forms an electric field with the pixel electrode 54. The common electrode 55 is arranged to correspond to multiple pixel electrodes 54 (it is provided in common). The display panel 2 is provided with a common wiring 56 that connects the common electrode 55 to the drive substrate 1.

[0030] Depending on the transmission state of the pixel TFT driven by the gate drive circuit 21 and the source drive circuit 22, multi-color display is possible by transmitting light from a BL (bulb ray) provided on the back of a display panel 2 (not shown), or by using a color filter and a BM (black matrix) placed on one of the two glass substrates sandwiching the liquid crystal that does not have drive bus lines or source bus lines.

[0031] The drive board 1 includes a control circuit (Tcon) 11, a power supply IC (Integrated Circuit) 12, and a level shifter circuit 13. The power supply IC 12 generates the voltage required to drive the display device 100 from the 3.3V voltage supplied from the PC system motherboard 3.

[0032] The control circuit 11 generates and outputs the signals necessary to drive the gate drive circuit 21 and the source drive circuit 22 based on the video signal output from the PC system motherboard 3. The control circuit 11 also controls the refresh rate, which is the frequency at which the image displayed on the display panel 2 is rewritten. Further details of the control circuit 11 will be described later.

[0033] The level shifter circuit 13 converts the control signal for the gate drive circuit 21 output from the control circuit (Tcon) 11 to a voltage level that can drive the glass-embedded gate drive circuit 21 and outputs it. In some cases, it may also generate signals required by the gate drive circuit 21 that are not output from the control circuit 11.

[0034] The PC system motherboard 3 is equipped with a CPU (Central Processing Unit) or a GPU (Graphical Processing Unit) 31 and supplies image data corresponding to a partial area and image data corresponding to the entire screen to the display device 100. When the full-screen data is updated, the PC system motherboard 3 outputs the full-screen data to the control circuit 11, and when only the partial area data is updated, it outputs only the partial area data to the control circuit 11.

[0035] The FPC (Flexible Print Circuit) 4 is a component that connects the drive board 1 and the display panel 2 in order to supply power and various signals generated by the drive board 1 to the gate drive circuit 21 and source drive circuit 22 mounted on the display panel 2.

[0036] Figure 5 is a block diagram showing an example configuration of the control circuit 11 of a display device 100 according to one embodiment of the present disclosure. The control circuit 11 controls the gate drive circuit 21 and the source drive circuit 22 to supply a pixel voltage at a high refresh rate (first refresh rate) to the pixel electrodes corresponding to a partial area.

[0037] Furthermore, the control circuit 11 controls the gate drive circuit 21 and the source drive circuit 22 to supply a pixel voltage to the pixel electrodes corresponding to areas other than the partial area at a low refresh rate (second refresh rate) that is lower than the high refresh rate (first refresh rate) and in which the polarity of the source signal alternately inverts between positive and negative polarity.

[0038] As shown in Figure 5, the control circuit 11 includes an input signal receiving unit 111, a write area control unit 112, an input frequency determination unit 113, a RAM (Random Access Memory) 114, a full-screen refresh rate determination unit 115, a read area control unit 116, a source driver control signal generation unit 117, a level shifter control signal generation unit 118, a source driver control signal output unit 119, and a level shifter control signal output unit 120.

[0039] The input signal receiving unit 111 receives full-screen data or partial area data as an input signal from the PC system motherboard 3 via the input connector 14. The input signal receiving unit 111 receives full-screen data when full-screen data is updated, and receives only partial area data when only partial area data is updated.

[0040] The write area control unit 112 writes full-screen data or partial-area data received from the PC system motherboard 3 to the appropriate area of ​​RAM 114. As shown in Figure 6, when the write area control unit 112 receives full-screen data from the PC system motherboard 3, it updates the display data for the entire screen in RAM 114. When the write area control unit 112 receives partial-area data from the PC system motherboard 3, it updates only the display data for the corresponding area in RAM 114.

[0041] The input frequency determination unit 113 determines the high refresh rate frequency (input frequency). The high refresh rate, as described above, is the frequency at which the moving image area is refreshed, for example, 120 Hz.

[0042] The full-screen refresh rate determination unit 115 determines the frequency of the full-screen refresh rate. The full-screen refresh rate (second refresh rate) is, as described above, the frequency at which the entire screen (still image area + moving image area) is refreshed, and is determined to be a frequency that is an odd number of the input frequency (first refresh rate). For example, the full-screen refresh rate may be 40Hz, which is 1 / 3 of the input frequency, or 24Hz, which is 1 / 5 of the input frequency.

[0043] Furthermore, the full-screen refresh rate determination unit 115 determines the area to be refreshed at a high refresh rate and outputs it to the read area control unit 116 and the level shifter control signal generation unit 118. The full-screen refresh rate determination unit 115 outputs the area of ​​the RAM 114 where the partial area data is stored to the read area control unit 116. The full-screen refresh rate determination unit 115 also outputs the position information of the gate bus line corresponding to the partial area (control gate bus line position information) to the level shifter control signal generation unit 118.

[0044] The read area control unit 116 reads full-screen data or partial area data from the RAM 114 and outputs it as video signal information to the source driver control signal generation unit 117. When displaying frames that support a high refresh rate on the display panel 2, only partial area data is read from the RAM 114 and output to the source driver control signal generation unit 117. When displaying frames that support a low refresh rate on the display panel 2, full-screen data is read from the RAM 114 and output to the source driver control signal generation unit 117.

[0045] The source driver control signal generation unit 117 generates a control signal (source driver control signal) to be output to the source drive circuit 22 according to the video signal information output from the read area control unit 116, and outputs it to the source driver control signal output unit 119.

[0046] The source driver control signal output unit 119 outputs the source driver control signal generated by the source driver control signal generation unit 117 to the source drive circuit 22. As described above, the source drive circuit 22 inverts the polarity of the source signal supplied to the source bus line.

[0047] The level shifter control signal generation unit 118 generates a control signal (level shifter control signal) for controlling the level shifter circuit 13 according to the control gate bus line position information output from the full-screen refresh rate determination unit 115, and outputs it to the level shifter control signal output unit 120.

[0048] The level shifter control signal output unit 120 outputs the level shifter control signal generated by the level shifter control signal generation unit 118 to the level shifter circuit 13. When displaying frames that support a high refresh rate, the level shifter control signal output unit 120 outputs only the level shifter control signal corresponding to the partial area to the level shifter circuit 13.

[0049] Figure 7 is a diagram illustrating a polarity reversal drive method for a display device 100 according to one embodiment of the present disclosure. In Example 1 of Figure 7, the high refresh rate frequency (F1) is set to 120 Hz, the low refresh rate frequency (F2) is set to 40 Hz, and the leftmost frame is the first frame, followed by the second frame, the third frame, and so on.

[0050] In the first frame, only a portion of the screen is refreshed and driven with positive polarity. In the second frame, only a portion of the screen is refreshed and driven with negative polarity. In the third frame, the entire screen is refreshed and driven with positive polarity.

[0051] In the fourth frame, only a portion of the screen is refreshed and driven with negative polarity. In the fifth frame, only a portion of the screen is refreshed and driven with positive polarity. In the sixth frame, the entire screen is refreshed and driven with negative polarity.

[0052] Thus, in frames corresponding to a high refresh rate (120Hz), positive and negative polarity drives are performed alternately, and in frames corresponding to a low refresh rate (40Hz), positive and negative polarity drives are also performed alternately.

[0053] In Example 2 of Figure 7, the high refresh rate frequency (F1) is set to 120Hz, and the low refresh rate frequency (F2) is set to 24Hz. The leftmost frame is the first frame, followed by the second frame, the third frame, and so on.

[0054] In frames 1 through 4, only a portion of the screen is refreshed, and positive and negative polarity drives alternate. In frame 5, the entire screen is refreshed, and positive polarity drives are performed.

[0055] In frames 6 through 9, only a portion of the screen is refreshed, and negative and positive polarity drives alternate. In frame 10, the entire screen is refreshed, and negative polarity drives are performed.

[0056] Thus, in frames corresponding to a high refresh rate (120Hz), positive and negative polarity drives are performed alternately, and in frames corresponding to a low refresh rate (24Hz), positive and negative polarity drives are also performed alternately.

[0057] <Effects and Effects> As described above, according to one embodiment of this disclosure, the following effects and advantages can be obtained.

[0058] In a display device 100 that uses a polarity inversion drive method that inverts the polarity of the source signal supplied to the source bus line every frame period, the control circuit 11 refreshes only a portion of the display panel 2 when displaying a frame corresponding to a high refresh rate. When displaying a frame corresponding to a low refresh rate on the display panel 2, it refreshes the entire screen area. Furthermore, the frequency of the low refresh rate is set to 1, which is an odd number of the frequency of the high refresh rate. As a result, positive polarity drive and negative polarity drive are performed alternately for frames corresponding to the high refresh rate, and also alternately for frames corresponding to the low refresh rate. Therefore, even when displaying at multiple refresh rates, it is possible to suppress burn-in and flicker.

[0059] (Second embodiment) In practice, when a display device is used as a laptop, attempting to achieve performance using only a fixed odd value can result in insufficient power saving, or even cause screen burn-in or flicker. Unlike televisions, the input frequency of a laptop varies depending on the content being displayed. For example, 24Hz is common for movie content, while faster frequencies such as 120Hz are used for live sports broadcasts like soccer to enhance the sense of realism. On platforms like YouTube, the frequency may also be determined by the creator based on their camera specifications or the specifications of their editing PC.

[0060] Furthermore, each LCD display has its own minimum refresh rate, which varies from display to display. Therefore, by selecting an odd number that is the maximum refresh rate while not falling below this minimum refresh rate setting, it becomes possible to achieve a high power saving effect and enable the simultaneous operation of multiple refresh rates while maintaining display quality.

[0061] For example, let's set a fixed odd number to 3, the next smallest after 1, to determine the low refresh rate, and assume that the minimum refresh rate of the liquid crystal display is F3 = 8Hz. In this case, if the input frequency F1 = 120Hz, the low refresh rate frequency F2 will be 40Hz. If the input frequency F1 = 60Hz, the low refresh rate frequency F2 will be 20Hz. If the input frequency F1 = 24Hz, the low refresh rate frequency F2 will be 8Hz.

[0062] Although none of them will fail as they do not fall below the minimum refresh rate F3, at an input frequency F1=120Hz, the low refresh rate frequency becomes 40Hz, which does not contribute sufficiently to reducing power consumption.

[0063] Furthermore, a fixed odd number is set to 15 to determine the low refresh rate, and the minimum refresh rate of the liquid crystal display is assumed to be F3 = 8Hz. In this case, if the input frequency F1 = 120Hz, the low refresh rate frequency F2 will be 8Hz. If the input frequency F1 = 60Hz, the low refresh rate frequency F2 will be 4Hz. If the input frequency F1 = 24Hz, the low refresh rate frequency F2 will be 1.6Hz.

[0064] At an input frequency F1=120Hz, the power reduction effect is greater than when a fixed odd number of 3 is used. However, at F1=60Hz and F1=24Hz, the refresh rate falls below the minimum refresh rate of the LCD, which can cause burn-in or flicker.

[0065] Furthermore, if we define the low refresh rate as the value obtained by dividing the input frequency by the largest odd number (a positive integer odd number) that does not fall below the minimum refresh rate F3=8Hz of the LCD display, then with an input frequency F1=120Hz, the fixed odd number is 15, and the low refresh rate frequency F2 is 8Hz. Also, with an input frequency F1=60Hz, the fixed odd number is 7, and the low refresh rate frequency F2 is 8.6Hz. Also, with an input frequency F1=24Hz, the fixed odd number is 3, and the low refresh rate frequency F2 is 8Hz.

[0066] In all cases, the low refresh rate frequency is around 8Hz, resulting in a significant power saving effect, while never falling below the minimum refresh rate for an LCD display, thus ensuring no impact on display quality. Thus, depending on the input frequency F1, it is necessary to increase the odd value from a small value, find the maximum value while F2 does not fall below F3, and adopt that value.

[0067] <Example of display device configuration> A display device according to one embodiment of this disclosure differs from the display device 100 according to the first embodiment only in the configuration of the control circuit. Hereinafter, the reference numeral 11A will be used to denote the reference numeral of the control circuit according to this embodiment.

[0068] Figure 8 shows an example of the configuration of the control circuit 11A of a display device 100 according to one embodiment of the present disclosure. As shown in Figure 8, the control circuit 11A includes an input signal receiving unit 111, a write area control unit 112, an input frequency determination unit 113, a RAM (Random Access Memory) 114, a full-screen refresh rate determination unit 115A, a read area control unit 116, a source driver control signal generation unit 117, a level shifter control signal generation unit 118, a source driver control signal output unit 119, a level shifter control signal output unit 120, and an internal register 121.

[0069] The internal register 121 holds the setting value for the minimum refresh rate (first predetermined refresh rate). For example, let's assume that 8Hz is set as the minimum refresh rate in the internal register 121.

[0070] The full-screen refresh rate determination unit 115A determines the full-screen refresh rate by dividing the input frequency by the largest odd number that is not less than the minimum refresh rate stored in the internal register 121. If the minimum refresh rate is set to 8Hz, the largest odd number is 15, so the full-screen refresh rate determination unit 115A sets the full-screen refresh rate frequency to 8Hz.

[0071] Furthermore, the full-screen refresh rate determination unit 115A determines the area to be refreshed at a high refresh rate and outputs it to the read area control unit 116 and the level shifter control signal generation unit 118. The full-screen refresh rate determination unit 115 outputs the area of ​​RAM 114 where partial area data is stored to the read area control unit 116. The full-screen refresh rate determination unit 115 also outputs the position information of the gate bus line corresponding to the partial area (control gate bus line position information) to the level shifter control signal generation unit 118.

[0072] Figure 9 is a diagram illustrating a polarity reversal driving method for a display device according to one embodiment of the present disclosure. Figure 9 shows a case where the input frequency switches from 120Hz to 24Hz, and the input frequency is 120Hz in frames N to N+15. When the input frequency is 120Hz, a full-screen refresh is performed in frames N and N+15.

[0073] Furthermore, the input frequency operates at 24Hz from the N+16th frame onward. When the input frequency is 24Hz, a full-screen refresh occurs at the N+18th frame. When the input frequency is 24Hz, the maximum odd number is 3, and the full-screen refresh rate frequency becomes 8Hz.

[0074] <Effects and Effects> As described above, according to one embodiment of this disclosure, the following effects and advantages can be obtained.

[0075] In a display device 100 that uses a polarity inversion drive method that inverts the polarity of the source signal supplied to the source bus line every frame period, the full-screen refresh rate determination unit 115A of the control circuit 11A sets the full-screen refresh rate to the value obtained by dividing the input frequency by the largest odd number that does not fall below the minimum refresh rate stored in the built-in register 121. Therefore, the frequency of the full-screen refresh rate can be set to a value close to the minimum refresh rate, further reducing power consumption and enabling mixed driving of multiple refresh rates while maintaining display quality. Note that the setting value stored in the built-in register 121 is not limited to the frequency of the minimum refresh rate, but may be any other predetermined frequency.

[0076] (Third embodiment) In practice, when a display device is used as a laptop, video data may not be transmitted from the system to the LCD module. This is especially true when displaying still images rather than videos. This situation can occur when using Office software, displaying screen savers, or during periods when the user is not touching input devices such as the keyboard or mouse.

[0077] In such cases, even with a liquid crystal module capable of handling multiple refresh rates, power consumption may be reduced by driving the entire screen at a fixed minimum frequency. In this case, the frequency may be set to a value smaller than the minimum refresh rate (first minimum refresh rate) described in the second embodiment (second refresh rate). This is used in driving situations where multiple refresh rates cannot be handled simultaneously, by using the value of the second minimum refresh rate.

[0078] <Example of display device configuration> A display device according to one embodiment of this disclosure differs from the display device 100 according to the first embodiment only in the configuration of the control circuit. Hereinafter, the reference numeral 11B will be used to denote the reference numeral of the control circuit according to this embodiment.

[0079] Figure 10 shows an example of the configuration of the control circuit 11B of a display device 100 according to one embodiment of the present disclosure. As shown in Figure 10, the control circuit 11B includes an input signal receiving unit 111, a write area control unit 112, an input frequency determination unit 113, a RAM (Random Access Memory) 114, a full-screen refresh rate determination unit 115A, a read area control unit 116, a source driver control signal generation unit 117, a level shifter control signal generation unit 118, a source driver control signal output unit 119, a level shifter control signal output unit 120, and built-in registers 121-1 and 121-2.

[0080] Internal register 121-1 holds the minimum refresh rate setting. For example, let's assume that 24Hz is set as the minimum refresh rate in internal register 121-1.

[0081] Furthermore, the internal register 121-2 holds a value smaller than the minimum refresh rate setting (the second minimum refresh rate (second predetermined refresh rate)). For example, let's assume that 4Hz is set as the setting for the second minimum refresh rate in the internal register 121-2.

[0082] The full-screen refresh rate determination unit 115B determines the full-screen refresh rate by dividing the input frequency by the largest odd number that does not fall below the minimum refresh rate stored in the internal register 121-1. If the minimum refresh rate is set to 24Hz, the largest odd number is 5, so the full-screen refresh rate determination unit 115A sets the full-screen refresh rate frequency to 24Hz.

[0083] Furthermore, if no screen data is input from the PC system motherboard 3 for a predetermined period of time, the full-screen refresh rate determination unit 115B sets the value of the second minimum refresh rate stored in the internal register 121-2 as the full-screen refresh rate frequency. In this case, since high refresh rate refresh is unnecessary, only the full-screen refresh rate refresh operation is performed.

[0084] <Effects and Effects> As described above, according to one embodiment of this disclosure, the following effects and advantages can be obtained.

[0085] In a display device 100 that uses a polarity inversion drive method that inverts the polarity of the source signal supplied to the source bus line every frame period, the full-screen refresh rate determination unit 115A of the control circuit 11A sets the value of the second minimum refresh rate stored in the built-in register 121-1 as the full-screen refresh rate frequency when there is no screen data input from the PC system motherboard 3. Therefore, if there is no screen data input from the PC system motherboard 3 for a predetermined time, the full-screen refresh rate frequency can be reduced, further reducing power consumption.

[0086] <Variation> Note that the internal register 121-2 may hold a setting value that is not smaller than the minimum refresh rate (first minimum refresh rate) held by the internal register 121-1, but rather the same as the minimum refresh rate (first minimum refresh rate) held by the internal register 121-1 (second minimum refresh rate (second predetermined refresh rate)). For example, the internal register 121-2 may be set to 4Hz as the setting value for the second minimum refresh rate.

[0087] If no screen data is input from the PC system motherboard 3 for a predetermined period of time, the full-screen refresh rate determination unit 115B sets the value of the second minimum refresh rate stored in the internal register 121-2 as the full-screen refresh rate frequency. In this case, since high refresh rate refresh is unnecessary, only the full-screen refresh rate refresh operation is performed.

[0088] Even in this modified case, if there is no screen data input from the PC system motherboard 3 for a predetermined period of time, the full-screen refresh rate frequency can be reduced, thereby reducing power consumption.

[0089] In the modified configuration, the control circuit 11B may be configured without the built-in register 121-2, and the full-screen refresh rate determination unit 115B may use the value of the minimum refresh rate stored in the built-in register 121-1 as the full-screen refresh rate frequency if there is no screen data input from the PC system motherboard 3 for a predetermined period of time.

[0090] 〔summary〕 This disclosure includes at least the following aspects:

[0091] (Aspect 1) A display device according to Embodiment 1 of the present disclosure includes a display panel including pixel electrodes and a common electrode that forms an electric field between itself and the pixel electrodes; a gate drive circuit that supplies a gate signal to the gate bus line of the display panel; a source drive circuit that supplies a pixel voltage to the pixel electrodes by sequentially supplying source signals to the source bus line of the display panel; and a control circuit that controls a refresh rate, which is the frequency at which the image displayed on the display panel is rewritten. The source drive circuit drives the polarity of the source signal supplied to the source bus line with alternating current, and the control circuit controls the gate drive circuit and the source drive circuit so that in a partial area the pixel voltage is supplied at a first refresh rate, and in areas other than the partial area the pixel voltage is supplied at a second refresh rate, which is lower than the first refresh rate and has a frequency of one odd number of the first refresh rate.

[0092] (Aspect 2) A display device according to aspect 2 of the present disclosure includes a display panel including pixel electrodes and a common electrode that forms an electric field with the pixel electrodes; a gate drive circuit that supplies a gate signal to the gate bus line of the display panel; a source drive circuit that supplies a pixel voltage to the pixel electrodes by sequentially supplying source signals to the source bus line of the display panel; and a control circuit that controls a refresh rate, which is the frequency at which the image displayed on the display panel is rewritten. The source drive circuit drives the polarity of the source signal supplied to the source bus line with alternating current, and the control circuit controls the gate drive circuit and the source drive circuit so that in a partial area the pixel voltage is supplied at a first refresh rate, and in areas other than the partial area the pixel voltage is supplied at a second refresh rate, which is at a frequency lower than the first refresh rate and in which the polarity of the source signal is driven with alternating current.

[0093] (Aspect 3) In the display device according to embodiment 3 of the present disclosure, in embodiment 2 described above, the second refresh rate is a frequency of one odd number of the first refresh rate.

[0094] (Aspect 4) A display device according to aspect 4 of the present disclosure further comprises a first register for storing a first predetermined refresh rate in any of aspects 1 to 3 above, and the control circuit sets the second refresh rate to a value obtained by dividing the frequency of the first refresh rate by the largest odd number that is not less than the first predetermined refresh rate.

[0095] (Appendix 5) The display device according to aspect 5 of the present disclosure further comprises a second register for storing a second predetermined refresh rate, and the control circuit sets the frequency of the second predetermined refresh rate stored in the second register to the frequency of the second refresh rate when there is no input of screen data from an external source.

[0096] (Aspect 6) The display device according to embodiment 6 of the present disclosure further comprises a second register for storing a second predetermined refresh rate, and the control circuit sets the second predetermined refresh rate stored in the second register to a frequency lower than the frequency of the second refresh rate when there is no input of screen data from an external source.

[0097] (Aspect 7) A method for driving a display device according to aspect 7 of this disclosure is the method for driving a display device described in any of aspects 1 to 3 above.

[0098] (Pattern 8) The electronic device according to aspect 8 of this disclosure comprises a display device as described in any of aspects 1 to 3 above, and a motherboard that supplies image data corresponding to a partial area and image data corresponding to the entire screen to the display device.

[0099] This disclosure is not limited to the embodiments described above, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of this disclosure. [Explanation of Symbols]

[0100] 1. Drive board 2 Display Panel 3. PC system motherboard 4 FPC 11, 11A, 11B control circuit (Tcon) 12 Power IC 13 Level Shifter Circuit 21 Gate drive circuit 22 Source Drive Circuit 100 display device 111 Input signal receiving unit 112 Writing Area Control Unit 113 Input frequency determination unit 114 RAM 115, 115A, 115B Full-screen refresh rate determination section 116 Read Area Control Unit 117 Source driver control signal generation unit 118 Level Shifter Control Signal Generation Unit 119 Source driver control signal output section 120 Level Shifter Control Signal Output Section 121, 121-1, 121-2 Internal Registers

Claims

1. A display panel including a pixel electrode and a common electrode that forms an electric field between the pixel electrode, A gate drive circuit that supplies a gate signal to the gate bus line of the display panel, A source drive circuit that supplies a pixel voltage to the pixel electrode by sequentially supplying source signals to the source bus line of the display panel, The system includes a control circuit that controls the refresh rate, which is the frequency at which the image displayed on the display panel is rewritten, The source drive circuit drives the polarity of the source signal supplied to the source bus line with AC power. A display device comprising a control circuit that controls the gate drive circuit and the source drive circuit so as to supply the pixel voltage at a first refresh rate in a partial area, and at a second refresh rate lower than the first refresh rate and having a frequency of one odd number of the first refresh rate in areas other than the partial area.

2. A display panel including a pixel electrode and a common electrode that forms an electric field between the pixel electrode, A gate drive circuit that supplies a gate signal to the gate bus line of the display panel, A source drive circuit that supplies a pixel voltage to the pixel electrode by sequentially supplying source signals to the source bus line of the display panel, The system includes a control circuit that controls the refresh rate, which is the frequency at which the image displayed on the display panel is rewritten, The source drive circuit drives the polarity of the source signal supplied to the source bus line with AC power. A display device comprising a control circuit that controls the gate drive circuit and the source drive circuit so that the control circuit supplies the pixel voltage at a first refresh rate in a partial area, and supplies the pixel voltage at a second refresh rate with a frequency lower than the first refresh rate and in areas other than the partial area, wherein the polarity of the source signal is AC driven.

3. The display device according to claim 2, wherein the second refresh rate is a frequency of one odd number of the first refresh rate.

4. The system further comprises a first register for storing a first predetermined refresh rate, The display device according to any one of claims 1 to 3, wherein the control circuit divides the frequency of the first refresh rate by the largest odd number that does not fall below the first predetermined refresh rate, and the result of this division is the second refresh rate.

5. The system further comprises a second register for storing a second predetermined refresh rate, The display device according to claim 4, wherein, when there is no input of screen data from an external source, the control circuit sets the frequency of the second predetermined refresh rate stored in the second register to the frequency of the second refresh rate.

6. The system further comprises a second register for storing a second predetermined refresh rate, The display device according to claim 4, wherein, when there is no input of screen data from an external source, the control circuit sets the second predetermined refresh rate stored in the second register to a frequency lower than the frequency of the second refresh rate.

7. A method for driving a display device according to any one of claims 1 to 3.

8. An electronic device comprising a display device according to any one of claims 1 to 3, and a motherboard that supplies image data corresponding to a partial area and image data corresponding to the entire screen to the display device.

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