semiconductor element

Abstract

The present invention provides a semiconductor device that can reduce leakage current in a configuration having a passivation film. [Solution] The semiconductor element 1 comprises an anode 10 and a cathode 20, a main semiconductor layer 30 sandwiched between the anode 10 and the cathode 20 and including a pn junction of a p-type semiconductor layer 31 and an n-type semiconductor layer 32, a passivation film 40 covering the space between the anode 10 or cathode 20 and the p-type semiconductor layer 31 and the p-type semiconductor layer, and a local insulating layer 50 locally provided in contact with at least the p-type semiconductor layer 31 and the n-type semiconductor layer 32, wherein the opposing surfaces of the local insulating layer 50 that are in contact with at least the p-type semiconductor layer 31 and the n-type semiconductor layer 32 are covered with the passivation film 40.

Description

TECHNICAL FIELD

[0001] The present invention mainly relates to a semiconductor element such as a mesa diode.

BACKGROUND ART

[0002] Conventionally, for the purpose of improving the breakdown voltage of semiconductor elements, a technique is known in which a mesa groove is provided on the side surface including the boundary of the pn junction of a semiconductor, and the surface of the mesa groove is covered with a passivation film such as glass.

[0003] FIG. 16 is a cross-sectional view showing the configuration of a semiconductor element according to the conventional technique. The conventional semiconductor element 100 is a single-mote type mesa diode having a rectangular outer shape in plan view. As shown in FIG. 16, the semiconductor element 100 mainly includes an anode 10, a cathode 20, and a main semiconductor layer 30 sandwiched between the anode 10 and the cathode 20 in a cross-sectional view.

[0004] The main semiconductor layer 30 is configured as a laminate of a p-type semiconductor layer 31 on which the anode 10 is disposed and an n-type semiconductor layer 32 on which the cathode 20 is disposed. The n-type semiconductor layer 32 has an n- layer 32a which has a lower impurity concentration and is located closer to the anode 10, and an n+ layer 32b which has a higher impurity concentration and is located closer to the cathode 20, according to the concentration difference of the contained impurities.

[0005] In the main semiconductor layer 30, on the side surface including a pair of opposing surfaces where the pn junction surface I1, which is the boundary between the p-type semiconductor layer 31 and the n-type semiconductor layer 32, is exposed, a mesa groove 30x having a concavely curved contour that forms a semi-U shape in cross-sectional view is formed. Further, the pair of opposing surfaces of the n-type semiconductor layer 32 where the boundary between the n- layer 32a and the n+ layer 32b is exposed are directly exposed to the outside as the end faces 30a of the semiconductor element 100.

[0006] Further, in the main semiconductor layer 30, an insulating passivation film 40 having a shape along the outer contour of the mesa groove 30x is provided on the surface of the mesa groove 30x. The passivation film 40 is made of, for example, Si glass.

[0007] A semiconductor element 100 having a mesa groove 30x with the above configuration is said to have excellent voltage resistance and be suitable for use with high currents, and is particularly suitable for rectifier diodes and the like (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 55-115337 [Overview of the project] [Problems that the invention aims to solve]

[0009] The conventional semiconductor device 100 described above had the following problems. Specifically, in the semiconductor device 100, the passivation film 40 is provided to cover and protect the pn junction surface I1 of the main semiconductor layer 30, and to increase the depletion layer width on the surface of the mesa groove 30x in order to improve the breakdown voltage. However, it also constitutes a path for leakage current that travels from the cathode 20 to the end face 30a of the main semiconductor layer 30. The generation of leakage current can cause localized heating of the semiconductor device 100, and ultimately lead to thermal runaway.

[0010] Therefore, the main objective of the present invention is to provide a semiconductor device that can reduce leakage current in a configuration having a passivation film. [Means for solving the problem]

[0011] The first aspect of the present invention is a semiconductor device comprising an anode and a cathode; a main semiconductor layer sandwiched between the anode and the cathode, including a pn junction of a first semiconductor layer and a second semiconductor layer separated from each other by a charge carrier; a passivation film covering the space between the anode or the cathode and the first semiconductor layer or the second semiconductor layer; and a locally provided insulating layer in contact with at least the first semiconductor layer or the second semiconductor layer, wherein the surface of the local insulating layer opposite the surface in contact with at least the first semiconductor layer or the second semiconductor layer is covered with the passivation film.

[0012] The second aspect of the present invention is a semiconductor element of the first aspect of the present invention, comprising a mesa groove formed on the side surface of the main semiconductor layer, straddling the boundary between the first semiconductor layer and the second semiconductor layer, the passivation film covering the mesa groove, and the local insulating layer provided within the mesa groove.

[0013] The third aspect of the present invention is a semiconductor element of the second aspect of the present invention, wherein the local insulating layer is provided at the lowest part of the mesa groove in a direction along the stacking direction of the first semiconductor layer and the second semiconductor layer.

[0014] The fourth aspect of the present invention is a semiconductor element of the third aspect of the present invention, wherein the local insulating layer is provided at a position that coincides with the side surface of the main semiconductor layer and is exposed to the outside, and is therefore exposed to the outside.

[0015] The fifth aspect of the present invention is a semiconductor device according to the fourth aspect of the present invention, wherein the thickness of the local insulating layer is 2000 Å or more.

[0016] The sixth aspect of the present invention is a semiconductor device of the fourth aspect of the present invention, wherein the maximum width of the local insulating layer is such that, in a view orthogonal to the stacking direction of the first semiconductor layer and the second semiconductor layer, the distance from the stacking boundary of the first semiconductor layer and the second semiconductor layer to the inner edge of the local insulating layer is less than the thickness of the semiconductor layer having a lower concentration in the first or second semiconductor layer of the main semiconductor layer.

[0017] A seventh aspect of the present invention provides a semiconductor element comprising: an anode and a cathode; a main semiconductor layer including a pn junction of a first semiconductor layer and a second semiconductor layer, which are distinguished from each other by charge carriers, and is sandwiched between the anode and the cathode; a passivation film covering between the anode or the cathode and the first semiconductor layer or the second semiconductor layer; and a local insulating layer locally provided in contact with at least the first semiconductor layer or the second semiconductor layer, wherein the local insulating layer is provided at a position on a side surface of the main semiconductor layer and inside an end face exposed to the outside.

Effects of the Invention

[0018] According to the present invention, it is possible to provide a semiconductor element capable of reducing leakage current in a configuration having a passivation film.

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments for carrying out the invention with reference to the drawings.

Brief Description of the Drawings

[0020] [Figure 1] It is a cross-sectional view showing the configuration of the semiconductor element according to the embodiment of the present invention. [Figure 2] It is a cross-sectional view for explaining the behavior of a semiconductor element according to a conventional configuration when a voltage is applied. [Figure 3] It is a cross-sectional view for explaining the operational effects of the semiconductor element according to the embodiment of the present invention. [Figure 4] It is a cross-sectional view for explaining the behavior of a semiconductor element according to a conventional configuration when a voltage is applied. [Figure 5] It is a cross-sectional view for explaining the operational effects of the semiconductor element according to the embodiment of the present invention. [Figure 6] It is a cross-sectional view of a principal part for explaining the configuration of the semiconductor element according to the embodiment of the present invention. [Figure 7]This figure illustrates the conditions for the thickness dimension of the local insulating layer in a semiconductor device according to an embodiment of the present invention. [Figure 8] This figure illustrates the conditions for the width dimension of the local insulating layer in a semiconductor device according to an embodiment of the present invention. [Figure 9A] (A) This figure illustrates the conditions for the width dimension of the local insulating layer in a semiconductor device according to an embodiment of the present invention. (B) This figure illustrates the conditions for the width dimension of the local insulating layer in a semiconductor device according to an embodiment of the present invention. [Figure 9B] (C) This figure illustrates the conditions for the width dimension of the local insulating layer in a semiconductor device according to an embodiment of the present invention. [Figure 10] This figure illustrates the conditions for the width dimension of the local insulating layer in a semiconductor device according to an embodiment of the present invention. [Figure 11] (A) This figure illustrates the conditions for the width dimension of the local insulating layer in a semiconductor device according to an embodiment of the present invention. (B) This figure illustrates the conditions for the width dimension of the local insulating layer in a semiconductor device according to an embodiment of the present invention. [Figure 12] This figure illustrates the conditions for the width dimension of the local insulating layer in a semiconductor device according to an embodiment of the present invention. [Figure 13] This is a cross-sectional view showing the configuration of a semiconductor element according to a modified example of the present invention. [Figure 14] (A) A cross-sectional view showing the configuration of a semiconductor element according to a modified example of the present invention. (B) A cross-sectional view showing the configuration of a semiconductor element according to a modified example of the present invention. (C) A cross-sectional view showing the configuration of a semiconductor element according to a modified example of the present invention. (D) A cross-sectional view showing the configuration of a semiconductor element according to a modified example of the present invention. [Figure 15] This is a cross-sectional view showing the configuration of a semiconductor element according to a modified example of the present invention. [Figure 16] This is a cross-sectional view showing the configuration of a semiconductor device using a conventional design. [Modes for carrying out the invention]

[0021] The semiconductor device of the present invention will be described below in this embodiment.

[0022] A semiconductor element according to an embodiment of the present invention will now be described. Figure 1 is a cross-sectional view showing the configuration of the semiconductor element 1. However, components that are the same as or equivalent to those in the conventional example shown in Figure 16 are denoted by the same reference numerals, and detailed explanations of common components and operations are omitted.

[0023] As shown in Figure 1, the semiconductor element 1 according to an embodiment of the present invention further comprises a local insulating layer 50 in addition to the configuration of a conventional semiconductor element 100, which is a single-moat type mesa diode having a rectangular shape in plan view.

[0024] The local insulating layer 50 is provided within the mesa groove 30x in the main semiconductor layer 30 of the semiconductor device 1. Specifically, the local insulating layer 50 is provided on the n+ layer 32b of the n-type semiconductor layer 32, which is the lowest part of the mesa groove 30x, in a direction along the stacking direction of the p-type semiconductor layer 31 and the n-type semiconductor layer 32, and is located at a position that coincides with the externally exposed end face 30a of the main semiconductor layer 30. Furthermore, the local insulating layer 50 is arranged to be embedded in the passivation film 40, and only the end face 50b that is flush with the end face 30a of the main semiconductor layer 30 is exposed to the outside. In other words, the local insulating layer 50 has a configuration in which at least the top surface 50a, which is the surface facing the contact surface with the main semiconductor layer 30, is covered by the passivation film 40.

[0025] In the semiconductor device 1, the compositions of the local insulating layer 50 and the passivation film 40 are preferably as follows. The passivation film 40 is preferably a glass structure mainly composed of SiO2 and containing Al2O3, B2O3, PbO2, ZnO2, and Ba-based oxides as additives, and may also be semi-insulating polysilicon (SIPOS). The local insulating layer 50 is preferably mainly composed of an insulating SiO2 film, an insulating SiN film, or an insulating SiON film.

[0026] A semiconductor element 1 according to an embodiment of the present invention having the above configuration is characterized in that the main semiconductor layer 30 of the semiconductor element 1 includes a local insulating layer 50 provided within a mesa groove 30x.

[0027] As shown in Figure 2, consider a conventional semiconductor device 100 in a state where a reverse bias is applied. This is a state where a negative voltage is applied to the anode 10 and a positive voltage is applied to the cathode 20. At this time, depletion layers are formed on both sides of the pn junction surface I1. A depletion layer edge 60 is formed within the n-type semiconductor layer 32.

[0028] The passivation film 40 contains additives that induce minority carriers in the main semiconductor layer 30 directly beneath the passivation film 40 and near the interface I2. As a result, a depletion layer is formed in the mesa groove 30x, which is the interface I2 between the passivation film 40 and the n-type semiconductor layer 32, toward the n-type semiconductor layer 32. Consequently, the depletion layer edge 60 is also formed at the edge 30a of the semiconductor layer 30, becoming the edge 60a.

[0029] As shown in Figure 3, in the semiconductor element 1 according to an embodiment of the present invention, the local insulating layer 50 is provided in a position close to the end face 30a of the main semiconductor layer 30, more specifically, in a position where only the end face 50b that is flush with the end face 30a is exposed to the outside. In the n-layer 32a directly beneath the local insulating layer 50, dangling bonds (unbonded covalent bonds) are generated due to the reaction during the formation of the local insulating layer 50, and negative charges are generated due to these dangling bonds. Therefore, the formation of the inversion layer 70 is prevented at the interface between the local insulating layer 50 and the n-layer 32a. Consequently, the depletion layer edge 60 does not reach the end face 30a as shown by edge 60a in Figure 2, but remains inside the n-type semiconductor layer 32 beyond the edge of the local insulating layer 50, as shown by edge 60b, and the leakage current path is blocked.

[0030] This reduces the leakage current in the semiconductor device 1 having the passivation film 40.

[0031] The semiconductor element 1 according to an embodiment of the present invention is characterized by having a local insulating layer 50 in the main semiconductor layer 30, which is provided such that only the end face 50b that is flush with the end face 30a of the main semiconductor layer 30 and is located within the mesa groove 30x is exposed to the outside.

[0032] As shown in Figure 4, in the conventional semiconductor device 100, negative fixed charges are generated on the passivation film 40 side near the interface I2 between the mesa groove 30x and the passivation film 40, and fractional carriers tend to accumulate very easily in the n-type semiconductor layer 32 near the interface I2. As a result, an inversion layer 70 is formed on the side of the interface I2 closer to the main semiconductor layer 30. Since the inversion layer 70 has a polarity close to that of the p-type semiconductor layer 31 with respect to the n-type semiconductor layer 32, a conductive path is formed within the n-type semiconductor layer 32, which forms a leakage current path along the interface I2.

[0033] In contrast, as shown in Figure 5, in the semiconductor element 1 according to an embodiment of the present invention, the formation of the inversion layer 70 is prevented in the n-layer 32a directly beneath the local insulating layer 50 due to negative charges caused by a dangling bond. As a result, the formation of a leakage current path along the interface I2 is suppressed.

[0034] This reduces the leakage current in the semiconductor device 1 having the passivation film 40.

[0035] Next, the semiconductor element 1 according to an embodiment of the present invention is characterized by having a local insulating layer 50 in the main semiconductor layer 30, which is provided such that only the end face 50b that is flush with the end face 30a of the main semiconductor layer 30 and is located within the mesa groove 30x is exposed to the outside. This provides the following further advantages.

[0036] In other words, as shown in Figure 4, in a conventional semiconductor device 100, the end face 30a of the main semiconductor layer 30 is obtained by breaking down the semiconductor wafer that serves as the substrate into smaller pieces in a chip splitting process. Generally, the chip splitting process involves scribing the chip with a dicing blade, so the chip end face, i.e., the completed end face 30a, is formed as a damaged portion 71 where the crystal is partially broken. Because the damaged portion 71 has the property of conducting current more easily than other parts of the main semiconductor layer 30, the damaged portion 71, including the end face 30a, together with the inversion layer 70 forms a path for leakage current.

[0037] In contrast, as shown in Figure 5, in the semiconductor element 1 according to an embodiment of the present invention, the local insulating layer 50 is provided such that only the end face 50b that is flush with the end face 30a of the main semiconductor layer 30 is exposed to the outside, thereby insulating the inversion layer 70 within the main semiconductor layer 30 from the damaged portion 71. This prevents the formation of a leakage current path from the damaged portion 71 to the inversion layer 70.

[0038] This reduces the leakage current in the semiconductor device 1 having the passivation film 40.

[0039] In semiconductor device 1, the local insulating layer 50 has a configuration in which at least the surface facing the contact surface with the main semiconductor layer 30 is covered with a passivation film 40. This simplifies the formation of the passivation film 40. In other words, after forming the local insulating layer 50 in the mesa groove 30X, the material that will become the passivation film 40 is applied by spin coating, and before solidification, the parts other than the mesa groove 30x are removed with a squeegee. Thus, the passivation film 40 can be easily formed without using an electrodeposition process to prevent the passivation film 40 from forming on the local insulating layer 50.

[0040] Next, the appropriate conditions for the dimensions of the local insulating layer 50 in the semiconductor device 1 will be explained with reference to Figure 6. As shown in Figure 6, in a cross-sectional view of the semiconductor device 1, when the stacking direction of the p-type semiconductor layer 31 and the n-type semiconductor layer 32 is defined as the height direction, and the direction perpendicular to the height direction in which the contour shape of the mesa groove 30x can be seen is defined as the width direction, it is preferable that the thickness dimension Tox and the width dimension Wox of the local insulating layer 50 are defined as follows.

[0041] First, let's explain the thickness of the local insulating layer 50. The dimension Tox in the thickness direction of the local insulating layer 50 can be any value. The theoretical minimum dimension is sufficient if an oxide film is present in the mesa groove, and the theoretical maximum dimension is unlimited, however, for manufacturing purposes, it is preferable to be 2000 Å or more, referring to the simulation diagram in Figure 7. Here, Figure 7 is a simulation diagram showing the dependence of the rate of change of the leakage current IR on the dimension in the thickness direction of the local insulating layer 50 when a voltage of 1600 V is applied to the semiconductor device 1.

[0042] As shown in Figure 7, the rate of change of the leakage current IR decreases almost monotonically in the region where the thickness dimension Tox of the local insulating layer 50 is less than 2000 Å, and stabilizes at a value of less than 20% when it reaches 2000 Å. Similar to the case shown in Figure 2, in the region where the thickness dimension Tox is less than 2000 Å, the main semiconductor layer 30 is affected by the passivation film 40, and the depletion layer edge 60 reaches the end face 30a, forming a leakage current path. Furthermore, as shown in Figure 3, in the region where the thickness dimension Tox is 2000 Å or more, the main semiconductor layer 30 is prevented from having the depletion layer edge 60 reach the end face 30a due to the influence of the local insulating layer 50, and the leakage current propagating from the end face 30a is prevented from being transmitted inside the depletion layer. As a result, the formation of a leakage current path is suppressed. For the reasons stated above, it is preferable that the thickness dimension Tox of the local insulating layer 50 is at least 2000 Å for manufacturing purposes. Furthermore, from a manufacturing perspective, considering throughput, it is preferable that the thickness dimension Tox of the local insulating layer 50 is at least 30,000 Å or less.

[0043] Next, we will explain the width dimension Wox of the local insulating layer 50. The widthwise dimension Wox of the local insulating layer 50 can take any value. Here, we will explain the position of the end of the local insulating layer 50 on the n-layer 32a side. In this explanation, the position on the end face 30a side of the local insulating layer 50 is arbitrary. Referring to Figure 6, it is preferable that it is within the range that satisfies the following relationship. That is, the widthwise dimension Wox of the local insulating layer 50 can extend inward from point O1, which coincides with the end face 30a of the main semiconductor layer 30. When position O2 is the point where the pn junction surface I1 is exposed to the mesa groove 30x, it is preferable that the distance WMox is less than the distance at which the straight line D2 connecting the foot of a perpendicular line drawn from one end of the local insulating layer film 50 on the inside side of the n-layer 32a toward the interface I3 between the n-layer 32a and the n+ layer 32b and position O2 is equal to the thickness D1 of the n-layer 32a. If D2 > D1, the end of the end face 30a of the local insulating layer 50 may be located inside the end face 30a (towards the n-layer 32a).

[0044] This is based on the following reason: If the widthwise dimension Wox is greater than or equal to the distance WMox, then in the mesa groove 30x, at least the entire n-layer 32a will be covered by the local insulating layer 50. As explained in the description of Figure 5, this will prevent the formation of the inversion layer 70, and although the leakage current will decrease, the withstand voltage will not be sufficient compared to when the passivation film 40 is formed, and the original function will be impaired. For this reason, it is preferable that the widthwise dimension Wox of the local insulating layer 50 be less than the distance WMox. Furthermore, the widthwise dimension Wox of the local insulating layer 50 can be determined based on simulation data and prototype data, for example, as follows. Figure 8 plots the relationship between the widthwise dimension Wox and the rate of change of leakage current from simulations and prototypes of semiconductor device 1 at Tox = 5000 Å. When there is no local insulating layer 50, the depletion layer edge 60 reaches the end face 30a, as shown in state (1) in Figure 9A(A). Next, when the widthwise dimension Wox of the local insulating layer 50 is less than 30 μm, simulations show that the depletion layer edge 60 reaches the end face 30a, as shown in state (2) in Figure 9A(B). Next, when the widthwise dimension Wox of the local insulating layer 50 is 80 μm or more, simulations and prototypes show that the depletion layer edge 60 is prevented from reaching the end face 30a, as shown in state (3) in Figure 9B(C). From the above, it can be said from Figure 8 that the minimum manufacturing dimension Wox of the local insulating layer 50 is 40 μm. In other words, it can be said that the depletion layer edge 60 below the local insulating layer 50 does not reach the edge face 30a of the main semiconductor layer 30. Here, we will explain how to determine the lower bound of Wox. Figure 11(A) is a state diagram of the depletion layer edge 60 near the local insulating layer 50. Figure 11(B) is an enlarged view of the main part R in Figure 11(A). In Figure 11(B), the distance from the end of the n-layer 32 side below the local insulating layer 50 to the tip of the depletion layer edge 60 is defined as W and is called the elongation of the depletion layer edge 60. Figure 10 shows the relationship between the applied voltage Va and the required width Wox of the local insulating layer 50. In Figure 10, the thickness Tox of the local insulating layer 50 is set to 2000 Å or more, and in the simulation, the n-type carrier concentration of the n-layer 32a and the positive charge density within the local insulating layer 50 near the interface I4 (see Figure 6) are used as parameters. The reason for using a positive charge in the local insulating layer 50 in the simulation is that it is not possible to set the n-type carrier density only in the portion of the n-layer 32a directly beneath interface I4, and not in the portion directly beneath I4. In other words, while the simulation requires that the n-layer 32a have a single n-type carrier density throughout the entire layer, in reality, due to dangling bonds (unbonded covalent bonds) that occur during the manufacturing of the local insulating layer 50, the electron density near interface I4 is higher than in other parts of the n-layer 32a, and this electron density generates a positive fixed charge near interface I4 within the local insulating layer 50. The parameters that determine the elongation W at the edge of the depletion layer are (a) the concentration of the n-layer 32a, (b) the charge density on the local insulating layer 50 side at the interface I4 between the n-layer 32a and the local insulating layer 50 (see Figure 6), and (c) the voltage applied to the semiconductor device 1. Using the above parameters (a) to (c), the elongation W at the depletion layer edge 60 below the local insulating layer 50 is derived from the simulation data as follows: (Math 1) W[μm]=A×ln(Va)+B+3……(Formula 1) however (Math 2) A = (2.79 × 10 -10 ×qf -0.3 ) × ρ + (7 × 10 4 ×qf -0.33 )……(Formula 2) (Math 3) B = (7.42 × 10 -5 ×qf -0.74 )×ρ-(3.62×10 19 ×qf -1.6 )……(Formula 3) Wox must be greater than or equal to the width of W determined by (Equation 1). Next, I will explain the upper limit of Wox. Figure 12 shows the relationship between the ratio of the line D2, which connects the foot of a perpendicular line drawn from position O2 where the pn junction surface I1 is exposed in the mesa groove 30x to the interface I3 between the n-layer 32a and the n+ layer 32b, to position O2, and the thickness D1 of the n+ layer 32a, and the breakdown voltage change of the semiconductor device 1. In Figure 12, the ratio of D1 to D2 is defined as D2 / D1. As shown in the figure, the breakdown voltage increases sharply in the region where D2 / D1 is greater than 1, and when this ratio exceeds approximately 1.2, the breakdown voltage change becomes almost constant. From this, it can be concluded that the portion of the pn junction surface I1 exposed in the mesa groove 30x does not need to be covered by the local insulating layer 50, but only needs to be covered by the passivation film 40, and the upper limit width of Wox is determined based on this.

[0045] As described above, the present invention makes it possible to provide a semiconductor element that can reduce leakage current in a configuration having a passivation film.

[0046] (Variations, etc.) In the semiconductor element 1 according to an embodiment of the present invention, the local insulating layer 50 is arranged to be embedded in the passivation film 40, and only the surface that is flush with the end face 30a of the main semiconductor layer 30 is exposed to the outside. However, the configuration of the present invention is not limited to this. That is, in the semiconductor element of the present invention, it is sufficient that the local insulating layer is provided within the mesa groove 30x.

[0047] For example, in the example shown in Figure 13, at least the top surface 50a of the local insulating layer 50 is positioned to protrude from the surface of the passivation film 40, and most of the end face 50b of the local insulating layer 50 is covered by the passivation film 40 without coinciding with the end face 30a of the main semiconductor layer 30. In other words, the local insulating layer 50 is located inward from the side surface 30a of the main semiconductor layer that is exposed to the outside.

[0048] Even with this configuration, it is possible to provide a semiconductor device that can suppress the elongation of the depletion layer edge 60 of the local insulating layer 50 and prevent the formation of the inversion layer 70, thereby preventing the formation of leakage current paths and reducing leakage current.

[0049] Furthermore, although the semiconductor element 1 according to the embodiment of the present invention is a single-moat type mesa diode having a rectangular outer shape in plan view, the configuration of the present invention is not limited thereto. That is, the semiconductor element of the present invention is configured such that the local insulating layer is provided at the lowest part of the mesa groove in a direction along the stacking direction of the n-type semiconductor layer and the p-type semiconductor layer, and is not limited by the specific type of semiconductor element.

[0050] For example, as exemplified by the double-moat diode shown in Figure 14(A), the double-mesa double-moat diode shown in Figure 14(C), and the isolated-diffusion diode shown in Figure 14(D), the local insulating layer 50 may be provided at a position different from the end face 30a of the diode. Furthermore, this may be implemented in diodes in which mesa grooves 30x are formed on both sides of the main semiconductor layer 30, such as the double-mesa single-moat diode shown in Figure 14(B) and the double-mesa double-moat diode shown in Figure 14(C).

[0051] Furthermore, although the semiconductor element 1 according to the embodiment of the present invention is described as a mesa-type diode, the configuration of the present invention is not limited thereto. That is, the semiconductor element of the present invention comprises a passivation film covering the space between the anode or cathode and the n-type semiconductor layer and the p-type semiconductor layer, and a locally provided insulating layer in contact with at least the n-type semiconductor layer or the p-type semiconductor layer, and the surface opposite to at least the surface in contact with the n-type semiconductor layer and the p-type semiconductor layer of the local insulating layer is covered with the passivation film. The present invention is not limited by any other specific configuration of the semiconductor element.

[0052] For example, this may be implemented in a planar diode having an FLR (Field Limiting Ring) structure as shown in Figure 15.

[0053] Furthermore, while the semiconductor element 1 according to the embodiment of the present invention is configured such that the main semiconductor layer 30 is a stack of a p-type semiconductor layer 31 on which the anode 10 is located and an n-type semiconductor layer 32 on which the cathode 20 is located, the configuration of the present invention is not limited thereto. That is, the semiconductor element of the present invention may have any configuration in which the main semiconductor layer includes a pn junction of a first semiconductor layer and a second semiconductor layer that are classified from each other by a charge carrier.

[0054] Therefore, in the above embodiment, the p-type semiconductor layer 31 is an example of the first semiconductor layer and the n-type semiconductor layer 32 is an example of the second semiconductor layer. However, the first semiconductor layer may be an n-type semiconductor layer and the second semiconductor layer may be a p-type semiconductor layer.

[0055] In this case, if the polarity of the charge distributed near the interface I2 between the mesa groove 30x and the passivation film 40 is positive, the compositions of the local insulating layer 50 and the passivation film 40 in the semiconductor device 1 are preferably as follows: The local insulating layer 50 is preferably a glass structure mainly composed of SiO2 and containing Al2O3, B2O3, PbO2, ZnO2, and Ba-based oxides as additives, and may also be semi-insulating polysilicon (SIPOS). For the passivation film 40 corresponding to the glass structure, it is preferable to use an insulating SiO2 film, an insulating SiN film, or an insulating SiON film as the main material.

[0056] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto.

[0057] In other words, without departing from the scope of the technical idea and objectives of the present invention, various changes can be made to the embodiments and each of the modifications described above in terms of mechanism, shape, material, quantity, position or arrangement, etc., and these are included in the present invention. [Explanation of Symbols]

[0058] 1,100 semiconductor devices 10 anodes 20 Cathode 30 Main semiconductor layer 30a, 50b end face 30x Mesa Groove 31 p-type semiconductor layer 32 n-type semiconductor layer 32a n-layer 32b n+ layer 40 Passivation membrane 50 Local insulating layer 50a Top surface 60 Depletion layer edge 60a, 60b end 70 Inversion Layer 71 Damaged area

Claims

1. anode and cathode, A main semiconductor layer including a pn junction of a first semiconductor layer and a second semiconductor layer, which are separated from each other by a charge carrier, sandwiched between the anode and the cathode, A passivation film covering the space between the anode or cathode and the first semiconductor layer or the second semiconductor layer, The device comprises at least a local insulating layer provided locally in contact with the first semiconductor layer or the second semiconductor layer, The surface of the local insulating layer opposite to the surface in contact with at least the first semiconductor layer or the second semiconductor layer is covered with the passivation film. Semiconductor element.

2. The main semiconductor layer is provided with a mesa groove formed on its side surface, spanning the boundary between the first semiconductor layer and the second semiconductor layer. The passivation film covers the mesa groove, The local insulating layer is provided within the mesa groove. The semiconductor device according to claim 1.

3. The aforementioned local insulating layer is In the direction along the stacking direction of the first semiconductor layer and the second semiconductor layer, the lowest part of the mesa groove is provided, The semiconductor device according to claim 2.

4. The aforementioned local insulating layer is It is provided at a position that coincides with the side surface of the main semiconductor layer that is exposed to the outside, and is exposed to the outside, The semiconductor device according to claim 3.

5. The thickness of the local insulating layer is 2000 Å or more. The semiconductor device according to claim 4.

6. The maximum value of the width of the local insulating layer is, In a view orthogonal to the stacking direction of the first and second semiconductor layers, the distance from the stacking boundary of the first and second semiconductor layers to the inner edge of the local insulating layer is less than the thickness of the semiconductor layer having a lower concentration in the first or second semiconductor layer of the main semiconductor layer. The semiconductor device according to claim 4.

7. anode and cathode, A main semiconductor layer including a pn junction of a first semiconductor layer and a second semiconductor layer, which are separated from each other by a charge carrier, sandwiched between the anode and the cathode, A passivation film covering the space between the anode or cathode and the first semiconductor layer or the second semiconductor layer, The device comprises at least a local insulating layer provided locally in contact with the first semiconductor layer or the second semiconductor layer, The aforementioned local insulating layer is It is provided on the side surface of the main semiconductor layer, in a position inside the end face that is exposed to the outside, Semiconductor element.

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