Semiconductor equipment
Patent Information
- Application Number
- JP2025060049
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2026-10-14
Smart Images
Figure 2026166835000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device, for example, to a semiconductor device having a voltage regulator.
Background Art
[0002] Non-Patent Document 1 discloses a configuration in which a switched capacitor regulator and an LDO (Low Drop Out) regulator are connected in series. The switched capacitor regulator generates power for the LDO regulator from an external power supply and supplies the generated power to the LDO regulator.
Prior Art Documents
Non-Patent Documents
[0003]
Non-Patent Document 1
Summary of Invention
Problems to be Solved by the Invention
[0004] Voltage regulators can be broadly classified into two types, switching regulators and linear regulators, based on the difference in conversion schemes. High power efficiency can be achieved by using a DC-DC converter that is a switching regulator. However, as a disadvantage, the BoM (Bill of Materials) cost may increase due to an increase in circuit area, mounting of external elements, and the like. That is, such a DC-DC converter usually requires a large external capacitor, an external inductor, and the like.
[0005] Furthermore, using a linear regulator such as an LDO regulator reduces the number of external components and circuit area, thereby lowering the Bank of Manufacturing (BOM) cost. In addition, it enables fast load transient response. However, a disadvantage is that power efficiency may decrease. In other words, LDO regulators experience power loss based on the difference between the input power supply voltage and the output power supply voltage.
[0006] In recent years, there has been a demand for power-saving voltage regulators, particularly in the field of energy harvesting. Therefore, the application of DC-DC converters, which have high power efficiency, is being considered. However, the increase in Bank of Materials (BOM) costs associated with using DC-DC converters cannot be ignored. Thus, as shown in Non-Patent Document 1, for example, a method combining a switched-capacitor regulator (a type of DC-DC converter) and an LDO regulator is being considered.
[0007] The method described in Non-Patent Document 1 primarily achieves high power efficiency and fast load transient response. However, in this method, the switched-capacitor regulator needs to output a voltage to the LDO regulator that is even higher than the LDO regulator's output power supply voltage in order for the LDO regulator to operate normally. Consequently, the voltage difference between the input power supply voltage and the output power supply voltage in the switched-capacitor regulator becomes small. In order to secure the desired current supply amount with such a small voltage difference, the size of the flying capacitor constituting the switched-capacitor regulator needs to be increased. As a result, the capacitor cannot be integrated into the chip, which may lead to an increase in the Bank of Materials (BOM) cost.
[0008] The embodiments described later were made in view of these considerations, and other issues and novel features will become clear from the description and accompanying drawings of this specification. [Means for solving the problem]
[0009] A semiconductor device according to one embodiment comprises a first power supply wiring, an LDO regulator, a switched-capacitor circuit, a current sensing circuit, and a clock supply circuit. The first power supply wiring supplies power to a predetermined load. The LDO regulator receives an input power supply voltage and outputs a first output power supply voltage lower than the input power supply voltage and a first output power supply current to the first power supply wiring. The switched-capacitor circuit receives an input power supply voltage and outputs a second output power supply current to the first power supply wiring by switching between charging and discharging operations for the flying capacitor in accordance with the clock signal. The current sensing circuit detects the magnitude of the first output power supply current. The clock supply circuit supplies a clock signal to the switched-capacitor circuit based on the detection result of the current sensing circuit. [Effects of the Invention]
[0010] According to the above embodiment, high power efficiency, fast load transient response, and reduced Bank of Materials (BOM) costs can be achieved. [Brief explanation of the drawing]
[0011] [Figure 1] Figure 1 is a circuit block diagram showing a schematic configuration example of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a circuit diagram showing an example of the configuration of the LDO regulator in Figure 1. [Figure 3A] Figure 3A is a circuit diagram showing an example of the configuration of the switched-capacitor circuit in Figure 1. [Figure 3B] Figure 3B is a timing chart showing a schematic example of the operation of the switch control circuit in Figure 3A. [Figure 4] Figure 4 is a schematic diagram comparing the various electrical characteristics of the LDO regulator shown in Figure 2 and the switched-capacitor circuit shown in Figure 3A with respect to load current. [Figure 5A] Figure 5A is a schematic diagram illustrating a more detailed example of the operation of the switched-capacitor circuit shown in Figure 3A. [Figure 5B]FIG. 5B is a schematic diagram illustrating a more detailed operation example of the switched capacitor circuit shown in FIG. 3A. [Figure 6] FIG. 6 is a circuit block diagram showing a schematic configuration example of the voltage regulator according to the first embodiment. [Figure 7] FIG. 7 is a schematic diagram showing an operation example of the voltage regulator shown in FIG. 6. [Figure 8] FIG. 8 is a schematic diagram showing another operation example of the voltage regulator shown in FIG. 6. [Figure 9] FIG. 9 is a circuit block diagram showing a more detailed configuration example of the voltage regulator shown in FIG. 6. [Figure 10A] FIG. 10A is a circuit diagram showing a configuration example of the voltage controlled oscillator in FIG. 9. [Figure 10B] FIG. 10B is a circuit diagram showing a configuration example of the ring oscillator in FIG. 10A. [Figure 11] FIG. 11 is a circuit block diagram showing a modified configuration example of the voltage regulator shown in FIG. 9. [Figure 12] FIG. 12 is a schematic diagram showing an operation example of the voltage regulator shown in FIG. 11. [Figure 13] FIG. 13 is a circuit block diagram showing a detailed configuration example of the voltage regulator shown in FIG. 6 in the semiconductor device according to the second embodiment. [Figure 14] FIG. 14 is a circuit block diagram showing a detailed configuration example of the voltage regulator shown in FIG. 6 in the semiconductor device according to the third embodiment. [Figure 15] FIG. 15 is a schematic diagram showing an operation example of the voltage regulator shown in FIG. 14. [Figure 16] FIG. 16 is a circuit block diagram showing a detailed configuration example of the voltage regulator shown in FIG. 6 in the semiconductor device according to the fourth embodiment. [Figure 17] FIG. 17 is a schematic diagram showing an arrangement example of the voltage regulator shown in FIG. 16 in the semiconductor device. [Figure 18A]Figure 18A is a circuit block diagram showing a detailed configuration example of the voltage regulator shown in Figure 6 in a semiconductor device according to the fifth embodiment. [Figure 18B] Figure 18B is a circuit diagram showing an example of the configuration of the voltage-controlled oscillator in Figure 18A. [Figure 19] Figure 19 is a timing chart showing an example of the operation of the voltage regulator shown in Figure 18A. [Figure 20] Figure 20 is a circuit block diagram showing an example configuration of a voltage regulator as a comparative example. [Modes for carrying out the invention]
[0012] In the following embodiments, the description will be divided into multiple sections or embodiments where necessary for convenience. However, unless otherwise specified, they are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, when referring to the number of elements (including number, numerical value, quantity, range, etc.), the number is not limited to that specific number unless otherwise specified or when it is clearly limited in principle. In other words, the number of elements may be greater than or less than a specific number.
[0013] Furthermore, in the embodiments, the constituent elements (including element steps) are not necessarily essential unless specifically stated or considered fundamentally essential. Similarly, when referring to the shape, positional relationship, etc., of constituent elements, it includes those that substantially approximate or resemble their shape, etc., unless specifically stated or considered fundamentally not essential. The same applies to the numerical values and ranges mentioned above.
[0014] Furthermore, in this embodiment, a MOSFET (MOS Field Effect Transistor) is referred to as a MOS transistor. A p-channel MOSFET and an n-channel MOSFET are referred to as a pMOS transistor and an nMOS transistor, respectively. In this embodiment, for the sake of simplicity, the explanation will be given using a MOS transistor that uses an oxide film as the gate insulating film. However, the gate insulating film is not necessarily limited to an oxide film.
[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all drawings used to illustrate the embodiments, the same reference numerals are generally used for identical components, and repeated descriptions of such components will be omitted.
[0016] (First Embodiment) <Overview of Semiconductor Device> Figure 1 is a circuit block diagram showing a schematic configuration example of a semiconductor device according to the first embodiment. The semiconductor device 10 shown in Figure 1 is, for example, a microcontroller unit (MCU) or SoC (System on Chip) realized on a single semiconductor chip. The semiconductor device 10 includes an LDO regulator LDOR_AON, a voltage regulator VREG, an external power supply circuit 15, and two internal power supply circuits 16 and 17.
[0017] The LDO regulator LDOR_AON receives the external power supply voltage VCC via the power supply wiring PLvc. The LDO regulator LDOR_AON then generates an internal power supply voltage VDD1, which is lower than the external power supply voltage VCC, and outputs it to the power supply wiring PLvd1. For example, the external power supply voltage VCC is approximately 3.3V, and the internal power supply voltage VDD1 is approximately 0.8V. Note that the external power supply voltage VCC may vary depending on the situation, for example, if it is the battery voltage.
[0018] The voltage regulator VREG also receives the external power supply voltage VCC as input via the power supply wiring PLvc. The voltage regulator VREG then generates an internal power supply voltage VDD2, which is lower than the external power supply voltage VCC, and outputs it to the power supply wiring PLvd2. For example, the internal power supply voltage VDD2 is also about 0.8V. As will be described in detail later, the voltage regulator VREG includes an LDO regulator LDOR_MAIN, a clock supply circuit CKS, and a switched capacitor circuit SCC. In this specification, each LDO regulator LDOR_AON and LDOR_MAIN are collectively referred to as the LDO regulator LDOR.
[0019] The external power supply circuit 15 is a circuit that operates on the external power supply voltage VCC supplied via the power supply wiring PLvc. The external power supply circuit 15 includes, for example, a power management unit PMU. The power management unit PMU controls the active / inactive states of the LDO regulator LDOR_AON and the voltage regulator VREG.
[0020] The internal power supply circuit 16 is a circuit that operates on the internal power supply voltage VDD1 supplied from the LDO regulator LDOR_AON via the power supply wiring PLvd1. The power management unit PMU controls the LDO regulator LDOR_AON to be active, even when, for example, the semiconductor device 10 is switched to a power saving mode. Accordingly, the internal power supply circuit 16 is always in the ON state (AON state). The internal power supply circuit 16 includes, for example, a timer TMR, a power saving timer ULPT, and a low-frequency clock generator LOCO.
[0021] The internal power supply circuit 17 is a circuit that operates on the internal power supply voltage VDD2 supplied from the voltage regulator VREG via the power supply wiring PLvd2. The power management unit PMU controls the voltage regulator VREG to an inactive state when, for example, the semiconductor device 10 is switched to a power saving mode. The power management unit PMU also controls the voltage regulator VREG to an active state when the semiconductor device 10 is operated in normal mode. Accordingly, the internal power supply circuit 17 becomes the main circuit responsible for the normal operation of the semiconductor device 10.
[0022] The internal power supply circuit 17 includes, for example, a processor PRC, volatile memory RAM, non-volatile memory NVM, and various peripheral circuits PERI. The processor PRC is typically a CPU (Central Processing Unit). The volatile memory RAM is, for example, SRAM (Static Random Access Memory). The non-volatile memory NVM is, for example, MRAM (Magnetoresistive RAM). In this case, the processor PRC uses SRAM as temporary memory while executing a predetermined program stored in MRAM.
[0023] The test switch SWt shown in Figure 1 is controlled to be ON during testing, connecting the two power supply wires PLvd1 and PLvd2. This allows, for example, test power from the test terminal to be supplied to both power supply wires PLvd1 and PLvd2 during testing. Also, in Figure 1, power supply wire PLvd2 is connected to an output capacitor Cout, which is provided outside the semiconductor device 10. The output capacitor Cout may be provided inside the semiconductor device 10.
[0024] <About the components of a voltage regulator> Figure 2 is a circuit diagram showing an example configuration of the LDO regulator LDOR in Figure 1. The LDO regulator LDOR shown in Figure 2 comprises a pMOS transistor MPd, resistors R1 and R2, and an amplifier circuit AMP1. The pMOS transistor (output transistor) MPd is connected between the power supply wiring PL2 to which the input power supply voltage Vin is applied and the power supply wiring PL1 to which the output power supply voltage Vout is output. The output power supply voltage Vout is the voltage obtained by stepping down the input power supply voltage Vin through the output transistor.
[0025] The amplifier circuit AMP1 applies a gate voltage (control voltage) VG to the pMOS transistor MPd so that the error between the output power supply voltage Vout and the target value approaches zero. Specifically, the amplifier circuit AMP1 outputs a gate voltage VG so that the feedback voltage Vfb matches the reference voltage VREF, which corresponds to the target value. The feedback voltage Vfb is generated by creating a voltage divider between the output power supply voltage Vout and the ground power supply voltage GND using two high-resistance resistors R1 and R2.
[0026] Figure 3A is a circuit diagram showing an example configuration of the switched-capacitor circuit SCC in Figure 1. Figure 3B is a timing chart showing a schematic example of the operation of the switch control circuit SWCT in Figure 3A. Figure 3A shows, for example, the switched-capacitor circuit SCC when "VCR (Voltage conversion ratio) = 1 / 2". This switched-capacitor circuit SCC comprises four switches, one flying capacitor Cfly, and a switch control circuit SWCT.
[0027] The four switches are composed of, for example, one pMOS transistor MPs1 and three nMOS transistors MNs2-MNs4. The pMOS transistor MPs1 and nMOS transistor MNs3 are connected in series between power supply wiring PL2, to which the input power supply voltage Vin is applied, and power supply wiring PL1, which is the output destination of the output power supply voltage Vout. The two nMOS transistors MNs2 and MNs4 are connected in series between power supply wiring PL1 and power supply wiring PL3, to which the ground power supply voltage GND is applied.
[0028] The flying capacitor Cfly is connected between the shared node of the pMOS transistor MPs1 and the nMOS transistor MNs3, and the shared node of the two nMOS transistors MNs2 and MNs4. The switch control circuit SWCT generates the switching signals S1P, S2P, S1N, and S2N for the four switches in synchronization with the input clock signal CLK.
[0029] Switching signal S1P controls the on / off state of pMOS transistor MPs1. Switching signal S2P controls the on / off state of nMOS transistor MNs2. Switching signal S1N controls the on / off state of nMOS transistor MNs4. Switching signal S2N controls the on / off state of nMOS transistor MNs3.
[0030] As shown in Figure 3B, the switch control circuit SWCT controls the two switching signals S1P and S2P to the ON level and the two switching signals S1N and S2N to the OFF level during the "L" level period of the clock signal CLK. In this case, the input power supply voltage Vin and the output power supply voltage Vout are applied across the flying capacitor Cfly. As a result, the flying capacitor Cfly performs a charging operation based on the input power supply current Iin flowing through the power supply wiring PL2.
[0031] On the other hand, the switch control circuit SWCT controls the two switching signals S1N and S2N to the ON level and the two switching signals S1P and S2P to the OFF level during the H level period of the clock signal CLK. In this case, the ground power supply voltage GND and the output power supply voltage Vout are applied across the flying capacitor Cfly. As a result, the flying capacitor Cfly discharges by flowing the output power supply current Iout through the power supply wiring PL1.
[0032] In this way, the switched-capacitor circuit SCC receives the input power supply voltage Vin and switches between charging and discharging the flying capacitor Cfly by switching in accordance with the clock signal CLK. As a result, the switched-capacitor circuit SCC outputs the output power supply current Iout to the power supply wiring PL1.
[0033] Figure 4 is a schematic diagram comparing the various electrical characteristics with respect to load current between the LDO regulator LDOR shown in Figure 2 and the switched-capacitor circuit SCC shown in Figure 3A. Figure 4 shows the relationship between the load current Iload, the input power supply current Iin, the output power supply current Iout, and the power efficiency "Pout / Pin". The output power supply current Iout is the same for both the LDO regulator LDOR and the switched-capacitor circuit SCC.
[0034] Furthermore, in the LDO regulator LDOR, the input power supply current Iin flowing through the power supply wiring PL2 is equivalent to the output power supply current Iout. That is, in Figure 2, the currents flowing through the resistors R1 and R2 can be ignored because they are high-resistance elements. On the other hand, the input power supply current Iin of the switched-capacitor circuit SCC is half of the output power supply current Iout when "VCR = 1 / 2".
[0035] Furthermore, the power efficiency "Pout / Pin" is determined by "(Vout*Iout) / (Vin*Iin)". The power efficiency of an LDO regulator (LDOR) is "Vout / Vin" when "Iin=Iout". For example, when "Vout=Vin / 2", the power efficiency of the LDO regulator (LDOR) is "0.5". On the other hand, the power efficiency of a switched-capacitor circuit (SCC) is ideally "1.0" when "Iin=Iout / 2" and "Vout=Vin / 2". Thus, the switched-capacitor circuit (SCC) can achieve higher power efficiency compared to the LDO regulator (LDOR).
[0036] Figures 5A and 5B are schematic diagrams illustrating a more detailed operational example of the switched-capacitor circuit SCC shown in Figure 3A. Figure 5A shows the on / off states of the four switches SW1-SW4 during the charging and discharging operations described in Figure 3A, i.e., the charging phase PH1 and the discharging phase PH2. Furthermore, the output capacitor Cout and load LD are connected to the power supply wiring PL1, which outputs the output power supply voltage Vout and output power supply current Iout. The load LD is a load resistance element R L It is represented as follows.
[0037] In the charging phase PH1, the flying capacitor Cfly is charged with the flying capacitor Cfly connected in series with the output capacitor Cout. During this time, the input power supply voltage Vin is applied to the flying capacitor Cfly with the output power supply voltage Vout as the reference. Consequently, the input power supply current Iin flows through the power supply wiring PL2. On the other hand, in the discharging phase PH2, the flying capacitor Cfly is discharged from the flying capacitor Cfly to the output capacitor Cout with the flying capacitor Cout connected in parallel.
[0038] Focusing on the amount of charge transferred in the flying capacitor Cfly, the average value of the input power supply current Iin, "Iin(ave)", can be calculated using equation (1). As shown in Figure 5B, in the charging phase PH1, the flying capacitor Cfly is charged with an amount of charge based on "Vin-Vout". In the subsequent discharging phase PH2, an amount of charge based on the voltage difference between "Vin-Vout" and "Vout", "Vin-2Vout", is transferred to the output capacitor Cout. The average value of the input power supply current Iin, "Iin(ave)", is determined based on this amount of transferred charge. In equation (1), "f" is the frequency of the clock signal CLK. Iin(ave) = Cfly(Vin - 2Vout) * f (1)
[0039] Furthermore, the average value of the output power supply current Iout, "Iout(ave)", is calculated using equation (2), since "Iout = 2 * Iin" as mentioned above. On the other hand, the load resistance element R L In this case, “Iout(ave)=Vout / R L The relationship " holds true. Based on this relationship and equation (2), the output power supply voltage Vout can be calculated using equation (3). Here, as can be seen from equation (2) and Figure 5B, when "Vin ≤ 2Vout", the switched-capacitor circuit SCC loses its current supply capability. Also, as can be seen from equation (3), when the frequency "f" of the clock signal CLK is increased, the output power supply voltage Vout converges to a voltage value of "Vin / 2". Iout(ave) = 2Cfly(Vin - 2Vout) * f (2) Vout = (2Cfly * f * R L ) / (4Cfly * f * R L + 1) * Vin (3)
[0040] <Regarding voltage regulators (comparative example)> First, let's explain the method described in Non-Patent Document 1. In this method, the switched-capacitor circuit SCC is connected in series with the LDO regulator LDOR and outputs the input power supply voltage Vin to the LDO regulator LDOR. In this case, the switched-capacitor circuit SCC needs to output a voltage that is higher than the output power supply voltage Vout of the LDO regulator LDOR by the amount of the drain-source voltage (VDS) of the pMOS transistor MPd. That is, the switched-capacitor circuit SCC needs to guarantee the drain-source voltage (VDS) of the pMOS transistor MPd.
[0041] Consequently, the voltage difference between the input power supply voltage Vin and the output power supply voltage Vout in the switched-capacitor circuit SCC becomes smaller. In order to secure the desired current supply under these conditions, as can be seen from equation (2), it is necessary to either increase the frequency "f" of the clock signal CLK or increase the size of the flying capacitor Cfly. In practice, the frequency "f" can only be increased to a certain extent, so it is necessary to increase the size of the flying capacitor Cfly. As a result, it becomes difficult to implement the flying capacitor Cfly on-chip, which can increase the cost of materials under construction (BOM).
[0042] Therefore, for example, the method shown in Figure 20 can be considered. Figure 20 is a circuit block diagram showing an example configuration of a voltage regulator as a comparative example. In Figure 20, the switched-capacitor regulator SCRx is connected in parallel with the LDO regulator LDOR. The switched-capacitor regulator SCRx and the LDO regulator LDOR operate independently of each other and output the output power supply voltage Vout to a common power supply wiring PL1. The switched-capacitor regulator SCRx includes an amplifier circuit AMP2, a voltage-controlled oscillator VCO, and a switched-capacitor circuit SCC.
[0043] The amplifier circuit AMP2 detects the error between the output power supply voltage Vout and the reference voltage VREF2. The voltage-controlled oscillator VCO generates a clock signal CLK and controls the frequency "f" of the clock signal CLK based on the detected error. The switched-capacitor circuit SCC performs switching operations based on the clock signal CLK from the voltage-controlled oscillator VCO, outputting the output power supply current IoutS to the power supply wiring PL1. In this way, the switched-capacitor regulator SCRx generates the output power supply current IoutS so that the error between the output power supply voltage Vout and the target voltage, i.e., the reference voltage VREF2, approaches zero.
[0044] Unlike the series connection method described above, in this parallel connection method, the switched capacitor regulator SCRx does not need to guarantee the drain-source voltage (VDS) of the pMOS transistor MPd. Consequently, a certain voltage difference can be maintained between the input power supply voltage Vin and the output power supply voltage Vout in equation (2). As a result, the size of the flying capacitor Cfly can be reduced to a level that allows it to be implemented on-chip.
[0045] However, in the method shown in Figure 20, the output power supply current IoutL from the LDO regulator LDOR and the output power supply current IoutS from the switched-capacitor regulator SCRx are generated independently of each other. As a result, the source of the output power supply current to the load may be biased towards one regulator or the other.
[0046] Specifically, for example, a difference in the target voltage of each regulator may occur depending on the offset difference between the amplifier circuit AMP1 in the LDO regulator LDOR and the amplifier circuit AMP2 in the switched-capacitor regulator SCRx. The source of the output power supply current will be biased towards the regulator with the higher target voltage. If the source is biased towards the LDO regulator LDOR, it becomes difficult to improve power efficiency. On the other hand, if the source is biased towards the switched-capacitor regulator SCRx, it becomes particularly difficult to speed up the load transient response. In other words, it becomes difficult to achieve the advantages of both. Therefore, it is beneficial to use the method described below.
[0047] <Outline of a voltage regulator (embodiment)> Figure 6 is a circuit block diagram showing a schematic configuration example of a voltage regulator according to the first embodiment. The voltage regulator shown in Figure 6 is applied, for example, to the voltage regulator VREG shown in Figure 1, and supplies power to the internal power supply circuit 17. This voltage regulator includes an LDO regulator LDOR and a switched capacitor regulator SCR connected in parallel, similar to the case in Figure 20.
[0048] The LDO regulator LDOR receives an input power supply voltage Vin via the power supply wiring (second power supply wiring) PL2. The LDO regulator LDOR then outputs an output power supply voltage Vout, which is lower than the input power supply voltage Vin, and an output power supply current (first output power supply current) IoutL to the power supply wiring (first power supply wiring) PL1. Referring to Figure 1, power supply wiring PL2 and the input power supply voltage Vin correspond to power supply wiring PLvc and the external power supply voltage VCC, respectively. Power supply wiring PL1 and the output power supply voltage Vout correspond to power supply wiring PLvd2 and the internal power supply voltage VDD2, respectively. Power supply wiring PL1 supplies power to a predetermined load through which the load current Iload flows, for example, the internal power supply circuit 17.
[0049] The switched-capacitor regulator SCR includes a current sensing circuit CSEN and a clock supply circuit CKS in addition to the switched-capacitor circuit SCC. The switched-capacitor circuit SCC has the configuration shown in Figure 3A. Schematically, the switched-capacitor circuit SCC receives the same input power supply voltage Vin as the LDO regulator LDOR. The switched-capacitor circuit SCC then alternately switches between charging and discharging the flying capacitor Cfly by switching in response to the clock signal CLK. As a result, the switched-capacitor circuit SCC outputs the output power supply current (second output power supply current) IoutS to the same power supply wiring PL1 as the LDO regulator LDOR.
[0050] The current sensing circuit CSEN detects the magnitude of the output power supply current IoutL from the LDO regulator LDOR. The clock supply circuit CKS supplies a clock signal CLK to the switched-capacitor circuit SCC based on the control signal CT representing the detection result of the current sensing circuit CSEN. By using this configuration, unlike in the case of Figure 20, a relationship can be established between the output power supply current IoutL from the LDO regulator LDOR and the output power supply current IoutS from the switched-capacitor regulator SCR. Specifically, the output power supply current IoutS can be controlled based on the magnitude of the output power supply current IoutL.
[0051] Figure 7 is a schematic diagram illustrating an example of the operation of the voltage regulator shown in Figure 6. Figure 7 shows the relationship between the load current Iload, the two output power supply currents IoutL and IoutS, and the power efficiency "Pout / Pin". Note that Figure 7 assumes that "Vin > 2Vout", meaning that the switched-capacitor circuit SCC has the capability to supply current. Also, the load current Iload is equal to the output power supply current Iout (= IoutL + IoutS), which is the sum of the two output power supply currents IoutL and IoutS.
[0052] More specifically, the clock supply circuit CKS starts supplying the clock signal CLK to the switched-capacitor circuit SCC when the output power supply current IoutL from the LDO regulator LDOR exceeds the threshold Ith. The clock supply circuit CKS then controls the frequency "f" of the clock signal CLK to increase in accordance with the increase in the output power supply current IoutL due to the increase in the load current Iload. In this way, the clock supply circuit CKS controls the system so that the increase in the load current Iload is covered by the output power supply current IoutS of the switched-capacitor circuit SCC.
[0053] With this control, within the operating range of the switched-capacitor circuit SCC, the increase in the output power supply current IoutL from the LDO regulator LDOR is suppressed. In other words, the output power supply current IoutL remains almost constant. Furthermore, within the operating range of the switched-capacitor circuit SCC, the more the output power supply current IoutS from the switched-capacitor circuit SCC increases, the higher the power efficiency "Pout / Pin" as a voltage regulator can be.
[0054] Figure 8 is a schematic diagram showing another example of operation of the voltage regulator shown in Figure 6. Figure 8 shows the relationship between the load current Iload and the two output power supply currents IoutL and IoutS. Here, unlike in Figure 7, it is assumed that "Vin ≤ 2Vout", that is, that the switched-capacitor circuit SCC has lost its current supply capability. Even in this case, the LDO regulator LDOR can maintain the output power supply current Iout to the load. On the other hand, in the series connection method shown in Non-Patent Literature 1, for example, if the switched-capacitor circuit SCC loses its current supply capability, the LDO regulator LDOR also loses its current supply capability.
[0055] Here, when the input power supply voltage Vin is low, the power efficiency of the LDO regulator LDOR can be increased accordingly. Therefore, the benefits of being able to lower the lower limit of the input power supply voltage Vin, for example, to cope with a decrease in battery voltage, outweigh the disadvantages associated with power efficiency. In other words, by using a parallel connection method, a wider range of input power supply voltage Vin can be achieved compared to the series connection method.
[0056] As described above, by using the voltage regulator shown in Figure 6, high power efficiency, fast load transient response, and reduced BoM cost can be achieved. In other words, unlike the case in Figure 20, it is possible to moderately combine the advantages of the LDO regulator LDOR and the switched-capacitor circuit SCC. More specifically, by increasing the output power supply current IoutS from the switched-capacitor circuit SCC in response to the increase in load current Iload, higher power efficiency can be achieved compared to the case of the LDO regulator LDOR alone.
[0057] Furthermore, by ensuring a constant output power supply current IoutL from the LDO regulator LDOR, a fast load transient response equivalent to that of the LDO regulator LDOR alone can be achieved. In addition, by using a parallel connection method, the size of the flying capacitor Cfly can be reduced, as in the case of Figure 20. As a result, the flying capacitor Cfly can be formed on-chip, thereby reducing the Bank of Materials (BOM) cost.
[0058] <Details of the voltage regulator> Figure 9 is a circuit block diagram showing a more detailed configuration example of the voltage regulator shown in Figure 6. The voltage regulator shown in Figure 9 differs from the configuration example shown in Figure 6 in the following two ways. The first difference is that a specific configuration example of the current sensing circuit CSEN is shown. The second difference is that the clock supply circuit CKS is composed of a voltage-controlled oscillator VCO.
[0059] The current sensing circuit CSEN comprises a pMOS transistor MPsen and a sense resistor element Rsen. The pMOS transistor MPsen is composed of transistors set to a predetermined size ratio with respect to the pMOS transistor (output transistor) MPd in the LDO regulator LDOR.
[0060] Specifically, the pMOS transistor MPsen has a transistor size, specifically a gate width, that is several thousand times smaller than that of a pMOS transistor MPd. Furthermore, the same gate voltage (control voltage) VG, specifically the gate-source voltage (VGS), as that of the pMOS transistor MPd is applied to the MPsen. As a result, the pMOS transistor MPsen functions as a current sense transistor, supplying a sense current Isen proportional to the output power supply current IoutL from the LDO regulator LDOR. Meanwhile, the sense resistor Rsen converts the sense current Isen into a frequency control voltage Vctl. In other words, the sense resistor Rsen functions as a current-voltage converter IVC.
[0061] Figure 10A is a circuit diagram showing an example configuration of the voltage-controlled oscillator VCO in Figure 9. Figure 10B is a circuit diagram showing an example configuration of the ring oscillator ROSC in Figure 10A. The voltage-controlled oscillator VCO shown in Figure 10A comprises an integrating circuit ITC, a high-potential bias circuit IBS1 and a low-potential bias circuit IBS2, and a ring oscillator ROSC. As shown in Figure 10B, the ring oscillator ROSC comprises multiple cascaded inverter circuits IV and feedback wiring between input and output.
[0062] The integrating circuit ITC comprises an amplifier circuit AMPc and an integrating capacitor Cc. The amplifier circuit AMPc integrates the error between a predetermined reference voltage VREFc and a frequency control voltage Vctl using the integrating capacitor Cc. The amplifier circuit AMPc then outputs the integration result as a gate voltage (bias control voltage) VGc. Two bias circuits IBS1 and IBS2 generate a bias current Ibs based on this integration result. The ring oscillator ROSC operates using this bias current Ibs.
[0063] In detail, the bias circuit IBS1 comprises a pMOS transistor MPc2 and a resistor Rc2. The pMOS transistor MPc2 supplies a bias current Ibs based on the gate voltage VGc to the high-potential side power supply node of the ring oscillator ROSC. The resistor Rc2 is connected between the source of the pMOS transistor MPc2 and the power supply wiring PL2.
[0064] The bias circuit IBS2 comprises a pMOS transistor MPc1, a resistor Rc1, and two nMOS transistors MNc1 and MNc2. The pMOS transistor MPc1 supplies a bias current Ibs based on its gate voltage VGc. The resistor Rc1 is connected between the source of the pMOS transistor MPc1 and the power supply wiring PL2. The nMOS transistors MNc1 and MNc2 form a current mirror circuit. The nMOS transistor MNc1 transfers the bias current Ibs flowing through the pMOS transistor MPc1 to the nMOS transistor MNc2. The nMOS transistor MNc2 supplies the transferred bias current Ibs to the low-potential side power supply node of the ring oscillator ROSC.
[0065] The inverter circuit IV within the ring oscillator ROSC performs signal inversion at a speed corresponding to the magnitude of the supplied bias current Ibs. As a result, the ring oscillator ROSC generates a clock signal CLK with a frequency corresponding to the magnitude of the supplied bias current Ibs.
[0066] Here, when, for example, "Vctl<VREFc" is satisfied, the integrating circuit ITC outputs a relatively high voltage as the gate voltage (bias control voltage) VGc. As a result, the two bias circuits IBS1 and IBS2 do not output a desired bias current Ibs, and the ring oscillator ROSC does not generate the clock signal CLK. On the other hand, when "Vctl>VREFc" is satisfied, the integrating circuit ITC outputs a voltage that decreases in accordance with the error "Vctl-VREFc" as the gate voltage VGc. Along with this, the two bias circuits IBS1 and IBS2 supply a bias current Ibs proportional to the magnitude of the error to the ring oscillator ROSC. As a result, the ring oscillator ROSC starts the generation operation of the clock signal CLK.
[0067] In this manner, the voltage controlled oscillator VCO starts the generation operation of the clock signal CLK at the stage when the frequency control voltage Vctl exceeds the operation lower limit value based on the reference voltage VREFc. Then, the voltage controlled oscillator VCO controls the frequency of the clock signal CLK based on the magnitude of the error "Vctl-VREFc". As a result, the switched capacitor circuit SCC outputs an output power supply current IoutS based on the magnitude of the error "Vctl-VREFc".
[0068] Further, the output power supply current IoutL from the LDO regulator LDOR decreases by the amount corresponding to the output power supply current IoutS from the switched capacitor circuit SCC. As a result, the error "Vctl-VREFc" in the integrating circuit ITC becomes zero, and the voltage regulator operates in a steady state. In this manner, within the operation range of the switched capacitor circuit SCC, the voltage controlled oscillator VCO performs control so that an increment of the load current Iload is covered by the output power supply current IoutS from the switched capacitor circuit SCC.
[0069] <Details of Voltage Regulator (Modification)> Figure 11 is a circuit block diagram showing a modified configuration of the voltage regulator shown in Figure 9. The voltage regulator shown in Figure 11 differs from the configuration shown in Figure 9 in the following respect: the sense resistor element RVsen in the current sensing circuit CSEN is composed of a variable resistor element.
[0070] Figure 12 is a schematic diagram showing an example of the operation of the voltage regulator shown in Figure 11. Similar to Figure 7, Figure 12 shows the relationship between the load current Iload and the two output power supply currents IoutL and IoutS. However, in Figure 12, a variable resistor element is provided, allowing the threshold value Ith shown in Figure 7 to be set variably. Accordingly, the magnitude of the output power supply current IoutS from the switched-capacitor circuit SCC for a given load current Iload can be adjusted by a predetermined adjustment range ΔIoutS. Based on this, the magnitude of the output power supply current IoutL from the LDO regulator LDOR within the operating range of the switched-capacitor circuit SCC can also be adjusted by a predetermined adjustment range ΔIoutL.
[0071] For example, using a low threshold Ith-L widens the operating range of the switched-capacitor circuit (SCC). Consequently, the output power supply current IoutL from the LDO regulator (LDOR) within that range decreases. In this case, the wider operating range of the switched-capacitor circuit (SCC) allows for higher power efficiency. On the other hand, the reduced output power supply current IoutL can lead to a slower load transient response.
[0072] Furthermore, using a high threshold Ith-H narrows the operating range of the switched-capacitor circuit (SCC). Consequently, the output power supply current IoutL from the LDO regulator (LDOR) in that range increases. In this case, the power efficiency decreases due to the narrower operating range of the switched-capacitor circuit (SCC). On the other hand, the increased output power supply current IoutL allows for faster load transient response.
[0073] In this way, by using a variable resistor element as the sense resistor element RVsen, the balance between power efficiency and load transient response can be flexibly changed according to the required specifications. The resistance value of the variable resistor element can be determined statically, for example by trimming, or dynamically by an electrical setting signal.
[0074] <Main effects of the first embodiment> In the first embodiment described above, the LDO regulator LDOR and the switched capacitor circuit SCC are connected in parallel. The output power supply current IoutL from the LDO regulator LDOR is detected, and the clock signal CLK to the switched capacitor circuit SCC is controlled based on the detection result. This enables high power efficiency, fast load transient response, and reduced BoM cost in the voltage regulator.
[0075] (Second Embodiment) <Details of the voltage regulator> Figure 13 is a circuit block diagram showing a detailed configuration example of the voltage regulator shown in Figure 6 in a semiconductor device according to the second embodiment. The voltage regulator shown in Figure 13 differs from the configuration example shown in Figure 9 in the following two points. The first difference is that the current sensing circuit CSEN includes a pMOS transistor MPsen2 and a sense resistor Rsen2 in addition to the pMOS transistor MPsen1 and sense resistor Rsen1 similar to those in Figure 9. The second difference is that the clock supply circuit CKS includes a comparator circuit CMPe, an AND gate AD, and a selector circuit SEL in addition to the voltage-controlled oscillator VCO similar to those in Figure 9.
[0076] The same gate voltage VG as that of the pMOS transistor MPsen1 and, consequently, the output transistor pMOS transistor MPd, is applied to the pMOS transistor MPsen2. As a result, a detection current Isen2, proportional to the magnitude of the output power supply current IoutL, flows through the pMOS transistor MPsen2. The sense resistor Rsen2 converts this detection current Isen2 into an enable voltage Ven. The sense resistor Rsen1, as in the case of Figure 9, converts the detection current Isen1 flowing through the pMOS transistor MPsen1 into a frequency control voltage Vctl and outputs it to the voltage-controlled oscillator VCO.
[0077] The comparator circuit CMPe compares the enable voltage Ven with the reference voltage VREFe and outputs a high-level signal if Ven > VREFe. The AND gate AD outputs an externally input variable clock signal CLKVe when the comparator circuit CMPe is outputting a high level. The selector circuit SEL selects either the variable clock signal CLKVe from the AND gate AD or the clock signal CLK1 from the voltage-controlled oscillator VCO, as in Figure 9. The selector circuit SEL then supplies the selected clock signal CLK to the switched-capacitor circuit SCC.
[0078] Here, for example, the processor PRC shown in Figure 1, which is one of the loads of the voltage regulator, may be supplied with a clock signal whose frequency changes depending on the processing load. The AND gate AD shown in Figure 13 receives this clock signal as a variable clock signal CLKVe. The comparator circuit CMPe then causes the AND gate AD to output the variable clock signal CLKVe when the magnitude of the detected current Isen2, and consequently the output power supply current IoutL, exceeds a threshold based on the reference voltage VREFe. On the other hand, if the magnitude of the output power supply current IoutL does not exceed the threshold, the comparator circuit CMPe causes the AND gate AD to mask the output of the variable clock signal CLKVe.
[0079] As a result, the same operation as in Figure 7 is performed using the variable clock signal CLKVe. In this case, the threshold Ith shown in Figure 7 is determined based on the reference voltage VREFe to the comparator circuit CMPe. Furthermore, the variable clock signal CLKVe is a signal whose frequency increases in accordance with the increase in the output power supply current IoutL, similar to the clock signal CLK from the voltage-controlled oscillator VCO shown in Figure 9.
[0080] Note that the variable clock signal CLKVe is not necessarily provided. For this reason, in the example shown in Figure 13, the selector circuit SEL is configured to also select the clock signal CLK1 from the voltage-controlled oscillator VCO. On the other hand, if the variable clock signal CLKVe is provided and the load current is largely determined by the processor PRC, a configuration using only the variable clock signal CLKVe may be used. In this case, the pMOS transistor MPsen1 and sense resistor Rsen1 shown in Figure 13, as well as the voltage-controlled oscillator VCO and selector circuit SEL, can be omitted.
[0081] In this example, the variable clock signal CLKVe was used directly as the clock signal CLK to the switched-capacitor circuit SCC. However, the clock signal CLK to the switched-capacitor circuit SCC may also be a clock signal obtained by dividing the variable clock signal CLKVe by a fixed frequency division ratio, for example. In other words, the clock signal CLK can be any signal based on the variable clock signal CLKVe.
[0082] Furthermore, the variable clock signal CLKVe is not necessarily limited to the clock signal to the processor PRC; it can be an external clock signal input from outside the clock supply circuit CKS. In this case, the external clock signal should be a signal whose frequency changes according to the processing load at the load.
[0083] <Main effects of the second embodiment> As described above, by using the method according to the second embodiment, the same effects as those described in the first embodiment can be obtained. Furthermore, these effects can be obtained by effectively utilizing the existing variable clock signal CLKVe.
[0084] (Third embodiment) <Regarding the underlying issues> A switched-capacitor circuit (SCC), as shown in Figure 5B, generates the output power supply current Iout by periodically repeating charging and discharging operations on a flying capacitor Cfly. Therefore, in principle, a periodic ripple occurs in the output power supply voltage Vout. For example, if a large ripple voltage causes the output power supply voltage Vout to exceed the expected voltage range, malfunctions may occur in the load, such as the internal power supply circuit 17. Therefore, it is beneficial to use the method described below.
[0085] <Details of the voltage regulator> Figure 14 is a circuit block diagram showing a detailed configuration example of the voltage regulator shown in Figure 6 in a semiconductor device according to the third embodiment. The voltage regulator shown in Figure 14 differs from the configuration example shown in Figure 11 in the following respects: the voltage regulator comprises multiple sets, in this case two sets, of the pMOS transistor MPsen, sense resistor RVsen, voltage-controlled oscillator VCO, and switched capacitor circuit SCC shown in Figure 11.
[0086] In the first set, the pMOS transistor MPsen1 and sense resistor RVsen1 generate a frequency control voltage Vctl1 based on the sensed current Isen1. The voltage-controlled oscillator VCO1 generates a clock signal CLK1 based on the frequency control voltage Vctl1 and supplies it to the switched capacitor circuit SCC1. Similarly, in the second set, the pMOS transistor MPsen2 and sense resistor RVsen2 generate a frequency control voltage Vctl2 based on the sensed current Isen2. The voltage-controlled oscillator VCO2 generates a clock signal CLK2 based on the frequency control voltage Vctl2 and supplies it to the switched capacitor circuit SCC2.
[0087] Switched capacitor circuit SCC1 outputs an output power supply current IoutS1 to power supply wiring PL1. Switched capacitor circuit SCC2 outputs an output power supply current IoutS2 to the same power supply wiring PL1. The two sense resistor elements RVsen1 and RVsen2 are variable resistor elements, as in the case of Figure 11. Here, we assume that the values of the two sense currents Isen1 and Isen2 are the same, that is, the sizes of the two pMOS transistors MPsen1 and MPsen2 are the same. In this case, the two sense resistor elements RVsen1 and RVsen2 are set to have different resistance values.
[0088] Thus, in Figure 14, the single switched-capacitor circuit SCC shown in Figure 11 is divided into multiple switched-capacitor circuits SCC1 and SCC2. Consequently, the capacitance value of the flying capacitor Cfly per divided switched-capacitor circuit can be reduced, thereby suppressing the ripple voltage. Furthermore, since the output current per divided switched-capacitor circuit can be reduced, the control gain of the control loop can be lowered.
[0089] A control loop is a loop in which the output power supply current IoutS of a switched capacitor circuit SCC changes in response to the output power supply current IoutL of an LDO regulator LDOR, and the output power supply current IoutL changes again accordingly. In such a control loop, phase compensation can be easily performed by adding an integrating capacitor Cc to the amplifier circuit AMPc, or by lowering the gain of the amplifier circuit AMPc, as shown in Figure 10A. As a result, it becomes easier to ensure the stability of the control loop.
[0090] Figure 15 is a schematic diagram showing an example of the operation of the voltage regulator shown in Figure 14. Similar to Figure 7, Figure 15 shows the relationship between the load current Iload, the two output power supply currents IoutL and IoutS, and the power efficiency "Pout / Pin". The value of the output power supply current IoutS is the sum of the two output power supply currents IoutS1 and IoutS2 from the two switched capacitor circuits SCC1 and SCC2.
[0091] In Figure 15, the voltage-controlled oscillator VCO1 starts generating the clock signal CLK1 when the output power supply current IoutL from the LDO regulator LDOR exceeds the threshold (first threshold) Ith1. Then, as in Figure 7, the voltage-controlled oscillator VCO1 controls the increase in load current Iload to be covered by the output power supply current IoutS1 of the switched-capacitor circuit SCC1. This improves the power efficiency "Pout / Pin". The threshold Ith1 is determined by the resistance value of the sense resistor element RVsen1.
[0092] Here, the divided switched-capacitor circuit SCC1 has a smaller current supply capacity compared to the case in Figure 9, due to the smaller capacitance of the flying capacitor Cfly. Therefore, if the load current Iload increases beyond the current supply capacity of the switched-capacitor circuit SCC1, the increase is supplied by the LDO regulator LDOR. In this way, as the output power supply current IoutL of the LDO regulator LDOR increases, the power efficiency "Pout / Pin" decreases by that amount.
[0093] However, if the load current Iload increases further, and consequently the output power supply current IoutL from the LDO regulator LDOR also increases further, the switched-capacitor circuit SCC2 is activated. That is, the voltage-controlled oscillator VCO2 starts generating the clock signal CLK2 when the output power supply current IoutL exceeds the threshold (second threshold) Ith2. The voltage-controlled oscillator VCO2 then controls the output power supply current IoutS2 of the switched-capacitor circuit SCC2 to cover any further increase in the load current Iload. Note that the threshold Ith2 is determined by the resistance value of the sense resistor element RVsen2 and is different from the threshold Ith1.
[0094] <Main effects of the third embodiment> As described above, by using the method according to the third embodiment, the same effects as those described in the first embodiment can be obtained. Furthermore, by dividing the switched-capacitor circuit SCC, the ripple voltage generated in the output power supply voltage Vout can be suppressed.
[0095] (Fourth embodiment) <Details of the voltage regulator> Figure 16 is a circuit block diagram showing a detailed configuration example of the voltage regulator shown in Figure 6 in a semiconductor device according to the fourth embodiment. The voltage regulator shown in Figure 16 differs from the configuration example shown in Figure 14 in the following two points. The first difference is that multiple LDO regulators, two in this example, LDOR1 and LDOR2, are provided. The second difference is that the current sensing circuit CSEN includes two current sense transistor groups TRS1 and TRS2 corresponding to the two LDO regulators LDOR1 and LDOR2.
[0096] The two LDO regulators LDOR1 and LDOR2 output two output power supply currents IoutL1 and IoutL2, respectively, to a common power supply wiring PL1. Meanwhile, the current sense transistor group TRS1 comprises two pMOS transistors MPsen1 and MPsen2, as in the case of Figure 14. These two pMOS transistors MPsen1 and MPsen2 carry two sense currents Isen11 and Isen12, which are proportional to the magnitude of the output power supply current IoutL1 of the LDO regulator LDOR1. These two sense currents Isen11 and Isen12 may be the same value, as in the case of Figure 14.
[0097] Similarly, the current sense transistor group TRS2, although not shown in the diagram, includes two pMOS transistors MPsen1 and MPsen2. These two pMOS transistors MPsen1 and MPsen2 supply two sense currents Isen21 and Isen22, which are proportional to the magnitude of the output power supply current IoutL2 of the LDO regulator LDOR2. These two sense currents Isen21 and Isen22 may also be the same value.
[0098] The sense resistor element RVsen1 adds the currents from the two pMOS transistors MPsen1 included in the two current sense transistor groups TRS1 and TRS2 and converts them into a frequency control voltage Vctl1. In other words, the sense resistor element RVsen1 converts the sum of the two detection currents Isen11 and Isen21 into a frequency control voltage Vctl1. Similarly, the sense resistor element RVsen2 adds the currents from the two pMOS transistors MPsen2 included in the two current sense transistor groups TRS1 and TRS2 and converts them into a frequency control voltage Vctl2. In other words, the sense resistor element RVsen2 converts the sum of the two detection currents Isen12 and Isen22 into a frequency control voltage Vctl2.
[0099] In this way, the current sensing circuit CSEN detects the magnitude of the sum of the two output power supply currents IoutL1 and IoutL2 from multiple LDO regulators, LDOR1 and LDOR2 in this example. The clock supply circuit CKS then supplies a clock signal CLK to the switched-capacitor circuit SCC based on the magnitude of this sum. In this example, the voltage-controlled oscillator VCO1 supplies a clock signal CLK1 to the switched-capacitor circuit SCC1 based on a frequency-controlled voltage Vctl1 representing the magnitude of the sum. Similarly, the voltage-controlled oscillator VCO2 supplies a clock signal CLK2 to the switched-capacitor circuit SCC2 based on a frequency-controlled voltage Vctl2 representing the magnitude of the sum.
[0100] Note that although the example here uses two switched-capacitor circuits SCC1 and SCC2, the same applies when using a single switched-capacitor circuit SCC. In this case, the pMOS transistor MPsen2, sense resistor RVsen2, voltage-controlled oscillator VCO2, and switched-capacitor circuit SCC2 are removed from Figure 16.
[0101] In other words, as a basic configuration, one switched-capacitor circuit SCC is assigned to each of the N LDO regulators LDOR. This single switched-capacitor circuit SCC is then controlled based on the sum of the currents of the N LDO regulators LDOR. In addition to this basic configuration, the switched-capacitor circuit SCC may be divided, as shown in Figure 14.
[0102] Here, for example, one configuration is conceivable in which the LDO regulator LDOR and switched capacitor regulator SCR shown in Figure 11 are considered as one set, and multiple sets are connected in common to the power supply wiring PL1. However, in this case, the operation of the switched capacitor regulator SCR may be biased towards one of the multiple sets. On the other hand, as shown in Figure 16, such bias can be prevented by using the sum current of N LDO regulators LDOR.
[0103] Figure 17 is a schematic diagram showing an example of the arrangement of the voltage regulators shown in Figure 16 within a semiconductor device. In the example shown in Figure 17, the two LDO regulators LDOR1 and LDOR2 are arranged in a dispersed manner within the semiconductor device 10. The voltage-controlled oscillator VCO1 and the switched-capacitor circuit SCC1 are located near the LDO regulator LDOR1. On the other hand, the voltage-controlled oscillator VCO2 and the switched-capacitor circuit SCC2 are located at a distance from the LDO regulator LDOR2.
[0104] Thus, each of the multiple LDO regulators (LDOR) and the multiple switched capacitor circuits (SCC) can be appropriately distributed within the semiconductor device 10. Specifically, they can be placed near locations where loads with high current consumption are located. This suppresses IR drop throughout the semiconductor device 10. Furthermore, the number of LDO regulators (LDOR) and switched capacitor circuits (SCC) can be appropriately adjusted according to the amount of current required by the load.
[0105] <Main effects of the fourth embodiment> As described above, by using the method according to the fourth embodiment, the same effects as those described in the first embodiment can be obtained. Furthermore, even when multiple LDO regulators LDOR are connected to a common power supply wiring, it becomes possible to operate the switched-capacitor circuit SCC appropriately.
[0106] (Fifth embodiment) <Regarding the underlying issues> For example, consider a scenario where the load current Iload suddenly decreases in response to an external reset command. In this case, the LDO regulator LDOR can rapidly reduce the output power supply current IoutL in response to the sudden decrease in load current Iload due to its fast load transient response. On the other hand, the switched-capacitor circuit SCC, due to its circuit configuration, has a slower load transient response compared to the LDO regulator LDOR.
[0107] Furthermore, in the embodiment described above, a control loop is formed. This control loop can also slow down the load transient response of the switched-capacitor circuit SCC. As a result, the switched-capacitor circuit SCC continues to output the output power supply current IoutS for a certain period of time, even though the load current Iload has decreased sharply. Consequently, there was a risk that the output power supply voltage Vout would rise above the load's withstand voltage. Therefore, it is beneficial to use the method described below.
[0108] <Details of the voltage regulator> Figure 18A is a circuit block diagram showing a detailed configuration example of the voltage regulator shown in Figure 6 in the semiconductor device according to the fifth embodiment. Figure 18B is a circuit diagram showing a configuration example of the voltage-controlled oscillator VCOa in Figure 18A. The voltage regulator shown in Figure 18A differs from the configuration example shown in Figure 11 in the following three points.
[0109] The first difference is that the current sensing circuit CSEN includes a pMOS transistor MPsen2 and a sense resistor RsenS, in addition to the pMOS transistor MPsen1 and sense resistor RVsen1 similar to those in Figure 11. The second difference is that the clock supply circuit CKS includes a voltage-controlled oscillator VCOa, which is slightly different from that in Figure 11. The third difference is that the clock supply circuit CKS includes a cutoff circuit 20.
[0110] The same gate voltage VG as that of the pMOS transistor MPsen1 and, consequently, the output transistor, the pMOS transistor MPd, is applied to the pMOS transistor MPsen2. As a result, a detection current Isen2, proportional to the magnitude of the output power supply current IoutL, flows through the pMOS transistor MPsen2. The sense resistor RsenS converts this detection current Isen2 into a stop voltage Vstp. The sense resistor RVsen1, as in the case of Figure 11, converts the detection current Isen1 flowing through the pMOS transistor MPsen1 into a frequency control voltage Vctl and outputs it to the voltage-controlled oscillator VCOa.
[0111] As shown in FIG. 18B, the voltage controlled oscillator VCOa includes a pMOS transistor MPc3 and a resistance element Rc3 in addition to the respective circuits shown in FIG. 10A. The pMOS transistor MPc3 short-circuits the output node of the integrating circuit ITC to the power supply line PL2 via the resistance element Rc3 when the stop signal STP is asserted to the "L" level. On the other hand, the cutoff circuit 20 shown in FIG. 18A includes a comparator circuit CMPs. The comparator circuit CMPs compares the stop voltage Vstp and the reference voltage VREFs, and asserts the stop signal STP to the "L" level when "Vstp < VREFs".
[0112] When the stop signal STP is asserted, the two bias circuits IBS1 and IBS2 stop supplying the bias current Ibs with a predetermined time constant based on the resistance element Rc3 and the integration capacitor Cc. As a result, the voltage controlled oscillator VCOa stops supplying the clock signal CLK to the switched capacitor circuit SCC. Note that the reference voltage VREFs is set to a value lower than, for example, the threshold value Ith shown in FIG. 7. Further, the predetermined time constant is set to a relatively short time.
[0113] As described above, the clock supply circuit CKS includes the cutoff circuit 20 that emergently stops supplying the clock signal CLK to the switched capacitor circuit SCC when the output power supply current IoutL becomes smaller than a predetermined value. For example, the voltage controlled oscillator VCO shown in FIG. 10A may require a certain amount of time to stop supplying the clock signal CLK in response to a sudden decrease in the load current Iload. In such a case, the clock signal CLK can be rapidly stopped by using the voltage controlled oscillator VCOa shown in FIG. 10B.
[0114] Figure 19 is a timing chart showing an example of the operation of the voltage regulator shown in Figure 18A. In Figure 19, for example, at a certain time, an external reset command RST is input, and the load current Iload decreases sharply. Accordingly, the output power supply current IoutL from the LDO regulator LDOR also decreases sharply. However, the output power supply current IoutS from the switched capacitor circuit SCC decreases gradually if the cutoff circuit 20 is not provided. In this case, the output power supply voltage Vout may rise above the load's withstand voltage.
[0115] On the other hand, when a cutoff circuit 20 as shown in Figure 18A is provided, the output power supply current IoutS from the switched-capacitor circuit SCC decreases sharply in response to the stop signal STP. As a result, the rise in the output power supply voltage Vout that accompanies the sharp decrease in the load current Iload can be suppressed. In other words, the output power supply voltage Vout can be kept from exceeding the load's withstand voltage.
[0116] <Main effects of the fifth embodiment> As described above, by using the method according to the fifth embodiment, the same effects as those described in the first embodiment can be obtained. Furthermore, the rise in the output power supply voltage Vout that occurs when the load current Iload suddenly decreases can be suppressed.
[0117] The present invention has been described in detail above based on embodiments, but the present invention is not limited to the embodiments described above and can be modified in various ways without departing from its essence. For example, the embodiments described above are described in detail in order to explain the present invention in an easy-to-understand manner and are not necessarily limited to those having all the described configurations. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add a configuration from another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with a configuration from another embodiment. [Explanation of Symbols]
[0118] 10 Semiconductor Devices 20. Cutoff circuit AMP1 Amplifier Circuit CKS Clock Supply Circuit CLK clock signal CLKVe variable clock signal CSEN current sensing circuit Cfly Flying Capacitor Cout output capacitor IBS1, IBS2 bias circuit ITC Integrator Circuit Iout, IoutL, IoutS Output power supply current Isen detection current Ith threshold LDOR LDO regulator MPd pMOS transistor (output transistor) MPsen pMOS transistor (current sense transistor) PL1, PL2 Power Wiring PRC Processor ROSC Ring Oscillator Rsen, RVsen sense resistor element SCC Switched Capacitor Circuit SCR Switched Capacitor Regulator VCO (Voltage Controlled Oscillator) VG Gate voltage (control voltage) Vin Input power supply voltage Vout Output power supply voltage
Claims
1. A first power supply wiring that supplies power to a predetermined load, An LDO (Low Drop Out) regulator that takes an input power supply voltage as input and outputs a first output power supply voltage lower than the input power supply voltage and a first output power supply current to the first power supply wiring, A switched capacitor circuit that receives the aforementioned input power supply voltage and alternately switches between charging and discharging operations for the flying capacitor by switching according to the clock signal, thereby outputting a second output power supply current to the first power supply wiring, A current detection circuit for detecting the magnitude of the first output power supply current, A clock supply circuit that supplies the clock signal to the switched-capacitor circuit based on the detection result of the current detection circuit, Equipped with, Semiconductor equipment.
2. In the semiconductor device described in claim 1, The clock supply circuit starts supplying the clock signal to the switched capacitor circuit when the magnitude of the first output power supply current exceeds a predetermined threshold. Semiconductor equipment.
3. In the semiconductor device described in claim 2, The clock supply circuit is further configured to increase the frequency of the clock signal in response to an increase in the first output power supply current. Semiconductor equipment.
4. In the semiconductor device described in claim 3, The LDO regulator is An output transistor is connected between the second power supply wiring to which the input power supply voltage is applied and the first power supply wiring, An amplifier circuit that applies a control voltage to the output transistor so that the error between the value of the first output power supply voltage and the target value approaches zero, Equipped with, The current detection circuit is, A current sense transistor is composed of a transistor set to a predetermined size ratio with respect to the output transistor, and when the same control voltage as the output transistor is applied, it flows a detection current proportional to the first output power supply current. A sense resistor element that converts the aforementioned detection current into a frequency control voltage, Equipped with, The clock supply circuit consists of a voltage-controlled oscillator. The voltage-controlled oscillator starts generating the clock signal when the frequency control voltage exceeds the lower limit of operation, and determines the frequency of the clock signal based on the frequency control voltage. Semiconductor equipment.
5. In the semiconductor device according to claim 4, The sense resistor element is a variable resistor element. Semiconductor equipment.
6. In the semiconductor device according to claim 4, The aforementioned voltage-controlled oscillator is An integrating circuit that integrates the error between the frequency control voltage and a predetermined reference voltage, A bias circuit that generates a bias current based on the integration result of the aforementioned integrating circuit, A ring oscillator that operates by the aforementioned bias current, Equipped with, Semiconductor equipment.
7. In the semiconductor device described in claim 2, The clock supply circuit is configured to receive an external clock signal from an external source and, when the magnitude of the first output power supply current exceeds the threshold, to supply the clock signal based on the external clock signal to the switched-capacitor circuit. Semiconductor equipment.
8. In the semiconductor device according to claim 7, The aforementioned load includes a processor, The processor is supplied with a variable clock signal whose frequency changes according to the processing load. The external clock signal is the variable clock signal. Semiconductor equipment.
9. In the semiconductor device described in claim 2, Multiple sets of the switched-capacitor circuit and the clock supply circuit are provided, including the first set and the second set. The clock supply circuit included in the first set starts supplying the clock signal to the switched capacitor circuit included in the first set when the magnitude of the first output power supply current exceeds a predetermined first threshold. The clock supply circuit included in the second set starts supplying the clock signal to the switched capacitor circuit included in the second set when the magnitude of the first output power supply current exceeds a predetermined second threshold. The first threshold and the second threshold are different from each other. Semiconductor equipment.
10. In the semiconductor device described in claim 2, Multiple LDO regulators are provided, Each of the plurality of LDO regulators outputs the first output power supply current to the common first power supply wiring. The current detection circuit detects the magnitude of the sum of the first output power supply currents output from each of the plurality of LDO regulators. Semiconductor equipment.
11. In the semiconductor device described in claim 2, The clock supply circuit includes a cutoff circuit that, when the magnitude of the first output power supply current falls below a predetermined value, emergency stops the supply of the clock signal to the switched capacitor circuit. Semiconductor equipment.