Semiconductor device, method for manufacturing a semiconductor device

Abstract

To improve corrosion resistance. [Solution] The semiconductor device 10 includes a semiconductor substrate 21, a semiconductor layer 22, a base layer 24, an emitter layer 26, an insulating layer 30, a base electrode 16, an emitter electrode 17, a resistive element 12, a wiring layer 18, and a passivation layer 80. The resistive element 12 is provided on the insulating layer 30 and is made of a material containing Si. The wiring layer 18 is provided on the insulating layer 30 and is electrically connected to the resistive element 12, and is made of a material containing Si and Cu. The passivation layer 80 covers the resistive element 12, the wiring layer 18, and the insulating layer 30. The passivation layer 80 includes a first film thickness portion 83 provided on the wiring layer 18 and having a first film thickness T1, and a second film thickness portion 84 provided on the resistive element 12 and having a second film thickness T2 that is greater than the first film thickness T1.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor element that is a bipolar transistor including a first resistance element. The first resistance element is connected in series to a first electrode in a conductive path between the first electrode disposed on an insulating layer and a base layer. The semiconductor element includes a first wiring layer that is connected in series to the first resistance element, disposed on the insulating layer, and in contact with the base layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] Improvement in corrosion resistance of electrodes and wiring layers for external connection is required.

[0005] A semiconductor device according to one aspect of the present disclosure includes: a semiconductor substrate of a first conductivity type including a first substrate surface; a semiconductor layer of a first conductivity type provided on the first substrate surface; a base layer of a second conductivity type provided on the first surface of the semiconductor layer and in contact with the semiconductor layer; an emitter layer of a first conductivity type provided on the first surface of the base layer and in contact with the base layer; an insulating layer disposed on the semiconductor layer, the base layer, and the emitter layer; a base electrode provided on the insulating layer and electrically connected to the base layer, and made of a material containing Si and Cu; and a semiconductor device provided on the insulating layer and electrically connected to the emitter layer. The device comprises an emitter electrode made of a material containing Si and Cu, a resistive element made of a material containing Si and provided on the insulating layer and electrically connected to the base electrode, a wiring layer made of a material containing Si and Cu and provided on the insulating layer and electrically connected to the resistive element, and a passivation layer covering the resistive element, the wiring layer and the insulating layer, wherein the passivation layer is provided on the wiring layer and includes a first film thickness portion having a first film thickness, and a second film thickness portion provided on the resistive element and having a second film thickness greater than the first film thickness. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a schematic plan view of an exemplary semiconductor device according to one embodiment. [Figure 2] Figure 2 is a schematic plan view showing the wiring structure of the semiconductor device shown in Figure 1. [Figure 3] Figure 3 is a schematic plan view showing the base layer and emitter layer of the semiconductor device shown in Figure 1. [Figure 4] Figure 4 is a schematic cross-sectional view illustrating the internal configuration of the semiconductor device shown in Figure 1. [Figure 5] Figure 5 is a circuit diagram of the semiconductor device shown in Figure 1. [Figure 6] Figure 6 is a schematic cross-sectional view illustrating the manufacturing process of the semiconductor device shown in Figure 1. [Figure 7] Figure 7 is a schematic cross-sectional view showing the manufacturing process following Figure 6. [Figure 8] Figure 8 is a schematic cross-sectional view showing the manufacturing process following Figure 7. [Figure 9] Figure 9 is a schematic cross-sectional view showing the manufacturing process following Figure 8. [Figure 10] Figure 10 is a schematic cross-sectional view showing the manufacturing process following Figure 9. [Figure 11] Figure 11 is a schematic cross-sectional view showing the manufacturing process following Figure 10. [Figure 12] Figure 12 is a schematic cross-sectional view showing the manufacturing process following Figure 11. [Figure 13] Figure 13 is a schematic cross-sectional view of an exemplary semiconductor device relating to a modification example. [Figure 14] Figure 14 is a schematic cross-sectional view of an exemplary semiconductor device relating to a modification example. [Figure 15] Figure 15 is a schematic cross-sectional view of an exemplary semiconductor device relating to a modification example. [Figure 16] Figure 16 is a schematic cross-sectional view of an exemplary semiconductor device relating to a modification example.

[0007] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of this disclosure will be described with reference to the attached drawings. Note that, for the sake of simplicity and clarity, the components shown in the drawings are not necessarily drawn to a consistent scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The attached drawings are merely illustrative of embodiments of this disclosure and should not be considered limiting. Terms such as "first," "second," and "third" in this disclosure are used simply to distinguish objects and do not rank them.

[0008] The following detailed description includes apparatus, systems, and methods that embody exemplary embodiments of the Disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the Disclosure or the application and use of such embodiments.

[0009] As used in this disclosure, the phrase "at least one" means "one or more" of the desired options. For example, if there are two options, the phrase "at least one" means "only one option" or "both of the two options." As another example, if there are three or more options, the phrase "at least one" means "only one option" or "any combination of two or more options."

[0010] As used in this disclosure, the term “on” includes both the meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, the expression “the first layer is formed on the second layer” is intended to mean that in one embodiment the first layer may be in contact with and directly positioned on the second layer, while in other embodiments the first layer may be positioned above the second layer without contact. In other words, the term “on” does not preclude structures in which another layer is formed between the first and second layers.

[0011] <Embodiment> Referring to Figures 1 to 5, one embodiment of the semiconductor device 10 will be described. Figure 1 is a schematic plan view of the semiconductor device 10. Figure 2 is a schematic plan view showing the wiring structure of the semiconductor device 10 shown in Figure 1. Figure 3 is a schematic plan view showing the base layer 24 and emitter layer 26 of the semiconductor device 10 shown in Figure 1. Figure 4 is a schematic cross-sectional view schematically showing the internal configuration of the semiconductor device 10 shown in Figure 1. Figure 5 is a circuit diagram of the semiconductor device 10 shown in Figure 1.

[0012] Figures 1 to 3 show mutually orthogonal XYZ axes. As used in this disclosure, the term "planar view" refers to viewing the semiconductor device 10 along the Z-axis direction of the mutually orthogonal XYZ axes shown in Figures 1 to 3. Unless explicitly stated otherwise, "planar view" refers to viewing the object (semiconductor device 10 and its components) along the Z-axis.

[0013] (Outline configuration of a semiconductor device) As shown in FIG. 5, the semiconductor device 10 includes a transistor 11 and a resistive element 12 connected to the transistor 11. This semiconductor device 10 may be referred to as a digital transistor. The semiconductor device 10 includes a collector electrode 15 connected to the collector of the transistor 11, a base electrode 16 connected to the base of the transistor 11, and an emitter electrode 17 connected to the emitter of the transistor 11. The resistive element 12 includes a first resistive element 13 and a second resistive element 14. The first resistive element 13 is connected between the base electrode 16 and the base of the transistor 11. The second resistive element 14 is connected between the base of the transistor 11 and the emitter electrode 17.

[0014] (Semiconductor substrate, semiconductor layer) As shown in FIG. 3 and FIG. 4, the semiconductor device 10 includes a semiconductor substrate 21 and a semiconductor layer 22.

[0015] The semiconductor substrate 21 has a rectangular flat plate shape. It can be said that the semiconductor substrate 21 is a flat plate whose thickness direction is the Z-axis direction. As shown in FIG. 4, the semiconductor substrate 21 includes a first substrate surface 21S and a second substrate surface 21R opposite to the first substrate surface 21S. As shown in FIG. 3, the semiconductor substrate 21 includes a plurality of side surfaces 211, 212, 213, 214. The first side surface 211 and the second side surface 212 constitute both side surfaces in the Y-axis direction in plan view. The third side surface 213 and the fourth side surface 214 constitute both side surfaces in the X-axis direction in plan view.

[0016] In one example, the semiconductor substrate 21 is made of a material containing silicon (Si). The semiconductor substrate 21 may be made of a material containing silicon carbide (SiC) or gallium nitride (GaN). The semiconductor substrate 21 contains impurities of the first conductivity type. The first conductivity type may be n-type in one example. The impurities of the first conductivity type may be antimony (Sb), arsenic (As) or phosphorus (P).

[0017] As shown in Figure 4, the semiconductor layer 22 is provided on the first substrate surface 21S of the semiconductor substrate 21. The semiconductor layer 22 includes the first surface 22S and the second surface 22R opposite to the first surface 22S. The second surface 22R of the semiconductor layer 22 is in contact with the first substrate surface 21S of the semiconductor substrate 21.

[0018] As shown in Figures 1 to 3, the semiconductor layer 22 includes a plurality of sides 221, 222, 223, and 224. The first side 221 and the second side 222 constitute both sides in the Y-axis direction in a plan view. The third side 223 and the fourth side 224 constitute both sides in the X-axis direction in a plan view. Each side 221 to 224 of the semiconductor layer 22 may be flush with each side 211 to 214 of the semiconductor substrate 21.

[0019] As shown in Figures 1 to 3, the semiconductor layer 22 includes a plurality of corner portions 231 to 234, each composed of two adjacent sides in a plan view. The first corner portion 231 is composed of a first side 221 and a third side 223. The second corner portion 232 is composed of a third side 223 and a second side 222. The third corner portion 233 is composed of a second side 222 and a fourth side 224. The fourth corner portion 234 is composed of a fourth side 224 and a first side 221.

[0020] The semiconductor layer 22 is, in one example, made of a material containing Si. The semiconductor layer 22 may, in one example, be an epitaxial layer provided on the first substrate surface 21S of the semiconductor substrate 21. The semiconductor layer 22 contains impurities of a first conductivity type. The impurity concentration of the semiconductor layer 22 may be lower than the impurity concentration of the semiconductor substrate 21.

[0021] As shown in Figures 2 to 4, a base layer 24 is provided on the first surface 22S of the semiconductor layer 22. The base layer 24 is in contact with the semiconductor layer 22. The base layer 24 contains an impurity of a second conductivity type different from the first conductivity type. The second conductivity type may be p-type, for example. The impurity of the second conductivity type may be boron (B), for example.

[0022] As shown in Figures 2 and 3, the base layer 24 is provided inside each side surface 221 to 224 of the semiconductor layer 22. The outer edge of the base layer 24 is separated from each side surface 221 to 224 of the semiconductor layer 22 and is located inside the semiconductor layer 22. Also, the outer edge of the base layer 24 is located closer to the first corner portion 231 than to the third corner portion 233 of the semiconductor layer 22. The base layer 24 includes a recessed portion 241 in the third corner portion 233. The recessed portion 241 is the portion of the semiconductor layer 22 where the base layer 24 is not provided. In one example, the recessed portion 241 may be provided such that the base electrode 16 and the first resistive element 13 do not overlap with the base layer 24, depending on the base electrode 16 and the first resistive element 13.

[0023] As shown in Figures 3 and 4, the first surface 24S of the base layer 24 is provided with a plurality of contact regions 25. The plurality of contact regions 25 are arranged along the X-axis and Y-axis directions. The plurality of contact regions 25 are positioned to overlap with the base wiring 61 shown in Figure 2 in a plan view. Also, the plurality of contact regions 25 are positioned not to overlap with the emitter wiring 71 shown in Figure 2 in a plan view. The plurality of contact regions 25 may contain impurities of the second conductivity type. The impurity concentration of the contact regions 25 may be higher than the impurity concentration of the base layer 24.

[0024] As shown in Figures 3 and 4, an emitter layer 26 is provided on the first surface 24S of the base layer 24. The emitter layer 26 is in contact with the base layer 24. The emitter layer 26 contains impurities of a first conductivity type. The impurity concentration of the emitter layer 26 may be higher than that of the semiconductor layer 22. A contact region 27 is provided on the first surface 26S of the emitter layer 26. The contact region 27 may contain impurities of a first conductivity type. The impurity concentration of the contact region 27 may be higher than that of the emitter layer 26.

[0025] As shown in Figure 3, the emitter layer 26 is located inside the outer edge of the base layer 24. The emitter layer 26 may be provided so as to surround each of the multiple contact regions 25 of the base layer 24.

[0026] (Insulating layer) As shown in Figure 4, an insulating layer 30 is provided on the first surface 22S of the semiconductor layer 22. The insulating layer 30 is located on the semiconductor layer 22, the base layer 24, and the emitter layer 26. The insulating layer 30 covers the semiconductor layer 22, the base layer 24, and the emitter layer 26.

[0027] The insulating layer 30 may include a first insulating layer 31 and a second insulating layer 32. The first insulating layer 31 may be provided in regions corresponding to the base electrode 16 and the emitter electrode 17. The second insulating layer 32 may cover the first insulating layer 31. The film thickness of the first insulating layer 31 and the second insulating layer 32 may be 0.5 μm or more and 10 μm or less. The film thickness of the first insulating layer 31 and the film thickness of the second insulating layer 32 may be equal to or different from each other.

[0028] The insulating layer 30 may be made of a material containing at least one of silicon oxide (SiO2), silicon oxynitride (SiON), and silicon nitride (SiN). In one example, the insulating layer 30 is made of a material containing SiO2. In one example, the first insulating layer 31 and the second insulating layer 32 are made of the same material. The first insulating layer 31 and the second insulating layer 32 may be a single, integrally constructed object.

[0029] In one example, the first insulating layer 31 is provided so as to overlap the base electrode 16 and the emitter electrode 17 in a plan view. The portion of the insulating layer 30 composed of the first insulating layer 31 and the second insulating layer 32 mitigates impacts such as wire bonding to the base electrode 16 and the emitter electrode 17.

[0030] The insulating layer 30 includes an opening 33 that partially exposes the base layer 24. The opening 33 exposes the contact area 25 of the base layer 24. The insulating layer 30 also includes an opening 34 that partially exposes the emitter layer 26. The opening 34 exposes the contact area 27 of the emitter layer 26.

[0031] (First resistive element, second resistive element) As shown in Figure 4, the semiconductor device 10 includes a resistive element 12. The resistive element 12 is provided on an insulating layer 30. In one example, the resistive element 12 includes a first resistive element 13 and a second resistive element 14. The first resistive element 13 and the second resistive element 14 are provided on an insulating layer 30. The first resistive element 13 and the second resistive element 14 are electrically insulated from the semiconductor layer 22 by the insulating layer 30.

[0032] The first resistive element 13 and the second resistive element 14 are made of a material containing Si. In one example, the first resistive element 13 and the second resistive element 14 are made of conductive polysilicon (polycrystalline silicon). The first resistive element 13 and the second resistive element 14 may contain impurities of a first conductivity type or a second conductivity type. The resistivity of the first resistive element 13 and the second resistive element 14 depends on the impurity concentration, for example, 5 × 10⁻⁶. 4 Ω cm or more 7×10 4 The resistance may be adjusted to be less than or equal to Ω·cm. The first resistive element 13 and the second resistive element 14 may have resistance values ​​corresponding to the area and length of the cross-section perpendicular to the current path.

[0033] As shown in Figures 1 and 2, the first resistive element 13 includes a first portion 41 and a second portion 42. In one example, the first portion 41 has a rectangular shape in plan view. The first portion 41 may have a rectangular frame shape in plan view. The second portion 42 extends from the first portion 41. In one example, the second portion 42 extends along the fourth side surface 224 of the semiconductor layer 22 toward the first side surface 221 of the semiconductor layer 22. The width of the second portion 42 gradually decreases from the first portion 41 toward the tip portion 42A. The second portion 42 is also folded back toward the first portion 41.

[0034] The second resistive element 14 is located at the first corner portion 231 of the semiconductor layer 22 in a plan view. The second resistive element 14 includes a first portion 51 and a second portion 52. In one example, the first portion 51 extends along the first side surface 221 of the semiconductor layer 22. In a plan view, the first portion 51 can be said to extend along the X-axis direction. The second portion 52 is the end of the first portion 51, extending from the end 51B near the third side surface 223 of the semiconductor layer 22 towards the second side surface 222 of the semiconductor layer 22, along the third side surface 223 of the semiconductor layer 22. In a plan view, the second portion 52 can be said to extend in the Y-axis direction. The widths of the first portion 51 and the second portion 52 may be equal to or different from each other.

[0035] (wiring layer, electrode) As shown in Figures 1, 2, and 4, the semiconductor device 10 includes a base electrode 16. In one example, the base electrode 16 has a rectangular shape in plan view. In plan view, the base electrode 16 is provided on a third corner portion 233 formed by a second side surface 222 and a fourth side surface 224 of the semiconductor layer 22. In plan view, the base electrode 16 is positioned inward from the second side surface 222 and the fourth side surface 224 of the semiconductor device 10.

[0036] As shown in Figure 4, the base electrode 16 is provided on the insulating layer 30. The base electrode 16 is made of a material containing silicon (Si) and copper (Cu). In one example, the base electrode 16 is made of an aluminum alloy containing both Si and Cu.

[0037] The base electrode 16 is electrically connected to the first resistive element 13. The first portion 41 of the first resistive element 13 is electrically connected to the base electrode 16. As shown in Figure 4, the semiconductor device 10 includes a wiring layer 18. The wiring layer 18 is provided on an insulating layer 30. The wiring layer 18 is electrically connected to the resistive element 12. The wiring layer 18 is electrically insulated from the semiconductor layer 22 by the insulating layer 30. The wiring layer 18 is made of a material containing Si and Cu. In one example, the wiring layer 18 is made of an aluminum alloy containing both Si and Cu.

[0038] As shown in Figures 1, 2, and 4, the wiring layer 18 includes, in one example, base wiring 61 and emitter wiring 71. The base wiring 61 is electrically connected to the base layer 24 and also to the first resistive element 13.

[0039] (Base wiring) As shown in Figure 2, the base wiring 61 includes a first wiring portion 62, a plurality of second wiring portions 63 and third wiring portions 64. The first wiring portion 62 extends along the outer edge of the base layer 24. The first wiring portion 62 has an open annular shape. The first wiring portion 62 has separated ends 62A and 62B at the first corner portion 231 of the semiconductor layer 22. The first wiring portion 62 includes a first wiring 621 extending along the first side surface 221 of the semiconductor layer 22, a second wiring 622 extending along the second side surface 222 of the semiconductor layer 22, a third wiring 623 extending along the third side surface 223 of the semiconductor layer 22, and a fourth wiring 624 connecting the first wiring 621 and the second wiring 622. The fourth wiring 624 includes a portion provided along the recessed portion 241 of the base layer 24 and a portion extending along the fourth side surface 224 of the semiconductor layer 22.

[0040] Multiple second wiring portions 63 extend from the second wiring 622 of the first wiring portion 62 towards the first wiring 621 along the Y-axis. Multiple third wiring portions 64 extend from the fourth wiring 624 of the first wiring portion 62 towards the third wiring 623. Multiple second wiring portions 63 and multiple third wiring portions 64 are electrically connected to the base layer 24 by contact areas 25 provided in the base layer 24.

[0041] The base wiring 61 includes a connection portion 65 provided in the first wiring portion 62. The connection portion 65 extends outward from the fourth wiring 624 towards the semiconductor device 10. In a plan view, the connection portion 65 can be said to extend from the fourth wiring 624 toward the fourth side surface 224 of the semiconductor layer 22. In a plan view, the connection portion 65 overlaps with the tip portion 42A of the first resistive element 13. The connection portion 65 is electrically connected to the first resistive element 13.

[0042] (Emitter wiring) In one example, the emitter wiring 71 is located in the area enclosed by the first wiring portion 62 of the base wiring 61. The first wiring portion 62 of the base wiring 61 can be said to be provided so as to surround the emitter wiring 71.

[0043] The emitter wiring 71 includes an emitter electrode 17, a first wiring portion 72, a plurality of second wiring portions 73 and third wiring portions 74. The emitter electrode 17 has a rectangular shape in plan view. In plan view, the emitter electrode 17 is located at the first corner portion 231 of the semiconductor layer 22.

[0044] The first wiring portion 72 extends from the emitter electrode 17. In one example, the first wiring portion 72 extends from the emitter electrode 17 in a plan view, diagonally across the semiconductor layer 22, toward the third corner portion 233.

[0045] Multiple second wiring portions 73 extend from the first wiring portion 72 along the Y-axis toward the second wiring portion 622 of the base wiring 61. The multiple second wiring portions 73 of the emitter wiring 71 and the multiple second wiring portions 63 of the base wiring 61 are arranged alternately in the X-axis direction.

[0046] Multiple third wiring portions 74 extend from the first wiring portion 72 along the X-axis toward the fourth wiring portion 624 of the base wiring 61. The multiple third wiring portions 74 of the emitter wiring 71 and the multiple third wiring portions 64 of the base wiring 61 are arranged alternately along the Y-axis.

[0047] The emitter wiring 71 includes a connection portion 75. The connection portion 75 extends outward from the emitter electrode 17 to the semiconductor device 10. In a plan view, the connection portion 75 can be said to extend from the emitter electrode 17 toward the first side surface 221 of the semiconductor layer 22. In a plan view, the connection portion 75 overlaps with the first end portion 51A, which is the tip of the first portion 51 of the second resistive element 14. The connection portion 75 is electrically connected to the second resistive element 14. The second resistive element 14 is electrically connected to the emitter electrode 17.

[0048] The second resistive element 14 includes a first end 51A and a second end 52A, which is the tip of the second portion of the second resistive element 14. In a plan view, the second end 52A of the second resistive element 14 overlaps with the second end 62B of the first wiring portion 62 of the base wiring 61. The second end 52A of the second resistive element 14 is electrically connected to the second end 62B of the first wiring portion 62 of the base wiring 61. The second resistive element 14 can be said to be electrically connected to the wiring layer 18 and the emitter electrode 17.

[0049] (Collector electrode) As shown in Figure 4, the semiconductor device 10 includes a collector electrode 15. The collector electrode 15 is provided on the second substrate surface 21R of the semiconductor substrate 21. The collector electrode 15 may be composed of at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, Cu alloy, and Al alloy. In one example, the collector electrode 15 is provided over the entire surface of the second substrate surface 21R of the semiconductor substrate 21.

[0050] (Passive layer) As shown in Figures 1 and 4, the semiconductor device 10 includes a passivation layer 80. The passivation layer 80 is provided on top of the semiconductor layer 22. The passivation layer 80 covers the resistive element 12, the wiring layer 18, and the insulating layer 30.

[0051] The passivation layer 80 covers the base electrode 16. The passivation layer 80 includes a base opening 80X1 that exposes a portion of the base electrode 16. In one example, the base opening 80X1 has a rectangular shape in plan view. The portion of the base electrode 16 exposed by the base opening 80X1 may be used as an external electrode (connection pad) for external connection of the semiconductor device 10.

[0052] The passivation layer 80 covers the wiring layer 18. The wiring layer 18 includes base wiring 61 and emitter wiring 71. The emitter wiring 71 includes emitter electrodes 17. The passivation layer 80 includes an emitter opening 80X2 that exposes a portion of the emitter electrodes 17. In one example, the emitter opening 80X2 has a rectangular shape in plan view. The portion of the emitter electrodes 17 exposed by the emitter opening 80X2 may be used as an external electrode (connection pad) for external connection of the semiconductor device 10.

[0053] As shown in Figure 4, the passivation layer 80 includes a first passivation film 81 and a second passivation film 82. The first passivation film 81 selectively covers the first resistive element 13 and the second resistive element 14. The first passivation film 81 may be made of a material containing at least one of SiO2, SiON, and SiN. In one example, the first passivation film 81 is made of a material containing SiN. The thickness T11 of the first passivation film 81 may be, for example, 0.5 μm or more and 3 μm or less.

[0054] The first passivation film 81 may include a first covering portion 81A that covers the first resistive element 13 and a second covering portion 81B that covers the second resistive element 14. As shown in Figures 2 and 4, the first covering portion 81A covers the top surface 131 and side surface 132 of the first resistive element 13. The first covering portion 81A is provided so as to expose the first portion 41 of the first resistive element 13 and the tip portion 42A of the second portion 42 of the first resistive element 13. The second covering portion 81B covers the top surface 141 and side surface 142 of the second resistive element 14. The second covering portion 81B is provided so as to expose the first end portion 51A of the second resistive element 14. Although not shown in the drawings, the second covering portion 81B is provided so as to expose the second end portion 52A of the second resistive element 14 (see Figures 1 and 2).

[0055] As shown in Figure 4, the second passivation film 82 covers the insulating layer 30, the wiring layer 18, and the first passivation film 81. The second passivation film 82 may be made of a material containing at least one of SiO2, SiON, and SiN. In one example, the second passivation film 82 is made of a material containing SiN. The thickness T12 of the second passivation film 82 may be, for example, 0.5 μm or more and 3 μm or less.

[0056] The second passivation film 82 includes a base opening 80X1 and an emitter opening 80X2 as shown in Figure 1. The second passivation film 82 covers the first passivation film 81 as described above. The second passivation film 82 includes a third covering portion 82A that covers the first covering portion 81A of the first passivation film 81, and a fourth covering portion 82B that covers the second covering portion 81B of the first passivation film 81.

[0057] The passivation layer 80 includes a portion with a laminated structure of the first passivation film 81 and the second passivation film 82, and a portion with a single-layer structure of only the second passivation film 82. Therefore, the passivation layer 80 includes a portion with a film thickness due to the second passivation film 82, and a portion with a film thickness due to both the first passivation film 81 and the second passivation film 82. The film thickness due to the second passivation film 82 is called the first film thickness T1. In the passivation layer 80, the portion with the first film thickness T1 is called the first film thickness portion 83. The first film thickness T1 is equal to the film thickness T12 of the second passivation film 82. The film thickness due to both the first passivation film 81 and the second passivation film 82 is called the second film thickness T2. In the passivation layer 80, the portion with the second film thickness T2 is called the second film thickness portion 84. The second film thickness T2 is equal to the sum of the film thickness T11 of the first passivation film 81 and the film thickness T12 of the second passivation film 82 (= T11 + T12).

[0058] The first film thickness portion 83 is the portion not covered by the first passivation film 81 and is provided on top of the insulating layer 30 and the wiring layer 18. The second film thickness portion 84 includes a second passivation film 82 and is provided on the first resistive element 13 and the second resistive element 14, that is, on the resistive element 12. The passivation layer 80 can be said to include a first film thickness portion 83 provided on the wiring layer 18 and having a first film thickness T1, and a second film thickness portion 84 provided on the resistive element 12 and having a second film thickness T2 that is greater than the first film thickness T1.

[0059] (Relationship between the wiring layer and the passivation layer) As shown in Figure 4, the connection portion 65 of the base wiring 61 overlaps with the tip portion 42A of the first resistive element 13 in a plan view. The connection portion 65 of the base wiring 61 is in contact with the upper surface 131 of the first resistive element 13. It can be said that the wiring layer 18 (base wiring 61) includes a portion that overlaps with the first resistive element 13.

[0060] Furthermore, the connection portion 65 of the base wiring 61 overlaps with the first passivation film 81 (first covering portion 81A) covering the first resistive element 13 in a plan view. The connection portion 65 of the base wiring 61 is in contact with the upper surface 811 of the first passivation film 81. It can be said that the wiring layer 18 (base wiring 61) includes a portion that overlaps with the first passivation film 81.

[0061] In a plan view, the base electrode 16 overlaps with the first portion 41 of the first resistive element 13. The base electrode 16 is in contact with the upper surface 131 of the first resistive element 13. It can be said that the base electrode 16 includes a portion that overlaps with the first resistive element 13.

[0062] Furthermore, in a plan view, the base electrode 16 overlaps with the first passivation film 81 (first covering portion 81A) that covers the first resistive element 13. The connection portion 65 of the base wiring 61 is in contact with the upper surface 811 of the first passivation film 81. It can be said that the base electrode 16 includes a portion that overlaps with the first passivation film 81.

[0063] The connection portion 75 of the emitter wiring 71 overlaps with the first end portion 51A of the second resistive element 14 in a plan view. The connection portion 75 of the emitter wiring 71 is in contact with the upper surface 141 of the second resistive element 14. It can be said that the wiring layer 18 (emitter wiring 71) includes a portion that overlaps with the second resistive element 14.

[0064] Furthermore, the connection portion 75 of the emitter wiring 71 overlaps with the first passivation film 81 (second covering portion 81B) covering the second resistive element 14 in a plan view. The connection portion 75 of the emitter wiring 71 is in contact with the upper surface 811 of the first passivation film 81. It can be said that the wiring layer 18 (emitter wiring 71) includes a portion that overlaps with the first passivation film 81.

[0065] As shown in Figure 2, the second end 62B of the first wiring portion 62 of the base wiring 61 overlaps with the second end 52A of the second resistive element 14 in a plan view. Although not shown in the drawing, the second end 62B of the first wiring portion 62 overlaps with the first passivation film 81 (second covering portion 81B) covering the second resistive element 14 in a plan view, similar to the connection portion 75 of the emitter wiring 71, and is in contact with the upper surface 811 of the first passivation film 81.

[0066] <Manufacturing method for semiconductor devices> A method for manufacturing the semiconductor device 10 will be described with reference to Figures 6 to 12. Figures 6 to 12 are schematic cross-sectional views illustrating an exemplary manufacturing process of the semiconductor device 10. Figures 6 to 12 correspond to the cross-sectional view in Figure 4. For ease of understanding, components similar to those in Figure 4 are denoted by the same reference numerals in Figures 6 to 12.

[0067] As shown in Figure 6, the method for manufacturing the semiconductor device 10 includes forming a base layer 24 and an emitter layer 26 on the semiconductor device 10. The semiconductor substrate 21 and semiconductor layer 22 may be prepared, for example, as a wafer including the semiconductor substrate 21 and the semiconductor layer 22. The semiconductor substrate 21 may be a Si substrate containing impurities of a first conductivity type. The semiconductor layer 22 may be, for example, an epitaxial layer of a first conductivity type formed by epitaxial growth from the first substrate surface 21S of the semiconductor substrate 21.

[0068] First, a base layer 24 is formed on the semiconductor layer 22. The base layer 24 is formed by adding a second-type impurity to a part of the semiconductor layer 22, for example by ion implantation. Next, an emitter layer 26 is formed on the base layer 24. The emitter layer 26 is formed by adding a first-type impurity to a part of the emitter layer 26, for example by ion implantation.

[0069] A method for manufacturing the semiconductor device 10 includes forming a first insulating layer 31. The first insulating layer 31 is formed by forming an insulating film covering the semiconductor layer 22, the base layer 24, and the emitter layer 26, for example by a CVD (Chemical Vapor Deposition) method, and then selectively removing the insulating film by, for example, wet etching. The selective removal may be performed by dry etching.

[0070] As shown in Figure 7, the method for manufacturing the semiconductor device 10 includes forming a second insulating layer 32. The second insulating layer 32 is formed, for example, by a CVD (Chemical Vapor Deposition) method, by an insulating film covering the first insulating layer 31, semiconductor layer 22, base layer 24, and emitter layer 26 shown in Figure 7.

[0071] As shown in Figure 8, the manufacturing method of the semiconductor device 10 includes forming resistive elements 12 (first resistive element 13, second resistive element 14) on an insulating layer 30 composed of a first insulating layer 31 and a second insulating layer 32. In one example, the resistive elements 12 are made of conductive polysilicon. First, a polysilicon film is formed over the entire surface, for example by a CVD method. Next, impurities are added to the polysilicon film, for example by ion implantation. Then, the resistive elements 12 are formed by selectively removing the polysilicon film.

[0072] As shown in Figure 9, the manufacturing method of the semiconductor device 10 includes forming a first passivation film 81. The first passivation film 81 is formed to cover the resistive elements 12 (first resistive element 13, second resistive element 14). The first passivation film 81 is also formed to expose the connection portions of the resistive elements 12. The connection portions of the resistive elements 12 include the first portion 41 and tip portion 42A of the first resistive element 13, the first end portion 51A of the first portion 51 and the second end portion 52A of the second portion 52 of the second resistive element 14. The first passivation film 81 is formed, for example, by forming a passivation film over the entire surface and selectively removing the passivation film, for example, by isotropic dry etching.

[0073] A method for manufacturing the semiconductor device 10 includes forming openings 33 and 34 in the insulating layer 30. The openings 33 and 34 are formed by partially removing the insulating layer 30, for example, by wet etching.

[0074] As shown in Figure 10, the method for manufacturing the semiconductor device 10 includes forming a conductive layer 90. The conductive layer 90 is formed to cover the insulating layer 30 and the first passivation film 81. The conductive layer 90 is formed to cover the connection portion of the resistive element 12. The conductive layer 90 is formed, for example, by depositing a material containing Si, Cu, and Al by a sputtering method.

[0075] As shown in Figure 11, the manufacturing method of the semiconductor device 10 includes forming a wiring layer 18 and a base electrode 16. The wiring layer 18 and the base electrode 16 are formed by selectively removing the conductive layer 90 shown in Figure 10. The selective removal of the conductive layer 90 is performed, for example, by wet etching using an etching solution that removes Al. The conductive layer 90 contains Si and Cu. Therefore, in wet etching using an etching solution that removes Al, Si residue may be generated. For this reason, in the step of forming the wiring layer 18 and the base electrode 16, in addition to wet etching using an etching solution that removes Al, wet etching to remove Si residue is performed.

[0076] As shown in Figure 12, the method for manufacturing the semiconductor device 10 includes forming a second passivation film 82. The second passivation film 82 is formed to cover the first passivation film 81, the wiring layer 18, and the base electrode 16. The first passivation film 81 includes a base opening 80X1 that exposes a portion of the base electrode 16 and an emitter opening 80X2 that exposes a portion of the emitter electrode 17. The second passivation film 82 is formed, for example, by forming a passivation film over the entire surface and selectively removing the passivation film, for example, by isotropic dry etching.

[0077] A method for manufacturing the semiconductor device 10 includes forming a collector electrode 15. The collector electrode 15 is formed, for example, by a sputtering method. The semiconductor device 10 is formed through the above process.

[0078] <Operation of the Embodiment> Next, the operation of the semiconductor device 10 of the embodiment will be described. The semiconductor device 10 includes a semiconductor substrate 21, a semiconductor layer 22, a base layer 24, an emitter layer 26, an insulating layer 30, a base electrode 16, an emitter electrode 17, a resistive element 12, a wiring layer 18, and a passivation layer 80. The semiconductor substrate 21 of the first conductivity type includes a first substrate surface 21S. The semiconductor layer 22 of the first conductivity type is provided on the first substrate surface 21S of the semiconductor substrate 21. The base layer 24 of the second conductivity type is provided on the first surface 22S of the semiconductor layer 22 and is in contact with the semiconductor layer 22. The emitter layer 26 of the first conductivity type is provided on the first surface 24S of the base layer 24 and is in contact with the base layer 24. The insulating layer 30 is arranged on the semiconductor layer 22, the base layer 24, and the emitter layer 26.

[0079] The base electrode 16 is provided on the insulating layer 30 and electrically connected to the base layer 24, and is made of a material containing Si and Cu. The emitter electrode 17 is provided on the insulating layer 30 and electrically connected to the emitter layer 26, and is made of a material containing Si and Cu. The resistive element 12 is provided on the insulating layer 30 and electrically connected to the base electrode 16, and is made of a material containing Si. The wiring layer 18 is provided on the insulating layer 30 and electrically connected to the resistive element 12, and is made of a material containing Si and Cu. The passivation layer 80 covers the resistive element 12, the wiring layer 18, and the insulating layer 30. The passivation layer 80 includes a first film thickness portion 83 provided on the wiring layer 18 and having a first film thickness T1, and a second film thickness portion 84 provided on the resistive element 12 and having a second film thickness T2 that is greater than the first film thickness T1.

[0080] The wiring layer 18 is made of a material containing Si and Cu. In one example, the wiring layer 18 is made of an Al alloy containing Si and Cu. If the wiring layer 18 is made of Al or an Al alloy, there is a risk of alloy spike formation or disconnection due to electromigration. In contrast, the inclusion of Si and Cu can suppress deterioration due to alloy spikes and electromigration. Therefore, the semiconductor device 10 of this embodiment can improve the corrosion resistance of the wiring layer 18.

[0081] The base electrode 16 and the emitter electrode 17 are made of materials containing Si and Cu. Therefore, the semiconductor device 10, which includes these base electrode 16 and emitter electrode 17, can have improved corrosion resistance.

[0082] The semiconductor device 10 includes a resistive element 12 made of a material containing Si. The resistive element 12 is covered by a first passivation film 81 of a passivation layer 80. For example, if the first passivation film 81 is not provided, the wiring layer 18 will be in contact with the upper surface of the resistive element 12. This wiring layer 18 is formed in the manufacturing process by selectively removing a conductive layer 90 (see Figure 10) that is provided to cover the resistive element 12. The wiring layer 18 is made of a material containing Si and Cu. Therefore, in the process of selectively removing the conductive layer 90, wet etching is performed to remove Si residue, and this wet etching may cause the resistive element 12 to be etched and thinned. When the resistive element 12 becomes thin, the resistance value of the resistive element 12 increases. Therefore, it becomes impossible to obtain a resistive element 12 with the desired resistance value. In addition, the resistance value of the resistive element 12 may vary greatly due to etching.

[0083] In contrast, the semiconductor device 10 of this embodiment includes a first passivation film 81 covering the resistive element 12. The conductive layer 90 (see Figure 10) for forming the wiring layer 18 is formed to cover the first passivation film 81. Therefore, when the conductive layer 90 is selectively etched to form the wiring layer 18, the resistive element 12 is not etched. As a result, a semiconductor device 10 including a resistive element 12 having a desired resistance value can be obtained. Furthermore, it becomes possible to reduce variations in the resistance value of the resistive element 12.

[0084] <Effects of the Embodiment> As described above, the semiconductor device 10 of this embodiment provides the following effects. (1) The semiconductor device 10 includes a semiconductor substrate 21, a semiconductor layer 22, a base layer 24, an emitter layer 26, an insulating layer 30, a base electrode 16, an emitter electrode 17, a resistive element 12, a wiring layer 18, and a passivation layer 80. The semiconductor substrate 21 of the first conductivity type includes a first substrate surface 21S. The semiconductor layer 22 of the first conductivity type is provided on the first substrate surface 21S of the semiconductor substrate 21. The base layer 24 of the second conductivity type is provided on the first surface 22S of the semiconductor layer 22 and is in contact with the semiconductor layer 22. The emitter layer 26 of the first conductivity type is provided on the first surface 24S of the base layer 24 and is in contact with the base layer 24. The insulating layer 30 is arranged on the semiconductor layer 22, the base layer 24, and the emitter layer 26.

[0085] The base electrode 16 is provided on the insulating layer 30 and electrically connected to the base layer 24, and is made of a material containing Si and Cu. The emitter electrode 17 is provided on the insulating layer 30 and electrically connected to the emitter layer 26, and is made of a material containing Si and Cu. The resistive element 12 is provided on the insulating layer 30 and electrically connected to the base electrode 16, and is made of a material containing Si. The wiring layer 18 is provided on the insulating layer 30 and electrically connected to the resistive element 12, and is made of a material containing Si and Cu. The passivation layer 80 covers the resistive element 12, the wiring layer 18, and the insulating layer 30. The passivation layer 80 includes a first film thickness portion 83 provided on the wiring layer 18 and having a first film thickness T1, and a second film thickness portion 84 provided on the resistive element 12 and having a second film thickness T2 that is greater than the first film thickness T1.

[0086] In this semiconductor device 10, the corrosion resistance of the wiring layer 18 can be improved by constructing the wiring layer 18 from a material containing Si and Cu. (2) The base electrode 16 is made of a material containing Si and Cu. Therefore, the corrosion resistance of the base electrode 16 can be improved.

[0087] (3) The emitter electrode 17 is made of a material containing Si and Cu. Therefore, the corrosion resistance of the emitter electrode 17 can be improved. (4) The passivation layer 80 includes a first passivation film 81 that selectively covers the resistive element 12, and a second passivation film 82 that covers the first passivation film 81, the wiring layer 18, and the insulating layer 30. Therefore, the first film thickness portion 83 and the second film thickness portion 84 in the passivation layer 80 can be easily formed.

[0088] (5) The semiconductor device 10 of the embodiment includes a first passivation film 81 covering the resistive element 12. The conductive layer 90 for forming the wiring layer 18 is formed to cover the first passivation film 81. Therefore, when the conductive layer 90 is selectively etched to form the wiring layer 18, the resistive element 12 is not etched. As a result, a semiconductor device 10 including a resistive element 12 having a desired resistance value can be obtained. Furthermore, it is possible to reduce the variation in the resistance value of the resistive element 12.

[0089] (6) The resistive element 12 includes a first resistive element 13. The first resistive element 13 is electrically connected between the base electrode 16 and the base wiring 61, that is, between the base electrode 16 and the base layer 24. Therefore, the transistor 11 can be stably controlled.

[0090] (7) The resistive element 12 includes a second resistive element 14. The second resistive element 14 is electrically connected between the emitter electrode 17 and the base wiring 61, that is, between the emitter electrode 17 and the base layer 24. Therefore, malfunction of the transistor 11 due to leakage current flowing into the base of the transistor 11 can be suppressed.

[0091] (8) The semiconductor device 10 includes a transistor 11 and a resistor 12 connected to the transistor 11. Therefore, an external resistor is not required, making it possible to miniaturize the circuit using the semiconductor device 10 and to easily implement it.

[0092] <Example of changes> The above embodiment can be modified as follows, for example. The above embodiment and the following modifications can be combined with each other as long as no technical inconsistencies arise. In the following modifications, parts common to the above embodiment are denoted by the same reference numerals as in the above embodiment, and their descriptions are omitted.

[0093] In the modified semiconductor device 10A shown in Figure 13, the first passivation film 81 covers the entire resistive element 12. More specifically, the first resistive element 13 is in contact with the base electrode 16 by the end face 411 of the first portion 41 and in contact with the wiring layer 18 (base wiring 61) by the end face 412 of the tip portion 42A. The base electrode 16 and the wiring layer 18 are not in contact with the upper surface 131 of the first resistive element 13.

[0094] The first covering portion 81A of the first passivation film 81 includes end faces 81A1 and 81A2 that face the same direction as the end faces 411 and 412 of the first resistive element 13. End face 81A1 of the first passivation film 81 is flush with end face 411 of the first resistive element 13. End face 81A2 of the first passivation film 81 is flush with end face 412 of the first resistive element 13.

[0095] The second resistive element 14 is in contact with the emitter electrode 17 by the end face 51A1 of the first end 51A. The second covering portion 81B of the first passivation film 81 includes an end face 81B1 that faces the same direction as the end face 51A1 of the second resistive element 14. The end face 81B1 of the first passivation film 81 is flush with the end face 51A1 of the second resistive element 14. Although not shown in the drawing, the second resistive element 14 is in contact with the first wiring portion 62 of the base wiring 61 by the end face of the second end 52A, and this end face is flush with the end face of the second covering portion 81B of the first passivation film 81.

[0096] The semiconductor device 10 may be configured to include either a first resistive element 13 or a second resistive element 14 as the resistive element 12. For example, as shown in Figure 14, semiconductor device 10B may include a first resistive element 13 as the resistive element 12, and the second resistive element 14 may be omitted. Also, as shown in Figure 15, semiconductor device 10C may include a second resistive element 14 as the resistive element 12, and the first resistive element 13 may be omitted.

[0097] For example, the base wiring 61 may be used to disable either the first resistive element 13 or the second resistive element 14. For example, in the semiconductor device 10 shown in Figures 1 and 2, the second resistive element 14 may be disabled by ensuring that the second end 62B of the first wiring portion 62 of the base wiring 61 does not overlap with the second end 52A of the second resistive element 14, thereby configuring the semiconductor device 10 to include the first resistive element 13. Alternatively, the first wiring portion 62 of the base wiring 61 may be extended toward the base electrode 16, and the first resistive element 13 may be electrically connected to the base electrode 16, thereby disabling the first resistive element 13 and configuring the semiconductor device 10 to include the second resistive element 14.

[0098] In the semiconductor device 10D shown in Figure 16, the first passivation film 81 and the second passivation film 82 are made of the same material, for example, SiN. In this case, the first passivation film 81 and the second passivation film 82 may be an integrated single unit. In Figure 16, the first passivation film 81 and the second passivation film 82 are shown with dashed lines for clarity. When they are made of the same material, the interface between the first passivation film 81 and the second passivation film 82 may not be clearly defined.

[0099] In the above embodiment, the first conductivity type was n-type and the second conductivity type was p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. <Note> The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0100] [Note 1] A semiconductor substrate (21) of a first conductivity type including a first substrate surface (21S), A first conductivity type semiconductor layer (22) is provided on the first substrate surface (21S), A second conductive base layer (24) is provided on the first surface (22S) of the semiconductor layer (22) and is in contact with the semiconductor layer (22), A first conductive emitter layer (26) is provided on the first surface (24S) of the base layer (24) and is in contact with the base layer (24), An insulating layer (30) is disposed on the semiconductor layer (22), the base layer (24), and the emitter layer (26), A base electrode (16) is provided on the insulating layer (30) and electrically connected to the base layer (24), and is made of a material containing Si and Cu, An emitter electrode (17) is provided on the insulating layer (30) and is electrically connected to the emitter layer (26), and is made of a material containing Si and Cu, Resistor elements (12, 13, 14) are provided on the insulating layer (30) and are electrically connected to the base electrode (16), and are made of a material containing Si. A wiring layer (18) is provided on the insulating layer (30) and is electrically connected to the resistive elements (12, 13, 14), and is made of a material containing Si and Cu, The resistive elements (12, 13, 14), the wiring layer (18), and the passivation layer (80) covering the insulating layer (30), Includes, The passivation layer (80) is A first film thickness portion (83) is provided on the wiring layer (18) and has a first film thickness, A second film thickness portion (84) is provided on the resistive element (12, 13, 14) and has a second film thickness greater than the first film thickness, including, Semiconductor equipment.

[0101] [Note 2] The passivation layer (80) is A first passivation film (81) selectively covers the aforementioned resistive elements (12, 13, 14), A second passivation film (82) covers the first passivation film (81), the wiring layer (18), and the insulating layer (30), Includes, The first film thickness portion (83) is composed of the second passivation film (82), The second film thickness portion (84) is composed of the first passivation film (81) and the second passivation film (82). The semiconductor device described in Appendix 1.

[0102] [Note 3] The first passivation film (81) and the second passivation film (82) are made of the same material, and the first passivation film (81) is integrated. Semiconductor device as described in Appendix 2.

[0103] [Note 4] The first passivation film (81) and the second passivation film (82) are made of different materials, and the first passivation film (81) and the second passivation film (82) have a laminated structure. Semiconductor device as described in Appendix 2.

[0104] [Note 5] The insulating layer (30) includes an opening (33) that exposes a portion of the base layer (24), The wiring layer (18) is in contact with the base layer (24) through the opening (33). The base electrode (16) is positioned at a location separated from the wiring layer (18), The resistive element includes a first resistive element (13) provided between the base electrode (16) and the wiring layer (18) on the insulating layer (30) and electrically connected to the base electrode (16) and the wiring layer (18). A semiconductor device as described in any one of the appendices 1 to 4.

[0105] [Note 6] The resistive element includes a second resistive element (14) provided between the wiring layer (18) and the emitter electrode (17) on the insulating layer (30), and electrically connected to the wiring layer (18) and the emitter electrode (17). Semiconductor device as described in Appendix 5.

[0106] [Note 7] The resistive element includes a second resistive element (14) provided between the base electrode (16) and the emitter electrode (17) on the insulating layer (30) and electrically connected to the base electrode (16) and the emitter electrode (17). A semiconductor device as described in any one of the appendices 1 to 4.

[0107] [Note 8] The wiring layer (18) has a portion that overlaps with the resistive elements (12, 13, 14) when viewed from the thickness direction of the semiconductor substrate (21). The semiconductor device described in Appendix 1.

[0108] [Note 9] The first passivation film (81), when viewed from the thickness direction of the semiconductor substrate (21), has a portion that overlaps with the wiring layer (18) on the resistive elements (12, 13, 14). Semiconductor device as described in Appendix 2.

[0109] [Note 10] The first passivation film (81) covers the top and side surfaces of the resistive elements (12, 13, 14). Semiconductor device as described in Appendix 9.

[0110] [Note 11] The resistive elements (12, 13, 14) include end faces that are in contact with the wiring layer (18), The first passivation film (81) includes a side surface that faces the same direction as the end face of the resistive element (12, 13, 14), The end faces of the resistive elements (12, 13, 14) and the side surfaces of the first passivation film (81) are flush. Semiconductor device as described in Appendix 10.

[0111] [Note 12] The aforementioned resistive elements (12, 13, 14) are made of a material containing polysilicon. A semiconductor device as described in any one of the appendices 1 through 11.

[0112] [Note 13] The first passivation film (81) is composed of one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. A semiconductor device as described in any one of the appendices 2 to 4.

[0113] [Note 14] The second passivation film (82) is composed of one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. A semiconductor device as described in any one of the appendices 2 to 4.

[0114] [Note 15] The base electrode (16), the emitter electrode (17), and the wiring layer (18) are made of an aluminum alloy containing Si and Cu. A semiconductor device as described in any one of the appendices 1 through 14.

[0115] [Note 16] A semiconductor substrate (21) of a first conductivity type including a first substrate surface (21S), A first conductivity type semiconductor layer (22) is provided on the first substrate surface (21S), A second conductive base layer (24) is provided on the first surface of the semiconductor layer (22) and is in contact with the semiconductor layer (22), A first conductive emitter layer (26) is provided on the first surface of the base layer (24) and is in contact with the base layer (24), A method for manufacturing a semiconductor device, including Forming an insulating layer (30) on the semiconductor layer (22), the base layer (24), and the emitter layer (26), Resistor elements (12, 13, 14) are formed on the insulating layer (30) using a material containing Si, To form a first passivation film (81) covering the aforementioned resistive elements (12, 13, 14), A conductive layer (90) is formed on the insulating layer (30) and the first passivation film (81) using a material containing Si and Cu. By selectively etching the conductive layer (90), including the portion on the first passivation film (81), an emitter electrode (17) electrically connected to the emitter layer (26), a wiring layer (18) electrically connected to the base layer (24), and a base electrode (16) electrically connected to the wiring layer (18) through the resistive elements (12, 13, 14), To form a second passivation film (82) that covers the first passivation film (81), the wiring layer (18), and the insulating layer (30), including, A method for manufacturing a semiconductor device.

[0116] [Note 17] The conductive layer (90) is formed from an aluminum alloy containing Si and Cu. The method for manufacturing a semiconductor device as described in Appendix 16.

[0117] The above description is for illustrative purposes only. Those skilled in the art will recognize that many more possible combinations and substitutions are possible beyond the components and methods (manufacturing processes) enumerated for the purpose of illustrating the technology of this disclosure. This disclosure is intended to encompass all alternatives, variations, and modifications that fall within the scope of this disclosure, including the claims. [Explanation of Symbols]

[0118] 10, 10A~10D... Semiconductor equipment 11… Transistor 12… Resistor 13…First resistive element 13A…First part 13B…Second part 131…Top surface 132... Side view 14…Second resistive element 141...Top surface 142... Side view 15...Collector electrode 16…Base electrode 17…Emitter electrode 18...Wiring layer 21… Semiconductor substrates 21S...1st board surface 21R…Second substrate side 211~214...1st side~4th side 22... Semiconductor layer 22S…Side 1 22R…Second side 221~224...1st side~4th side 231-234...Corner 1 section to Corner 4 section 24…Base layer 24S…Side 1 241... recessed area 25… Contact area 26…Emitter layer 26S…Side 1 27… Contact area 30…Insulating layer 31…First insulating layer 32…Second insulating layer 33, 34… opening 41…Part 1 411,412...end face 42…Second part 42A...Tip 51…Part 1 51A…First end 51A1…End face 51B...End part 52…Second part 52A…Second end 61...Base wiring 62...1st wiring part 62A…First end 62B…Second end 621~624...1st wiring~4th wiring 63…Second wiring part 64...Third wiring part 65...Connection part 71…Emitter wiring 72...1st wiring part 73…Second wiring part 74...Third wiring part 75...Connection part 80... Passivation layer 80X1…Base opening 80X2…Emitter opening 81…First passivation membrane 81A...First coating portion 81A1, 81A2…End face 81B...Second covering portion 81B1…End face 811…Top surface 82...Second passivation membrane 82A...Third coating portion 82B...Fourth covering section 83...First film thickness section 84...Second film thickness section T1...First film thickness T2…Second film thickness T11, T12…Film thickness (thickness)

Claims

1. A semiconductor substrate of a first conductivity type including a first substrate surface, A first conductivity type semiconductor layer provided on the first substrate surface, A second conductivity type base layer is provided on the first surface of the semiconductor layer and is in contact with the semiconductor layer, A first conductive emitter layer is provided on the first surface of the base layer and is in contact with the base layer, An insulating layer disposed on the semiconductor layer, the base layer, and the emitter layer, A base electrode provided on the insulating layer and electrically connected to the base layer, and made of a material containing Si and Cu, An emitter electrode provided on the insulating layer and electrically connected to the emitter layer, and made of a material containing Si and Cu, A resistive element provided on the insulating layer and electrically connected to the base electrode, and made of a material containing Si, A wiring layer provided on the insulating layer and electrically connected to the resistive element, and composed of a material containing Si and Cu, The resistive element, the wiring layer and the insulating layer are covered by a passivation layer, Includes, The aforementioned passivation layer is A first film thickness portion is provided on the wiring layer and has a first film thickness, A second film thickness portion is provided on the resistive element and has a second film thickness greater than the first film thickness, including, Semiconductor equipment.

2. The aforementioned passivation layer is A first passivation film selectively covers the resistive element, The first passivation film, the wiring layer, and the second passivation film covering the insulating layer, Includes, The first film thickness portion is composed of the second passivation film, The second film thickness portion is composed of the first passivation film and the second passivation film. The semiconductor device according to claim 1.

3. The first passivation film and the second passivation film are made of the same material, and the first passivation film is integrated. The semiconductor device according to claim 2.

4. The first passivation film and the second passivation film are made of different materials, and the first passivation film and the second passivation film have a laminated structure. The semiconductor device according to claim 2.

5. The insulating layer includes a base opening that exposes a portion of the base layer, The wiring layer is in contact with the base layer through the base opening. The base electrode is positioned at a location separated from the wiring layer. The resistive element includes a first resistive element provided between the base electrode and the wiring layer on the insulating layer and electrically connected to the base electrode and the wiring layer. A semiconductor device according to any one of claims 1 to 4.

6. The resistive element includes a second resistive element provided between the wiring layer and the emitter electrode on the insulating layer, and electrically connected to the wiring layer and the emitter electrode. The semiconductor device according to claim 5.

7. The resistive element includes a second resistive element provided between the base electrode and the emitter electrode on the insulating layer and electrically connected to the base electrode and the emitter electrode. A semiconductor device according to any one of claims 1 to 4.

8. The wiring layer has a portion that overlaps with the resistive element when viewed from the thickness direction of the semiconductor substrate. The semiconductor device according to claim 1.

9. The first passivation film, when viewed from the thickness direction of the semiconductor substrate, has a portion that overlaps with the wiring layer on the resistive element. The semiconductor device according to claim 2.

10. The first passivation film covers the top and side surfaces of the resistive element. The semiconductor device according to claim 9.

11. The resistive element includes an end face that is in contact with the wiring layer, The first passivation film includes a side surface that faces the same direction as the end face of the resistive element, The end face of the resistive element and the side surface of the first passivation film are flush. The semiconductor device according to claim 10.

12. The resistive element is made of a material containing polysilicon. A semiconductor device according to any one of claims 1 to 4.

13. The first passivation film is composed of one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. A semiconductor device according to any one of claims 2 to 4.

14. The second passivation film is composed of one of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. A semiconductor device according to any one of claims 2 to 4.

15. The base electrode, the emitter electrode, and the wiring layer are made of an aluminum alloy containing Si and Cu. A semiconductor device according to any one of claims 1 to 4.

16. A semiconductor substrate of a first conductivity type including a first substrate surface, A first conductivity type semiconductor layer provided on the first substrate surface, A second conductivity type base layer is provided on the first surface of the semiconductor layer and is in contact with the semiconductor layer, A first conductive emitter layer is provided on the first surface of the base layer and is in contact with the base layer, A method for manufacturing a semiconductor device, including Forming an insulating layer on the semiconductor layer, the base layer, and the emitter layer, A resistive element is formed on the insulating layer using a material containing Si, To form a first passivation film covering the resistive element, A conductive layer is formed on the insulating layer and on the first passivation film using a material containing Si and Cu. By selectively etching the conductive layer, including the portion on the first passivation film, an emitter electrode electrically connected to the emitter layer, a wiring layer electrically connected to the base layer, and a base electrode electrically connected to the wiring layer through the resistive element are formed. To form a second passivation film that covers the first passivation film, the wiring layer, and the insulating layer, including, A method for manufacturing a semiconductor device.

17. The conductive layer is formed from an aluminum alloy containing Si and Cu. The method for manufacturing a semiconductor device according to claim 16.

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