Drive circuit and electro-optical device

Abstract

To provide a drive circuit that allows easy acquisition of calibration results for multiple capacitive elements. [Solution] The driver 1 includes a DAC 11 and an amplifier 12, a first drive circuit 10 that outputs a video signal Dv, a second drive circuit 20 that outputs a video signal Dv, a plurality of capacitive elements C21 and a capacitive drive circuit 21 that drives the plurality of capacitive elements C21, a verification circuit 50 that verifies the output of the second drive circuit 20 and outputs a verification result R, an output node NODE1 to which the video signal Dv or the verification result R is output, a switch SW11 that electrically connects the first drive circuit 10 and the output node NODE1, a switch SW21 that electrically connects the second drive circuit 20 and the output node NODE1, a switch SW22 that electrically connects the plurality of capacitive elements C21 and the verification circuit 50, and a switching circuit 40 that selectively outputs the video signal Dv and the verification result R to the output node NODE1.

Description

Technical Field

[0001] The present invention relates to a drive circuit and an electro-optical device.

Background Art

[0002] Patent Document 1 discloses a verification circuit that verifies a capacitive element included in a driver circuit of an electro-optical device. When verifying the capacitive element, the verification circuit of Patent Document 1 first disconnects the capacitive element to be verified from the test node of the comparison circuit, writes a verification voltage, then connects the capacitive element to be verified to the test node of the comparison circuit to redistribute the written verification voltage. The comparison circuit outputs the result of comparing the verified voltage at the test node and the voltage Vref as an H-level or L-level signal, and the control circuit verifies whether the capacitive element is normal or abnormal based on the logic level of the signal output from the comparison circuit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the driver circuit of the electro-optical device of Patent Document 1, the control circuit verifies whether the capacitive element is normal or abnormal based on the logic level of the signal output from the comparison circuit. That is, in the driver circuit of the electro-optical device of Patent Document 1, the output of the comparison circuit is output to the control circuit. Therefore, when a user checks whether the capacitive element is malfunctioning, the user has to connect a device to a service port and extract the normal or abnormality information from the control circuit.

Means for Solving the Problems

[0005] A drive circuit according to one aspect of the present invention includes a DA conversion circuit and an amplifier circuit, a first drive circuit that outputs a video signal based on grayscale data, a second drive circuit that includes a plurality of capacitive elements and a capacitive drive circuit that drives the plurality of capacitive elements, and outputs the video signal based on the grayscale data, a verification circuit that verifies the output of the second drive circuit and outputs the verification result, an output node to which the video signal or the verification result is output, a first switch that electrically connects the first drive circuit and the output node, a second switch that electrically connects the second drive circuit and the output node, a third switch that electrically connects the plurality of capacitive elements and the verification circuit, and a switching circuit that selectively outputs the video signal and the verification result to the output node.

[0006] An electro-optical device according to one aspect of the present application comprises an electro-optical panel and the above-described drive circuit for driving the electro-optical panel. [Brief explanation of the drawing]

[0007] [Figure 1] A perspective view showing the external appearance of an electro-optical device equipped with the drive circuit according to this embodiment. [Figure 2] A block diagram showing the general configuration of the drive circuit. [Figure 3] A timing chart showing the operation during inspection of the drive circuit. [Figure 4] Circuit diagram of the drive circuit according to Embodiment 2. [Figure 5] Circuit diagram of a drive circuit according to a modified example of Embodiment 2. [Figure 6] A timing chart showing the operation of the drive circuit during inspection according to a modified example of Embodiment 2. [Figure 7] Circuit diagram of the drive circuit according to Embodiment 3. [Figure 8] A timing chart showing the operation of the drive circuit according to Embodiment 3 during inspection. [Figure 9] Circuit diagram of a drive circuit according to a modified example of Embodiment 3. [Figure 10] A timing chart showing the operation of the drive circuit during inspection according to a modified example of Embodiment 3. [Figure 11] Circuit diagram of the drive circuit according to Embodiment 4. [Figure 12] A timing chart showing the operation of the drive circuit according to Embodiment 4 during inspection. [Figure 13] An explanatory diagram showing an example of how the test results are displayed during inspection of the drive circuit according to Embodiment 4. [Figure 14] A circuit diagram showing a first circuit example of the verification circuit according to Embodiment 4. [Figure 15] A circuit diagram showing a second circuit example of the verification circuit according to Embodiment 4. [Figure 16] A circuit diagram showing a third circuit example of the verification circuit according to Embodiment 4. [Modes for carrying out the invention]

[0008] 1. Embodiment 1 1.1. Configuration of the electro-optical device 100 Figure 1 is a perspective view showing an example of the external appearance of the electro-optical apparatus 100 according to this embodiment. As shown in Figure 1, the electro-optical device 100 includes a driver 1, an electro-optical panel 2, and a flexible substrate 3. The driver 1 includes a calibration circuit 50 (see Figure 2), which will be described later.

[0009] The electro-optical device 100 is preferably used as a display device for a projector. Alternatively, the electro-optical device 100 may be used as a display device for smartphones, cameras, televisions, car navigation systems, personal computers, displays, POS (Point of Sale) terminals, printers, scanners, copiers, video players, or devices equipped with touch panels.

[0010] (The electro-optical panel 2 is an active-drive transmissive liquid crystal display panel that has pixels P in a display region TD and includes a TFT (Thin Film Transistor) as a switching element for each pixel P. Note that the electro-optical panel 2 may be a reflective liquid crystal display panel or a transflective liquid crystal display panel. Further, the electro-optical panel 2 may be a display device other than a liquid crystal display panel, for example, an organic EL display.)

[0011] The pixels P are provided corresponding to intersections of scan lines 2x and data lines 2y arranged in a matrix. The electro-optical panel 2 has an element substrate 2s and an opposing substrate 2t, and a flexible substrate 3 is mounted on a protruding portion 21a of the element substrate 2s.

[0012] The driver 1 outputs, to the electro-optical panel 2, a video signal Dv that drives the electro-optical panel 2 based on grayscale data Db, or a video signal Rv that drives the electro-optical panel 2 based on verification result data Rb. The video signal Dv and the video signal Rv are positive-polarity or negative-polarity grayscale voltages corresponding to a predetermined grayscale value. The verification result data Rb is n-bit grayscale data, similarly to the grayscale data Db. In the present embodiment, the verification result data Rb and the video signal Rv are an example of a verification result R.

[0013] In the present embodiment, the driver 1 is configured by an integrated circuit device (IC). The integrated circuit device is, for example, an IC chip in which a circuit is formed on a silicon substrate, or a device in which an IC chip is housed in a package.

[0014] In the present embodiment, the driver 1 is mounted on the flexible substrate 3. That is, the video signal Dv or the video signal Rv output from the driver 1 is supplied to the electro-optical panel 2 via the flexible substrate 3. Note that the driver 1 may be mounted on the protruding portion 21a of the electro-optical panel 2, or may be mounted on a rigid substrate (not illustrated) and configured to supply the video signal Dv or the video signal Rv to the electro-optical panel 2 via the flexible substrate 3.

[0015] The electro-optical panel 2 is supplied with a video signal Dv or Rv, power supply voltage, timing signal, control signal, etc., via a flexible substrate 3, but some or all of the power supply voltage, timing signal, control signal, etc., may be output by the driver 1.

[0016] 1.2. Driver 1 Configuration Figure 2 is a block diagram showing the schematic configuration of driver 1 equipped with a calibration circuit 50. As shown in Figure 2, the driver 1 includes a first drive circuit 10, a second drive circuit 20, a balance capacitance circuit 30, a switching circuit 40, a calibration circuit 50, a control circuit 60, and an output node NODE1. The output node NODE1 is electrically connected to the input node NODE4 of the electro-optical panel 2 via a flexible substrate 3. The video signal Dv and the calibration result R are output from the output node NODE1. In this embodiment, the driver 1 is an example of a drive circuit.

[0017] The first drive circuit 10 includes a DAC (Digital to Analog Converter) 11 and an amplifier 12, and outputs a gradation voltage V10. The gradation voltage V10 is a video signal Dv based on gradation data Db input from input node NODE2 or a video signal Rv based on verification result data Rb input from verification circuit 50. In this embodiment, the DAC 11 is an example of a DA conversion circuit, and the amplifier 12 is an example of an amplifier circuit.

[0018] The second drive circuit 20 outputs a video signal Dv by redistributing the charge of capacitive elements. The balancing capacitance circuit 30 is used to appropriately drive various electro-optic panels 2 with different electro-optic panel side capacitances CP.

[0019] The first drive circuit 10 is electrically connected to the output node NODE1 via switch SW11. The second drive circuit 20 is electrically connected to the output node NODE1 via switch SW21. The balance capacitance circuit 30 is electrically connected to the output node NODE1 via switch SW31. In this embodiment, switch SW11 is an example of a first switch, and switch SW21 is an example of a second switch.

[0020] When driver 1 drives the electro-optical panel 2, switches SW21 and SW31 are turned ON during the first period and OFF during the second period following the first period. On the other hand, switch SW11 is turned OFF during the first period and ON during the second period following the first period. In other words, driver 1 outputs a video signal Dv from output node NODE1 during the first period driven by the second drive circuit 20, and outputs a video signal Dv from output node NODE1 during the second period following the first period driven by the first drive circuit 10. By controlling it in this way, driver 1 can be driven at high speed and with high precision.

[0021] The control terminal of switch SW11 is supplied with the control signal AENB from the control circuit 60, the control terminal of switch SW21 is supplied with the control signal DENB from the control circuit 60, and the control terminal of switch SW31 is supplied with the control signal LENB from the control circuit 60. In other words, the ON / OFF state of switches SW11, SW21, and SW31 is controlled by the control circuit 60.

[0022] The second drive circuit 20 is electrically connected to the test node TEST_NODE1 via switch SW22. The balance capacitor circuit 30 is electrically connected to the test node TEST_NODE2 via switch SW32. In other words, the second drive circuit 20 and the balance capacitor circuit 30 are connected to different test nodes. Therefore, the driver 1 can perform tests on the second drive circuit 20 and the balance capacitor circuit 30 in parallel, thereby improving the test speed. In this embodiment, switch SW22 is an example of a third switch.

[0023] The test node TEST_NODE1 is electrically connected to the test circuit 50 via the test line TEST_LINE1. The test node TEST_NODE2 is electrically connected to the test circuit 50 via the test line TEST_LINE2.

[0024] The calibration circuit 50 is a circuit that inspects the accuracy of the second drive circuit 20 and the balance capacitance circuit 30, and outputs a calibration result R as the inspection result. The calibration result R from the calibration circuit 50 allows us to determine whether the second drive circuit 20 and the balance capacitance circuit 30 are good or bad, and whether any malfunctions have occurred. Specifically, the calibration result from the calibration circuit 50 allows us to determine whether each of the n capacitance elements C21 and m capacitance elements C31 are good or bad.

[0025] In this embodiment, the driver 1 outputs the verification result R output by the verification circuit 50 as a video signal Rv. Therefore, the user can confirm the verification result R as a video on the display area TD of the electro-optical panel 2.

[0026] Driver 1 outputs the verification result R from the same output node NODE1 as the video signal Dv. Therefore, there is no need to provide a separate service port for outputting the verification result R, and driver 1 can be made smaller. In addition, users can easily obtain the verification result R without having to connect any equipment to the service port.

[0027] Note that the verification result R is not limited to the video signal Rv. Any signal or data based on the verification result R is acceptable. The verification result R may also be the verification result data Rb, the verification result signal Rs (see Figure 3), or the verification result signal Rh (see Figure 6).

[0028] The video signal Rv is a positive or negative polarity grayscale voltage. The verification result data Rb is n-bit grayscale data, similar to the grayscale data Db. The verification result signals Rs and Rh are signals consisting of two voltages, high and low, and the verification result signal Rh is a signal where the potential difference between the high voltage and the low voltage is greater than that of the verification result signal Rs.

[0029] The verification circuit 50 includes a verification circuit 50b that outputs verification result data Rb, a verification circuit 50s that outputs a verification result signal Rs, a verification circuit 50h that outputs a verification result signal Rh, and a verification circuit 50v that outputs a video signal Rv. The verification circuits 50s, 50h, and 50v will be described in subsequent embodiments.

[0030] The verification circuit 50b outputs data corresponding to high gradation as verification result data Rb if the verification result R is Pass, and outputs data corresponding to low gradation as verification result data Rb if the verification result R is Fail.

[0031] If the grayscale data Db is 12-bit grayscale data, the verification result data Rb indicating "Pass" is 1_1111_1111_1111 when positive polarity and 0_0000_0000_0000 when negative polarity. The video signal Rv based on this verification result data Rb is the grayscale voltage for white grayscale when the electro-optical panel 2 is normally black, and displays white in the display area TD of the electro-optical panel 2.

[0032] Furthermore, if the grayscale data Db is 12-bit grayscale data, the verification result data Rb indicating Failure is 1_1000_0000_0000 when positive polarity is positive and 0_0111_1111_1111 when negative polarity is negative. The video signal Rv based on this verification result data Rb is the grayscale voltage for black when the electro-optical panel 2 is normally black, and displays black in the display area TD of the electro-optical panel 2.

[0033] In this way, if the grayscale data that the verification circuit 50b outputs as verification result data Rb is predetermined for cases where the verification result R is Pass and cases where it fails, the user can observe the verification result R as a grayscale display of the display area TD of the electro-optical panel 2.

[0034] The calibration circuit 50 is preferably formed on the same silicon substrate as the second drive circuit 20 and the balance capacitance circuit 30. By forming it on the same silicon substrate, the calibration circuit 50 can be formed at a low cost.

[0035] When the second drive circuit 20 is being tested by the test circuit 50, switch SW22 is turned ON and switch SW21 is turned OFF. As a result, the voltage under test V20 is output to the test circuit 50 via switch SW22 through the test node TEST_NODE1 and the test line TEST_LINE1.

[0036] Thus, since the second drive circuit 20 is disconnected from the output node NODE1 during inspection, the influence of the output node NODE1 and the balance capacitance circuit 30 can be eliminated, and the amplitude of the inspection voltage can be increased. Therefore, according to this embodiment, the accuracy of the inspection of the second drive circuit 20 by the verification circuit 50 can be improved.

[0037] When testing the balance capacitance circuit 30 using the calibration circuit 50, switch SW32 is turned ON and switch SW31 is turned OFF. As a result, the voltage under test V30 is output to the calibration circuit 50 via switch SW32 through the calibration node TEST_NODE2 and calibration line TEST_LINE2.

[0038] Thus, since the balance capacitance circuit 30 is disconnected from the output node NODE1 during testing, the influence of the output node NODE1 and the second drive circuit 20 can be eliminated, and the amplitude of the test voltage can be increased. Therefore, according to this embodiment, the accuracy of testing the balance capacitance circuit 30 by the verification circuit 50 can be improved.

[0039] The control terminal of switch SW22 receives control signal TENB1 from the control circuit 60, and the control terminal of switch SW32 receives control signal TENB2 from the control circuit 60. In other words, the ON / OFF state of switches SW22 and SW32 is controlled by the control circuit 60.

[0040] The control circuit 60 is connected to the input / output node NODE3. The control circuit 60 performs the various controls described above based on control information stored in a memory (not shown). The setting or modification of this control information can be performed externally via the input / output node NODE3.

[0041] As described above, it is preferable that the calibration circuit 50 be formed on the same silicon substrate as the second drive circuit 20 and the balance capacitance circuit 30, but all or part of the calibration circuit 50 may be formed on a different silicon substrate from the second drive circuit 20 and the balance capacitance circuit 30. In other words, the calibration circuit 50 may be provided on a separate IC chip from the driver 1.

[0042] 1.2.1. Regarding the switching circuit 40 The switching circuit 40 outputs either the grayscale data Db or the verification result data Rb to the DAC11. The grayscale data Db is input via the input node NODE2, and the verification result data Rb is input from the verification circuit 50b via the output line R_LINE.

[0043] The switching of gradation data Db and verification result data Rb by the switching circuit 40 is controlled by the control signal TEST_MODE output from the control circuit 60. When performing testing using the verification circuit 50b, the switching circuit 40 outputs verification result data Rb based on the control signal TEST_MODE. On the other hand, when displaying an image using grayscale data Db, the switching circuit 40 is controlled by the control signal TEST_MODE and outputs grayscale data Db.

[0044] 1.2.2. Regarding the first drive circuit 10 The first drive circuit 10 includes a DAC 11 and an amplifier 12. The DAC 11 receives grayscale data Db or verification result data Rb via a switching circuit 40.

[0045] When grayscale data Db is input to DAC11, DAC11 generates and outputs grayscale voltages corresponding to each value of the grayscale data Db. If the grayscale data Db is, for example, 12 bits, DAC11 generates and outputs grayscale voltages for 4096 levels.

[0046] When the test result data Rb is input to DAC11, DAC11 generates and outputs a grayscale voltage corresponding to white or black that corresponds to the test result data Rb.

[0047] Amplifier 12 amplifies, inverts, inverts, and performs impedance conversion on the gradation voltage output from DAC 11 to output a gradation voltage V10. The gradation voltage V10 is output as video signal Dv or video signal Rv from output node NODE1 via switch SW11.

[0048] 1.2.3. Regarding the second drive circuit 20 The second drive circuit 20 is a circuit that outputs a video signal Dv by redistributing the charge of a capacitive element. The second drive circuit 20 outputs the video signal Dv to the output node NODE1 via a switch SW21, one end of which is electrically connected to the output node NODE1.

[0049] The second drive circuit 20 includes n capacitive elements C21 and a capacitive drive circuit 21 that drives the n capacitive elements C21 based on grayscale data Db representing video information. Here, n is an integer of 2 or more, and for example, n can be set to the same number of bits as the grayscale data Db.

[0050] The capacitance values ​​of the n capacitive elements C21 are weighted by powers of 2 corresponding to, for example, the bits D0, D1, ..., Dn-1, and Dn of the grayscale data Db. Then, each drive unit of the second drive circuit 20 outputs a low-level or high-level potential according to the bits D0, D1, ..., Dn-1, and Dn, and the n capacitive elements C21 are driven by that potential. The low-level potential is, for example, 0V, and the high-level potential is, for example, 15V.

[0051] This drive causes charge redistribution between the n capacitive elements C21 and the electro-optic panel side capacitance CP, resulting in the output of the video signal Dv to the output node NODE1. The electro-optic panel side capacitance CP is determined by the substrate capacitance CP1 and the panel capacitance CP2.

[0052] The electro-optic panel capacitance CP is the sum of the capacitances visible from output node NODE1. For example, the electro-optic panel capacitance CP is the sum of the substrate capacitance CP1, which is the parasitic capacitance of the flexible substrate 3, and the panel capacitance CP2, which is the parasitic capacitance and pixel capacitance within the electro-optic panel 2. The TFTs within the electro-optic panel 2 have parasitic capacitance between the source and gate. Since many TFTs are connected to the data line 2y (see Figure 1), the data line 2y has parasitic capacitance from many TFTs. In addition, there is parasitic capacitance between the data line 2y and the scan line 2x. Furthermore, in a liquid crystal display panel, there is capacitance in the pixels P. The sum of these is the panel capacitance CP2.

[0053] 1.2.4. About the Balance Capacitance Circuit 30 The balanced capacitance circuit 30 is a capacitance connected to the output node NODE1 via the switch SW31, and its capacitance value can be set to a variable value.

[0054] The balancing capacitance circuit 30 includes m switches SW33 and m capacitance elements C31 for capacitance adjustment, where m is an integer greater than or equal to 1. Each of the m switches SW33 has one end electrically connected to the other end of switch SW31. Control signals EN0, EN1, ..., ENm-1, ENm are supplied to each of the control terminals of the m switches SW33 from the control circuit 60.

[0055] The balancing capacitance circuit 30 is used to set the capacitance ratio between the capacitances of the n capacitance elements C31 and the capacitance CP on the electro-optic panel side to a predetermined value. By having the balancing capacitance circuit 30, the driver 1 can appropriately drive electro-optic panels 2 with different capacitances CP on the electro-optic panel side due to manufacturing variations or different models, thereby increasing the versatility of the driver 1.

[0056] The balancing capacitance circuit 30 has a buffer 31. The buffer 31 is used to output the voltage under test V30 when the balancing capacitance circuit 30 is being tested. One end of the buffer 31 is connected to one of the m capacitance elements C31, and a drive signal T0 is supplied to the other end of the buffer 31.

[0057] 1.3. Operation of the verification circuit 50 Figure 3 is a timing chart showing the operation of the calibration circuit 50. In Figure 3, the waveform shown by TEST_NODE1 is the waveform showing the amplitude of the voltage under test V20 applied to the test node TEST_NODE1 and applied to the comparator 53 (see Figures 14 to 16). The waveform shown by VREF is the waveform showing the amplitude of the voltage of the reference potential VREF applied to the comparator 53 of the test circuit 50. The waveform shown by POL is the waveform of the polarity signal POL, which indicates the polarity of the video signal Dv or video signal Rv, with a high level indicating positive polarity and a low level indicating negative polarity. The waveform shown by Rs is the waveform showing the amplitude of the voltage output from the comparator 53 of the test circuit 50. The waveform shown by Rv is the waveform showing the amplitude of the voltage of the video signal Rv output by the first drive circuit 10 based on the test result data Rb output from the test circuit 50b. The waveforms shown for AENB, DENB, LENB, and TENB1 are the waveforms of the control signals AENB, DENB, LENB, and TENB1 input to the control terminals of switches SW11, SW21, SW31, and SW22. The waveforms shown for TEST_MODE and TEST_CTRL are the waveforms of the control signals TEST_MODE and TEST_CTRL input to the switching circuit 40 and the calibration circuit 50b. The waveforms shown for D0, D1, D2, and D3 are the waveforms showing bits D0, D1, D2, and D3 of the grayscale data Dd input to the capacitive drive circuit 21, either 1 or 0.

[0058] As shown in Figure 3, when the verification is performed by the verification circuit 50, the control signals AENB, TENB1, TEST_MODE, and TEST_CTRL are set to a high level, and the control signals DENB and LENB are set to a low level. As a result, switches SW11 and SW22 are turned ON, and switches SW21 and SW31 are turned OFF. In addition, the verification circuit 50b becomes active, and the switching circuit 40 switches the output from the grayscale data Db to the verification result data Rb.

[0059] The comparator 53 of the calibration circuit 50b outputs a low-level signal as the calibration result signal Rs until the potential of the voltage under test V20 applied to the calibration node TEST_NODE1 exceeds the reference potential VREF. After the potential applied to the calibration node TEST_NODE1 exceeds the reference potential VREF, it outputs a high-level signal as the calibration result signal Rs.

[0060] While the verification result signal Rs is at a low level, the verification circuit 50b outputs verification result data Rb corresponding to black, according to its polarity, and inputs it to the first drive circuit 10 via the switching circuit 40. Based on the verification result data Rb, the first drive circuit 10 outputs a black video signal Rv.

[0061] While the verification result signal Rs is at a high level, the verification circuit 50b outputs verification result data Rb corresponding to white, according to the polarity, and inputs it to the first drive circuit 10 via the switching circuit 40. Based on the verification result data Rb, the first drive circuit 10 outputs a white video signal Rv.

[0062] The black video signal Rv and the white video signal Rv display a black or white image in the display area TD of the electro-optical panel 2. Therefore, according to this embodiment, the user can confirm the verification result R as a black or white image in the display area TD of the electro-optical panel 2.

[0063] As described above, the following effects can be obtained according to this embodiment. The driver 1 in this embodiment includes a DAC 11 as a DA conversion circuit and an amplifier 12 as an amplifier circuit, and comprises a first drive circuit 10 that outputs a video signal Dv based on grayscale data Db, a second drive circuit 20 that outputs a video signal Dv based on grayscale data Db, a plurality of capacitive elements C21 and a capacitive drive circuit 21 that drives the plurality of capacitive elements C21, and comprises a verification circuit 50 that verifies the output of the second drive circuit 20 and outputs a verification result R, an output node NODE1 to which the video signal Dv or the verification result R is output, a switch SW11 as a first switch that electrically connects the first drive circuit 10 and the output node NODE1, a switch SW21 as a second switch that electrically connects the second drive circuit 20 and the output node NODE1, a switch SW22 as a third switch that electrically connects the plurality of capacitive elements C21 and the verification circuit 50, and a switching circuit 40 that selectively outputs the video signal Dv and the verification result R to the output node NODE1.

[0064] Thus, the driver 1 of this embodiment includes a switching circuit 40 that selectively outputs the video signal Dv and the verification result R to the output node NODE1. Therefore, according to the driver 1 of this embodiment, the verification result R can be output from the same output node NODE1 as the video signal Dv. Thus, the user can easily obtain the verification result R.

[0065] In the driver 1 of this embodiment, the verification circuit 50b, which is the verification circuit 50, outputs verification result data Rb consisting of n bits (where n is a natural number of 2 or more) of grayscale data as the verification result R. Therefore, according to the driver 1 of this embodiment, the test result R can be easily confirmed.

[0066] In the driver 1 of this embodiment, the verification circuit 50b, which is the verification circuit 50, causes the verification result R to be different when the polarity is positive and when the polarity is negative. Therefore, according to the driver 1 of this embodiment, the test result R can be displayed on the electro-optical panel 2, which consists of a liquid crystal display panel.

[0067] In the driver 1 of this embodiment, the switching circuit 40 selectively inputs the verification result R and the gradation data Db to the DAC 11. Therefore, according to the driver 1 of this embodiment, the test result R can be confirmed as a display on the electro-optical panel 2.

[0068] The electro-optical device 100 of this embodiment comprises an electro-optical panel 2 and the driver 1 described above for driving the electro-optical panel 2. Therefore, with the electro-optical device 100 of this embodiment, the verification result R can be easily confirmed. Furthermore, the verification result R can be confirmed as a display on the electro-optical panel 2.

[0069] 2. Embodiment 2 Next, the driver 1 according to Embodiment 2 will be described based on Figures 4 to 6. Figure 4 is a circuit diagram of driver 1 according to Embodiment 2. Figure 5 is a circuit diagram of driver 1 according to a modified example of Embodiment 2. Figure 6 is a timing chart showing the operation of driver 1 according to a modified example of Embodiment 2 during inspection.

[0070] The driver 1 according to Embodiment 2 differs from the driver 1 according to Embodiment 1 in that it outputs a verification result signal Rh as the verification result R from the output node NODE1. In Embodiment 2, the verification circuit 50h includes a comparator 53 made of a high-voltage transistor, and outputs a verification result signal Rh as the verification result R. Note that components identical to those in Embodiment 1 may be denoted by the same reference numerals and their descriptions may be omitted.

[0071] As mentioned above, the test result signal Rh is a signal consisting of two voltage values, high and low. Users can check the test result R using the same output node NODE1 as the video signal Dv. Therefore, there is no need to provide a separate service port for outputting the test result R. Furthermore, users do not need to connect any equipment to the service port. Thus, users can easily obtain the test result R.

[0072] When a user wants to verify the test result R using the test result signal Rh, they can easily visualize and verify the test result signal Rh by, for example, placing a probe such as an oscilloscope on the output node NODE1.

[0073] In Embodiment 2, the switching circuit 40 consists of switches SW11, SW21, SW31, and SW41. Switch SW41 is controlled by the control signal TEST_OUT. Switch SW41 is turned ON when the verification circuit 50 is performing verification, electrically connecting the verification circuit 50 and the output node NODE1, and is turned OFF at other times. On the other hand, switches SW11, SW21, and SW31 are turned OFF when the verification circuit 50 is performing verification, and are turned ON at other times.

[0074] 2.1. Driver 1 related to the modified example As shown in Figure 5, the modified driver 1 of Embodiment 2 differs from the driver 1 of Embodiment 2 described above in that the verification circuit 50s outputs a verification result signal Rs as the verification result R, and includes a level shifter (L / S) 54 that level-shifts the verification result signal Rs to a verification result signal Rh. Note that components identical to those in Embodiment 1 and Embodiment 2 are denoted by the same reference numerals and their descriptions may be omitted.

[0075] The calibration circuit 50s includes a comparator 53 composed of low-voltage transistors. In the modified calibration circuit 50s, since it is composed of low-voltage transistors, the circuit area of ​​the calibration circuit 50s can be reduced, and the operating speed and accuracy can be improved.

[0076] 2.2. Operation of the verification circuit 50 Figure 6 is a timing chart showing the operation of the calibration circuit 50 according to Embodiment 2 and a modified example of Embodiment 2.

[0077] In Figure 6, the waveform shown for TEST_OUT is the waveform of the control signal TEST_OUT input to the control terminal of switch SW41 of the switching circuit 40. The waveform shown for Rh is the waveform of the verification result signal Rh output from output node NODE1.

[0078] When the verification is performed by the verification circuit 50s, the control signal TEST_OUT is set to a high level, and the control signals AENB, DENB, and LENB are set to a low level. As a result, switch SW41 of the switching circuit 40 is turned ON, and switches SW11, SW21, and SW31 are turned OFF.

[0079] As described above, the driver 1 of Embodiment 2 provides the following additional effects in addition to those of the driver 1 of Embodiment 1.

[0080] In the driver 1 of Embodiment 2, the switching circuit 40 has a switch SW41 as a fourth switch that electrically connects the verification circuit 50 and the output node NODE1, and outputs the verification result R to the output node NODE1 when the switch SW41 is ON.

[0081] Therefore, according to the driver 1 of Embodiment 2, the verification result R can be easily confirmed. Furthermore, the verification result R can be confirmed as a display on the electro-optical panel 2. Since the switching circuit 40 that outputs the verification result R from output node NODE1 can be realized with a simple configuration, the circuit area and cost can be reduced, and reliability can be improved.

[0082] In the driver 1 of Embodiment 2, the calibration circuit 50s is a low-voltage circuit and further comprises a level shifter 54 provided between the calibration circuit 50s and the switch SW41.

[0083] Therefore, according to the driver 1 of Embodiment 2, the calibration circuit 50s can be constructed using a low-voltage transistor, which reduces the circuit area and improves the operating speed and accuracy.

[0084] 3. Embodiment 3 Next, the driver 1 according to Embodiment 3 will be described based on Figures 7 to 10. Figure 7 is a circuit diagram of driver 1 according to Embodiment 3. Figure 8 is a timing chart showing the operation of driver 1 during inspection according to Embodiment 3. Figure 9 is a circuit diagram of driver 1 according to a modified example of Embodiment 3. Figure 10 is a timing chart showing the operation of driver 1 during inspection according to a modified example of Embodiment 3.

[0085] The driver 1 according to Embodiment 3 differs from the driver 1 according to Embodiment 2 in that the discharge circuit 71 is electrically connected to the output line R_LINE, which electrically connects the calibration circuit 50 and the switch SW41. Note that components identical to those in Embodiment 1 may be given the same reference numerals and their descriptions may be omitted.

[0086] The discharge circuit 71 has one end electrically connected to the output line R_LINE and the other end electrically connected to ground. The discharge circuit 71 is controlled ON / OFF by the control signal TEST_PROT and functions to discharge the charge on the output line R_LINE, thereby lowering the potential of the output line R_LINE to within the withstand voltage range of the calibration circuit 50.

[0087] In Embodiment 3, the calibration circuit 50s is composed of a low-voltage transistor. Therefore, the discharge circuit 71 lowers the potential of the output line R_LINE to within the voltage range of the calibration circuit 50s. Thus, it is possible to prevent the calibration circuit 50s from failing.

[0088] 3.1. Operation of the 50s test circuit In Figure 8, the waveform shown for TEST_PROT is the waveform of the control signal TEST_PROT input to the control terminal of the discharge circuit 71.

[0089] When the calibration is performed using the calibration circuit 50s, the control signal TEST_PROT is at a low level, and the discharge circuit 71 is turned OFF. On the other hand, during other periods, the control signal TEST_PROT is at a high level, the discharge circuit 71 is turned ON, and the charge on the output line R_LINE is discharged.

[0090] 3.2. Regarding variations As shown in Figure 9, the modified driver 1 differs from the driver 1 of Embodiment 3 described above in that the discharge circuit 71 is electrically connected to the output line OUT_LINE between the switch SW41 of the switching circuit 40 and the output node NODE1. Furthermore, the modified driver 1 includes a high-voltage calibration circuit 50h and a level shifter 54 that level-shifts the high-voltage calibration result signal Rh to a low-voltage calibration result signal Rs.

[0091] When performing a test using the test circuit 50h, before the switch SW41 of the switching circuit 40 is turned ON, the control signal TEST_PROT temporarily becomes high level, the discharge circuit 71 temporarily turns ON, and the charge on the output line OUT_LINE is discharged. After the discharge circuit 71 turns OFF, the control signal TEST_OUT becomes high level, and the switch SW41 of the switching circuit 40 is turned ON.

[0092] When the switch SW41 of the switching circuit 40 is turned ON, the charge on the output line OUT_LINE is discharged. Therefore, the application of voltages exceeding their withstand voltage to the calibration circuit 50h and the level shifter 54 is suppressed, thereby preventing characteristic degradation or damage to the calibration circuit 50h and the level shifter 54, and improving the quality of the driver 1.

[0093] In Figure 10, the waveform indicated by Rh is the waveform of the test result signal Rh output by the test circuit 50h to the output line R_LINE. The waveform indicated by Rs is the waveform of the test result signal Rs output from the level shifter 54. As shown in Figure 10, the level shifter 54 levels-shifts the high-voltage test result signal Rh to a low-voltage test result signal Rs and outputs it.

[0094] As described above, the driver 1 of Embodiment 3 provides the following additional effects in addition to the effects of the verification circuit 50 of Embodiments 1 and 2.

[0095] The driver 1 of Embodiment 3 further includes a discharge circuit 71, one end of which is electrically connected between the calibration circuit 50 and the switch SW41, and the other end of which is electrically connected to ground.

[0096] Thus, according to the driver 1 of Embodiment 3, the discharge circuit 71 can discharge the charge on the output line R_LINE that electrically connects the calibration circuit 50 and the switch SW41. Therefore, the application of a voltage exceeding the withstand voltage of the calibration circuit 50 is suppressed, thereby suppressing the degradation or destruction of the calibration circuit 50 and improving the quality of the driver 1.

[0097] The driver 1 of Embodiment 3 further includes a discharge circuit 71, one end of which is electrically connected between the output node NODE1 and the switch SW41, and the other end of which is electrically connected to ground.

[0098] Thus, according to the driver 1 of Embodiment 3, the discharge circuit 71 can discharge the charge on the output line OUT_LINE that electrically connects the output node NODE1 and the switch SW41. Therefore, the application of a voltage exceeding the withstand voltage of the calibration circuit 50 is suppressed, thereby suppressing the degradation or destruction of the calibration circuit 50 and improving the quality of the driver 1.

[0099] 4. Embodiment 4 Next, the driver 1 according to Embodiment 4 will be described based on Figures 11 to 16. Figure 11 is a circuit diagram of the driver 1 according to Embodiment 4. Figure 12 is a timing chart showing the operation of the driver 1 according to Embodiment 4 during inspection. Figure 13 is an explanatory diagram showing an example of the display of the verification result R during inspection of the driver 1 according to Embodiment 4. Figure 14 is a circuit diagram showing a first circuit example of the verification circuit 50v according to Embodiment 4. Figure 15 is a circuit diagram showing a second circuit example of the verification circuit 50v according to Embodiment 4. Figure 16 is a circuit diagram showing a third circuit example of the verification circuit 50v according to Embodiment 4.

[0100] The driver 1 according to Embodiment 4 differs from the driver 1 according to Embodiments 1 to 3 in that it includes a verification circuit 50v that outputs a video signal Rv as the verification result R. Note that components identical to those in Embodiments 1 to 3 may be denoted by the same reference numerals, and their descriptions may be omitted.

[0101] Figures 14 to 16 show an example of the calibration circuit 50V. As shown in Figures 14 to 16, the calibration circuit 50V includes a comparator 53 and a gradation voltage conversion circuit 55. The calibration circuit 50V shown in Figures 14 and 15 is equipped with a high-voltage comparator 53, while the calibration circuit 50V shown in Figure 16 is equipped with a low-voltage comparator 53. The calibration circuit 50V shown in Figure 16 is equipped with a level shifter 54 in the gradation voltage conversion circuit 55.

[0102] The gradation voltage conversion circuit 55 receives the verification result signal Rh or verification result signal Rs and the polarity signal POL as inputs and outputs one of the following voltages: voltage VDRH, voltage VDRL, or voltage VC. Voltage VDRH is the highest voltage of the gradation voltage, voltage VDRL is the lowest voltage of the gradation voltage, and voltage VC is the intermediate voltage between the highest and lowest voltages of the gradation voltage.

[0103] When the electro-optic panel 2 is normally black, it displays white by voltages VDRH and VDRL, and black by voltage VC. Therefore, the user can observe the calibration result R as a grayscale display of white or black in the display area TD of the electro-optic panel 2.

[0104] 4.1. Operation of the verification circuit 50 As shown in Figure 12, the waveforms shown by D0 to D11 are waveforms that represent bits D0 to D11 of the grayscale data Dd input to the capacitive drive circuit 21, either 1 or 0.

[0105] The waveform shown by TEST_NODE1 corresponds to the test voltage V20 applied to the test node TEST_NODE1, corresponding to bits D0 through D11, and the voltage doubles in magnitude sequentially from bit D0. Note that in Figure 12, the waveforms shown by TEST_NODE1 from bit D5 onwards are simplified for space limitations.

[0106] Figure 12 shows that there are defects in the test voltage V20 corresponding to bit D5 and the test voltage V20 corresponding to bit D9. Therefore, the verification result signal Rh corresponding to bits D5 and D9 will be at a low level, and the video signal Rv will be the intermediate voltage corresponding to black.

[0107] Figure 13 shows an example of the display of the test result R of the driver 1 in Embodiment 4, and shows the test result R displayed in the display area TD of the electro-optical panel 2.

[0108] The video signal Rv, as the verification result R, is output corresponding to bits D0, D1, ..., Dn-1, and Dn of the second drive circuit 20. In the example shown in Embodiment 4, the positions corresponding to bits D5 and D9 are displayed in black, and from this display, it can be confirmed that there is a defect in the configuration of the second drive circuit 20 corresponding to bits D5 and D9.

[0109] In the example shown in Figure 13, the video signal Rv, representing the verification result R, is output vertically in units of several lines for each bit D0, D1, ..., Dn-1, Dn. OUT8 indicates an area containing several lines of data lines 2y corresponding to bit D5, and OUT13 indicates an area containing several lines of data lines 2y corresponding to bit D9. By outputting the video signal Rv in this way, the visibility of the verification result R displayed in the display area TD of the electro-optical panel 2 can be improved.

[0110] As described above, the driver 1 of Embodiment 4 provides the following additional effects in addition to the effects of the verification circuit 50 of Embodiments 1 to 3.

[0111] In the driver 1 of Embodiment 4, the calibration circuit 50v, which is a calibration circuit 50, outputs a video signal Rv as a grayscale value as the calibration result R. Therefore, according to the driver 1 of Embodiment 4, the test result R can be easily confirmed. Furthermore, the test result R can be confirmed as a display on the electro-optical panel 2.

[0112] In the driver 1 of Embodiment 4, the test circuit 50V, which serves as the test circuit 50, causes the test result Rv to differ between the positive and negative polarity states. Therefore, according to the driver 1 of Embodiment 4, the test result Rv can be displayed on the electro-optical panel 2, which consists of a liquid crystal display panel.

[0113] In the driver 1 of Embodiment 4, the verification circuit 50 outputs the verification result R for each of the multiple capacitive elements C21. Therefore, according to the driver 1 of Embodiment 4, it is possible to check whether or not there is a malfunction in each of the multiple capacitive elements C21.

[0114] The driver 1 of Embodiment 4 further includes a gradation voltage conversion circuit 55 provided between the calibration circuit 50 and the switch SW41. Therefore, according to the driver 1 of Embodiment 4, the verification result R can be output as a video signal Rv as a gradation voltage. Thus, the verification result R can be confirmed as a display on the electro-optical panel 2.

[0115] In the driver 1 of Embodiment 4, the grayscale voltage conversion circuit 55 outputs a video signal Rv consisting of grayscale voltages corresponding to white grayscale or black grayscale as the verification result R. Therefore, according to the driver 1 of Embodiment 4, the test result R can be easily confirmed. Furthermore, the test result R can be confirmed as a display on the electro-optical panel 2.

[0116] Although preferred embodiments have been described above, the present invention is not limited to the embodiments described above. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that performs a similar function to that of the embodiments described above, and any configuration can be added. [Explanation of Symbols]

[0117] 1…Driver, 2…Electro-optical panel, 2s…Element substrate, 2t…Opposite substrate, 2x…Scan line, 2y…Data line, 21a…Protruding part, 3…Flexible substrate, 10…First drive circuit, 11…DAC, 12…Amplifier, 20…Second drive circuit, 21…Capacitive drive circuit, 30…Balanced capacitance circuit, 31…Buffer, 40…Switching circuit, 50…Certification circuit, 50b…Certification circuit, 50h…Certification circuit, 50s, 50v…Certification circuit, 53…Comparator, 54…Level shifter, 55…Gradation voltage conversion circuit, 60…Control circuit, 71…Discharge circuit, 100…Electro-optical device, C21, C31…Capacitive elements, CP…Electro-optical panel side capacitance, CP1…Substrate capacitance, CP2…Panel capacitance, P…Pixel, TD…Display area, SW11, SW21, SW22, SW31 SW32, SW33, SW41… Switches, TEST_LINE1, TEST_LINE2… Test lines, OUT_LINE, R_LINE… Output lines, NODE1… Output node, NODE2… Input node, NODE3… Input / output node, NODE4… Input node, TEST_NODE1, TEST_NODE2… Test nodes, AENB, DENB, LENB, TENB1, TENB2, EN0, TEST_CTRL, TEST_PROT, TEST_OUT, TEST_MODE… Control signals, POL… Polarity signal, Db… Grayscale data, D0, D5, D9, D11… Bits, V10… Grayscale voltage, V20, V30… Voltage under test, Dv… Video signal, R… Test result, Rv… Video signal, Rb… Test result data, Rs, Rh… Test result.

Claims

1. A first drive circuit that includes a DA conversion circuit and an amplifier circuit and outputs a video signal based on grayscale data, A second drive circuit includes a plurality of capacitive elements and a capacitive drive circuit that drives the plurality of capacitive elements, and outputs the video signal based on the grayscale data, A verification circuit that verifies the output of the second drive circuit and outputs the verification result, An output node to which the aforementioned video signal or the aforementioned test result is output, A first switch electrically connects the first drive circuit and the output node, A second switch electrically connects the second drive circuit and the output node, A third switch electrically connects the plurality of capacitive elements and the calibration circuit, The system includes a switching circuit that selectively outputs the video signal and the verification result to the output node. Drive circuit.

2. The verification circuit outputs n bits of grayscale data (where n is a natural number greater than or equal to 2) as the verification result. The drive circuit according to claim 1.

3. The verification circuit outputs a grayscale value as the verification result. The drive circuit according to claim 1.

4. The aforementioned verification circuit causes the verification result to differ between positive and negative polarity. The drive circuit according to claim 1.

5. The verification circuit outputs the verification result for each of the multiple capacitive elements. The drive circuit according to claim 1.

6. The switching circuit selectively inputs the verification result and the grayscale data to the DA conversion circuit. The drive circuit according to claim 1.

7. The switching circuit has a fourth switch that electrically connects the verification circuit and the output node, and outputs the verification result to the output node when the fourth switch is ON. The drive circuit according to claim 1.

8. The calibration circuit is a low-voltage circuit and further comprises a level shifter provided between the calibration circuit and the fourth switch. The drive circuit according to claim 7.

9. The system further comprises a discharge circuit, one end of which is electrically connected between the verification circuit and the fourth switch, and the other end of which is electrically connected to ground. The drive circuit according to claim 7.

10. The system further comprises a discharge circuit, one end of which is electrically connected between the output node and the fourth switch, and the other end of which is electrically connected to ground. The drive circuit according to claim 7.

11. The system further includes a gradation voltage conversion circuit provided between the calibration circuit and the fourth switch. The drive circuit according to claim 7.

12. The aforementioned grayscale voltage conversion circuit outputs a video signal consisting of grayscale voltages corresponding to white grayscale or black grayscale as a result of the verification. The drive circuit according to claim 11.

13. Electro-optical panel and The device comprises a drive circuit according to any one of claims 1 to 12 for driving the electro-optical panel, Electro-optical device.

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