Semiconductor equipment

Abstract

A semiconductor device is provided, comprising: an emitter electrode provided above a semiconductor substrate and having a first main region, a second main region and a third main region; a gate pad provided above the semiconductor substrate; a gate metal layer electrically connected to the gate pad; and a gate runner portion electrically connected to the gate metal layer, wherein the plurality of trench portions have a plurality of gate trench portions; the emitter electrode has a first emitter bridge portion connecting the first main region and the second main region, and a second emitter bridge portion connecting the second main region and the third main region; and below the first emitter bridge portion, a gate trench portion different from the gate trench portion provided below the second emitter bridge portion is provided.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device.

BACKGROUND ART

[0002] Patent Document 1 describes that "a connection portion 15 is formed to electrically connect the emitter electrodes 14 on both sides of the first gate wiring 18 and the second gate wiring 20". [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Unexamined Patent Publication No. 2010-98250

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0003] In such a connection portion of the emitter electrodes, metal gate wirings cannot be used and only polysilicon gate wirings are used, so that the resistance value of the gate wirings is higher than that in other portions.

MEANS FOR SOLVING THE PROBLEMS

[0004] In the first embodiment, a semiconductor substrate is provided with a drift region of a first conductivity type, a base region of a second conductivity type provided above the drift region, an emitter region of a first conductivity type provided above the drift region and having a higher doping concentration than the drift region, a plurality of contact regions of a second conductivity type provided above the drift region and having a higher doping concentration than the base region, a plurality of trenches on the front surface of the semiconductor substrate extended in a predetermined trench extension direction, and an emitter electrode provided above the semiconductor substrate and having a first main region, a second main region and a third main region, and the A semiconductor device is provided, comprising a gate pad provided above a semiconductor substrate, a gate metal layer electrically connected to the gate pad, and a gate runner portion electrically connected to the gate metal layer, wherein the plurality of trench portions have a plurality of gate trench portions, and the emitter electrode has a first emitter bridge portion connecting the first main region and the second main region, and a second emitter bridge portion connecting the second main region and the third main region, and below the first emitter bridge portion thereof a gate trench portion different from the gate trench portion provided below the second emitter bridge portion.

[0005] In the semiconductor device described above, the gate trench below the first emitter bridge does not need to be located below the second emitter bridge.

[0006] In any of the semiconductor devices described above, the first emitter bridge portion may be positioned differently from the second emitter bridge portion in the trench arrangement direction.

[0007] In any of the semiconductor devices described above, the gate metal layer may have a first gate metal portion extending between the first main region and the second main region, and a second gate metal portion extending between the second main region and the third main region, and the plurality of gate trenches may be provided below at least one of the first gate metal portion and the second gate metal portion.

[0008] In any of the semiconductor devices described above, the gate runner portion may include a first gate runner extending in the trench arrangement direction between the first main region and the second main region, and a second gate runner extending in the trench arrangement direction between the second main region and the third main region.

[0009] In any of the semiconductor devices described above, the first emitter bridge portion may be sandwiched between the gate metal layers in the trench arrangement direction, and the second emitter bridge portion may be sandwiched between the gate metal layers in the trench arrangement direction.

[0010] In any of the semiconductor devices described above, the first gate runner may be located below the first emitter bridge, and the second gate runner may be located below the second emitter bridge.

[0011] In any of the semiconductor devices described above, at least one end of the plurality of gate trenches in the trench extension direction may be located below the gate metal layer.

[0012] In any of the semiconductor devices described above, the gate pad may be provided on the edge side of the semiconductor substrate rather than on the active portion in the trench arrangement direction.

[0013] In any of the semiconductor devices described above, the first emitter bridge portion may be provided closer to the gate pad than the virtual center line of the active portion in the trench arrangement direction, and the second emitter bridge portion may be provided further away from the gate pad than the virtual center line.

[0014] In any of the semiconductor devices described above, the distance between the first emitter bridge portion and the gate pad-side end of the active portion in the trench arrangement direction may be 2.5% or more and 97.5% or less of the distance between the second emitter bridge portion and the gate pad-side end of the active portion.

[0015] Any of the above semiconductor devices may comprise a first active region, a second active region, and a third active region obtained by dividing the active portion into three equal parts in the trench arrangement direction, the first active region being close to the gate pad, the second active region being further away from the gate pad than the first active region, and the third active region being further away from the gate pad than the second active region, and the first emitter bridge portion and the second emitter bridge portion may be provided in the second active region.

[0016] In any of the above semiconductor devices, the distance between the first emitter bridge portion and the second emitter bridge portion in the trench arrangement direction may be 150 μm or more and 500 μm or less.

[0017] In any of the semiconductor devices described above, the distance between the first emitter bridge portion and the virtual center line in the trench arrangement direction may be equal to the distance between the second emitter bridge portion and the virtual center line.

[0018] In any of the semiconductor devices described above, the distance between the first emitter bridge portion and the gate pad-side end of the active portion in the trench arrangement direction may be 40% or more and 60% or less of the distance between the second emitter bridge portion and the gate pad-side end of the active portion.

[0019] In any of the semiconductor devices described above, the gate pad may be provided on the edge side of the semiconductor substrate rather than on the active portion in the trench extension direction.

[0020] In any of the semiconductor devices described above, the gate pad may be provided on the edge side of the semiconductor substrate relative to the virtual center line of the active portion in the trench extension direction.

[0021] The above summary of the invention does not enumerate all of its features. Subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0022] [Figure 1] This is a top view showing an example of the semiconductor device 100. [Figure 2] This is an enlarged view of the region R1 in FIG. 1. [Figure 3] This is a diagram showing an example of the a-a' cross section in FIG. 2. [Figure 4] This is an enlarged view of the region R2 in FIG. 1. [Figure 5] This is a diagram showing an example of the b-b' cross section in FIG. 4. [Figure 6] This is a top view showing an example of the semiconductor device 1100 according to a comparative example. [Figure 7] This is a graph showing the relationship between the position of the emitter bridge portion 53 and the parasitic resistance value in the gate trench portion 40. [Figure 8] This is a top view showing another example of the semiconductor device 100 according to the embodiment. [Figure 9] This is a top view showing another example of the semiconductor device 100 according to the embodiment. [Mode for Carrying Out the Invention]

[0023] Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the scope of claims. In addition, not all combinations of features described in the embodiments are necessarily essential to the solution means of the invention.

[0024] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper" or "front", and the other side is referred to as "lower" or "back". Of the two main surfaces of a substrate, layer or other member, one surface is referred to as the top surface or front surface, and the other surface is referred to as the bottom surface or back surface. The directions of "upper", "lower", "front" and "back" are not limited to the direction of gravity or the direction when the semiconductor device is mounted.

[0025] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0026] In this specification, the orthogonal axes parallel to the front and back surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the front and back surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the front and back surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0027] The region from the center of the semiconductor substrate in the depth direction to the front surface of the semiconductor substrate is sometimes referred to as the front side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the back surface of the semiconductor substrate is sometimes referred to as the back side.

[0028] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0029] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0030] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N D , the acceptor concentration is N A Therefore, the net doping concentration at any given position is N D -N A In this specification, net doping concentration may be simply referred to as doping concentration.

[0031] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the bonding of vacancies (V), oxygen (O), and hydrogen (H) in a semiconductor, function as electron donors. In this specification, VOH defects may be referred to as hydrogen donors.

[0032] In this specification, when P+ type or N+ type is mentioned, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is mentioned, it means that the doping concentration is lower than that of P type or N type. Unless otherwise specified, the units used in this specification are the SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m).

[0033] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration (atomic density) can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by spheroidal resistance (SR) spectroscopy may be used as the net doping concentration. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0034] If the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in that region. If the concentrations of the donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of the donor, acceptor, or net doping in that region may be used as the concentration of the donor, acceptor, or net doping. In this specification, concentrations per unit volume are expressed as atoms / cm³. 3 , or / cm 3 This unit is used for donor or acceptor concentrations in semiconductor substrates, or for chemical concentrations. The atom notation may be omitted.

[0035] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0036] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements that act as donors or acceptors. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentrations of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration. The concentrations used herein may be values ​​at room temperature. For example, values ​​at 300 K (Kelvin) (approximately 26.9°C) may be used.

[0037] Figure 1 is a top view showing an example of a semiconductor device 100. In Figure 1, the positions of each component projected onto the top surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted.

[0038] The semiconductor device 100 comprises a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 10 has edges 102 when viewed from above. In this specification, when simply referred to as "viewed from above," it means viewed from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 102 that face each other when viewed from above. In Figure 1, the X and Y axes are parallel to one of the edges 102. The Z axis is perpendicular to the top surface of the semiconductor substrate 10. In Figure 1, of the edges 102 extending in the Y-axis direction, the edge 102 on the negative side in the X-axis direction is designated as edge 102-1, and clockwise from edge 102-1, they are designated as edge 102-2, edge 102-3, and edge 102-4 in order. Multiple trenches, which will be described later, are provided extending in the Y-axis direction and arranged along the X-axis direction.

[0039] The semiconductor substrate 10 is provided with an active area 120. The active area 120 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be ON. An emitter electrode 52, which will be described later, is provided above the active area 120. In this example, the active area 120 is the region surrounded by the outer peripheral gate runner 48-0, which will be described later, when viewed from above the semiconductor substrate 10.

[0040] The emitter electrode 52 may be divided into multiple main regions. In this example, the emitter electrode 52 has a first main region 52-1, a second main region 52-2, and a third main region 52-3. In this example, the first main region 52-1, the second main region 52-2, and the third main region 52-3 are arranged sequentially along the Y-axis from the positive side (side 102-2) to the negative side (side 102-4). In this example, the first main region 52-1, the second main region 52-2, and the third main region 52-3 are spaced apart from each other.

[0041] The emitter electrode 52 may have an emitter bridge portion 53 that connects each main region. The emitter bridge portion 53 may be made of the same material as the emitter electrode 52. In this example, the emitter bridge portion 53 has a first emitter bridge portion 53-1 that connects the first main region 52-1 and the second main region 52-2, and a second emitter bridge portion 53-2 that connects the second main region 52-2 and the third main region 52-3.

[0042] In this example, the first emitter bridge portion 53-1 is positioned differently from the second emitter bridge portion 53-2 in the X-axis direction. That is, if the position of the gate pad 50 side end of the active portion 120 is taken as the reference position Xo in the X-axis direction, the distance X1 between the first emitter bridge portion 53-1 and the reference position Xo is different from the distance X2 between the second emitter bridge portion 53-2 and the reference position Xo. In the X-axis direction, the distance ΔX between the first emitter bridge portion 53-1 and the second emitter bridge portion 53-2 may be between 150 μm and 500 μm.

[0043] The reference position Xo may lie on a virtual line passing through the outermost end of the active section 120, on the side 102-1. The positions of the first emitter bridge section 53-1 and the second emitter bridge section 53-2 may be their center positions in the X-axis direction.

[0044] In this example, the first emitter bridge section 53-1 is positioned closer to the gate pad 50 than the virtual center line Xc of the active section 120 in the X-axis direction, and the second emitter bridge section 53-2 is positioned further away from the gate pad 50 than the virtual center line Xc. In this example, in the X-axis direction, the distance d1 between the first emitter bridge section 53-1 and the virtual center line Xc is equal to the distance d2 between the second emitter bridge section 53-2 and the virtual center line Xc.

[0045] In this example, by providing the first emitter bridge section 53-1 and the second emitter bridge section 53-2 at equal offsets from the center of the active section 120, variations in the emitter potential in the X-axis direction can be reduced.

[0046] In the X-axis direction, the distance X1 between the first emitter bridge section 53-1 and the reference position Xo may be between 2.5% and 97.5% of the distance X2 between the second emitter bridge section 53-2 and the reference position Xo. In this example, distance X1 is between 40% and 60% of distance X2.

[0047] If the active portion 120 is divided into three equal parts in the X-axis direction, and these are designated as the first active region 120-1, the second active region 120-2, and the third active region 120-3 in order of proximity to the gate pad 50, then the first emitter bridge portion 53-1 and the second emitter bridge portion 53-2 may be located in the second active region 120-2.

[0048] The active section 120 is provided with a transistor section including a transistor element such as an IGBT. The active section 120 may further be provided with a diode section including a diode element such as an FWD. Multiple trench sections are provided on the front surface of the semiconductor substrate 10 in the active section 120. In this example, the multiple trench sections are provided extending in the Y-axis direction. The multiple trench sections have a gate trench section and a dummy trench section. The gate trench section functions as a gate electrode to which a gate potential is applied in the transistor section. The dummy trench section is provided in the transistor section or the diode section and to which an emitter potential is applied. The dummy trench section is electrically connected to the emitter electrode 52.

[0049] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 50. In this example, the gate pad 50 is located on the negative side of the X-axis (side of edge 102-1) from the active part 120. The semiconductor device 100 may also have an anode pad, a cathode pad, a pad for current detection, etc. These pads may be located near the edge 102-3 opposite to the gate pad 50. When mounting the semiconductor device 100, each pad may be connected to an external circuit via wiring such as wires.

[0050] A gate potential is applied to the gate pad 50. The gate pad 50 is electrically connected to the gate conductive portion of the gate trench portion of the active portion 120. The semiconductor device 100 includes gate wiring connecting the gate pad 50 and the gate trench portion. In this example, the gate wiring has a gate metal layer 49 electrically connected to the gate pad 50 and a gate runner portion 48 electrically connected to the gate metal layer 49. In Figure 1, the gate metal layer 49 is shown with diagonal hatching, and the gate runner portion 48 is shown with a dashed line.

[0051] The gate metal layer 49 is positioned above the semiconductor substrate 10. The gate metal layer 49 may be a metal wiring. In this example, the gate metal layer 49 has an outer peripheral gate metal portion 49-0 and a first gate metal portion 49-1 and a second gate metal portion 49-2 connected to the outer peripheral gate metal portion 49-0 and extending in the X-axis direction over the active portion 120. In a top view of the semiconductor substrate 10, the outer peripheral gate metal portion 49-0 is positioned between the emitter electrode 52 and the edge 102 of the semiconductor substrate 10. In this example, the outer peripheral gate metal portion 49-0 surrounds the active portion 120 in a top view of the semiconductor substrate 10.

[0052] In this example, the first gate metal portion 49-1 extends between the first main region 52-1 and the second main region 52-2, and the second gate metal portion 49-2 extends between the second main region 52-2 and the third main region 52-33. By providing the first gate metal portion 49-1 and the second gate metal portion 49-2 in the active portion 120, variations in the wiring length from the gate pad 50 can be reduced for each region of the semiconductor substrate 10.

[0053] In this example, the gate metal layer 49 is provided separately from the emitter electrode 52. That is, in a top view of the semiconductor substrate 10, the first gate metal portion 49-1 is provided spaced apart from the region surrounded by the first main region 52-1, the second main region 52-2, and the first emitter bridge portion 53-1, and in a top view of the semiconductor substrate 10, the second gate metal portion 49-2 is provided spaced apart from the region surrounded by the second main region 52-2, the third main region 52-3, and the first emitter bridge portion 53-1. The first emitter bridge portion 53-1 is sandwiched between the first gate metal portion 49-1 in the X-axis direction, and the second emitter bridge portion 53-2 is sandwiched between the second gate metal portion 49-2 in the X-axis direction.

[0054] The gate runner portion 48 is positioned above the semiconductor substrate 10. The gate runner portion 48 may be a wiring made of a semiconductor such as polysilicon doped with impurities. In this example, the gate runner portion 48 has an outer peripheral gate runner 48-0 and a first gate runner 48-1 and a second gate runner 48-2 connected to the outer peripheral gate runner 48-0 and extending in the X-axis direction on the active portion 120.

[0055] In this example, the outer periphery gate runner 48-0 is provided around the active portion 120. In other words, the active portion 120 in this example refers to the region surrounded by the outer periphery gate runner 48-0. In this example, the outer periphery gate runner 48-0 is provided below the outer periphery gate metal portion 49-0. However, in the vicinity of the gate pad 50 in this example, the outer periphery gate metal portion 49-0 is positioned between the gate pad 50 and the edge 102-1, and the outer periphery gate runner 48-0 is positioned along the outer circumference of the gate pad 50, spaced apart from the outer periphery gate metal portion 49-0.

[0056] In this example, the first gate runner 48-1 extends between the first main region 52-1 and the second main region 52-2, and the second gate runner 48-2 extends between the second main region 52-2 and the third main region 52-33. In this example, the first gate runner 48-1 is located below the first emitter bridge section 53-1, and the second gate runner 48-2 is located below the second emitter bridge section 53-2.

[0057] In this way, the emitter electrode 52 is divided into multiple main regions along the trench extension direction (Y-axis direction), and gate runner sections 48 (first gate runner 48-1, second gate runner 48-2) extending in a direction intersecting the trench section (X-axis direction) are provided between each main region. As a result, even in semiconductor devices 100 with large chip sizes, the wiring length of the gate wiring from the gate pad 50 is reduced, thereby suppressing an increase in parasitic resistance in the gate trench section 40 and preventing a decrease in switching withstand capability.

[0058] Furthermore, by connecting each main region with the emitter bridge section 53, the emitter potential in each main region can be kept at the same potential. In addition, by providing the emitter bridge section 53, variations in the inductance components of the wires coupled to each main region can be reduced in a semiconductor module on which the semiconductor device 100 is mounted, thereby suppressing a decrease in switching withstand capability.

[0059] The semiconductor device 100 may be provided with an edge termination structure between the active portion 120 and the edge 102. The edge termination structure mitigates electric field concentration on the front side of the semiconductor substrate 10. The edge termination structure may have, for example, at least one of the following structures: a guard ring, a field plate, and a resurf, arranged in an annular shape around the active portion 120, or a combination of several of these structures.

[0060] Note that Figure 1 shows an example in which the emitter electrode 52 is divided into three main regions, but this is merely an example. The emitter electrode 52 may be divided into two main regions, or into four or more main regions. Between each main region, a gate runner portion 48 is provided that extends in a direction intersecting the trench portion (X-axis direction).

[0061] Figure 2 is an enlarged view of region R1 in Figure 1. Figure 2 shows an example of the structure near the Y-axis end of the emitter electrode 52. Region R1 includes a part of the third main region 52-3 adjacent to the positive X-axis end (side 102-3) and the negative Y-axis end (side 102-4), as well as the outer gate metal portion 49-0 and the outer gate runner 48-0. However, here, the third main region 52-3, the outer gate metal portion 49-0, and the outer gate runner 48-0 will be described as the emitter electrode 52, the gate metal layer 49, and the gate runner portion 48, respectively. Furthermore, the structure near the Y-axis end of each main region of the emitter electrode 52 is common to region R1, so its description is omitted.

[0062] The semiconductor device 100 includes a gate trench 40, a dummy trench 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided on the front surface of the semiconductor substrate 10. The gate trench 40 and the dummy trench 30 are examples of trenches.

[0063] The semiconductor device 100 in this example includes a gate metal layer 49 and an emitter electrode 52 provided above the front surface of a semiconductor substrate 10. The gate metal layer 49 and the emitter electrode 52 are provided separately from each other. The gate metal layer 49 and the emitter electrode 52 are electrically insulated from each other.

[0064] An interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 49 and the front surface of the semiconductor substrate 10, but this is omitted in Figure 2. Contact holes 54, 55, and 56 are provided through the interlayer insulating film in this example. In Figure 2, each contact hole is hatched with diagonal lines.

[0065] The emitter electrode 52 is located above the gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. The emitter electrode 52 is electrically connected to the emitter region 12, base region 14, and contact region 15 on the front surface of the semiconductor substrate 10 by contact holes 54.

[0066] Furthermore, the emitter electrode 52 is connected to a dummy conductive part in the dummy trench portion 30 by a contact hole 56. A connecting portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive part. The connecting portion 25 is provided on the front surface of the semiconductor substrate 10 via insulating films such as the interlayer insulating film and the dummy insulating film of the dummy trench portion 30.

[0067] The gate metal layer 49 is electrically connected to the gate runner portion 48 by contact holes 55. The gate runner portion 48 may be formed of polysilicon doped with impurities or the like. On the front surface of the semiconductor substrate 10, the gate runner portion 48 is connected to the gate conductive portion in the gate trench portion 40. The gate runner portion 48 is not electrically connected to the dummy conductive portion in the dummy trench portion 30 or the emitter electrode 52.

[0068] The gate runner portion 48 and the emitter electrode 52 are electrically isolated by an insulator such as an interlayer insulating film and an oxide film. In this example, the gate runner portion 48 is provided from below the contact hole 55 to the tip portion 41 of the gate trench portion 40. At the tip portion 41 of the gate trench portion 40, the gate conductive portion is exposed on the front surface of the semiconductor substrate 10 and connects to the gate runner portion 48.

[0069] The emitter electrode 52 and gate metal layer 49 are formed from a conductive material containing metal. For example, at least a portion of the emitter electrode 52 and gate metal layer 49 are formed from aluminum or an alloy mainly composed of aluminum, such as AlSi, AlSiCu, or other metal alloys. The emitter electrode 52 and gate metal layer 49 may have a barrier metal made of titanium or titanium nitride below the region made of aluminum or the like. The barrier metal may be in contact with the semiconductor substrate 10. The emitter electrode 52 and gate metal layer 49 may also have a metal plug made of tungsten or the like below the region made of aluminum or the like.

[0070] The well region 11 is provided overlapping the gate runner portion 48 when viewed from above on the semiconductor substrate 10. The well region 11 also extends to a predetermined width in areas that do not overlap with the gate runner portion 48. In this example, the well region 11 is provided away from the Y-axis end of the contact hole 54 towards the gate runner portion 48. The well region 11 is a second conductivity type region with a higher doping concentration than the base region 14. The gate runner portion 48 is electrically insulated from the well region 11.

[0071] In this example, the base region 14 is P-type, and the well region 11 is P+ type. The well region 11 is formed from the top surface of the semiconductor substrate 10 to a position deeper than the lower edge of the base region 14. The base region 14 is provided in contact with the well region 11. Therefore, the well region 11 is electrically connected to the emitter electrode 52.

[0072] The active portion 120 is provided with a plurality of trenches arranged in the alignment direction. In this example, the extension direction of the trenches is perpendicular to the alignment direction, with the alignment direction being the X-axis direction and the extension direction being the Y-axis direction. The plurality of trenches have a plurality of gate trenches 40.

[0073] In this example, at least one end of the gate trench portion 40 in the Y-axis direction is provided below the gate metal layer 49. The gate trench portion 40 in this example may have two straight portions 39 (the trench portion which is straight along the direction of extension) extending along the Y-axis direction, and a tip portion 41 connecting the two straight portions 39.

[0074] At least a portion of the tip portion 41 may be curved in shape when viewed from above on the semiconductor substrate 10. The tip portion 41 connects the ends of the two straight portions 39 in the Y-axis direction to the gate runner portion 48, thereby functioning as a gate electrode to the gate trench portion 40. On the other hand, by making the tip portion 41 curved, electric field concentration at the end can be mitigated compared to having it end with the straight portions 39.

[0075] The active section 120 may have one or more gate trench sections 40 and one or more dummy trench sections 30 alternately arranged along the X-axis direction. In this example, the dummy trench sections 30 are provided between each straight section 39 of the gate trench section 40. In other examples, one dummy trench section 30 may be provided between each straight section 39, or multiple dummy trench sections 30 may be provided.

[0076] Furthermore, dummy trench sections 30 are not required between each linear section 39, but gate trench sections 40 may be provided. This structure allows for an increase in the electron current from the emitter region 12, thereby reducing the on-voltage.

[0077] The dummy trench portion 30 may have a linear shape extending in the extension direction, and like the gate trench portion 40, it may have a linear portion 29 and a tip portion 31. In this example, only the dummy trench portion 30 having a tip portion 31 is provided, but in other examples, the active portion 120 may include a linear dummy trench portion 30 without a tip portion 31.

[0078] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located in the well region 11 when viewed from above the semiconductor substrate 10. In other words, at the Y-axis end of each trench portion, the lower end in the depth direction (Z-axis direction) of each trench portion is covered by the well region 11. Furthermore, the trench portion provided on the X-axis end side of the active portion 120 may also be covered by the well region 11. This makes it possible to mitigate electric field concentration at the lower end of each trench portion.

[0079] A mesa is provided between adjacent trenches in the X-axis direction. The mesa refers to the region within the semiconductor substrate 10 that is sandwiched between trenches. For example, the range of the mesa in the Z-axis direction is from the front surface of the semiconductor substrate 10 to the lower end of the trench. In this example, the mesa is sandwiched between adjacent trenches in the X-axis direction and extends in the Y-axis direction along the trenches on the front surface of the semiconductor substrate 10.

[0080] Each mesa portion is provided with a base region 14. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in the region sandwiched between the base regions 14 when viewed from above on the semiconductor substrate 10. In this example, the emitter region 12 is N+ type and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate 10 in the Z-axis direction.

[0081] The mesa portion has an emitter region 12 exposed on the front surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion in contact with the gate trench portion 40 is provided with a contact region 15 exposed on the front surface of the semiconductor substrate 10.

[0082] Each of the contact region 15 and emitter region 12 in the mesa section extends from one trench section to the other in the X-axis direction. As an example, the contact region 15 and emitter region 12 of the mesa section are arranged alternately along the extension direction (Y-axis direction) of the trench section.

[0083] In other examples, the contact region 15 and emitter region 12 of the mesa may be arranged in a stripe pattern along the extension direction (Y-axis direction) of the trench. For example, in a top view of the semiconductor substrate 10, the emitter region 12 is provided in the region in contact with the trench, and the contact region 15 is provided in the region sandwiched between the emitter regions 12.

[0084] A contact hole 54 is provided above each mesa portion. The contact hole 54 is located in the region sandwiched between the base region 14 in its extension direction (Y-axis direction). In this example, the contact hole 54 is provided above the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 may be located in the center in the alignment direction (X-axis direction) of the mesa portions.

[0085] Figure 3 shows an example of the a-a' cross-section in Figure 2. The a-a' cross-section is the XZ plane passing through the emitter region 12, contact region 15, base region 14, gate trench 40, and dummy trench 30. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the a-a' cross-section.

[0086] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is an insulating film such as silicate glass to which impurities such as boron or phosphorus have been added. The interlayer insulating film 38 may be in contact with the front surface 21 of the semiconductor substrate 10, and other films such as an oxide film may be provided between the interlayer insulating film 38 and the front surface 21. The interlayer insulating film 38 is provided with contact holes 54 and 55 as described in Figure 2.

[0087] The emitter electrode 52 is provided on the front surface 21 of the semiconductor substrate 10 and the upper surface of the interlayer insulating film 38. The emitter electrode 52 is electrically connected to the front surface 21 of the semiconductor substrate 10 by contact holes 54 in the interlayer insulating film 38. Plug areas of tungsten (W) or the like may be provided inside the contact holes 54 and 55. The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed from a material containing metal or a laminated film thereof.

[0088] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. In this example, the semiconductor substrate 10 is a silicon substrate.

[0089] The semiconductor substrate 10 has a drift region 18 of the first conductivity type. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doping regions being provided.

[0090] One or more storage regions 16 may be provided above the drift region 18 in the Z-axis direction. The storage region 16 is a region in which the same dopant as the drift region 18 is stored at a higher concentration than in the drift region 18. The doping concentration in the storage region 16 is higher than the doping concentration in the drift region 18. In this example, the storage region 16 is N-type. By providing the storage region 16, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced.

[0091] Above the base region 14, a first-conductivity type emitter region 12 is provided in contact with the front surface 21 of the semiconductor substrate 10. In this example, the emitter region 12 is of the N+ type. The emitter region 12 is provided in contact with the gate trench portion 40. The doping concentration of the emitter region 12 is higher than that of the drift region 18. Examples of dopants for the emitter region 12 include arsenic (As), phosphorus (P), and antimony (Sb).

[0092] A buffer region 20 of a first conductivity type may be provided below the drift region 18. In this example, the buffer region 20 is of the N-type. A collector region 22 of a second conductivity type may be provided below the buffer region 20. In this example, the collector region 22 is of the P+ type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer to prevent the depletion layer extending from the lower surface of the base region 14 from reaching the collector region 22.

[0093] In this example, the gate trench 40 and dummy trench 30 are provided so as to penetrate the base region 14 and the storage region 16 from the front surface 21 of the semiconductor substrate 10 to reach the drift region 18. The statement that the trench penetrates the doping region is not limited to cases where the doping region is formed first and then the trench is formed. Cases where the doping region is formed between the trenches after the trenches have been formed are also included in cases where the trench penetrates the doping region.

[0094] The gate trench portion 40 has a gate trench, a gate insulating film, and a gate conductive portion provided on the front surface 21 of the semiconductor substrate 10. The gate insulating film is provided covering the inner wall of the gate trench. The gate insulating film may be formed of an oxide film or a nitride film. The gate conductive portion is provided so as to fill the inside of the gate trench, beyond the gate insulating film. The upper surface of the gate conductive portion may be in the same XY plane as the front surface 21 of the semiconductor substrate 10. The gate insulating film insulates the gate conductive portion from the semiconductor substrate 10. The gate conductive portion may be formed of polysilicon doped with impurities or the like.

[0095] The gate conductive portion may be provided to a position deeper than the lower end of the base region 14 in the depth direction (Z-axis direction). The gate trench portion 40 is covered by an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion, a channel formed by an electron inversion layer is formed on the surface layer of the interface in contact with the gate trench in the base region 14.

[0096] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the XZ cross-section. The dummy trench portion 30 has a dummy trench, a dummy insulating film, and a dummy conductive portion provided on the front surface 21 of the semiconductor substrate 10. The dummy insulating film is provided covering the inner wall of the dummy trench. The dummy insulating film may be formed of an oxide film or a nitride film. The dummy conductive portion is provided so as to be embedded inside the dummy trench, beyond the dummy insulating film. The upper surface of the dummy conductive portion may be in the same XY plane as the front surface 21 of the semiconductor substrate 10. The dummy insulating film insulates the dummy conductive portion from the semiconductor substrate 10. The dummy conductive portion may be formed of the same material as the gate conductive portion.

[0097] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. The lower ends of the dummy trench portion 30 and the gate trench portion 40 may be curved in a convex shape towards the bottom (curved in the XZ cross section).

[0098] Figure 4 is an enlarged view of region R2 in Figure 1. Region R2 shows an example of the structure near the first emitter bridge section 53-1. In Figure 4, the main regions 52-1 and 52-2, the first gate metal section 49-1, the first gate runner 48-1, the connecting section 25, the gate trench section 40, and the dummy trench section 30 are shown, with other components omitted. In Figure 4, the gate trench section 40 is denoted by the symbol G, and the dummy trench section 30 is denoted by the symbol E. Note that the structure near the second emitter bridge section 53-2 can be applied by substituting the main regions 52-1 and 52-2, the first gate metal section 49-1, and the first gate runner 48-1 in Figure 4 with the main regions 52-2 and 52-3, the second gate metal section 49-2, and the second gate runner 48-2, so the explanation is omitted here.

[0099] In this example, the main regions 52-1 and 52-2 are spaced apart in the Y-axis direction and connected by the first emitter bridge 53-1. In this example, the first gate metal portion 49-1 and the first gate runner 48-1 extend in the X-axis direction between the main regions 52-1 and 52-2. In Figure 4, the first gate runner 48-1 is shown by a dotted line. The first gate runner 48-1 is located below the first gate metal portion 49-1 and is connected to the first gate metal portion 49-1 by a contact hole 55.

[0100] In this example, the first gate runner 48-1 is located below the first emitter bridge section 53-1. In other words, the first gate runner 48-1 in this example extends in the X-axis direction from one end of the outer peripheral gate runner 48-0, which extends in the Y-axis direction, to the other end.

[0101] In this example, the first gate metal portion 49-1 is provided spaced apart from the main regions 52-1 and 52-2. The first gate metal portion 49-1 in this example extends in the X-axis direction from the outer peripheral gate metal portion 49-0 which extends in the Y-axis direction, and terminates without contacting the first emitter bridge portion 53-1. In other words, in a top view of the semiconductor substrate 10, the first gate metal portion 49-1 in this example is provided spaced apart from the region enclosed by the first main region 52-1, the second main region 52-2, and the first emitter bridge portion 53-1. The first emitter bridge portion 53-1 is sandwiched between the first gate metal portions 49-1 in the X-axis direction.

[0102] The gate trench portion 40 and the dummy trench portion 30 have an elongated length in the Y-axis direction when viewed from above the semiconductor substrate 10. In other words, the gate trench portion 40 and the dummy trench portion 30 are provided extending in the Y-axis direction. The gate trench portion 40 and the dummy trench portion 30 may have a straight portion parallel to the Y-axis direction.

[0103] The gate trench section 40 and the dummy trench section 30 are arranged at predetermined intervals in the X-axis direction. Note that the arrangement pattern of the gate trench section 40 and the dummy trench section 30 is not limited to the example shown in Figure 4.

[0104] Each trench section may have two straight sections connected at the ends of a curved tip. In the example shown in Figure 4, the dummy trench section 30 has two straight sections and one tip. In this example, the dummy trench section 30 does not overlap with the first gate runner 48-1 when viewed from above on the semiconductor substrate 10. In other words, in this example, each dummy trench section 30 is positioned to overlap with one of the first main region 52-1, the second main region 52-2, and the third main region 52-3 when viewed from above on the semiconductor substrate 10, and does not span multiple main regions. In this example, the dummy trench section 30 is connected to the emitter electrode 52 via connection sections 25 provided at the tip ends at both ends in the Y-axis direction. The connection sections 25 may be made of polysilicon doped with impurities or the like. By providing the connection sections 25, the dummy trench section 30 and the emitter electrode 52 can be easily connected.

[0105] The gate trench portion 40 intersects with the first gate runner 48-1 when viewed from above on the semiconductor substrate 10. In other words, in this example, the gate trench portion 40 extends beyond the first gate runner 48-1 and in the Y-axis direction from the first main region 52-1 to the second main region 52-2 when viewed from above on the semiconductor substrate 10. The gate trench portion 40 in this example is also provided below the first emitter bridge portion 53-1.

[0106] In this example, the gate trench portion 40 extends in the Y-axis direction from one end of the outer periphery gate runner 48-0, which extends in the X-axis direction, to the other end. Although only the straight portion of the gate trench portion 40 is shown in Figure 4, the ends of the straight portion may be connected by curved tip portions. In this example, the gate trench portion 40 is connected to the gate runner portion 48 in the region that overlaps with the gate runner portion 48 when viewed from above the semiconductor substrate 10.

[0107] In other examples, the gate trench portion 40 may be positioned overlapping with one of the first main region 52-1, the second main region 52-2, and the third main region 52-3 when viewed from above the semiconductor substrate 10, and may not span multiple main regions. In this case, the gate trench portion 40 provided below the first main region 52-1 extends in the Y-axis direction from the outer peripheral gate runner 48-0 on the positive Y-axis side (end side 102-2 side) to the first gate runner 48-1, the gate trench portion 40 provided below the second main region 52-2 extends in the Y-axis direction from the first gate runner 48-1 to the second gate runner 48-2, and the gate trench portion 40 provided below the third main region 52-3 extends in the Y-axis direction from the second gate runner 48-2 to the outer peripheral gate runner 48-0 on the negative Y-axis side (end side 102-4 side).

[0108] Figure 5 shows an example of the b-b' cross section in Figure 4. The b-b' cross section is the YZ plane passing through the first gate runner 48-1 and the first gate metal part 49-1 between the first main region 52-1 and the second main region 52-2.

[0109] In this example, the interlayer insulating film 38 is provided above the front surface 21 of the semiconductor substrate 10. In this example, the first gate metal portion 49-1 is connected to the first gate runner 48-1 by a contact hole 55 provided in the interlayer insulating film 38.

[0110] In this example, the first emitter bridge portion 53-1 is provided spaced apart from the first gate metal portion 49-1. The width of the first emitter bridge portion 53-1 in the X-axis direction may be 150 μm or more and 500 μm or less. In this example, the first gate runner 48-1 is provided extending in the X-axis direction below the first gate metal portion 49-1 and the first emitter bridge portion 53-1. In the gate wiring from the gate pad 50 to the gate trench portion 40 provided below the first emitter bridge portion 53-1, the proportion of gate wiring that does not include the gate metal layer 49 (gate wiring that includes only the first gate runner 48-1) is higher than the wiring path from the gate pad 50 to the gate trench portion 40 provided below the first gate metal portion 49-1. Since the resistance of the first gate runner 48-1 is higher than the resistance of the first gate metal part 49-1, the gate resistance component of the entire gate wiring increases in the gate trench section 40 located below the first emitter bridge section 53-1, and the parasitic resistance increases.

[0111] Figure 6 is a top view showing an example of a semiconductor device 1100 according to a comparative example. The semiconductor device 1100 according to the comparative example differs from the semiconductor device 100 in Figure 1 in that a first emitter bridge portion 53-1 and a second emitter bridge portion 53-1 are provided along the virtual center line Xc of the active portion 120 in the X-axis direction. The other structures of the semiconductor device 1100 are the same as those of the semiconductor device 100 described in Figures 1 to 5, so their description is omitted here.

[0112] The first emitter bridge portion 53-1 and the second emitter bridge portion 53-1 of the semiconductor device 1100 are located on the same virtual center line Xc in the X-axis direction. Therefore, in a top view of the semiconductor substrate 10, the gate trench portion 40 that overlaps with the first emitter bridge portion 53-1 also overlaps with the second emitter bridge portion 53-1. In a top view of the semiconductor substrate 10, only a high-resistance gate runner portion 48 is provided in the region where the emitter bridge portion 53 is located, and no gate metal layer 49 is provided. As a result, the parasitic resistance of the gate trench portion 40 that overlaps this region becomes high. In particular, in a top view of the semiconductor substrate 10, the parasitic resistance in the section between the first emitter bridge portion 53-1 and the second emitter bridge portion 53-1 becomes high, which may lead to a decrease in latch-up tolerance and RBSOA.

[0113] In contrast, in the semiconductor device 100 according to the embodiment, the gate trench portion 40 provided below the first emitter bridge portion 53-1 is different from the gate trench portion 40 provided below the second emitter bridge portion 53-2. That is, in the semiconductor device 100, the gate trench portion 40 below the first emitter bridge portion 53-1 is not provided below the second emitter bridge portion 53-2. In the semiconductor device 100, at least one end of the gate trench portion 40 in the Y-axis direction is provided below the gate metal layer 49, and the gate trench portion 40 is provided below at least one of the first gate metal portion 49-1 and the second gate metal portion 49-2. Therefore, in each gate trench portion 40, when viewed from above on the semiconductor substrate 10, there is no section sandwiched between the first emitter bridge portion 53-1 and the second emitter bridge portion 53-1, and variations in parasitic resistance can be suppressed.

[0114] Figure 7 is a graph showing the relationship between the position of the emitter bridge portion 53 and the parasitic resistance value in the gate trench portion 40. In Figure 7, the horizontal axis represents the distance in the X-axis direction as a percentage from a reference position Xo, which is the position of the gate pad 50 side end of the active portion 120, with the reference position Xo being 0 and the opposite end (end side 102-3 side) of the active portion 120 being 100. The vertical axis represents the parasitic resistance value [Ω] in the gate trench portion 40. In Figure 7, the parasitic resistance value in the gate trench portion 40 of the semiconductor device 100 according to the embodiment is plotted as a black circle, and the parasitic resistance value in the gate trench portion 40 of the semiconductor device 1100 according to the comparative example is plotted as a black square.

[0115] In the semiconductor device 100 according to the embodiment, the parasitic resistance value in the gate trench portion 40 increases at two locations spanning the first emitter bridge portion 53-1 and the second emitter bridge portion 53-2. On the other hand, in the semiconductor device 1100 according to the comparative example, the parasitic resistance value in the gate trench portion 40 increases at only one location spanning the first emitter bridge portion 53-1 and the second emitter bridge portion 53-2, but the magnitude of this increase is greater than the magnitude of the increase in the semiconductor device 100.

[0116] Thus, in the semiconductor device 100 according to this embodiment, by providing the first emitter bridge portion 53-1 and the second emitter bridge portion 53-2 at different positions in the X-axis direction, the gate trench portion 40 is either not provided below the emitter bridge portion 53, or is provided below only one of the first emitter bridge portion 53-1 and the second emitter bridge portion 53-2. This suppresses a steep increase in parasitic resistance, distributes the high-resistance portion throughout the semiconductor device 100, and suppresses a decrease in switching withstand capability.

[0117] Furthermore, in the semiconductor device 100 according to the embodiment, the first emitter bridge portion 53-1 and the second emitter bridge portion 53-2 are offset to opposite sides of each other with respect to the virtual center line Xc of the active portion 120, thereby reducing variations in the emitter potential in the X-axis direction.

[0118] Figure 8 is a top view showing another example of the semiconductor device 100 according to the embodiment. Figure 8 differs from Figure 1 in that the gate pad 50 is located on the positive side of the Y-axis (side of edge 102-2) relative to the active part 120. The other structures are the same as those of the semiconductor device 100 described in Figures 1 to 5, so their description is omitted here.

[0119] In this example, by arranging the first emitter bridge section 53-1 and the second emitter bridge section 53-2 in the same manner as in Figures 1 to 5, the same effect as the semiconductor device 100 described in Figures 1 to 5 can be obtained, regardless of the position of the gate pad 50.

[0120] Figure 9 is a top view showing another example of the semiconductor device 100 according to the embodiment. Figure 9 differs from Figure 1 in that the gate pad 50 is provided close to the corner region of the active part 120, that is, it is provided on the negative side of the Y-axis direction (end side 102-4 side) of the virtual center line Yc of the active part 120 in the Y-axis direction. The other structures are the same as those of the semiconductor device 100 described in Figures 1 to 5, so their description is omitted here.

[0121] In this example, by arranging the first emitter bridge section 53-1 and the second emitter bridge section 53-2 in the same manner as in Figures 1 to 5, the same effect as the semiconductor device 100 described in Figures 1 to 5 can be obtained, regardless of the position of the gate pad 50. In Figure 9, the gate pad 50 is located on the negative side of the Y-axis direction (side of edge 102-4) relative to the virtual center line Yc, but the same effect can be obtained if it is located on the positive side of the Y-axis direction (side of edge 102-2) relative to the virtual center line Yc.

[0122] Although the invention has been described using embodiments, the technical scope of the present invention is not limited to the scope described in the embodiments above. It will be apparent to those skilled in the art that various modifications or improvements can be made to the embodiments described above. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0123] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before" or "prior to," and can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc., for convenience, this does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0124] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 18...Drift region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 29...Straight portion, 30...Dummy trench portion, 31...Tip portion, 38...Interlayer insulating film, 39...Straight portion, 40...Gate trench portion, 41...Tip portion, 48...Gate runner portion, 48-0...Outer periphery gate runner, 48-1...First gate runner, 48-2...Second gate runner, 49...Gate metal layer 49-0... Outer gate metal part, 49-1... First gate metal part, 49-2... Second gate metal part, 50... Gate pad, 52... Emitter electrode, 52-1... First main region, 52-2... Second main region, 52-3... Third main region, 53... Emitter bridge part, 53-1... First emitter bridge part, 53-2... Second emitter bridge part, 54... Contact hole, 55... Contact hole, 56... Contact hole, 100... Semiconductor device, 102... Edge, 120... Active part, 120-1... First active region, 120-2... Second active region, 120-3... Third active region, 1100... Semiconductor device

Claims

1. A first-conductivity drift region provided on the semiconductor substrate, A second conductivity type base region is provided above the drift region, An emitter region of a first conductivity type is provided above the drift region and has a doping concentration higher than that of the drift region, A plurality of contact regions of a second conductivity type, provided above the drift region and having a higher doping concentration than the base region, On the front surface of the semiconductor substrate, a plurality of trench portions are provided, which are extended in a predetermined trench extension direction. An emitter electrode provided above the semiconductor substrate, having a first main region, a second main region, and a third main region, A gate pad provided above the semiconductor substrate, The gate pad and the gate metal layer electrically connected, The gate metal layer and the gate runner portion electrically connected, Equipped with, The plurality of trench sections have a plurality of gate trench sections, The emitter electrode is, A first emitter bridge section connecting the first main region and the second main region, A second emitter bridge section connecting the second main region and the third main region, It has, Below the first emitter bridge section, a gate trench section different from the gate trench section provided below the second emitter bridge section is provided. Semiconductor equipment.

2. The gate trench below the first emitter bridge is not provided below the second emitter bridge. The semiconductor device according to claim 1.

3. The first emitter bridge portion is positioned differently from the second emitter bridge portion in the trench arrangement direction. The semiconductor device according to claim 1.

4. The gate metal layer is A first gate metal portion extending between the first main region and the second main region, A second gate metal portion extending between the second main region and the third main region, It has, The plurality of gate trenches are provided below at least one of the first gate metal portion and the second gate metal portion. The semiconductor device according to claim 1.

5. The gate runner section is, A first gate runner extending in the trench arrangement direction between the first main region and the second main region, A second gate runner extending in the trench arrangement direction between the second main region and the third main region, has The semiconductor device according to claim 1.

6. The first emitter bridge portion is sandwiched by the gate metal layers in the trench arrangement direction, The second emitter bridge portion is sandwiched between the gate metal layers in the trench arrangement direction. The semiconductor device according to claim 5.

7. The first gate runner is located below the first emitter bridge section. The second gate runner is located below the second emitter bridge section. The semiconductor device according to claim 5.

8. At least one end of the plurality of gate trenches in the trench extension direction is provided below the gate metal layer. The semiconductor device according to claim 6.

9. The gate pad is located on the edge side of the semiconductor substrate, relative to the active portion, in the trench arrangement direction. The semiconductor device according to claim 1.

10. The first emitter bridge portion is provided closer to the gate pad than the virtual center line of the active portion in the trench arrangement direction, The second emitter bridge section is provided at a distance from the gate pad from the virtual center line. The semiconductor device according to claim 9.

11. In the trench arrangement direction, the distance between the first emitter bridge portion and the gate pad-side end of the active portion is 2.5% or more and 97.5% or less of the distance between the second emitter bridge portion and the gate pad-side end of the active portion. The semiconductor device according to claim 10.

12. The active portion is divided into three equal parts in the trench arrangement direction, forming a first active region, a second active region, and a third active region, A first active region adjacent to the gate pad, A second active region that is spaced further away from the gate pad than the first active region, A third active region located further away from the gate pad than the second active region, Equipped with, The first emitter bridge portion and the second emitter bridge portion are provided in the second active region. The semiconductor device according to claim 10.

13. In the trench arrangement direction, the distance between the first emitter bridge portion and the second emitter bridge portion is 150 μm or more and 500 μm or less. The semiconductor device according to claim 10.

14. In the trench arrangement direction, the distance between the first emitter bridge portion and the virtual centerline is equal to the distance between the second emitter bridge portion and the virtual centerline. The semiconductor device according to claim 10.

15. In the trench arrangement direction, the distance between the first emitter bridge portion and the gate pad-side end of the active portion is 40% or more and 60% or less of the distance between the second emitter bridge portion and the gate pad-side end of the active portion. The semiconductor device according to claim 10.

16. The gate pad is located on the edge side of the semiconductor substrate, relative to the active portion, in the trench extension direction. The semiconductor device according to claim 1.

17. The gate pad is located on the edge side of the semiconductor substrate, relative to the virtual center line of the active portion in the trench extension direction. The semiconductor device according to claim 9.

Images