Semiconductor module

Abstract

This invention provides a semiconductor module with excellent thermal conductivity and heat dissipation characteristics, enabling suppression of signal delay and reduced power consumption. [Solution] The semiconductor module includes a cube chip comprising a plurality of IC chips stacked along the first direction parallel to a plane formed by a second direction perpendicular to the first direction and a third direction perpendicular to the second direction, and a first metal wiring layer electrically connected to the stack chip, a semiconductor chip capable of controlling the cube chip, and a first bump portion electrically connecting the semiconductor chip and the first metal wiring layer, wherein the cube chip is vertically mounted on the first bump portion along the third direction.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor module.

Background Art

[0002] In recent years, the amount of data communication in computers such as data centers has been increasing. In addition, the power consumption of computers is rising sharply due to the increase in the amount of data communication. For example, a computer includes a plurality of logic chips and a plurality of memory chips electrically connected to the plurality of logic chips. The logic chip is, for example, an IC (Integrated Circuit) chip on which a logic circuit is mounted, and the memory chip is an IC chip on which a memory circuit is mounted. For example, stacking a logic chip and a memory chip for three-dimensional mounting leads to a reduction in the distance between the logic chip and the memory chip, and is one of the effective solutions for reducing the power consumption of computers.

[0003] As an example of a three-dimensional mounting method, Patent Documents 1 to 3 disclose a mounting method for a semiconductor module in which a structure (vertically stacked cube chip) formed by stacking a plurality of memory chips such that the plurality of memory chips are parallel to a substrate or a logic chip is arranged on the substrate or the logic chip, and Patent Document 4 discloses a mounting method for a semiconductor module in which a structure (horizontally stacked cube chip) formed by stacking a plurality of memory chips such that the plurality of memory chips are perpendicular to a substrate or a logic chip is vertically installed (stood upright) on the substrate or the logic chip.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

[0005] For example, a semiconductor module includes a large-scale DRAM (Dynamic Random Access Memory) system such as HBM (High Bandwidth Memory), logic chips such as a CPU (Central Processing Unit), and an interposer (e.g., a silicon interposer) capable of high-density interconnection (HDI). For example, the DRAM system and logic chips are mounted in 2.5 dimensions on the interposer. As the scale of the DRAM increases, the area of ​​the interposer increases, and the cost required to manufacture the semiconductor module increases.

[0006] Furthermore, for example, the semiconductor modules described in Patent Documents 1 to 3 include a configuration in which multiple IC chips are stacked parallel to the stacking direction. As a result, the oxide film contained in the stacked memory chips increases the thermal resistance of the semiconductor module. For example, when the thermal resistance of a semiconductor module increases, the thermal conductivity of the semiconductor module decreases, making it difficult for the semiconductor module to dissipate heat from the IC chips. As a result, the temperature of the semiconductor module rises, which may cause malfunctions in the semiconductor module due to the temperature rise. In order to suppress malfunctions in the semiconductor module, it is necessary to suppress the temperature rise of the semiconductor module to a temperature range in which the semiconductor module operates normally. Therefore, the number of stacked chips in each of the semiconductor modules described in Patent Documents 1 to 3 is limited so as to suppress the thermal resistance of the semiconductor module.

[0007] Furthermore, for example, in the semiconductor modules described in Patent Documents 1 to 3, the logic chip (including the memory controller) and the multiple memory chips are mounted on a package substrate, so the logic chip is connected to the multiple memory chips via the package substrate. As a result, the length of the wiring for connecting the logic chip and the multiple memory chips increases, and the parasitic capacitance between the package substrate, the logic chip, and the multiple memory chips also increases. Consequently, for example, the power required for transmitting and receiving signals between the logic chip and the multiple memory chips increases, the energy loss in transmitting and receiving signals between the logic chip and the multiple memory chips increases, and the delay in transmitting and receiving signals between the logic chip and the multiple memory chips increases. As a result, the semiconductor modules described in Patent Documents 1 to 3 have difficulty transmitting high-speed signals (high-frequency signals) and their performance for processing signals deteriorates.

[0008] Furthermore, for example, in the semiconductor module described in Patent Document 4, the stacked memory chips are connected to the logic chips via wireless communication, but the multiple logic chips are connected via a package substrate. As a result, similar to the semiconductor modules described in Patent Documents 1 to 3, the semiconductor module described in Patent Document 4 suffers from increased power consumption, increased energy loss, and increased signal delay due to signal transmission between multiple logic chips, making it difficult to transmit high-speed signals (high-frequency signals) and degrading the performance for processing signals.

[0009] In view of these problems, one embodiment of the present invention aims to provide a semiconductor module that has good thermal conductivity and excellent heat dissipation characteristics, and that can suppress signal delay and reduce power consumption. [Means for solving the problem]

[0010] A semiconductor module according to one embodiment of the present invention comprises a cube chip including a stacked chip arranged parallel to a plane formed by a second direction perpendicular to the first direction and a third direction perpendicular to the second direction, a first metal wiring layer electrically connected to the stacked chip, a semiconductor chip capable of controlling the cube chip, and a first bump portion electrically connecting the semiconductor chip and the first metal wiring layer, wherein the cube chip is vertically mounted on the first bump portion along the third direction.

[0011] The first metal wiring layer may be a rewiring layer having the function of rearranging the positions of wiring on the laminated chip that are exposed from the side of the cube chip.

[0012] The first bump portion contains solder, and the first metal wiring layer may be a UBM layer that has the function of suppressing the diffusion of the solder.

[0013] The first bump portion includes solder, and the first metal wiring layer may include a rewiring layer that has the function of rearranging the position of wiring on the laminated chip that is exposed from the side surface of the cube chip, and a UBM layer that has the function of suppressing the diffusion of the solder.

[0014] The laminated chip has a first surface which is one of the outermost surfaces with the third direction as its normal vector, a second surface which is the other outermost surface with the third direction as its normal vector and is opposite to the first surface, a third surface which is one of the outermost surfaces with the second direction as its normal vector, a fourth surface which is the other outermost surface with the second direction as its normal vector and is opposite to the third surface, a fifth surface which is one of the outermost surfaces with the first direction as its normal vector, and a sixth surface which is the other outermost surface with the first direction as its normal vector and is opposite to the fifth surface, and the metal wiring layer has a plurality of wirings which may be in contact with the first surface.

[0015] Each of the plurality of IC chips has a plurality of electrodes exposed on the first surface, the plurality of electrodes are electrically connected to the first bump portion, and some of the plurality of electrodes may be supplied with voltage and control signals for driving the cube chip.

[0016] The material further includes a second metal wiring layer in contact with the third surface and a third metal wiring layer in contact with the fourth surface, wherein each of the second and third metal wiring layers may contain a plurality of wirings.

[0017] Each of the plurality of IC chips has a first electrode exposed on the third surface, a second electrode exposed on the fourth surface, and a third electrode exposed on the first surface, wherein the first electrode is electrically connected to a plurality of wirings of the third metal wiring layer using a plurality of wirings of the first metal wiring layer, the second electrode is electrically connected to a plurality of wirings of the third metal wiring layer using a plurality of wirings of the second metal wiring layer, and the plurality of wirings of the third metal wiring layer may be electrically connected to the first bump portion.

[0018] The plurality of IC chips include a first memory chip on which memory is formed, a first computing die electrically connected to the first memory chip and capable of controlling the first memory chip, a second memory chip on which memory is formed, and a second computing die electrically connected to the second memory chip and capable of controlling the second memory chip, wherein the first computing die may be in contact with the fifth surface, and the second computing die may be in contact with the sixth surface.

[0019] The semiconductor chip includes a third computing die capable of controlling the cube chip, and an input / output die electrically connected to the third computing die, wherein the third computing die has a plurality of circuits, and the input / output die has a plurality of network routers, and the cube chip and the plurality of circuits may be electrically connected using the plurality of network routers.

[0020] Each of the third computing die and the input / output die may have a transistor layer including a substrate, a through electrode penetrating the substrate, an electrode exposed on the substrate, and a plurality of transistors, and a wiring layer laminated on the transistor layer and including an electrode exposed on a surface, wherein the electrode exposed on the surface of the third computing die and the through electrode of the input / output die are electrically connected, and the through electrode of the third computing die and the electrode exposed on the substrate are electrically connected to the first bump portion.

[0021] The cube chip may have a first input / output interface, the plurality of circuits may have a second input / output interface, the first input / output interface may include a protection circuit electrically connected to the first bump portion, and any one of a comparator, a hysteresis comparator, and an injection-locked oscillator electrically connected to the protection circuit, and the second input / output interface may include a protection circuit electrically connected to the first bump portion, and a comparator electrically connected to the protection circuit.

[0022] The semiconductor device may further include a heat sink, and the heat sink may be in contact with the second surface, a surface opposite to the fifth surface in contact with the first computing die, and a surface opposite to the sixth surface in contact with the second computing die.

[0023] Each of the third computing die and the input / output die may have a transistor layer including a substrate, a through electrode penetrating the substrate, an electrode exposed on the substrate, and a plurality of transistors, and a wiring layer laminated on the transistor layer and including an electrode exposed on a surface, wherein the electrode exposed on the surface of the third computing die and the electrode exposed on the surface of the input / output die are electrically connected, and the through electrode of the third computing die and the electrode exposed on the substrate are electrically connected to the first bump portion.

[0024] The third computing die and the input / output die further include a package substrate, the side opposite to the side on which the first bump portion of the semiconductor chip is electrically connected, and a second bump portion electrically connected between the package substrate and the semiconductor chip, and each of the third computing die and the input / output die includes a substrate, a transistor layer including through electrodes penetrating the substrate, electrodes exposed on the substrate, and a plurality of transistors, and a wiring layer laminated on the transistor layer and including electrodes exposed on the surface, and the third computing die further includes a lower wiring layer laminated on the side of the transistor layer opposite to the side on which the wiring layer is laminated and capable of supplying power, and electrodes exposed on the surface of the input / output die and electrodes exposed on the surface of the third computing die are electrically connected, the through electrodes of the input / output die and electrodes exposed on the substrate are electrically connected to the first bump portion, and electrodes exposed on the lower wiring layer are electrically connected to the second bump portion.

[0025] The semiconductor chip further comprises a package substrate, the side opposite to the side on which the first bump portion of the semiconductor chip is electrically connected, and a second bump portion electrically connected between the package substrate and the semiconductor chip, wherein the semiconductor chip includes a transistor layer including a substrate, through-electrodes penetrating the substrate, electrodes exposed on the substrate, and a plurality of transistors, a wiring layer laminated on the transistor layer and including electrodes exposed on its surface, a lower wiring layer laminated on the side of the transistor layer opposite to the side on which the wiring layer is laminated and capable of supplying power, a plurality of circuits capable of controlling the cube chip composed of the transistor layer, the wiring layer, and the lower wiring layer, and a plurality of network routers electrically connecting the cube chip and the plurality of circuits, wherein the through-electrodes of the semiconductor chip and the electrodes exposed on the substrate may be electrically connected to the first bump portion, and the electrodes exposed on the lower wiring layer may be electrically connected to the second bump portion.

[0026] The plurality of IC chips include a first memory chip having a plurality of electrodes exposed on a substrate and on which a memory is formed, and a first computing die having a plurality of electrodes electrically connected to the plurality of electrodes exposed on the substrate and capable of controlling the first memory chip, wherein the first computing die may be in contact with the sixth surface.

[0027] The plurality of IC chips include a first memory chip having a first inductor and having a memory formed thereon, and a first computing die having a second inductor that can communicate with the first inductor and can control the first memory chip, wherein the first computing die may be in contact with the sixth surface.

[0028] The plurality of wirings in the first metal wiring layer include first wirings exposed on the first metal wiring layer, and the plurality of wirings in the second metal wiring layer include second wirings exposed on the second metal wiring layer, and may further include: a first conductive film electrically connected to the first wirings and in contact with the surface of the first metal wiring layer on which the first wirings are exposed; a second conductive film electrically connected to the second wirings and in contact with the surface of the second metal wiring layer on which the second wirings are exposed; a first voltage supply unit in contact with the first conductive film and capable of supplying voltage to the first conductive film; and a second voltage supply unit in contact with the second conductive film and capable of supplying voltage to the second conductive film.

[0029] The plurality of IC chips further include a first heat spreader capable of diffusing heat and supplying a power supply voltage, a second heat spreader capable of diffusing heat and supplying a reference voltage, a first conductive layer electrically connected to the first heat spreader, and a second conductive layer electrically connected to the second heat spreader, wherein each of the plurality of IC chips may further include a fourth electrode exposed on the second surface and electrically connected to the first conductive layer, and a fifth electrode exposed on the second surface and electrically connected to the second conductive layer.

[0030] The plurality of IC chips further includes a first heat spreader capable of diffusing heat, a second heat spreader capable of diffusing heat, a first conductive layer electrically connected to the first heat spreader, a second conductive layer electrically connected to the second heat spreader, a space formed by the first heat spreader, the second heat spreader, the first conductive layer, the second conductive layer, and the cube chip, wherein each of the plurality of IC chips further has a plurality of fourth electrodes exposed on the second surface, the first conductive layer is electrically connected to the plurality of fourth electrodes, and the second conductive layer may be in contact with the surface opposite to the fifth surface to which the first computing die is in contact, and the surface opposite to the sixth surface to which the second computing die is in contact.

[0031] The semiconductor chip and the cube chip are arranged along the first direction and further comprise an input / output die electrically connected upward along the third direction using the first bump portion, a package substrate, and a second bump portion electrically connected between the input / output die and the package substrate, wherein each of the plurality of IC chips may be an IC chip on which memory is formed.

[0032] The present invention further includes a memory controller electrically connected between the semiconductor chip and the first bump portion, wherein the memory controller is electrically connected to the semiconductor chip using a third bump portion, electrically connected to the input / output die using the first bump portion, and configured to control the cube chip.

[0033] The semiconductor chip and the cube chip are arranged along the first direction and electrically connected upward along the third direction using the first bump portion of the package substrate; a conductive layer is provided on the opposite side of the package substrate along the third direction and is connected to the semiconductor chip and the cube chip; a thermal conductive sheet is electrically connected to the conductive layer; a lid is provided on the package substrate and is connected to the thermal conductive sheet, covers the semiconductor chip and the cube chip, and is a sealing structure that fixes the semiconductor chip and the cube chip to the package substrate; each of the plurality of IC chips is an IC chip including a DRAM; and the semiconductor chip has an input / output interface. The package substrate comprises a CPU electrically connected to a first input / output die including a face, a GPU electrically connected to a second input / output die including an input / output interface, and a support substrate supporting the CPU and the GPU, wherein the package substrate has a plurality of electrodes exposed on its surface and a multilayer wiring structure electrically connected to the plurality of electrodes, the semiconductor chip is electrically connected to a plurality of electrodes exposed on the package substrate using the plurality of electrodes exposed on the first input / output die and the second input / output die, and the cube chip may be electrically connected to the semiconductor chip by the first bump portion, the plurality of electrodes exposed on its surface, the multilayer wiring structure, and the plurality of electrodes exposed on the first input / output die and the second input / output die.

[0034] Each of the aforementioned plurality of IC chips may be an IC chip having multiple memory banks and including DRAM. [Brief explanation of the drawing]

[0035] [Figure 1] This is a perspective view showing the configuration of a semiconductor module according to one embodiment of the present invention. [Figure 2] This is an end view showing the cross-sectional structure of the end of a semiconductor module along the line A1-A2 shown in Figure 1. [Figure 3] Figure 2 is an end view showing the configuration of the metal wiring layer. [Figure 4]This is an end view showing the cross-sectional structure of the end of a semiconductor module along the line B1-B2 shown in Figure 1. [Figure 5] Figure 4 is an end view showing the configuration around the first face of the cube chip. [Figure 6] This is a block diagram showing the configuration of a semiconductor module according to one embodiment of the present invention. [Figure 7] This is a block diagram showing an example of the configuration of an input / output (IO) interface according to the first embodiment of the present invention. [Figure 8] This is a block diagram showing an example of the configuration of an input / output (IO) interface according to the first embodiment of the present invention. [Figure 9] This is a block diagram showing an example of the configuration of an input / output (IO) interface according to the first embodiment of the present invention. [Figure 10] This is a block diagram showing an example of the configuration of an IC chip according to the first embodiment of the present invention. [Figure 11] This is an end view showing the cross-sectional structure of an IC chip end according to the first embodiment of the present invention. [Figure 12] This is an end view showing the end cross-sectional structure of a computing die according to the first embodiment of the present invention. [Figure 13] This is an end view showing the end cross-sectional structure of a computing die according to the first embodiment of the present invention. [Figure 14] This is an end view showing the end cross-sectional structure of an IO die according to the first embodiment of the present invention. [Figure 15] This is a perspective view showing the configuration of a semiconductor module according to one embodiment of the present invention. [Figure 16] Figure 15 is an end view showing the cross-sectional structure of the end of a semiconductor module along the line P1-P2. [Figure 17] This is a perspective view showing the configuration of a semiconductor module according to a second embodiment of the present invention. [Figure 18] Figure 17 is an end view showing the cross-sectional structure of the end of a semiconductor module along the C1-C2 line. [Figure 19]This is an end view showing the cross-sectional structure of the end portion of a semiconductor module according to a third embodiment of the present invention. [Figure 20] Figure 19 is an end view showing the configuration around the first face of the cube chip. [Figure 21] This is a perspective view showing a semiconductor module configuration according to a fourth embodiment of the present invention. [Figure 22] This is an end view showing the end cross-sectional structure of a computing die according to the fourth embodiment of the present invention. [Figure 23] This is a perspective view showing a semiconductor module configuration according to a fifth embodiment of the present invention. [Figure 24] Figure 23 is an end view showing the configuration around the first face of the cube chip. [Figure 25] This is a perspective view showing the semiconductor module configuration according to the sixth embodiment of the present invention. [Figure 26] This is an end view showing the end section structure in an example of a semiconductor module mounting according to the seventh embodiment of the present invention. [Figure 27] This is an end view showing the end cross-sectional structure in an example of a semiconductor module mounting according to the eighth embodiment of the present invention. [Figure 28] This is an end view showing the end cross-sectional structure in an example of a semiconductor module mounting according to the ninth embodiment of the present invention. [Figure 29] This is an end view showing the end cross-sectional structure in an example of a semiconductor module mounting according to the 10th embodiment of the present invention. [Figure 30] This is a perspective view showing the configuration of a semiconductor module according to an 11th embodiment of the present invention. [Figure 31] Figure 30 is an end view showing the cross-sectional structure of the end of a semiconductor module along the E1-E2 line. [Figure 32] This is a perspective view showing the configuration of a semiconductor module according to the 12th embodiment of the present invention. [Figure 33] Figure 32 is an end view showing the cross-sectional structure of the end of a semiconductor module along the F1-F2 line. [Figure 34]This is an end view showing the cross-sectional structure of the end of a semiconductor module along the line G1-G2 shown in Figure 32. [Figure 35] This is a perspective view showing the configuration of a semiconductor module according to the 13th embodiment of the present invention. [Figure 36] Figure 35 is an end view showing the cross-sectional structure of the end of a semiconductor module along the line H1-H2. [Figure 37] Figure 35 is an end view showing the cross-sectional structure of the end of a semiconductor module along the line I1-I2. [Figure 38] This is a perspective view showing the configuration of a semiconductor module according to the 14th embodiment of the present invention. [Figure 39] This is a plan view showing the configuration of a semiconductor module according to the 14th embodiment of the present invention. [Figure 40] Figure 38 is an end view showing the cross-sectional structure of the end of a semiconductor module along the line J1-J2. [Figure 41] This is a perspective view showing the configuration of a semiconductor module according to 15th embodiment of the present invention. [Figure 42] Figure 41 is an end view showing the cross-sectional structure of the end of a semiconductor module along the K1-K2 line. [Figure 43] This is a plan view showing an example of a conventional large-scale DRAM implementation. [Modes for carrying out the invention]

[0036] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described below. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals (or numerals followed by a, b, etc.), and detailed explanations may be omitted as appropriate. Furthermore, the letters "1st," "2nd," etc., attached to each element are convenient indicators used to distinguish each element and have no further meaning unless specifically explained.

[0037] In one embodiment of the present invention, when a member or region is said to be "above (or below)" another member or region, unless otherwise specified, this includes not only the case where it is directly above (or directly below) the other member or region, but also the case where it is above (or below) the other member or region, that is, it also includes the case where another component is included between them above (or below) the other member or region.

[0038] In one embodiment of the present invention, the first direction D1 intersects the second direction D2, and the third direction D3 intersects the first direction D1 and the second direction D2 (the D1D2 plane).

[0039] In one embodiment of the present invention, when the terms "same," "identical," and "consistent" are used, these terms may include design tolerances. Furthermore, in one embodiment of the present invention, when design tolerances are included, the terms "approximately the same," "approximately identical," and "approximately identical" may be used.

[0040] [1. First Embodiment] A semiconductor module 10 according to the first embodiment will be described with reference to Figures 1 to 14. A semiconductor module 10P according to the first embodiment will also be described with reference to Figures 15 and 16, etc.

[0041] [1-1. Overview of Semiconductor Module 10] First, an overview of the semiconductor module 10 will be described with reference to Figures 1 to 5. Figure 1 is a perspective view showing the configuration of the semiconductor module 10. Figure 2 is an end view showing the cross-sectional structure of the end of the semiconductor module 10 along the line A1-A2 shown in Figure 1. Figure 3 is an end view showing the configuration of the metal wiring layer 20B shown in Figure 2. Figure 4 is an end view showing the cross-sectional structure of the end of the semiconductor module 10 along the line B1-B2 shown in Figure 1. Figure 5 is an end view showing the configuration around the first face 146 of the cube chip 100 shown in Figure 4.

[0042] As shown in Figures 1, 2, 3, 4, or 5, the semiconductor module 10 includes a cube chip 100, a semiconductor chip section 300, and a package substrate 500. The semiconductor module 10 may include a bump section 800 that electrically connects the cube chip 100 and the semiconductor chip section 300, and a bump section 400 that electrically connects the semiconductor chip section 300 and the package substrate 500. The bump section 800 includes a plurality of bumps 801, and the bump section 400 includes a plurality of bumps 41.

[0043] As will be described in detail later, the cube chip 100 includes a stacked chip 30 and a plurality of metal wiring layers 20B, 20F, and 20D electrically connected to the stacked chip 30. The stacked chip 30 includes a plurality of IC chips 110 stacked along the first direction D1, parallel to a plane formed by a second direction D2 perpendicular to the first direction D1 and a third direction D3 perpendicular to the second direction D2. For example, the plurality of IC chips 110 include a plurality of junction chips 101, a plurality of SRAM chips 110S, and a plurality of DRAM chips 110D. That is, the plurality of IC chips 110 include a plurality of memory chips that form a memory. The semiconductor chip section 300 also includes a configuration that can control the cube chip 100. The bump section 800 electrically connects the semiconductor chip section 300 and the plurality of metal wiring layers 20B, 20F, and 20D of the cube chip 100. The cube chip 100 is vertically mounted on the bump section 800 along the third direction D3.

[0044] Specifically, the semiconductor module 10 includes cube chips 100 vertically mounted on the bump portion 800 (semiconductor chip portion 300) parallel to the third direction D3 and perpendicular to the first direction D1 and the second direction D2. The configuration in which the cube chips 100 are vertically mounted parallel to the third direction D3 and perpendicular to the first direction D1 and the second direction D2 has lower thermal resistance than a configuration that includes multiple IC chips stacked parallel to the first direction D1 and the second direction D2.

[0045] As a result, the semiconductor module 10 has high thermal conductivity and excellent heat dissipation characteristics, which can suppress malfunctions caused by temperature rise in the semiconductor module. Furthermore, because the semiconductor module 10 has excellent heat dissipation characteristics, the limit on the number of stacked chips within the cube chip 100 is relaxed compared to a configuration that includes multiple IC chips stacked parallel to the first direction D1 and the second direction D2.

[0046] Furthermore, the cube chip 100 is electrically connected to the semiconductor chip section 300 via the bump section 800. That is, each wire within the cube chip 100 is electrically connected to each wire within the semiconductor chip section 300 via the bump section 800. Therefore, multiple signals transmitted through each wire within the cube chip 100 are transmitted to each wire within the semiconductor chip section 300 via the bump section 800, and multiple signals transmitted through each wire within the semiconductor chip section 300 are transmitted to each wire within the cube chip 100 via the bump section 800.

[0047] As a result, the semiconductor module 10 can shorten the length of the wiring used to transmit signals compared to modules in which logic chips and multiple memory chips are mounted on a package substrate, and modules in which signals are transmitted via wireless communication. Therefore, it can suppress increases in wiring resistance and parasitic capacitance, suppress increases in power required for signal transmission and reception, suppress energy loss required for signal transmission and reception, and suppress delays in signal transmission and reception. Thus, the semiconductor module 10 is a module suitable for transmitting high-speed signals (high-frequency signals).

[0048] [1-1-1. Overview of Cube Chip 100 and Bump Section 800] The outlines of the cube chip 100 and bump section 800 will be explained with reference to Figures 1 to 5. Configurations that are the same as or similar to those described in "1-1. Outline of Semiconductor Module 10" will be explained as necessary.

[0049] The cube chip 100 includes a stacked chip 30 and metal wiring layers 20B, 20F, and 20D electrically connected to the stacked chip 30. The cube chip 100 also includes a first outermost surface (first surface 146) and a second outermost surface (second surface 148) opposite to the first outermost surface, which are two outermost surfaces with the third direction D3 as their normal vector; a third outermost surface (third surface 145) and a fourth outermost surface (fourth surface 147) opposite to the third outermost surface, which are two outermost surfaces parallel to the third direction D3 and the first direction D1 and with the second direction D2 as their normal vector; and a fifth outermost surface (fifth surface 142) and a sixth outermost surface (sixth surface 144) opposite to the fifth outermost surface, which are two outermost surfaces parallel to the third direction D3 and the second direction D2 and with the first direction D1 as their normal vector.

[0050] The stacked chip 30 includes a first outermost surface (first surface 46) and a second outermost surface (second surface 48) opposite to the first outermost surface, which are two outermost surfaces with the third direction D3 as their normal vector; a third outermost surface (third surface 45) and a fourth outermost surface (fourth surface 47) opposite to the third outermost surface, which are two outermost surfaces parallel to the third direction D3 and the first direction D1 and with the second direction D2 as their normal vector; and a fifth outermost surface (fifth surface 42) and a sixth outermost surface (sixth surface 44) opposite to the fifth outermost surface, which are two outermost surfaces parallel to the third direction D3 and the second direction D2 and with the first direction D1 as their normal vector.

[0051] Furthermore, the first face 46, second face 48, third face 45, fourth face 47, fifth face 42, and sixth face 44 of the stacked chip 30 are parallel to the first face 146, second face 148, third face 145, fourth face 147, fifth face 142, and sixth face 144 of the cube chip 100. For example, the first face 46 is parallel to the first face 146, and the second face 48 is parallel to the second face 148. The third faces 45 to the sixth face 44 and the third faces 145 to the sixth face 144 are parallel to their respective faces, similar to the first face 46 and the first face 146, and the second face 48 and the second face 148. The first face 146 and the first face 46 may be referred to as the bottom face. The second face 148 and the second face 48 may be referred to as the top face.

[0052] Furthermore, the stacked chip 30 includes a plurality of IC chips 110. Each of the plurality of IC chips 110 includes a first surface 102, a second surface 104 opposite the first surface 102, a plurality of side wirings 180D exposed on the first surface 46, a plurality of side wirings 180F exposed on the third surface 45, and a plurality of side wirings 180B exposed on the fourth surface 47. In addition, each of the plurality of IC chips 110 may include a through-electrode 160 exposed on the first surface 102. For example, the IC chip 110 may be a storage medium capable of storing (remembering) data, such as an SRAM (Static Random Access Memory), a DRAM chip, or an NVM (Non-Volatile Memory) chip, a computing die capable of processing data, or an I / O die including an input / output interface to connect a plurality of IC chips.

[0053] The number of IC chips 110 stacked on the stacked chip 30 is just one example, and the number of stacked IC chips 110 is not limited to eight (eight layers). The number of stacked IC chips 110 may be appropriately selected based on the application, specifications, etc., of the semiconductor module 10.

[0054] For example, as shown in Figure 5, the stacked chip 30 includes a plurality of junction chips 101, a plurality of SRAM chips 110S, and a plurality of DRAM chips 110D. Each of the plurality of junction chips 101 includes a computing die 200 and an SRAM chip 110S. Thus, the stacked chip 30 includes eight IC chips 110, including two computing dies 200, four SRAM chips 110S, and two DRAM chips 110D.

[0055] Multiple IC chips 110 may simply be referred to as multiple boards. If the multiple IC chips 110 are not distinguished from each other, the IC chip is referred to as IC chip 110. If the multiple IC chips 110 are distinguished from each other, the IC chip is referred to as IC chip 110n, IC chip 110n+1, SRAM chip 110S, DRAM chip 110D, computing die 200, etc.

[0056] For example, the computing die 200 includes a first surface 202, a second surface 204 opposite to the first surface 202, a plurality of through-electrodes 260 exposed on the first surface 202, and a plurality of side wirings 280D exposed on the first surface 46. Each of the plurality of through-electrodes 260 of the computing die 200 is electrically connected to the corresponding plurality of through-electrodes 160 of the SRAM chip 110S. The plurality of through-electrodes 260 and the plurality of through-electrodes 160 are formed using a conductor made of, for example, a metal. A conductor made of a metal is a conductor including, for example, copper.

[0057] For example, stacking (joining) two different IC chips 110 so that their second faces 104 (second face 204) face each other is referred to as F2F joining (Face to Face Fusion). Also, stacking (joining) two different IC chips 110 so that their first faces 102 (first face 202) face each other is referred to as B2B joining (Back to Back Fusion). Also, stacking (joining) two different IC chips 110 so that their second faces 104 (second face 204) face each other and their first faces 102 (first face 202) face each other is referred to as F2B joining (Face to Back Fusion). For example, stacking (joining) two different IC chips 110 can be done using techniques such as welding (fusion bonding, FB), silicon direct bonding (SDB), or thermal compression bonding (TCB).

[0058] As shown in Figure 5, the stacked chip 30 is constructed by bonding the computing die 200 and the SRAM chip 110S together in a B2B configuration, connecting the bonding chip 101 and the SRAM chip 110S via an adhesive layer 103 in an F2F configuration, connecting the SRAM chips 110S together via an adhesive layer 103 in an F2B configuration, connecting the SRAM chip 110S and the DRAM chip 110D together via an adhesive layer 103 in an F2B configuration, connecting the DRAM chips 110D together via an adhesive layer 103 in an F2B configuration, connecting the DRAM chip 110D and the bonding chip 101 via an adhesive layer 103 in an F2B configuration, and bonding the computing die 200 and the SRAM chip 110S together in a B2B configuration.

[0059] The adhesive layer 103 may be an adhesive containing, for example, an epoxy resin or an acrylic polymer, a die bonding film (DBF) containing an epoxy resin or an acrylic polymer, or an adhesive film such as a die attach film (DAF). The adhesive layer 103 can be appropriately selected depending on the application and specifications of the semiconductor module 10.

[0060] For example, as shown in Figures 2 and 3, the metal wiring layer 20B is provided in contact with the fourth surface 47. For example, the metal wiring layer 20B includes an insulating layer 21, a wiring layer containing multiple wires 22, an insulating layer 23, a wiring layer containing multiple wires 24, and an insulating layer 25. The insulating layer 21 is provided on and in contact with the fourth surface 47 along the second direction. The wiring layer containing multiple wires 22 is provided in an array on the fourth surface 47. Each of the multiple wires 22 is provided on the corresponding side wiring 180B along the second direction D2 and is electrically connected to the corresponding side wiring 180B. The wiring layer containing multiple wires 24 is provided on the wiring layer containing multiple wires 22 and the insulating layer 21 along the second direction D2. Each of the multiple wires 24 is provided on the corresponding wire 22 and is electrically connected to the corresponding wire 22, and extends toward the metal wiring layer 20D along the third direction D3. The insulating layer 25 is provided on top of the wiring layer and insulating layer 23, which include a plurality of wires 24. For example, the end face 20BE of the metal wiring layer 20B is polished, and the end face 24BE of the wires 24 is exposed from the end face 20BE.

[0061] For example, as shown in Figure 2, the metal wiring layer 20F is configured similarly to the metal wiring layer 20B. The metal wiring layer 20F is provided in contact with the third surface 45 and includes an insulating layer 21, a wiring layer containing a plurality of wires 22, an insulating layer 23, a wiring layer containing a plurality of wires 24, and an insulating layer 25. The insulating layer 21 is provided on the third surface 45 along the second direction and in contact with the third surface 45. The wiring layer containing a plurality of wires 22 is provided in an array on the third surface 45. Each of the plurality of wires 22 is provided on the corresponding side wiring 180F along the second direction D2 and is electrically connected to the corresponding side wiring 180F. The wiring layer containing a plurality of wires 24 is provided on the wiring layer containing a plurality of wires 22 and the insulating layer 21 along the second direction D2. Each of the plurality of wires 24 is provided on the corresponding wiring 22 and is electrically connected to the corresponding wiring 22, and extends toward the metal wiring layer 20D along the third direction D3. The insulating layer 25 is provided on top of the wiring layer and insulating layer 23, which include a plurality of wires 24. For example, the end face 20FE of the metal wiring layer 20F is polished, and the end face 24FE of the wires 24 is exposed from the end face 20FE.

[0062] For example, as shown in Figures 2 to 5, the metal wiring layer 20D is provided in contact with the first surface 46, the end surface 20BE, and the end surface 20FE, and includes an insulating layer 21 and a wiring layer containing a plurality of wires 22. The insulating layer 21 is provided on the first surface 46, the end surface 20BE, and the end surface 20FE along the third direction and is provided in contact with the first surface 46, the end surface 20BE, and the end surface 20FE. The wiring layer containing the plurality of wires 22 is provided in an array on the first surface 46. In addition, each of the plurality of wires 22 is provided on the corresponding side wiring 180D along the third direction D3 and is electrically connected to the corresponding side wiring 180D, the end surface 24BE, and the end surface 24FE of the wiring 24. The plurality of wires 22 included in the metal wiring layer 20D are exposed on the first surface 146 of the cube chip 100. For example, the computing die 200 within the bonding chip 101 on the sixth surface 44 (sixth surface 144) side shown in Figure 5 is electrically connected to the bonding chip 101 and adjacent SRAM chips 110S and further adjacent SRAM chips 110S using multiple wirings 22 of the metal wiring layer 20D, and the computing die 200 within the bonding chip 101 on the fifth surface 42 (fifth surface 142) side shown in Figure 5 is electrically connected to the bonding chip 101 and adjacent DRAM chips 110D and further adjacent DRAM chips 110D using multiple wirings 22 of the metal wiring layer 20D.

[0063] In other words, the side wirings 180B and 180F within the IC chip 110 are electrically connected to the wirings 22 and 24 within the metal wiring layers 20B and 20F on the outermost side (third face 145 and fourth face 147) of the cube chip 100 along the second direction D2, and are also electrically connected to the wiring 22 within the metal wiring layer 20D on the outermost side (first face 146) along the third direction D3 of the cube chip 100, and are exposed from the cube chip 100. Similarly, the side wiring 180D within the IC chip 110 is electrically connected to the wiring 22 within the metal wiring layer 20D on the outermost side (first face 146) along the third direction D3 of the cube chip 100, and is exposed from the cube chip 100. Therefore, the signals transmitted through the side wirings 180B and 180F within the IC chip 110, as well as the signals transmitted through the side wiring 180D within the IC chip 110, are transmitted from the outermost surface (first face 146) of the cube chip 100 to an external circuit connected to the cube chip 100. In addition, the signals transmitted from the external circuit are transmitted back into the cube chip 100 from the outermost surface (first face 146) of the cube chip 100.

[0064] The number of layers of wiring in the metal wiring layers 20B, 20F, and 20D is not limited to the number of layers shown in Figures 2 to 5. The number of layers of wiring in the metal wiring layers 20B, 20F, and 20D can be adjusted as appropriate depending on the specifications and application of the semiconductor module 10.

[0065] For example, the bump portion 800, which includes multiple bumps 801, is formed after the cube chip 100 is formed, so as to be in contact with the wiring 22 exposed on the first surface 146 of the cube chip 100. For example, the material used to form the multiple bumps 801 may be solder, and may contain tin, gold, copper, etc. Also, for example, the multiple bumps 801 may be formed using an electroplating method, or they may be formed using an inkjet method of a printer. Depending on the application and specifications of the semiconductor module 10, the multiple bumps 801 can be formed using materials and methods capable of forming multiple bumps 801.

[0066] The cube chip 100, including the configuration described above, allows wiring to be routed from any position within the cube chip 100 to multiple wirings 22 exposed on the first surface 146, and allows multiple signals transmitted through the multiple wirings 22 to be transmitted to the first surface 146 (bottom surface) of the cube chip 100. Furthermore, the semiconductor module 10 includes a configuration in which the cube chip 100 and the bump portion 800 are electrically connected, and allows multiple signals transmitted within the cube chip 100 to be transmitted to any position on the corresponding bump 801.

[0067] In other words, the semiconductor module 10, through its metal wiring layers 20B, 20F, and 20D, and the multiple bumps 801, can reconnect multiple wirings located at any position on the stacked chip 30 within the cube chip 100, and extend them to any of the multiple bumps 801 located at any position. In other words, the semiconductor module 10, through its metal wiring layers 20B, 20F, and 20D, and the multiple bumps 801, can transmit multiple signals transmitted within the cube chip 100 (stacked chip 30) to any of the multiple bumps 801.

[0068] More specifically, multiple wirings (side wirings 180D) exposed from the side surface (e.g., the first surface 46) of the multilayer chip 30 are electrically connected to the metal wiring layer 20D, and are rerouted by the metal wiring layer 20D from their original positions to different positions. In other words, the metal wiring layer 20D has the function of reconnecting and relocating the original positions of the multiple wirings exposed from the side surface of the multilayer chip 30. For example, the metal wiring layer 20D may be referred to as a rewiring layer. The metal wiring layer 20D also functions as an underbump metal (UBM) that suppresses the diffusion of the material used in the bump section 800, which includes multiple bumps 801. For example, the metal wiring layer 20D may be referred to as a UBM layer. The material used in the UBM layer may include nickel, copper, or alloys mainly composed of these, and the UBM layer may be composed of multiple layers combining nickel, copper, or alloys mainly composed of these. The metal wiring layer 20D may have either the function of a redistribution layer or the function of a UBM, or it may have both the function of a redistribution layer and the function of a UBM. If the metal wiring layer 20D has both the function of a redistribution layer and the function of a UBM, the metal wiring layer 20D may include both a redistribution layer and a UBM layer.

[0069] Furthermore, the metal wiring layer 20D has the function of reconnecting and rearranging the positions of multiple wirings (side wirings 180B and 180F) exposed from the sides of the stacked chip 30 (for example, the third side 45 and the fourth side 47) via the metal wiring layers 20B and 20F.

[0070] [1-1-2. Overview of Semiconductor Chip Section 300] The overview of the semiconductor chip section 300 will be explained with reference to Figures 1 to 5. Configurations that are the same as or similar to those described in "1-1. Overview of the semiconductor module 10" and "1-1-1. Overview of the cube chip 100 and bump section 800" will be explained as necessary. The semiconductor chip section 300 includes a computing die 600 and an IO die 700.

[0071] For example, the computing die 600 includes a transistor layer 630 and a wiring layer 650 stacked on the transistor layer 630. The transistor layer 630 includes a first surface 602, which is the exposed surface of the computing die 600, and a plurality of through electrodes 660 exposed on the first surface 602. The wiring layer 650 includes a second surface 604, which is the exposed surface of the computing die 600 opposite to the first surface 602, and a plurality of electrodes 682 exposed on the second surface 604. A plurality of through electrodes 690 are provided on the transistor layer 630 and the wiring layer 650, and the plurality of through electrodes 690 penetrate the transistor layer 630 and are exposed on the first surface 602, and are electrically connected to the electrodes 682. The first surface 602 and the second surface 604 are surfaces parallel to the first direction D1 and the second direction D2.

[0072] The first surface 602 of the computing die 600 is in contact with the bump portion 800 and is positioned to face the second surface 148 of the cube chip 100. Each of the multiple through electrodes 690 and 660 is electrically connected to the corresponding multiple wirings 22 via the corresponding multiple bumps 801. As a result, the computing die 600 (semiconductor chip portion 300) and the cube chip 100 are electrically connected.

[0073] As will be described in detail later, the substrate 673 (see Figure 13) included in the computing die 600 is located above the computing die 600 (on the first surface 602 side) along the third direction D3, and the N-type transistor 668 and P-type transistor 669 (see Figure 13) are stacked below the substrate 673 (on the second surface 604 side) with respect to the third direction D3. In other words, the stacking direction of each layer constituting the computing die 600 is downward along the third direction D3.

[0074] For example, a mounting structure in which the stacking direction is upward along the third direction D3 is called face-up mounting, and a mounting structure in which the stacking direction is downward along the third direction D3 is called face-down mounting. In the semiconductor module 10, the computing die 600 is placed on the IO die 700 with its first face 602 facing downward along the third direction D3, and the computing die 600 is face-down mounted on the IO die 700.

[0075] For example, the IO die 700 includes a transistor layer 730 and a wiring layer 750 stacked on the transistor layer 730. The transistor layer 730 includes a first surface 702, which is the exposed surface of the IO die 700, and a plurality of through electrodes 760 exposed on the first surface 702. The wiring layer 750 includes a second surface 704, which is the exposed surface of the IO die 700 opposite to the first surface 702, and a plurality of electrodes 782 exposed on the second surface 704. A plurality of through electrodes 790 are provided on the transistor layer 730 and the wiring layer 750, and the plurality of through electrodes 790 penetrate the transistor layer 730 and are exposed on the first surface 702, and are electrically connected to the electrodes 782. The first surface 702 and the second surface 704 are surfaces parallel to the first direction D1 and the second direction D2.

[0076] The first surface 702 of the IO die 700 is positioned to face the second surface 604 of the computing die 600 and is the surface that is joined to the second surface 604 of the computing die 600. More specifically, each of the multiple through electrodes 790 and multiple through electrodes 760 exposed on the first surface 702 of the IO die 700 is joined (stacked) to the corresponding multiple electrodes 682 exposed on the second surface 604 of the computing die 600. As a result, the IO die 700 and the computing die 600 are electrically connected.

[0077] As will be described in detail later, similar to the computing die 600, the substrate 773 (see Figure 14) included in the IO die 700 is located below the IO die 700 (towards the first surface 702) along the third direction D3, and the N-type transistor 768 and P-type transistor 769 (see Figure 14) are stacked above the substrate 773 with respect to the third direction D3. In other words, the stacking direction of each layer constituting the IO die 700 is downward along the third direction D3. In the semiconductor module 10, the IO die 700 is placed on the package substrate 500 with its first surface 702 facing downward along the third direction D3, and the IO die 700 is face-down mounted on the package substrate 500.

[0078] As an example, the semiconductor chip section 300 in the semiconductor module 10 is composed of two different IC chips 110 (a computing die 600 and an I / O die 700), but the semiconductor chip section 300 may also be composed of a single IC chip 110 that includes the functions and configuration of the computing die 600 and the functions and configuration of the I / O die 700.

[0079] As an example, the semiconductor chip portion 300 in the semiconductor module 10 includes a configuration in which each of the multiple through electrodes 790 and multiple through electrodes 760 exposed on the first surface 702 of the IO die 700 is electrically connected to a multiple electrode 682 exposed on the second surface 604 of the computing die 600. However, each of the multiple through electrodes 790 and multiple through electrodes 760 exposed on the first surface 702 of the IO die 700 may be electrically connected to a multiple electrode 682 exposed on the second surface 604 of the computing die 600 via bumps.

[0080] [1-1-3. Overview of Package Substrate 500] The overview of the package substrate 500 will be explained with reference to Figures 1 to 5. Configurations that are the same as or similar to those described in "1-1. Overview of Semiconductor Module 10" to "1-1-2. Overview of Semiconductor Chip Section 300" will be explained as necessary.

[0081] The package substrate 500 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. For example, the package substrate 500 includes a first surface 502 which is the exposed surface of the package substrate 500, a second surface 504 opposite to the first surface 502, and a plurality of electrodes 52. The plurality of electrodes 52 are exposed on the first surface 502. Each of the plurality of electrodes 52 is electrically connected to the wiring and electrodes inside the package substrate 500. The wiring and electrodes inside the package substrate 500, as well as the insulating layers alternately stacked with the wiring and electrodes, are not shown. Furthermore, the number of layers in the multilayer wiring structure of the package substrate 500 can be adjusted as appropriate based on the application or specifications of the semiconductor module 10.

[0082] Furthermore, the package substrate 500 is electrically connected to the semiconductor chip portion 300 via a plurality of bumps 41 provided between the semiconductor chip portion 300 and the package substrate 500. The package substrate 500 may be electrically connected to an external substrate and external circuits, etc., via a plurality of electrodes 52 different from the plurality of electrodes 52 to which the semiconductor chip portion 300 is electrically connected. Although not shown in the figures, the package substrate 500 may also include wiring or electrodes exposed on the second surface 504, and may be electrically connected to an external substrate and external circuits, etc., via wiring or electrodes exposed on the second surface 504.

[0083] [1-1-4. Overview of Bump Section 400] The bump section 400 will be described with reference to Figures 1 to 5. Configurations that are the same as or similar to those described in "1-1. Overview of Semiconductor Module 10" to "1-1-3. Overview of Package Substrate 500" will be described as necessary.

[0084] For example, a bump section 400 including multiple bumps 41 is formed to contact multiple electrodes 782 exposed on the second surface 704 of the semiconductor chip section 300 after the cube chip 100 and the semiconductor chip section 300 are connected using the bump section 800, and is electrically connected to multiple electrodes 52 exposed on the first surface 502 of the package substrate 500. Alternatively, for example, a bump section 400 including multiple bumps 41 may be formed to contact multiple electrodes 52 exposed on the first surface 502 of the package substrate 500, and is electrically connected to multiple electrodes 782 exposed on the second surface 704 of the semiconductor chip section 300 which is electrically connected to the cube chip 100 using the bump section 800. For example, the material and method for forming multiple bumps 41 are the same as the material and method for forming multiple bumps 801. Also, like multiple bumps 801, multiple bumps 41 can be formed using materials and methods capable of forming multiple bumps 801, depending on the application and specifications of the semiconductor module 10.

[0085] [1-2. Configuration of Semiconductor Module 10] The functional configuration of the semiconductor module 10 will be described with reference to Figure 6. Figure 6 is a block diagram showing an example of the functional configuration of the semiconductor module 10. Configurations that are the same as or similar to those described with reference to Figures 1 to 5 will be described as necessary.

[0086] The cube chip 100 is electrically connected to the semiconductor chip section 300 using a bump section 800 which includes multiple bumps 801. Each circuit within the semiconductor chip section 300 is electrically connected using a signal bus 340 via multiple network routers (Router, R) 318 (318a~318l).

[0087] For example, as described in "1-1-1. Overview of Cube Chip 100 and Bump Section 800," the cube chip 100 includes multiple junction chips 101, multiple SRAM chips 110S, and multiple DRAM chips 110D. Each of the multiple junction chips 101 includes a computing die 200 and an SRAM chip 110S. The computing die 200 is electrically connected to the SRAM chips 110S using a signal bus 240. For example, the signal bus 240 represents a bundle of wiring in which multiple through electrodes 160 (see Figure 5) and multiple through electrodes 260 corresponding to each of the multiple through electrodes 160 (see Figure 5) are electrically connected.

[0088] The computing die 200 includes multiple I / O interfaces 212 and multiple logic modules 211. The multiple I / O interfaces 212 are electrically connected to the logic modules 211. Although the computing die 200 includes multiple I / O interfaces 212, in Figure 6, the number of I / O interfaces 212 is simplified to one for clarity.

[0089] The I / O interface 212 includes a transmit / receive circuit 214 and a parallel-to-serial conversion circuit 213. The transmit / receive circuit 214 is electrically connected to the parallel-to-serial conversion circuit 213. The parallel-to-serial conversion circuit 213 is electrically connected to the logic module 211.

[0090] The transmitting / receiving circuit 214 is electrically connected to the transmitting / receiving circuit 314 of the semiconductor chip section 300 using a bump 801. The transmitting / receiving circuit 214 and the transmitting / receiving circuit 314 have the function of transmitting and receiving signals to each other.

[0091] For example, the transmitting / receiving circuit 214 has the function of amplifying the received signal (data) and the function of removing noise from the received signal (data). The signal received by the transmitting / receiving circuit 214 includes a large number of parallel signals from the semiconductor chip section 300 or a large number of parallel signals from the logic module 211.

[0092] The parallel-to-serial conversion circuit 213, for example, in step 1, converts multiple parallel signals from the semiconductor chip unit 300 into a series signal (serial signal). The series signal is transmitted at high speed using a single signal path (wiring). In step 2, just before the logic module 211, the parallel-to-serial conversion circuit 213 converts the series signal back into multiple parallel signals, and then transmits the multiple parallel signals to the logic module 211 via the signal bus 240. When transmitting a signal (data) from the logic module 211 to the semiconductor chip unit 300, the parallel-to-serial conversion circuit 213, for example, executes step 1 after step 2. The parallel-to-serial conversion circuit 213 is, for example, denoted as a SerDes circuit (Serialize and Deseriarise Circuit).

[0093] The logic module 211 has functions for controlling the transmission of signals (data) to the IO interface 212, or the reception of signals (data) from the IO interface 212. The logic module 211 also has functions for driving the memory module 111S (see Figure 10) within the SRAM chip 110S and the memory module 111D within the DRAM chip 110D. For example, the logic module 211 transmits signals to drive the memory modules 111S and 111D via the IO interface 212. The logic module 211 may include, for example, an arithmetic circuit such as a CPU. Furthermore, as shown in Figure 6, two logic modules 211 may be configured to independently control the SRAM chip 110S (memory module 111S) and the DRAM chip 110D (memory module 111D).

[0094] Furthermore, for example, the semiconductor chip section 300 shown in Figure 6 includes multiple I / O interfaces 312, multiple R318s, a DRAM interface (DRAMIO) 311, a PCIe interface (PCI Express Interface (PCIeIF)) 315, an Ethernet interface (Ethernet Interface (EIF)) 316, a memory controller 319, a GPU 320, and a CPU 321.

[0095] For example, the IO die 700 of the semiconductor chip section 300 includes multiple IO interfaces 312 and multiple R318, and the computing die 600 of the semiconductor chip section 300 includes a DRAM interface (DRAMIO) 311, a PCIe interface (PCI Express Interface (PCIeIF)) 315, an Ethernet interface (Ethernet Interface (EIF)) 316, a memory controller 319, a GPU 320 and a CPU 321.

[0096] The IO interface 312, DRAMIO 311, PCIeIF 315, EIF 316, memory controller 319, GPU 320, and CPU 321 are functional blocks that constitute an LSI (Large Scale Integration). Functional blocks that constitute an LSI are called, for example, IP (Intellectual Property) cores, IP, or macros. An IP core also includes storage media such as SRAM chips and DRAM chips.

[0097] The configuration and functions of the semiconductor chip unit 300 are not limited to those shown in Figure 6. That is, the number of IO interfaces 312 and the number and types of IP cores included in the semiconductor chip unit 300 are not limited to those shown in Figure 6. The configuration and functions of the semiconductor chip unit 300 are appropriately selected depending on the specifications and application of the semiconductor module 10, and the number of IP cores included in the semiconductor module 10. For example, the semiconductor chip unit 300 may include a plurality of DRAMIO 311s, a plurality of memory controllers 319s, a plurality of GPUs 320s, a plurality of CPUs 321s, and external IO (not shown).

[0098] The IP cores, including multiple I / O interfaces 312, DRAMIO 311, PCIeIF 315, EIF 316, memory controller 319, GPU 320, and CPU 321, include a Network Interface (NI) 317.

[0099] Furthermore, the IP cores such as the multiple IO interfaces 312, DRAMIO311, PCIeIF315, EIF316, memory controller 319, GPU320, and CPU321 do not include NI317, and NI317 is located outside the multiple IO interfaces 312, DRAMIO311, PCIeIF315, EIF316, memory controller 319, GPU320, and CPU321. Each of the multiple IO interfaces 312, DRAMIO311, PCIeIF315, EIF316, memory controller 319, GPU320, and CPU321 may be electrically connected to the R318 corresponding to their respective circuits via NI317.

[0100] Multiple IP cores, such as the I / O interface 312, DRAMIO311, PCIeIF315, EIF316, memory controller 319, GPU320, and CPU321, are electrically connected to the R318 corresponding to the NI317 of each IP core. Thus, the multiple IP cores, such as the I / O interface 312, DRAMIO311, PCIeIF315, EIF316, memory controller 319, GPU320, and CPU321, are connected in a network using multiple R318s. These multiple R318s are electrically connected, for example, using multiple signal buses 340.

[0101] The network configuration of the IP core using multiple R318s may be a mesh configuration as shown in Figure 6. The network configuration of the IP core shown in Figure 6 is just one example, and the network configuration of the IP core is not limited to the configuration shown in Figure 6. The network configuration of the IP core is appropriately selected depending on the specifications and application of the semiconductor module 10, as well as the number of IP cores included in the semiconductor module 10.

[0102] The multiple IO interfaces 312 include, for example, IO interfaces 312a to 312e and 312k. If the multiple IO interfaces 312 are not distinguishable, the IO interface is denoted as IO interface 312. If the multiple IO interfaces 312 are distinguishable, the multiple IO interfaces are individually denoted as IO interfaces 312a to 312e and 312k, etc. There is no limit to the number of multiple IO interfaces 312 included in the semiconductor module 10; they are selected as appropriate depending on the specifications and application of the semiconductor module 10, as well as the number of IP cores included in the semiconductor module 10.

[0103] The IO interface 312 includes a transmit / receive circuit 314, a parallel-to-serial converter circuit 313, and an NI317. The transmit / receive circuit 314 is electrically connected to the parallel-to-serial converter circuit 313. The parallel-to-serial converter circuit 313 is electrically connected to the NI317. The IO interface 312 (NI317) is electrically connected to R318.

[0104] The configuration and functions of the transmitting / receiving circuit 314, the parallel / serial conversion circuit 313, and the memory controller 319 are the same as those of the transmitting / receiving circuit 214, the parallel / serial conversion circuit 213, and the logic module 211. Therefore, a description of the configuration and functions of the transmitting / receiving circuit 314, the parallel / serial conversion circuit 313, and the memory controller 319 is omitted here.

[0105] For example, the NI317 can convert data transmitted and received using the signal bus 340 into a data format corresponding to the IP core electrically connected to the NI317, and can convert the data format corresponding to the IP core into a data format corresponding to the signal bus 340. As a result, the semiconductor module 10 can transmit and receive both addresses and data using the signal bus 340, thus reducing the bus width compared to modules with centrally located signal buses. Furthermore, since the semiconductor module 10 can transmit and receive data without depending on the data format corresponding to each IP core, it is possible to suppress an increase in the number of signal buses 340.

[0106] Here, the data transmitted and received using the signal bus 340 includes, for example, an address that can identify an IP core electrically connected to the NI317.

[0107] Multiple R318s include, for example, R318a to 318k. Similar to I / O interfaces, if multiple R318s are not distinguishable, the multiple Rs are denoted as R318. If multiple R318s are distinguishable, the multiple Rs are individually denoted as R318a to 318k, etc. There is no limit to the number of multiple R318s included in the semiconductor module 10; they are selected as appropriate depending on the specifications and application of the semiconductor module 10, as well as the number of IP cores included in the semiconductor module 10.

[0108] Each of the multiple R318s is electrically connected to the IP core and the signal bus 340. Each of the multiple R318s includes multiple switches and, based on its address, can control the data transmission and reception path to each network-connected IP core. As a result, the semiconductor module 10 can transmit and receive data to a desired IP core among the network-connected IP cores by controlling the multiple switches of the multiple R318s. Furthermore, because the semiconductor module 10 can change the placement and address of the R318s in conjunction with controlling the data transmission and reception path to the IP core using the R318s, it can flexibly configure the data transmission and reception path.

[0109] Furthermore, R318 can function as a repeater (also called a bus buffer) that aggregates multiple signal buses 340 and appropriately divides the routed signal buses 340. Therefore, the semiconductor module 10 can suppress the concentration of multiple signal buses 340. As a result, for example, the degree of freedom in the position of R318 is improved, and the constraints on the placement of IP cores connected to R318 can be relaxed.

[0110] For example, DRAMIO311 has the function of sending and receiving signals between the DRAM chip and the computing die 200.

[0111] For example, PCIeIF315 is an interface that conforms to the serial bus standard used to connect expansion cards and other components within a computer. PCIeIF315 has the capability to transfer data at high speed to components such as the CPU, memory, and storage connected to expansion cards installed in a computer.

[0112] For example, the EIF316 is an interface that has the function of connecting the semiconductor module 10 and all devices (computers, printers, etc.) that communicate via the network with the network medium (cable).

[0113] For example, the external I / O may include NI317 and be electrically connected to R318 via NI317. The external I / O is electrically connected to the cube chip 100 and external circuitry (not shown, e.g., power supply circuitry) via R318 and has the function of sending and receiving signals between the external circuitry and the cube chip 100.

[0114] For example, the memory controller 319 includes NI317. For example, the memory controller 319 is electrically connected to R318h via NI317. The memory controller 319 is also connected to the cube chip 100 via R318h and has the function of controlling the IC chips 110 (e.g., SRAM chip 110S and DRAM chip 110D) contained in the cube chip 100.

[0115] For example, the CPU 321 is electrically connected to the R318l via the NI 317. The CPU 321 includes multiple arithmetic circuits and is capable of performing arithmetic processing. For example, the CPU 321 has the function of reading a control program stored in the DRAM chip 110D within the cube chip 100, expanding the control program, executing processing based on the control program, and sending instructions (commands) to each IP and each IC chip 110 to execute processing based on the control program.

[0116] For example, the GPU320 is electrically connected to the R318j via the NI317. The GPU320 includes multiple arithmetic circuits and is capable of image processing and video processing. In other words, the GPU320 has a configuration similar to that of the CPU321 and is a chip with functions specialized for image processing and video processing. For example, the GPU320 has the function of reading a control program stored in the DRAM chip 110D within the cube chip 100, expanding the control program and executing processing based on the control program, as well as sending instructions (commands) to each IP and each IC chip 110 to execute processing based on the control program.

[0117] Each of the multiple logic modules 211 described above has a function for controlling the transmission of signals (data) to multiple IO interfaces 212, SRAM chip 110S and DRAM chip 110D within the cube chip 100, multiple IO interfaces 312, DRAMIO311, PCIeIF315, EIF316, memory controller 319 and multiple R318 within the semiconductor chip section 300, or for receiving signals (data) from multiple IO interfaces 312 and SRAM chip 110S within the cube chip 100, multiple IO interfaces 312, DRAMIO311, PCIeIF315, EIF316 within the semiconductor chip section 300, memory controller 319, GPU 320, CPU 321 and multiple R318.

[0118] Also, for the sake of clarity in the diagram, the illustration is omitted, but the semiconductor chip section 300 includes USB, SDIO, SPI, and I 2 It may also include interfaces such as C and UCIe. For example, USB is an interface that has the function of connecting terminals such as personal computers and personal digital assistants to devices such as printers and cameras, SDIO is an interface that has the function of connecting memory cards (e.g., SD cards), and SPI (Serial Peripheral Interface) is an interface that has the function of connecting devices suitable for high-speed communication such as large-scale DRAM. Also, for example, I 2 C (Inter-Integrated Circuit, I-squared-C) is an interface with functions for connecting relatively low-speed peripherals to motherboards, embedded systems, and personal digital assistants, while UCIe is an interface with functions suitable for connecting very short distances on a chip-level circuit board.

[0119] Furthermore, although not shown in the diagram for clarity, the semiconductor chip section 300 may include an L1 cache memory, an L2 cache memory, and the like.

[0120] As explained above, each circuit within the semiconductor chip section 300 is connected in a network manner via a network router (Router(R)), and each circuit within the cube chip 100 is electrically connected to each circuit within the semiconductor chip section 300 using bumps 801. The semiconductor module 10 is a module that includes a so-called Network on Chip (NoC) in which multiple IP cores are connected in a network manner, and is capable of communication using the NoC.

[0121] For example, as shown in Figure 6, R318h, connected to the memory controller 319, is connected to R318g, R318e, R318i, and R318j within the semiconductor chip section 300. That is, the memory controller 319 connected to R318h is electrically connected via the signal bus 340 to the DRAMIO 311 connected to R318g, the IO interface 312e connected to R318e, the EIF 316 connected to R318i, and the GPU 320 connected to R318j. The IO interface 312e is connected to the computing die 200 within the cube chip 100 using a bump 801. Specifically, the IO interface 312e communicates with the IO interface 212 and connects to the computing die 200 (logic module 211) and the SRAM chip 110S or DRAM chip 110D corresponding to the communicated IO interface 212.

[0122] Therefore, the memory controller 319 transmits signals to the IO interface 312e via R318h and R318e to drive the SRAM chip 110S or DRAM chip 110D, and the IO interface 312e communicates with the IO interface 212 in the cube chip 100, which is electrically connected via the bump 801, and can transmit signals to the logic module 211 to drive the computing die 200 (logic module 211), SRAM chip 110S or DRAM chip 110D, which corresponds to the communicated IO interface 212.

[0123] The semiconductor module 10 includes a semiconductor chip section 300 in which routers connected to each of multiple IP cores are connected in a network manner using a signal bus, enabling communication using a network-type bus.

[0124] Furthermore, the semiconductor module 10 can electrically connect a semiconductor chip section 300 capable of communication using a network-type bus, a junction chip 101 including a computing die 200 and an SRAM chip 110S, a plurality of SRAM chips 110S and a plurality of DRAM chips 110D stacked on top of a cube chip 100 mounted vertically on the semiconductor chip section 300, and a cube chip 100 using bump sections 800. As a result, the semiconductor module 10 has excellent heat dissipation characteristics, electrically connects each IP core in the semiconductor chip section 300, the computing die 200, SRAM chips 110S and DRAM chips 110D in the cube chip 100 in a three-dimensional manner, suppresses the increase in resistance and parasitic capacitance due to wiring, and suppresses signal transmission delay between each IP core in the semiconductor chip section 300 and the computing die 200 and SRAM chips 110S in the cube chip 100. As a result, the semiconductor module 10 can suppress power consumption.

[0125] [1-3. An example of connection between the cube chip 100 and the semiconductor chip section 300] An example of the connection configuration between the cube chip 100 and the semiconductor chip section 300 will be described with reference to Figures 7 to 9. Figures 7 to 9 are block diagrams showing an example of the configuration of IO interfaces 212 and 312. Configurations that are the same as or similar to those described with reference to Figures 1 to 6 will be described as necessary.

[0126] The cube chip 100 is electrically connected to the semiconductor chip section 300 using the bump section 800. For example, if the pitch between bumps 801 is wider than P1μm, it is desirable to use the SerDes circuit described in "1-2. Configuration of Semiconductor Module 10" to combine multiple low-speed signals and convert them into a high-speed signal for transmission.

[0127] Furthermore, for example, if the pitch between bumps 801 is narrower than P1μm, a single low-speed signal may be transmitted without combining multiple low-speed signals. For example, P1 may be greater than 0 and less than 50, and more preferably, P1 may be greater than 0 and less than 10.

[0128] For example, a single low-speed signal can be transmitted by the circuit shown in Figure 7. As shown in Figure 7, the IO interface 312 includes a latch circuit 351, a plurality of amplification circuits 352, and a plurality of protection circuits 353. For example, the latch circuit 351 receives a signal SIG and a clock signal CLK as inputs, adjusts the signal SIG to a clock-synchronized signal in accordance with the timing of the clock signal CLK, and generates an output signal. For example, the amplification circuit 352 can shape the waveform of the signal. For example, the protection circuit 353 has the function of protecting the semiconductor module 10 from overcharging, over-discharging, or overcurrent. For example, the protection circuit 353 can suppress high-voltage pulses caused by electrostatic discharge from damaging the internal circuits of the semiconductor module 10 and prevent the semiconductor module 10 from malfunctioning.

[0129] Furthermore, as shown in Figure 7, the IO interface 212 includes multiple protection circuits 253, multiple comparators 252, and a latch circuit 251. The latch circuit 251, comparators 252, and protection circuit 253 have similar functions and configurations to the latch circuit 351, amplifier circuit 352, and protection circuit 353.

[0130] For example, when the input signal SIG and the clock signal CLK are transmitted from the IP of the semiconductor chip section 300 to the IO interface 312, the latch circuit 351 adjusts the signal SIG to a signal synchronized with the clock signal CLK and generates an output signal. Both the clock signal and the generated output signal are amplified and protected from overcharging, over-discharging, or overcurrent by passing through the amplification circuit 352 and the protection circuit 353, and then transmitted from the semiconductor chip section 300 to the cube chip 100. At this time, since the semiconductor chip section 300 is electrically connected to the cube chip 100 using the bump section 800, both the clock signal and the generated output signal are transmitted to the cube chip 100 with almost no effect of signal loss due to increased wiring resistance and increased parasitic capacitance.

[0131] For example, the clock signal and the generated output signal transmitted to the cube chip 100 are each shaped by passing through the protection circuit 253 and the comparator 252, while being protected from overcharging, over-discharging, or overcurrent. The shaped clock signal and the generated output signal are input to the latch circuit 251, which can generate an output signal OSIG synchronized with the shaped clock signal OCLK. As a result, the output signal OSIG is input to the logic module 211, the SRAM chip 110S, or the DRAM chip 110D.

[0132] For example, a single low-speed signal can be transmitted by the circuit shown in Figure 8. In the circuit shown in Figure 8, the two comparators 252 in the circuit shown in Figure 7 are replaced with a hysteresis comparator 252H and an injection-synchronous oscillator 254. For example, the injection-synchronous oscillator 254 is an oscillator that uses injection synchronization and can compensate for the error between the oscillator and the data delay of the signal. When the injection-synchronous oscillator 254 is used in the path of a clock signal CLK, the frequency of the clock signal CLK can be compensated, and the circuit to which the injection-synchronous oscillator 254 is applied can operate stably.

[0133] For example, the bump 801 may contain a molding defect, causing it to conduct electricity between the semiconductor chip section 300 and the cube chip 100, but with a high resistance value. Alternatively, the bump 801 may not be broken, but with a high resistance value. In such cases, as shown in Figure 8, the transmitted wave from the semiconductor chip section 300 may have a distorted waveform similar to the received wave at the cube chip 100.

[0134] On the other hand, for example, in the semiconductor module 10, the cube chip 100 on the signal receiving side has a configuration that includes a hysteresis comparator 252H, so the signal waveform after the comparator is shaped as shown in Figure 8. That is, even if the bump 801 contains a formation defect, the semiconductor module 10 can transmit the signal. In addition, by using an injection-synchronous oscillator 254, the semiconductor module 10 can latch the output signal of the hysteresis comparator 252H using a stable clock OCLK, so that a stable output signal OSIG can be supplied to the logic module 211, SRAM chip 110S, or DRAM chip 110D.

[0135] For example, a single low-speed signal may be transmitted by the circuit shown in Figure 9. In the circuit shown in Figure 9, the injection-synchronous oscillator 254 in the circuit shown in Figure 8 is replaced with a hysteresis comparator 252H. By using two hysteresis comparators 252H, the output signal of the hysteresis comparators 252H can be latched using the waveform-shaped clock signal OCLK, thereby supplying a stable output signal OSIG to the logic module 211, SRAM chip 110S, or DRAM chip 110D.

[0136] The circuits shown in Figures 7 to 9 are circuits through which each signal is transmitted from the IO interface 312 in the semiconductor chip section 300 to the IO interface 212 in the cube chip 100. Although not shown in the figures, the cube chip 100 includes a circuit similar to the IO interface 312, and the semiconductor chip section 300 includes a circuit similar to the IO interface 212, so that each signal is transmitted from the IO interface 212 in the cube chip 100 to the IO interface 312 in the semiconductor chip section 300. As a result, the semiconductor module 10 enables bidirectional communication between the semiconductor chip section 300 and the cube chip 100.

[0137] [1-4. Overview of IC Chip 110] Next, an overview of the IC chip 110 will be described with reference to Figures 10 and 11. Figure 10 is a block diagram showing an example of the configuration of the IC chip 110. Figure 11 is an end view showing the cross-sectional structure of the end of the IC chip 110. Configurations that are the same as or similar to those described in Figures 1 to 9 will be described as necessary.

[0138] As shown in Figure 10, the IC chip 110 includes a plurality of memory modules 111, power supply wiring 164, ground wiring 165, and signal transmission wiring 166. Each of the plurality of memory modules 111 includes a memory cell array 115.

[0139] The memory module 111 has functions for controlling the storage of signals (data) to the memory cell array 115 and the reading of signals (data) from the memory cell array 115. The memory module 111 also has functions for controlling the transmission of signals (data) to the I / O interface 312 and the reception of signals (data) from the I / O interface 312.

[0140] The memory cell array 115 includes multiple memory cells (not shown in the diagram). Each of the multiple memory cell arrays 115 is, for example, an SRAM (Static Random Access Memory), each of the multiple memory cells is an SRAM cell, and each of the multiple memory modules 111 is a memory module for SRAM. The SRAM, SRAM cells, and memory modules for SRAM can employ technologies used in the field of SRAM. Therefore, a detailed explanation is omitted here. Note that the multiple memory cell arrays 115 and the multiple memory cells may be memory cell arrays and memory cells other than SRAM, for example, DRAM (Dynamic Random Access Memory) and DRAM cells, MRAM (Magnetoresistive Random Access Memory) and MRAM cells, etc. When each of the multiple memory cell arrays 115 is an SRAM, the IC chip 110 is an SRAM chip 110S, and when each of the multiple memory cell arrays 115 is a DRAM, the IC chip 110 is a DRAM chip 110D.

[0141] Multiple memory modules 111 are electrically connected to power supply wiring 164, grounding wiring 165, and signal transmission wiring 166. Furthermore, for example, parts of power supply wiring 164, grounding wiring 165, and signal transmission wiring 166 are electrically connected to wiring 22 and 24 within metal wiring layers 20B, 20F, or 20D, and electrically connected to the package substrate 500 via multiple bumps 801, semiconductor chip sections 300, and multiple bumps 41. As a result, the IC chip 110 is supplied with voltage VDD and voltage VSS, as well as control signals, from an external circuit or external device. Voltage VDD is, for example, a power supply voltage such as 1V or 3V. Voltage VSS is, for example, a reference voltage that serves as a voltage reference, such as ground voltage or 0V.

[0142] As shown in Figure 11, for example, each of the multiple IC chips 110 includes a first surface 102 parallel to the first direction D1 and the second direction D2, a second surface 104 opposite to the first surface 102 with respect to the third direction D3, a transistor layer 130, and a wiring layer 150. The first surface 102 and the second surface 104 are parallel to the fifth surface 142 and the sixth surface 144.

[0143] The transistor layer 130 includes, for example, a substrate 173, wiring 163, through-electrode 160, insulating layer 174, fin 167, wiring 162, activation region 184, gate insulating film 175, gate electrode 176, N-type transistor 168, P-type transistor 169, and insulating layer 177. For example, the substrate 173 is an N-type silicon substrate (Si substrate) or an N-type silicon wafer (Si-wafer). The IC chip 110 is constructed using fin-type transistors as shown in Figure 11, but it may also be constructed using transistors other than fin-type transistors. The transistor structure of the IC chip 110 may be appropriately selected according to the specifications and application of the semiconductor module 10.

[0144] The wiring layer 150 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. For example, the wiring layer 150 includes a part of the wiring 178, insulating layer 179, wiring 180, insulating layers 181 and 183. The number of multilayer wiring layers in the wiring layer 150 is not limited to the two layers shown in Figure 11. The number of multilayer wiring layers in the wiring layer 150 may be three or more. The number of multilayer wiring layers in the wiring layer 150 can be appropriately changed depending on the specifications and application of the semiconductor module 10.

[0145] For example, wiring 180 is provided through the insulating layer 179 and is electrically connected to wiring 178. Wiring 178 is also provided through the insulating layer 179 and is electrically connected to the source or drain of an N-type transistor 168 or a P-type transistor 169. Wiring 178 is also electrically connected to wiring 162.

[0146] Furthermore, for example, wiring 178 and wiring 180 have a damascene structure, and wiring 162 has a structure corresponding to a through-electrode. Also, wiring 163 is a so-called embedded electrode. For example, wiring 178 and wiring 162 are electrically connected to wiring 22 and 24 in the metal wiring layers 20B, 20F, or 20D via wiring 180, side wiring 180D, 180B, or 180F, and are electrically connected to the package substrate 500 via a plurality of bumps 801, semiconductor chip portion 300, and a plurality of bumps 41.

[0147] Furthermore, for example, the through-electrode 160 is electrically connected to wiring 163, which is a so-called embedded wiring, and a portion of the through-electrode 160 is exposed on the first surface 102. For example, a portion of the through-electrode 160 is electrically connected to a through-electrode 260 that is exposed on the first surface 202 of the computing die 200.

[0148] Various control signal lines, such as the power supply wiring 164, grounding wiring 165, or signal transmission wiring 166 described above, are formed using wiring 180, 178, 162, 163, or through-electrode 160.

[0149] As a result, the IC chip 110 and the computing die 200 receive voltage VDD and voltage VSS, as well as control signals (data), etc., from an external circuit or external device via wiring 22 and 24 in the metal wiring layers 20B, 20F, or 20D.

[0150] Furthermore, if the IC chip 110 is provided at a distance from the outermost surface of the semiconductor module 10, conductive layers such as wiring, electrodes, and through electrodes may be exposed on the second surface 104. Also, conductive layers such as wiring, electrodes, and through electrodes exposed on the second surface 104 may be joined to adjacent IC chips 110 or computing dies 200.

[0151] [1-5. Overview of Computing Die 200] Next, an overview of the computing die 200 will be described with reference to Figure 12. Figure 12 is an end view showing the end cross-sectional structure of the computing die 200. Configurations that are the same as or similar to those described in Figures 1 to 11 will be described as necessary.

[0152] As shown in Figure 12, for example, each of the multiple computing dies 200 includes a first surface 202 parallel to the first direction D1 and the second direction D2, a second surface 204 opposite to the first surface 202 with respect to the third direction D3, a transistor layer 230, and a wiring layer 250. The first surface 202 and the second surface 204 are parallel to the fifth surface 142 and the sixth surface 144.

[0153] The transistor layer 230 includes, for example, a substrate 273, wiring 263, through-electrode 260, insulating layer 274, fin 267, wiring 262, activation region 284, gate insulating film 275, gate electrode 276, N-type transistor 268, P-type transistor 269, and insulating layer 277.

[0154] The wiring layer 250 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. For example, the wiring layer 250 includes wiring 278, insulating layer 279, wiring 280, insulating films 281 and 283.

[0155] The configurations and functions of the substrate 273, wiring 263, through-electrode 260, insulating layer 274, fin 267, wiring 262, activation region 284, gate insulating film 275, gate electrode 276, N-type transistor 268, P-type transistor 269, insulating layer 277, wiring 278, insulating layer 279, wiring 280, insulating films 281 and 283 are the same as those of the substrate 173, wiring 163, insulating layer 174, fin 167, wiring 162, activation region 184, gate insulating film 175, through-electrode 160, insulating layer 174, fin 167, wiring 162, activation region 184, gate insulating film 175, gate electrode 176, N-type transistor 168, P-type transistor 169, insulating layer 177, wiring 178, insulating layer 179, wiring 180, insulating layers 181 and 183 described in "1-4. Overview of IC Chip 110". Therefore, each layer and wiring constituting the transistor layer 230 and the wiring layer 350 will be explained as necessary.

[0156] [1-6. Overview of Computing Die 600] Next, an overview of the computing die 600 will be described with reference to Figure 13. Figure 13 is an end view showing the end cross-sectional structure of the computing die 600. Configurations that are the same as or similar to those described in Figures 1 to 10 will be described as necessary.

[0157] As shown in Figure 13, for example, each of the multiple computing dies 600 includes a first surface 602 parallel to the first direction D1 and the second direction D2, a second surface 604 opposite to the first surface 602 with respect to the third direction D3, a transistor layer 630, and a wiring layer 650. The first surface 602 and the second surface 604 are parallel to the fifth surface 142 and the sixth surface 144.

[0158] The transistor layer 630 includes, for example, a substrate 673, wiring 663, through-electrode 660, insulating layer 674, fin 667, wiring 662, activation region 684, gate insulating film 675, gate electrode 676, N-type transistor 668, P-type transistor 669, and insulating layer 677.

[0159] The wiring layer 650 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. For example, the wiring layer 650 includes wiring 678, insulating layer 679, wiring 680, insulating layers 681 and 683.

[0160] The configurations and functions of the substrate 673, wiring 663, through-electrode 660, insulating layer 674, fin 667, wiring 662, activation region 684, gate insulating film 675, gate electrode 676, N-type transistor 668, P-type transistor 669, insulating layer 677, wiring 678, insulating layer 679, wiring 680, insulating layers 681 and 683 are the same as those of the substrate 173, wiring 163, insulating layer 174, fin 167, wiring 162, activation region 184, gate insulating film 175, through-electrode 160, insulating layer 174, fin 167, wiring 162, activation region 184, gate insulating film 175, gate electrode 176, N-type transistor 168, P-type transistor 169, insulating layer 177, wiring 178, insulating layer 179, wiring 180, insulating layers 181 and 183 as described in "1-4. Overview of IC Chip 110". Therefore, each layer and wiring constituting the transistor layer 630 and the wiring layer 350 will be explained as necessary.

[0161] Furthermore, as described in "1-1-2. Overview of Semiconductor Chip Section 300," the computing die 600 includes a plurality of electrodes 682 exposed on the second surface 604, and a plurality of through electrodes 690 exposed on the first surface 602 and electrically connected to the electrodes 682. The plurality of electrodes 682 are formed to be embedded in the insulating layer 683. For example, the electrodes 682 may have a damascene structure, similar to the wiring 178 and wiring 180. The plurality of through electrodes 690 are provided to penetrate the insulating layers 683, 681, 679, 677 and 674, as well as the substrate 673.

[0162] [1-7. Overview of IO Die 700] Next, an overview of the IO die 700 will be described with reference to Figure 14. Figure 14 is an end view showing the cross-sectional structure of the end of the IO die 700. Configurations that are the same as or similar to those described in Figures 1 to 13 will be described as necessary.

[0163] As shown in Figure 14, for example, each of the multiple IO dies 700 includes a first surface 702 parallel to the first direction D1 and the second direction D2, a second surface 704 opposite to the first surface 702 with respect to the third direction D3, a transistor layer 730, and a wiring layer 750. The first surface 702 and the second surface 704 are parallel to the fifth surface 142 and the sixth surface 144.

[0164] The transistor layer 730 includes, for example, a substrate 773, wiring 763, through-electrode 760, insulating layer 774, fin 767, wiring 762, activation region 784, gate insulating film 775, gate electrode 776, N-type transistor 768, P-type transistor 769, and insulating layer 777.

[0165] The wiring layer 750 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. For example, the wiring layer 750 includes wiring 778, insulating layer 779, wiring 780, insulating layers 781 and 783.

[0166] The configurations and functions of the substrate 773, wiring 763, through-electrode 760, insulating layer 774, fin 767, wiring 762, activation region 784, gate insulating film 775, gate electrode 776, N-type transistor 768, P-type transistor 769, and insulating layers 777, wiring 778, insulating layer 779, wiring 780, insulating layers 781 and 783 are the same as those of the substrate 173, wiring 163, insulating layer 174, fin 167, wiring 162, activation region 184, gate insulating film 175, through-electrode 160, insulating layer 174, fin 167, wiring 162, activation region 184, gate insulating film 175, gate electrode 176, N-type transistor 168, P-type transistor 169, insulating layer 177, wiring 178, insulating layer 179, wiring 180, insulating layers 181 and 183 described in "1-4. Overview of IC Chip 110". Therefore, each layer and wiring constituting the transistor layer 730 and the wiring layer 350 will be explained as necessary.

[0167] Furthermore, as described in "1-1-2. Overview of Semiconductor Chip Section 300," the IO die 700 includes a plurality of electrodes 782 exposed on the second surface 704, and a plurality of through electrodes 790 exposed on the first surface 702 and electrically connected to the electrodes 782. The plurality of electrodes 782 are formed to be embedded in the insulating layer 783. For example, the electrodes 782 may have a damascene structure, similar to the wiring 178 and wiring 180. The plurality of through electrodes 790 are provided to penetrate the insulating layers 783, 781, 779, 777 and 774, as well as the substrate 773.

[0168] [1-8. Overview of Semiconductor Module 10P] An overview of semiconductor module 10P, which includes a configuration different from that of semiconductor module 10 according to the first embodiment, will be described with reference to Figures 15 and 16, etc. Figure 15 is a perspective view showing the configuration of semiconductor module 10P. Figure 16 is an end view showing the cross-sectional structure of the end of semiconductor module 10P along the line P1-P2 shown in Figure 15. Configurations that are the same as or similar to those described in Figures 1 to 14 will be described as necessary.

[0169] As shown in Figures 15 and 16, the semiconductor module 10P includes a cube chip 100P, a semiconductor chip portion 300, and a package substrate 500. The semiconductor module 10P may also include, similar to the cube chip 100, a bump portion 800 for electrically connecting the cube chip 100P and the semiconductor chip portion 300, and a bump portion 400 for electrically connecting the semiconductor chip portion 300 and the package substrate 500.

[0170] The configurations and functions of the semiconductor chip section 300, package substrate 500, bump section 800, and bump section 400 in the semiconductor module 10P are the same as those of the semiconductor chip section 300, package substrate 500, bump section 800, and bump section 400 in the semiconductor module 10.

[0171] As shown in Figures 15 and 16, the semiconductor module 10P includes a configuration similar to that of the semiconductor module 10, but with the metal wiring layers 20F and 20D removed from the semiconductor module 10.

[0172] More specifically, the semiconductor module 10P differs from the semiconductor module 10 in at least the configurations P1 to P3 shown below, as well as the configurations related to configurations P1 to P3. (Configuration P1) The semiconductor module 10P includes a configuration in which the cube chip 100 in the semiconductor module 10 is replaced with a cube chip 100P. (Configuration P2) The cube chip 100P includes a configuration in which the stacked chip 30 in the cube chip 100 is replaced by a stacked chip 30P, and a configuration in which the metal wiring layers 20F and 20D are removed from the cube chip 100. In this case, the wiring 180 in the stacked chip 30P (each IC chip 110) is not exposed on the third surface 45 and the fourth surface 47, and the stacked chip 30P (each IC chip 110) does not include a plurality of side wirings 180F exposed on the third surface 45 and a plurality of side wirings 180B exposed on the fourth surface 47. As shown in Figure 5, the cube chip 100P includes a through electrode 160 that is electrically connected to the through electrode 260 in the computing die 200. (Configuration P3) The cube chip 100P includes a metal wiring layer 20D, and the stacked chip 30P is electrically connected to the metal wiring layer 20D.

[0173] The configurations of semiconductor module 10P other than configurations P1 to P3, and configurations other than those related to configurations P1 to P3, are the same as those of semiconductor module 10. Therefore, when describing semiconductor module 10P, configurations that are the same as or similar to those of semiconductor module 10 will be described as necessary. In addition, the configurations of semiconductor module 10P other than configurations P1 to P3, and configurations other than those related to configurations P1 to P3, include the same configurations and functions as those described with reference to Figures 4 to 14.

[0174] As shown in Figures 4 and 15, the first face 46, second face 48, third face 45, fourth face 47, fifth face 42, and sixth face 44 of the stacked chip 30P are parallel to the first face 146, second face 148, third face 145, fourth face 147, fifth face 142, and sixth face 144 of the cube chip 100P. Also, the second face 48 is the same face as the second face 148. The third faces 45 to the sixth face 44 and the third faces 145 to the sixth face 144 are the same faces as their corresponding faces, similar to the second face 48 and the second face 148.

[0175] Furthermore, as shown in Figures 4 and 15, the metal wiring layer 20D in the semiconductor module 10P is provided in contact with the first surface 46 and includes an insulating layer 21 and a wiring layer containing a plurality of wires 22. The insulating layer 21 is provided on the first surface 46 along the third direction and is provided in contact with the first surface 46. The wiring layer containing the plurality of wires 22 is provided in an array on the first surface 46. In addition, each of the plurality of wires 22 is provided on the corresponding side wiring 180D along the third direction D3 and is electrically connected to the corresponding side wiring 180D. The plurality of wires 22 included in the metal wiring layer 20D are exposed on the first surface 146 of the cube chip 100P. For example, the computing die 200 within the bonding chip 101 on the sixth surface 44 (sixth surface 144) side shown in Figure 5 is electrically connected to the bonding chip 101 and adjacent SRAM chips 110S and further adjacent SRAM chips 110S using multiple wirings 22 of the metal wiring layer 20D, and the computing die 200 within the bonding chip 101 on the fifth surface 42 (fifth surface 142) side shown in Figure 5 is electrically connected to the bonding chip 101 and adjacent DRAM chips 110D and further adjacent DRAM chips 110D using multiple wirings 22 of the metal wiring layer 20D.

[0176] In other words, the side wiring 180D within the IC chip 110 in the semiconductor module 10P is electrically connected to the wiring 22 in the metal wiring layer 20D on the outermost surface (first surface 146) side of the cube chip 100P along the third direction D3, and is exposed from the cube chip 100P. Therefore, multiple signals transmitted through each signal transmission wiring 166 within the IC chip 110, as well as the power supply voltage and reference voltage supplied to the power supply wiring 164 and ground wiring 165 within the cube chip 100P, are transmitted from the outermost surface (first surface 146) of the cube chip 100P to an external circuit connected to the cube chip 100P. In addition, signals transmitted from the external circuit are transmitted into the cube chip 100 from the outermost surface (first surface 146) of the cube chip 100.

[0177] Furthermore, each wiring within the cube chip 100P is electrically connected to each wiring within the semiconductor chip section 300 via the bump section 800 using the side wiring 180D and the metal wiring layer 20D electrically connected to the side wiring 180D. Therefore, multiple signals transmitted through each signal transmission wiring 166 within the cube chip 100P, as well as the power supply voltage and reference voltage supplied to the power supply wiring 164 and ground wiring 165 within the cube chip 100P, are transmitted via the bump section 800 to each wiring through which signals are transmitted within the semiconductor chip section 300, as well as to the power supply wiring and ground wiring. In addition, each wiring through which signals are transmitted within the semiconductor chip section 300, as well as the power supply wiring and ground wiring, are transmitted to each signal transmission wiring 166 within the cube chip 100P, as well as to the power supply wiring 164 and ground wiring 165, via the bump section 800 and the metal wiring layer 20D.

[0178] The number of wiring layers in the metal wiring layer 20D of the semiconductor module 10P can be adjusted as appropriate according to the specifications and application of the semiconductor module 10P, similar to the number of wiring layers in the metal wiring layer 20D of the semiconductor module 10.

[0179] Furthermore, the stacked chip 30P, like the stacked chip 30, includes a plurality of IC chips 110 stacked along the first direction D1, parallel to the plane formed by the second direction D2 perpendicular to the first direction D1, and the third direction D3 perpendicular to the second direction D2. The bump portion 800 in the semiconductor module 10P electrically connects the semiconductor chip portion 300 and the metal wiring layer 20D of the cube chip 100P. The semiconductor module 10P, like the cube chip 100 in the semiconductor module 10, includes a cube chip 100P vertically mounted on the bump portion 800 (semiconductor chip portion 300) parallel to the third direction D3 and perpendicular to the first direction D1 and the second direction D2. In other words, the semiconductor module 10P, like the semiconductor module 10, includes a configuration with low thermal resistance.

[0180] As explained above, the semiconductor module 10P includes the same configuration as the semiconductor module 10 and produces the same effects as the semiconductor module 10.

[0181] [2. Second Embodiment] A semiconductor module 10A according to the second embodiment will be described with reference to Figures 17 and 18. Figure 17 is a perspective view showing the configuration of the semiconductor module 10A. Figure 18 is an end view showing the end cross-sectional structure of the semiconductor module 10A along the line C1-C2 shown in Figure 17. The end cross-sectional structure of the semiconductor module 10A along the line intersecting the C1-C2 line (the plane parallel to the third direction D3 and the first direction D1) may be the same as the end cross-sectional structure shown in Figure 2. That is, the semiconductor module 10A may include metal wiring layers 20B, 20F, and 20D, similar to the semiconductor module 10. Furthermore, the end cross-sectional structure of the semiconductor module 10A along the line intersecting the C1-C2 line (the plane parallel to the third direction D3 and the first direction D1) may be the same as the end cross-sectional structure shown in Figure 16. That is, the semiconductor module 10A may include a metal wiring layer 20D, similar to the semiconductor module 10P. Configurations identical or similar to those in Figures 1 to 16 will be described as necessary.

[0182] The semiconductor module 10A includes a cube chip 100A, a semiconductor chip section 300, and a package substrate 500. The semiconductor module 10A may also include a bump section 800 that electrically connects the cube chip 100A and the semiconductor chip section 300, and a bump section 400 that electrically connects the semiconductor chip section 300 and the package substrate 500.

[0183] The configurations and functions of the semiconductor chip section 300, package substrate 500, bump section 800, and bump section 400 in semiconductor module 10A are the same as those of the semiconductor chip section 300, package substrate 500, bump section 800, and bump section 400 in semiconductor module 10. Therefore, when describing semiconductor module 10A, configurations that are the same as or similar to those of semiconductor module 10 will be described as necessary.

[0184] Cube chip 100A differs from cube chip 100 or 100P in at least one of the configurations shown below. (Configuration 1) Includes heatsink 60

[0185] The configurations of cube chip 100A other than configuration 1, and configurations other than those related to configuration 1, are the same as those of cube chip 100 or 100P. Therefore, when describing cube chip 100A, configurations that are the same as or similar to those of cube chips 100 and 100P will be described as necessary.

[0186] Heatsink 60 includes heatsinks 60U, 60R, and 60L.

[0187] The heatsink 60U is positioned along the third direction D3 so as to be in contact with the second surface 48 (second surface 148) of the stacked chip 30.

[0188] The heatsink 60R is positioned along the first direction D1 so as to be in contact with the fifth surface 42 (fifth surface 142) and the side surface of the heatsink 60U on the fifth surface 42 (fifth surface 142) side. The fifth surface 42 is the same surface as the second surface 204 (see Figure 5) of the computing die 200 of the stacked chip 30. Therefore, the heatsink 60R is in contact with the second surface of the computing die 200 on the fifth surface 42 side of the stacked chip 30 and is positioned on the second surface 204 of the computing die 200.

[0189] The heatsink 60L is positioned along the first direction D1 so as to be in contact with the sixth surface 44 (sixth surface 144) and the side surface of the heatsink 60U on the sixth surface 44 (sixth surface 144) side. The sixth surface 44 is the same surface as the second surface 204 (see Figure 5) of the computing die 200 of the stacked chip 30. Therefore, the heatsink 60L is in contact with the second surface of the computing die 200 on the sixth surface 44 side of the stacked chip 30 and is positioned on the second surface 204 of the computing die 200.

[0190] Since semiconductor module 10A includes the same configuration as semiconductor module 10, it produces the same effects and benefits as semiconductor module 10.

[0191] Furthermore, as described above, the semiconductor module 10A includes a heat sink 60, which covers the second surface 48, fifth surface 42, and sixth surface 44 of the stacked chip 30, and also sandwiches the fifth surface 42 and sixth surface 44 of the stacked chip 30. The heat sink 60 can dissipate (release) the heat generated within the semiconductor module 10. For example, the computing die 200 of the semiconductor module 10A includes a configuration that enables computational processing and is prone to generating heat. Therefore, the semiconductor module 10A, which includes a configuration in which the heat sink 60 is in contact with the computing die 200, has superior heat dissipation characteristics compared to a semiconductor module that does not include a heat sink.

[0192] The heat sink 60 according to the second embodiment includes three components (heat sinks 60U, 60L, and 60R), but the heat sink 60 may be composed of one component, two components, or three or more components. Furthermore, the heat sink 60 may be provided so as to be in contact with the third surface 45 and the fourth surface 47 of the laminated chip 30. The configuration of the heat sink 60 can be appropriately adjusted according to the application and specifications of the semiconductor module 10A.

[0193] [3. Third Embodiment] A semiconductor module 10B according to the third embodiment will be described with reference to Figures 19 and 20. Figure 19 is an end view showing the end cross-sectional structure of the semiconductor module 10B along a plane parallel to the third direction D3 and the second direction D2. Figure 20 is an end view showing the configuration around the first face 146 of the cube chip 100B shown in Figure 19. The end cross-sectional structure of the semiconductor module 10B along a plane parallel to the third direction D3 and the first direction D1 that intersects the plane parallel to the third direction D3 and the second direction D2 shown in Figure 19 may be the same as the end cross-sectional structure shown in Figure 2. That is, the semiconductor module 10B may include metal wiring layers 20B, 20F and 20D, similar to the semiconductor module 10. Furthermore, the semiconductor module 10B may have the same configuration as the semiconductor module 10P and may include a metal wiring layer 20D. Configurations identical or similar to those in Figures 1 to 18 will be described as necessary.

[0194] The semiconductor module 10B includes a cube chip 100B, a semiconductor chip section 300B, and a package substrate 500. The semiconductor module 10B may also include a bump section 800 that electrically connects the cube chip 100B and the semiconductor chip section 300B, and a bump section 400 that electrically connects the semiconductor chip section 300B and the package substrate 500.

[0195] The configurations and functions of the package substrate 500, bump section 800, and bump section 400 in semiconductor module 10B are the same as those of the package substrate 500, bump section 800, and bump section 400 in semiconductor module 10 or 10P. Therefore, when describing semiconductor module 10B, configurations that are the same as or similar to those of semiconductor module 10 or 10P will be described as necessary.

[0196] The semiconductor module 10B differs from the semiconductor module 10 or 10P in at least the configurations 2 to 4 shown below. (Configuration 2) The semiconductor chip section 300 includes a computing die 600 and an IO die 700 that are joined using F2B bonding, whereas the semiconductor chip section 300B includes a computing die 600 and an IO die 700 that are joined using F2F bonding. (Configuration 3) While cube chip 100 includes eight IC chips corresponding to two junction chips 101, two SRAM chips 110S, and two DRAM chips 110D, cube chip 100B includes eight IC chips corresponding to one junction chip 101B, two SRAM chips 110S, and four DRAM chips 110D. (Configuration 4) In cube chip 100, the SRAM chip 110S and the computing die 200 within the bonding chip 101 are electrically connected by B2B bonding through their respective through electrodes. In contrast, in cube chip 100B, the SRAM chip 110S and the computing die 200 within the bonding chip 101B are bonded B2B by an adhesive layer 103 and electrically connected using wiring 22 within the metal wiring layer 20D.

[0197] The configurations of semiconductor module 10B other than configurations 2 to 4, and configurations other than those related to configurations 2 to 4, are the same as those of semiconductor module 10 or 10P. Therefore, when describing semiconductor module 10B, configurations that are identical or similar to those of semiconductor module 10 or 10P will be described as necessary.

[0198] As shown in Figure 19, the computing die 600 in semiconductor module 10B is positioned on top of the IO die 700 with its first surface 602 facing downward along the third direction D3. That is, the computing die 600 in semiconductor module 10B is face-down mounted on the IO die 700, similar to the computing die 600 in semiconductor module 10.

[0199] In semiconductor module 10B, the second surface 704 of the IO die 700 is positioned to face the second surface 604 of the computing die 600, and is the surface that is joined to the second surface 604 of the computing die 600. In other words, the IO die 700 and the computing die 600 are joined via a two-to-one (F2F) joint. More specifically, each of the multiple electrodes 782 exposed on the second surface 704 of the IO die 700 is joined (stacked) to the corresponding multiple electrodes 682 exposed on the second surface 604 of the computing die 600. As a result, the IO die 700 and the computing die 600 are electrically connected.

[0200] Furthermore, the stacking direction of each layer constituting the IO die 700 is upward along the third direction D3. That is, in the semiconductor module 10B, each of the multiple through electrodes 760 and 790 exposed on the first surface 702 of the IO die 700 is electrically connected to the corresponding multiple electrodes 52 of the package substrate 500 via the corresponding multiple bumps 41. Thus, the IO die 700 is face-up mounted on the package substrate 500.

[0201] As an example, the semiconductor chip section 300B in the semiconductor module 10B is composed of two different IC chips 110 (two IC chips 110) for the computing die 600 and the IO die 700, similar to the semiconductor chip section 300 in the semiconductor module 10. However, the semiconductor chip section 300B may be composed of a single IC chip 110 that includes the functions and configuration of the computing die 600 and the functions and configuration of the IO die 700.

[0202] Furthermore, as shown in Figure 20, in the stacked chip 30B, from left to right in the drawing, the SRAM chip 110S and the computing die 200 are connected B2B via the adhesive layer 103, and the computing die 200 within the bonded chip 101 and the adjacent SRAM chip 110S are connected F2F via the adhesive layer 103. In other words, the computing die 200 is sandwiched between the SRAM chip 110S via the adhesive layer 103. In addition, adjacent SRAM chips 110S are connected F2B via the adhesive layer 103, the SRAM chip 110S and the DRAM chip 110D are connected F2B via the adhesive layer 103, the DRAM chips 110D are connected F2B via the adhesive layer 103, and the DRAM chips 110D are connected F2B via the adhesive layer 103, thus forming the stacked chip 30B.

[0203] For example, as shown in Figures 19 and 20, multiple wirings 22 contained in the metal wiring layer 20D are exposed to and in contact with the first surface 146 of the cube chip 100B.

[0204] Furthermore, the computing die 200 is electrically connected to the two SRAM chips 110S that sandwich the computing die 200, the next SRAM chip 110S, and the next four DRAM chips 110D using multiple wirings 22 in the metal wiring layer 20D. In addition, the computing die 200 is electrically connected to the semiconductor chip section 300B via multiple wirings 22 and multiple bumps 801 within the metal wiring layer 20D.

[0205] The number of IC chips 110 stacked in the stacked chip 30B is just one example, and the number of IC chips 110 stacked is not limited to eight (eight layers). Furthermore, the configuration of the multiple IC chips 110 is not limited to eight IC chips corresponding to one junction chip 101B, two SRAM chips 110S, and four DRAM chips 110D. The number of stacked IC chips 110 and their configuration may be appropriately selected based on the application and specifications of the semiconductor module 10B.

[0206] Since semiconductor module 10B includes the same configuration as semiconductor module 10, it produces the same effects and benefits as semiconductor module 10.

[0207] Furthermore, the semiconductor chip section 300B in the semiconductor module 10B includes a configuration in which the IO die 700 and the computing die 600 are joined using an F2F junction. As a result, the semiconductor chip section 300B is joined using an F2F junction, which is simpler than an F2B junction, which is one of the so-called hybrid junctions, and the manufacturing load in the manufacturing of the semiconductor chip section 300B can be reduced when manufacturing the semiconductor module 10A.

[0208] As an example, the IO die 700 and the computing die 600 in the semiconductor module 10B are connected by an F2F junction, but the connection between the IO die 700 and the computing die 600 is not limited to an F2F junction. For example, the IO die 700 and the computing die 600 may be electrically connected via a bump section similar to the bump section 800 or bump section 400. Alternatively, each of the IO die 700 and the computing die 600 may include an inductor, and the IO die 700 and the computing die 600 may be connected by contactless inductor communication.

[0209] [4. Fourth Embodiment] A semiconductor module 10C according to the fourth embodiment will be described with reference to Figures 21 and 22. Figure 21 is an end view showing the end cross-sectional structure of the semiconductor module 10C along a plane parallel to the third direction D3 and the second direction D2. Figure 22 is an end view showing the end cross-sectional structure of the computing die 600C according to the fourth embodiment. The end cross-sectional structure of the semiconductor module 10C along a plane parallel to the third direction D3 and the first direction D1 that intersects the plane parallel to the third direction D3 and the second direction D2 shown in Figure 21 may be the same as the end cross-sectional structure shown in Figure 2. That is, the semiconductor module 10C may include metal wiring layers 20B, 20F, and 20D, similar to the semiconductor module 10. Furthermore, the semiconductor module 10C may have the same configuration as the semiconductor module 10P and may include a metal wiring layer 20D. Configurations identical or similar to those in Figures 1 to 20 will be described as necessary.

[0210] The semiconductor module 10C includes a cube chip 100B, a semiconductor chip section 300C, and a package substrate 500. The semiconductor module 10C may also include a bump section 800 for electrically connecting the cube chip 100B and the semiconductor chip section 300C, and a bump section 400 for electrically connecting the semiconductor chip section 300C and the package substrate 500.

[0211] The configurations and functions of the cube chip 100B, package substrate 500, bump section 800, and bump section 400 in semiconductor module 10C are the same as those of the cube chip 100B, package substrate 500, bump section 800, and bump section 400 in semiconductor module 10B.

[0212] The semiconductor module 10C differs from the semiconductor module 10B in at least configurations 5 and 6 shown below. (Configuration 5) The semiconductor chip section 300B includes a configuration in which the computing die 600 is provided on the IO die 700 and is joined F2F along the third direction D3, whereas the semiconductor chip section 300B also includes a configuration in which the IO die 700 is provided on the computing die 600C and is joined F2F along the third direction D3. (Configuration 6) The computing die 600C includes a lower wiring layer 610, which is a wiring layer for so-called backside power delivery (BPD).

[0213] The configurations of semiconductor module 10C other than configurations 5 and 6, and configurations other than those related to configurations 5 and 6, are the same as those of semiconductor module 10B. Therefore, when describing semiconductor module 10C, configurations that are the same as or similar to those of semiconductor module 10B will be described as necessary.

[0214] As shown in Figure 21, in the semiconductor chip portion 300C, the IO die 700 has multiple through electrodes 760 and 790 exposed on the first surface 702, each of which is electrically connected to a corresponding number of wirings 22 in the metal wiring layer 20D of the cube chip 100B via a corresponding number of bumps 801. Thus, the IO die 700 is electrically connected to the cube chip 100B, and the cube chip 100B is vertically mounted on the IO die 700.

[0215] Furthermore, the IO die 700 in the semiconductor chip section 300C is positioned on top of the computing die 600C with its second surface 704 facing downward along the third direction D3. In other words, the IO die 700 is face-down mounted on the computing die 600C.

[0216] The computing die 600C includes a configuration in which a lower wiring layer 610, a transistor layer 630, and a wiring layer 650 are stacked in this order along a third direction D3, and includes a first surface 602 parallel to the first direction D1 and the second direction D2, and a second surface 604 opposite to the first surface 602. The first surface 602 is the surface on which the lower wiring layer 610 is exposed. The second surface 604 is the surface on which the wiring layer 650 is exposed.

[0217] As will be described in detail later, the lower wiring layer 610 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked, and the wiring includes a plurality of wirings 628 and a plurality of electrode pads 620. Each of the plurality of wirings 628 is electrically connected to each of the corresponding plurality of electrodes 682 and plurality of through electrodes 690 exposed on the second surface 604. In addition, each of the plurality of wirings 628 is electrically connected to the plurality of electrode pads 620 exposed on the first surface 602 by the plurality of wirings within the lower wiring layer 610.

[0218] The second surface 604 of the computing die 600C in the semiconductor chip section 300C is positioned to face the second surface 704 of the IO die 700, and is the surface that is joined to the second surface 704 of the IO die 700. In other words, the computing die 600C and the IO die 700 are joined via a two-to-one (F2F) connection. More specifically, each of the corresponding electrodes 682 and through-electrodes 690 exposed on the second surface 604 of the computing die 600C is joined (stacked) to the corresponding electrodes 782 exposed on the second surface 704 of the IO die 700. As a result, the computing die 600C and the IO die 700 are electrically connected.

[0219] Furthermore, each of the multiple electrode pads 620 exposed on the first surface 602 of the computing die 600C is electrically connected to the corresponding multiple electrodes 52 of the package substrate 500 via the corresponding multiple bumps 41.

[0220] As an example, the semiconductor chip section 300C in the semiconductor module 10C is composed of two different IC chips 110 (two IC chips 110) for the IO die 700 and the computing die 600C. However, the semiconductor chip section 300C may be composed of a single IC chip 110 that includes the functions and configuration of the IO die 700 and the functions and configuration of the computing die 600C.

[0221] As shown in Figure 22, the transistor layer 630 and the wiring layer 650 have the same configuration as shown in Figure 13.

[0222] The lower wiring layer 610 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. For example, the lower wiring layer 610 includes electrode pads 620, 621, 622, insulating layer 623, through-electrode 624, 625, 626, insulating layer 627, wiring 628, and insulating layer 629. The number of layers of multilayer wiring in the lower wiring layer 610 is not limited to the configuration shown in Figure 22. The number of layers of multilayer wiring in the lower wiring layer 610 may be three or more. The number of layers of multilayer wiring in the lower wiring layer 610 can be appropriately changed depending on the specifications and application of the semiconductor module 10C.

[0223] As mentioned above, the lower wiring layer 610 is a wiring layer for a so-called BPD. BPD is a technology used in the field of semiconductor module technology, and a detailed explanation will be omitted here. Briefly, it is a technology that separates the supply of signals (data), power supply voltage, and voltage on the second side 604 and the first side 602 of the substrate 673, respectively. For example, by using a BPD, it becomes possible to scale the metal wiring connections inside the semiconductor module 10C, simplifying complex metal wiring patterning and reducing the manufacturing cost of the semiconductor module 10C.

[0224] The through-electrode 660 is electrically connected to the wiring 663, which is a so-called embedded wiring. For example, the through-electrodes 660 and 690 are electrically connected to the wiring 628 of the second layer, counting from the first surface 602 side. The second layer wiring 628 is electrically connected to the electrode pad 622 using, for example, multiple through-electrodes 626. Furthermore, the second layer wiring 628 is electrically connected to the electrode pad 621 using multiple through-electrodes 625, and also electrically connected to the electrode pad 620 using multiple through-electrodes 624.

[0225] For example, voltage VDD is supplied from an external circuit to electrode pad 621, voltage VSS is supplied from an external circuit to electrode pad 622, and signal (data) is supplied from an external circuit to electrode pad 620. As a result, signal (data), voltage VDD and voltage VSS are supplied from the external circuit to through electrodes 626, 625 and 624 via the electrode pads, and into the semiconductor chip section 300C, including the computing die 600C, and the cube chip 100B. Electrode pads 620, 621 and 622 are the first layer of wiring when counted from the first surface 602 side.

[0226] As described above, the semiconductor module 10C includes the same configuration as semiconductor modules 10, 10P, or 10B, and therefore produces the same effects and performance as semiconductor module 10.

[0227] [5. Fifth Embodiment] A semiconductor module 10D according to the fifth embodiment will be described with reference to Figures 23 and 24. Figure 23 is an end view showing the end cross-sectional structure of the semiconductor module 10D along a plane parallel to the third direction D3 and the second direction D2. Figure 24 is an end view showing the end cross-sectional structure of the computing die 600C according to the fifth embodiment. The end cross-sectional structure of the semiconductor module 10D along a plane parallel to the third direction D3 and the first direction D1 that intersects the plane parallel to the third direction D3 and the second direction D2 shown in Figure 23 may be the same as the end cross-sectional structure shown in Figure 2. That is, the semiconductor module 10D may include metal wiring layers 20B, 20F, and 20D, similar to the semiconductor module 10. Furthermore, the end cross-sectional structure of the semiconductor module 10D along a plane parallel to the third direction D3 and the first direction D1 that intersects the plane parallel to the third direction D3 and the second direction D2 shown in Figure 23 may be the same as the end cross-sectional structure shown in Figure 16. In other words, the semiconductor module 10D may include a metal wiring layer 20D, similar to the semiconductor module 10P. Configurations identical or similar to those in Figures 1 to 22 will be described as necessary.

[0228] The semiconductor module 10D includes a cube chip 100D, a semiconductor chip section 300D, and a package substrate 500. The semiconductor module 10D may also include a bump section 800 that electrically connects the cube chip 100D and the semiconductor chip section 300D, and a bump section 400 that electrically connects the semiconductor chip section 300D and the package substrate 500.

[0229] The configuration and function of the package substrate 500, bump portion 800, and bump portion 400 in semiconductor module 10D are the same as those of the package substrate 500, bump portion 800, and bump portion 400 in semiconductor module 10C.

[0230] The semiconductor module 10D differs from the semiconductor module 10C in at least configurations 7 and 8 shown below. (Configuration 7) In cube chip 100C (cube chip 100B), the SRAM chip 110S within the bonded chip 101B and the computing die 200 are bonded B2B by an adhesive layer 103 and electrically connected using wiring 22 within the metal wiring layer 20D, with the second face 104 of the SRAM chip 110S being the sixth face 144. In contrast, in cube chip 100D, the SRAM chip 110S within the bonded chip 101D and the computing die 200 are electrically connected by B2B bonding through electrodes, with the second face 104 of the computing die 200 being the sixth face 144. (Configuration 8) The semiconductor chip section 300C includes a configuration in which two IC chips 110 of a computing die 600C, which includes an IO die 700 and a lower wiring layer 610 for the BPD, are joined F2F, whereas the semiconductor chip section 300D includes a single IC chip 110 of a computing die 600D, which has the configuration and functions of an IO die and a computing die and includes a lower wiring layer 610 for the BPD.

[0231] The configurations of semiconductor module 10D other than configurations 7 and 8, and configurations other than those related to configurations 7 and 8, are the same as those of semiconductor module 10B or 10C. Therefore, when describing semiconductor module 10D, configurations that are identical or similar to those of semiconductor module 10B or 10C will be described as necessary.

[0232] The stacked structure of the Computing Die 600D is the same as that of the Computing Die 600C.

[0233] As shown in Figure 23, the second surface 604 of the computing die 600D in the semiconductor chip portion 300D is positioned to face the metal wiring layer 20D of the cube chip 100D and is electrically connected to the cube chip 100D via the bump portion 800. More specifically, each of the multiple electrodes 682 and multiple through electrodes 690 exposed on the second surface 604 of the computing die 600D is electrically connected to the corresponding multiple wirings 22 in the metal wiring layer 20D of the cube chip 100D via the corresponding multiple bumps 801. Thus, the cube chip 100D is vertically mounted on the semiconductor chip portion 300D.

[0234] Furthermore, each of the multiple electrode pads 620 exposed on the first surface 602 of the computing die 600D is electrically connected to the corresponding multiple electrodes 52 of the package substrate 500 via the corresponding multiple bumps 41.

[0235] As shown in Figure 24, the stacked chip 30D is configured such that, from left to right in the drawing, the second surface 104 of the computing die 200 within the bonded chip 101D is the sixth surface 144, the SRAM chip 110S and the computing die 200 within the bonded chip 101D are electrically connected by B2B bonding using their respective through electrodes 260 and 160, the SRAM chip 110S within the bonded chip 101D and adjacent SRAM chip 110S are connected F2F via the adhesive layer 103, adjacent SRAM chips 110S are connected F2B via the adhesive layer 103, the SRAM chip 110S and DRAM chip 110D are connected F2B via the adhesive layer 103, the DRAM chips 110D are connected F2B via the adhesive layer 103, and the DRAM chips 110D are connected F2B via the adhesive layer 103.

[0236] The computing die 200 may be electrically connected to two SRAM chips 110S and four DRAM chips 110D, which are positioned at a distance from the computing die 200, using multiple wirings 22 of the metal wiring layer 20D.

[0237] The number of IC chips 110 stacked in the stacked chip 30D is just one example, and the number of IC chips 110 stacked is not limited to eight (eight layers). Furthermore, the configuration of the multiple IC chips 110 is not limited to eight IC chips corresponding to one junction chip 101D, two SRAM chips 110S, and four DRAM chips 110D. The number of stacked IC chips 110 and their configuration may be appropriately selected based on the application and specifications of the semiconductor module 10B.

[0238] Furthermore, since the computing die 200 and the SRAM chip 110S within the junction chip 101D are electrically connected by a B2B junction, which is a type of hybrid junction, the computing die 200 and the SRAM chip 110S can transmit signals (data) over a wide bandwidth.

[0239] As described above, the semiconductor module 10D includes the same configuration as semiconductor module 10B or 10C, and therefore produces the same effects and performance as semiconductor module 10B or 10C.

[0240] Furthermore, the cube chip 100D in the semiconductor module 10D may be configured to be replaceable with any one of the cube chips 100, 100P, 100A, 100B, or 100C as appropriate, and the semiconductor chip section 300D in the semiconductor module 10D may be configured to be replaceable with any one of the semiconductor chip sections 300, 300B, or 300C as appropriate.

[0241] [6. Sixth Embodiment] A semiconductor module 10E according to the sixth embodiment will be described with reference to Figure 25. Figure 25 is an end view showing the cross-sectional structure of the end of the cube chip 100E of the semiconductor module 10E. Configurations identical or similar to those in Figures 1 to 24 will be described as necessary.

[0242] The semiconductor module 10E includes a configuration in which the cube chip 100D in the semiconductor module 10D is replaced with cube chip 100E. The configurations of the semiconductor module 10E other than the cube chip 100E and the configurations related to the cube chip 100E are the same as those of the semiconductor module 10D. Therefore, when describing the semiconductor module 10E, configurations that are identical or similar to those of the semiconductor module 10D will be described as necessary.

[0243] As shown in Figure 25, the stacked chip 30E is configured such that, from left to right in the drawing, the second surface 202 of the computing die 200E within the bonded chip 101E is the sixth surface 144, the SRAM chip 110SE and the computing die 200E within the bonded chip 101E are connected by inductor communication using multiple inductors 270 and 170, the SRAM chip 110SE and the adjacent SRAM chip 110S within the bonded chip 101E are connected F2F via the adhesive layer 103, adjacent SRAM chips 110S are connected F2B via the adhesive layer 103, the SRAM chip 110S and the DRAM chip 110D are connected F2B via the adhesive layer 103, the DRAM chips 110D are connected F2B via the adhesive layer 103, and the DRAM chips 110D are connected F2B via the adhesive layer 103.

[0244] The stacked structure of the computing die 200E is similar to the stacked structure of the computing die 200 shown in Figure 12. For example, the multiple inductors 270 may be provided spaced apart from the second surface 204 and formed using wiring 280, or they may be formed on the same layer as the wiring 280 using different wiring.

[0245] The stacked structure of the SRAM chip 110SE is similar to the stacked structure of the IC chip 110 shown in Figure 11. For example, the multiple inductors 170 are provided spaced apart from the second surface 104 and may be formed using wiring 180, or they may be formed on the same layer as wiring 180 using wiring different from wiring 180.

[0246] For example, among the plurality of inductors 170 and the plurality of inductors 370, one opposing inductor 170 and one opposing inductor 370 are magnetically coupled, whereby the respective inductors can perform one-to-one non-contact communication. Communication between the respective inductors accompanying the magnetic coupling is referred to as, for example, inductor communication, signal communication, data communication, or the like.

[0247] Further, the computing die 200E may be electrically connected to two SRAM chips 110S and four DRAM chips 110D that are arranged apart from the computing die 200 by using the plurality of wirings 22 of the metal wiring layer 20D.

[0248] Note that the number of stacked layers of the plurality of IC chips 110 in the stacked chip 30E is an example, and the number of stacked layers of the IC chips 110 is not limited to 8 (8 layers). Further, the configuration of the plurality of IC chips 110 is not limited to 8 IC chips corresponding to one bonded chip 101E, two SRAM chips 110S, and four DRAM chips 110D. The number of stacked layers and the configuration of the IC chips 110 may be appropriately selected based on the application, specifications, and the like of the semiconductor module 10B.

[0249] The semiconductor module 10E described above includes the same configuration as the semiconductor module 10D, and thus exhibits the same operational effects as the semiconductor module 10D.

[0250] Note that, similarly to the cube chip 100D, the cube chip 100E may be replaced with any one of the cube chips 100, 100P, 100A, 100B, or 100C.

[0251] [7. Seventh Embodiment] A semiconductor module 10F according to a seventh embodiment will be described with reference to FIG. 26. FIG. 26 is an end view showing an end cross-sectional structure in a mounting example of the semiconductor module 10F. Configurations identical or similar to those in FIGS. 1 to 25 will be described as necessary.

[0252] The semiconductor module 10F includes a cube chip 100F, a semiconductor chip portion 300, a package substrate 500, a conductive film 903, a conductive film 904, and a voltage supply unit 900. The semiconductor module 10F may include a bump portion 800 that electrically connects the cube chip 100F and the semiconductor chip portion 300, and a bump portion 400 that electrically connects the semiconductor chip portion 300 and the package substrate 500.

[0253] The respective configurations and functions of the package substrate 500, the bump portion 800, and the bump portion 400 in the semiconductor module 10F are the same as the respective configurations and functions of the package substrate 500, the bump portion 800, and the bump portion 400 in the semiconductor module 10.

[0254] The semiconductor module 10F differs from the semiconductor module 10 at least in Configuration 9 to Configuration 12 shown below. (Configuration 9) Includes a configuration in which the cube chip 100 in the semiconductor module 10 and the stacked chip 30 in the cube chip 100 are replaced with the cube chip 100F and the stacked chip 30F in the cube chip 100F. (Configuration 10) The cube chip 100F further includes a wiring layer including a plurality of wirings 26 embedded in the insulating layer 25, in addition to the configurations of the metal wiring layers 20B and 20F in the cube chip 100. (Configuration 11) The stacked chip 30F further includes a power supply wiring 164 exposed on the third surface 45 and the fourth surface 47, in addition to the side surface wirings 180B and 180F exposed on the third surface 45 and the fourth surface 47 in the stacked chip 30. (Configuration 12) Includes the conductive film 903, the conductive film 904, and the voltage supply unit 900.

[0255] Configurations other than Configuration 9 to Configuration 12 in the semiconductor module 10F and configurations other than those related to Configuration 9 to Configuration 12 are the same as the configurations of the semiconductor module 10. Therefore, in describing the semiconductor module 10F, configurations that are the same as or similar to those of the semiconductor module 10 will be described as necessary.

[0256] As described in configurations 9 to 11, the semiconductor module 10F includes a cube chip 100F. The cube chip 100F includes metal wiring layers 20B, 20F, and 20D similar to those of the cube chip 100. However, the metal wiring layers 20B and 20F of the cube chip 100F include wiring layers containing multiple wirings 26 embedded in the insulating layer 25.

[0257] Furthermore, as described in configurations 9 to 11, the cube chip 100F includes a stacked chip 30F. The stacked chip 30F includes side wiring 180F and power wiring 164 exposed on the third face 45, and side wiring 180B and power wiring 164 exposed on the fourth face 47.

[0258] For example, the power wiring 164 exposed on the third surface 45 and the power wiring 164 exposed on the fourth surface 47 are formed in the same layer as the side wiring 180F exposed on the third surface 45 and the side wiring 180B exposed on the fourth surface 47. For example, the end section structure shown in Figure 11 extends front to back toward the plane of the paper, and the third surface 45 and the fourth surface 47 are the end faces of the end section structure that extends front to back toward the plane of the paper, and the side wiring 180F and power wiring 164, and the side wiring 180B and power wiring 164 are exposed on these end faces.

[0259] Furthermore, as described in configuration 12, the semiconductor module 10F includes a conductive film 903, a conductive film 904, and a voltage supply unit 900.

[0260] For example, conductive films 903 and 904 are formed by electroplating (plating method). For example, conductive film 903 contains a conductor made of metal, specifically a conductor containing copper, silver, nickel, etc. For example, conductive film 904 contains a conductor made of metal, specifically a conductor containing gold, tin, nickel, etc.

[0261] As shown in Figure 26, the voltage supply unit 900 includes a support unit 901 which contains a plurality of pogo pins 902. The support unit 901 has the function of supporting the plurality of pogo pins 902. For example, each of the plurality of pogo pins 902 is a connector consisting of a terminal portion, a cylindrical member connected to the terminal portion, and an elastic member inserted through the cylindrical member. The voltage supply unit 900 may also be referred to as a pogo pin crimping mechanism.

[0262] The semiconductor module 10F can supply power to the cube chip 100F using the voltage supply unit 900.

[0263] As an example, the path by which the voltage supply unit 900 supplies power to the power wiring 164 exposed on the third surface 45 will be described. The path by which the voltage supply unit 900 supplies power to the power wiring 164 exposed on the fourth surface 47 is the same as the path by which it supplies power to the power wiring 164 exposed on the third surface 45.

[0264] For example, the power supply wiring 164 exposed on the third surface 45 and the fourth surface 47 is electrically connected to the wiring within the SRAM chip 110S, the DRAM chip 110D, and the computing die 200. The power supply wiring 164 exposed on the third surface 45 is electrically connected to the wiring 22, 24, and 26 of the metal wiring layer 20F.

[0265] The conductive film 903 is provided on the wiring 26 and the insulating layer 25 of the metal wiring layer 20F so as to be in contact with the wiring 26 and the insulating layer 25. The conductive film 904 is provided on the conductive film 903 so as to be in contact with the conductive film 903.

[0266] The voltage supply unit 900 crimps each of the multiple pogo pins 902 to the conductive film 904 and connects them to the conductive film 904. For example, each of the multiple pogo pins 902 is crimped to a metal film or the like and comes into contact with the metal film. At this time, each of the multiple pogo pins 902 comes into contact with the metal film due to the expansion and contraction of the elastic member.

[0267] As a result, the voltage supply unit 900 can supply voltage (e.g., voltage VDD) to multiple pogo pins 902 from an external source, and supply power to the power supply wiring 164 (i.e., the cube chip 100F) via the multiple pogo pins 902. In other words, the cube chip 100F is sandwiched between the voltage supply unit 900 and power is supplied directly from the voltage supply unit 900 without going through other circuits. Therefore, large fluctuations in the power supply voltage inside the semiconductor module 10F are suppressed, and the power supply voltage inside the semiconductor module 10F is stabilized, enabling good signal transmission.

[0268] Furthermore, since the semiconductor module 10F is supplied with power from a voltage supply unit 900 electrically connected to the third surface 45 (third surface 145) and the fourth surface 47 (fourth surface 147), several of the multiple wirings 22 exposed on the first surface 46 (first surface 146) that were previously used for power supply voltage can be used for signal transmission. Therefore, among the multiple input / output pins of the semiconductor module 10F, input / output pins electrically connected to the power supply voltage wiring can be used as input / output pins electrically connected to the signal transmission wiring. As a result, the number of signal transmission wirings in the semiconductor module 10F can be increased.

[0269] Furthermore, the semiconductor module 10F described above includes a configuration in which the cube chip 100F is vertically mounted on the semiconductor chip section 300. Compared to a configuration in which multiple IC chips and logic chips are stacked in parallel, the distance between each IC chip 110 within the cube chip 100F and the semiconductor chip section 300 can be kept close and constant. Therefore, the semiconductor module 10F can suppress the increase in wiring resistance due to wiring routing and the increase in parasitic capacitance, thereby realizing a low-power, high-capacity memory.

[0270] As described above, the semiconductor module 10F includes the same configuration as the semiconductor module 10, and therefore produces the same effects and benefits as the semiconductor module 10.

[0271] As an example, the voltage supply unit 900 shown in FIG. 26 illustrates an example in which a power supply voltage is supplied from the outside to the plurality of pogo pins 902, but the voltage supply unit 900 may supply a voltage other than the power supply voltage (for example, a reference voltage such as voltage VSS).

[0272] Further, the conductive film 903, the conductive film 904, and the voltage supply unit 900 in the semiconductor module 10F may be applied to the semiconductor modules 10, 10A, 10B, 10C, 10D, or 10E within an applicable range without departing from the semiconductor modules 10, 10A, 10B, 10C, 10D, or 10E.

[0273] [8. Eighth Embodiment] A semiconductor module 10G according to the eighth embodiment will be described with reference to FIG. 27. FIG. 27 is an end view showing an end cross-sectional structure in an implementation example of the semiconductor module 10G. Configurations identical or similar to those in FIGS. 1 to 26 will be described as necessary.

[0274] The semiconductor module 10G includes a configuration in which the voltage supply unit 900 in the semiconductor module 10F is replaced with an L-shaped member 905. Configurations of the semiconductor module 10G other than the L-shaped member 905, and configurations other than the configurations related to the L-shaped member 905, are the same as the configurations of the semiconductor module 10F. Therefore, in describing the semiconductor module 10G, configurations identical or similar to those of the semiconductor module 10F will be described as necessary.

[0275] The semiconductor module 10G can supply power to the cube chip 100F using the L-shaped member 905. For example, the L-shaped member 905 includes a conductor made of metal, and includes a conductor containing copper or the like.

[0276] As an example, a path through which the L-shaped member 905 supplies power to the power supply wiring 164 exposed on the third surface 45 will be described. The path through which the L-shaped member 905 supplies power to the power supply wiring 164 exposed on the fourth surface 47 is the same as the path through which power is supplied to the power supply wiring 164 exposed on the third surface 45.

[0277] The L-shaped member 905 is in contact with the conductive film 904 and is electrically connected to it.

[0278] As a result, the L-shaped member 905 can receive a voltage (e.g., voltage VDD) from an external source and supply power to the power wiring 164 (i.e., the cube chip 100F) via the conductive films 904 and 903.

[0279] As described above, the semiconductor module 10G includes the same configuration as the semiconductor module 10F, and therefore produces the same effects and benefits as the semiconductor module 10F.

[0280] As an example, the L-shaped member 905 shown in Figure 27 is shown as an example where the power supply voltage is supplied from an external source, but the L-shaped member 905 may also supply a voltage other than the power supply voltage (for example, a reference voltage such as voltage VSS). The L-shaped member 905 may be referred to as the voltage supply unit.

[0281] Furthermore, the conductive film 903, conductive film 904, and L-shaped member 905 in the semiconductor module 10G may be applied to semiconductor modules 10, 10A, 10B, 10C, 10D, or 10E to the extent that they are applicable without departing from the semiconductor modules 10, 10A, 10B, 10B, 10C, 10D, or 10E.

[0282] [9. Ninth Embodiment] The semiconductor module 10H according to the ninth embodiment will be described with reference to Figure 28. Figure 28 is an end view showing the end cross-sectional structure in an example of the semiconductor module 10H being mounted. Configurations identical or similar to those in Figures 1 to 27 will be described as necessary.

[0283] The semiconductor module 10H includes a configuration in which the voltage supply unit 900 in the semiconductor module 10F is replaced with a flexible substrate 906. The configuration of the semiconductor module 10H other than the flexible substrate 906, and the configuration other than those related to the flexible substrate 906, are the same as those of the semiconductor module 10F. Therefore, when describing the semiconductor module 10H, configurations that are identical or similar to those of the semiconductor module 10F will be described as necessary.

[0284] The semiconductor module 10H can supply power to the cube chip 100F using the flexible substrate 906.

[0285] As an example, the path by which the flexible circuit board 906 supplies power to the power wiring 164 exposed on the third surface 45 will be described. The path by which the flexible circuit board 906 supplies power to the power wiring 164 exposed on the fourth surface 47 is the same as the path by which it supplies power to the power wiring 164 exposed on the third surface 45.

[0286] The flexible substrate 906 is in contact with the conductive film 904 and is electrically connected to it.

[0287] As a result, the flexible substrate 906 can receive a voltage (e.g., voltage VDD) from an external source and supply power to the power wiring 164 (i.e., the cube chip 100F) via the conductive films 904 and 903.

[0288] As described above, the semiconductor module 10H includes the same configuration as the semiconductor module 10F, and therefore produces the same effects and benefits as the semiconductor module 10F.

[0289] As an example, the flexible circuit board 906 shown in Figure 28 is shown as one in which the power supply voltage is supplied from an external source. However, the flexible circuit board 906 may also be supplied with a voltage other than the power supply voltage (for example, a reference voltage such as voltage VSS). The flexible circuit board 906 may sometimes be referred to as the voltage supply unit.

[0290] Furthermore, the conductive film 903, conductive film 904, and flexible substrate 906 in the semiconductor module 10H may be applied to semiconductor modules 10, 10A, 10B, 10C, 10D, or 10E to the extent that they are applicable without departing from the semiconductor modules 10, 10A, 10B, 10B, 10C, 10D, or 10E.

[0291] [10. Tenth Implementation] A semiconductor module 10I according to the tenth embodiment will be described with reference to Figure 29. Figure 29 is an end view showing the end cross-sectional structure in an example of the semiconductor module 10I's mounting. Configurations identical or similar to those in Figures 1 to 28 will be described as necessary.

[0292] The semiconductor module 10I includes a cube chip 100I, a semiconductor chip section 300, a package substrate 500, side power wiring 907L, side ground wiring 907R, conductive layers 908L and 908R, and heat spreaders 909L and 909R. The semiconductor module 10I may also include a bump section 800 that electrically connects the cube chip 100I and the semiconductor chip section 300, and a bump section 400 that electrically connects the semiconductor chip section 300 and the package substrate 500.

[0293] The configuration and function of the package substrate 500, bump portion 800, and bump portion 400 in the semiconductor module 10I are the same as those of the package substrate 500, bump portion 800, and bump portion 400 in the semiconductor module 10 or 10P.

[0294] The semiconductor module 10I differs from the semiconductor module 10 or 10P in at least the configurations 13 to 15 shown below. (Configuration 13) Includes a configuration in which the cube chip 100 or 100P in the semiconductor module 10 or 10P, and the stacked chip 30 or 30P in the cube chip 100 or 100P are replaced with the cube chip 100I and the stacked chip 30I in the cube chip 100I. (Configuration 14) The stacked chip 30I has power wiring 164 exposed on the second surface 48 of each of the two computing dies 200, the SRAM chip 110S that is joined to the computing die 200, and the other of the two computing dies 200, the SRAM chip 110S that is joined to the other computing die 200, and the two DRAM chips 110D. (Configuration 15) Includes side power wiring 907L, side ground wiring 907R, conductive layers 908L and 908R, and heat spreaders 909L and 909R.

[0295] The configurations of semiconductor module 10I other than configurations 13 to 15, and configurations other than those related to configurations 13 to 15, are the same as those of semiconductor module 10. Therefore, when describing semiconductor module 10I, configurations that are the same as or similar to those of semiconductor module 10 will be described as necessary.

[0296] As described in configuration 13, the semiconductor module 10I includes a cube chip 100I. The cube chip 100I includes a stacked chip 30I.

[0297] As described in Configuration 14 and shown in Figure 29, the stacked chip 30I includes the following configuration. In the stacked chip 30I, from left to right in the drawing, the second surface 204 of the computing die 200 within one of the bonded chips 101 (see Figure 2) is the sixth surface 44, and power wiring 164 is exposed on the second surface 48 side of the computing die 200. Power wiring 164 is also exposed on the second surface 48 side of the SRAM chip 110S adjacent to the computing die 200 within the bonded chip 101, and power wiring 164 is also exposed on the second surface 48 side of each of the two SRAM chips 110S located next to it. The configuration includes a configuration in which a ground wire 165 is exposed on the second surface 48 side of two DRAM chips 110D located next to it, a power supply wire 164 is exposed on the second surface 48 side of an SRAM chip 110S adjacent to a computing die 200 within the other junction chip 101 (see Figure 2), and the second surface 204 of the computing die 200 within the other junction chip 101 (see Figure 2) is the fifth surface 42, and the power supply wire 164 is exposed on the second surface 48 side of the computing die 200.

[0298] Multiple power wirings 164 exposed on the second surface 48 are electrically connected to the side power wiring 907L. The heat spreader 909L is electrically connected to the conductive layer 908L, and through the conductive layer 908L, is electrically connected to the side power wiring 907L.

[0299] Similar to the multiple power wirings 164 exposed on the second surface 48, the multiple grounding wirings 165 exposed on the second surface 48 are electrically connected to the side grounding wiring 907R. The heat spreader 909R is electrically connected to the conductive layer 908R, and through the conductive layer 908R, is electrically connected to the side grounding wiring 907R.

[0300] For example, conductive layers 908L and 908R are solder. Heat spreaders 909L and 909R may be referred to as thermal conductive materials. The semiconductor module 10I may include a heat sink (not shown in the figure), and may also include 909L and 909R on which the heat sink is located.

[0301] As described above, the semiconductor module 10I includes a configuration in which the power supply wiring 164 and the heat spreader 909L are electrically connected, and the voltage VDD for driving the semiconductor module 10I is supplied to the power supply wiring 164 via the heat spreader 909L. Also, as described above, the semiconductor module 10I includes a configuration in which the ground wiring 165 and the heat spreader 909R are electrically connected, and the voltage VSS for driving the semiconductor module 10I is supplied to the ground wiring 165 via the heat spreader 909R.

[0302] For example, the upper limit T of the operating temperature of the SRAM chip 110S and the DRAM chip 110D jmaxm The upper limit of the operating temperature T of the computing die 200. jmaxr Lower. For example, upper limit T jmaxm It is approximately 85°C, and the upper limit T jmaxr The temperature is approximately 125°C. In other words, if the heat generated by the computing die 200 is transferred to the SRAM chip 110S and DRAM chip 110D, there is a risk that the cube chip 100I may not function properly.

[0303] The semiconductor module 10I includes heat spreaders 909L and 909R, which supply voltage to drive the semiconductor module 10I and dissipate heat generated within the semiconductor module 10I to the outside. Furthermore, the semiconductor module 10I includes a configuration in which a cube chip 100I is vertically mounted on the semiconductor chip section 300, and has a configuration that has superior heat dissipation characteristics compared to a configuration in which multiple IC chips and logic chips are stacked in parallel.

[0304] Therefore, the semiconductor module 10I has a configuration that can suppress malfunctions due to heat and can operate stably. Furthermore, because malfunctions due to heat are suppressed in the semiconductor module 10I, the thermal design of each circuit and element within the semiconductor module 10I can be simplified.

[0305] As described above, the semiconductor module 10I includes the same configuration as semiconductor module 10 or 10P, and therefore provides the same effects and benefits as semiconductor module 10 or 10P. Furthermore, the configuration of semiconductor module 10I may be applied to semiconductor modules 10A, 10B, 10C, 10D, or 10E to the extent that it is applicable without departing from semiconductor modules 10A, 10B, 10C, 10D, or 10E.

[0306] [11. Eleventh Embodiment] A semiconductor module 10J according to the 11th embodiment will be described with reference to Figures 30 and 31. Figure 30 is a perspective view showing the configuration of the semiconductor module 10J. Figure 31 is an end view showing the cross-sectional structure of the end of the semiconductor module 10J along the line E1-E2 shown in Figure 30. Configurations identical or similar to those in Figures 1 to 29 will be described as necessary.

[0307] As shown in Figure 30, the semiconductor module 10J includes a cube chip 100J, a semiconductor chip portion 300, a package substrate 500, a conductive film 903, a conductive film 904, a conductive film 907, a conductive film 908, a heat spreader 909, a heat spreader 910, and a resin 911. The semiconductor module 10J may include a bump portion 800 that electrically connects the cube chip 100J and the semiconductor chip portion 300, and a bump portion 400 that electrically connects the semiconductor chip portion 300 and the package substrate 500.

[0308] The configuration and function of the package substrate 500, bump portion 800, and bump portion 400 in semiconductor module 10J are the same as those of the package substrate 500, bump portion 800, and bump portion 400 in semiconductor module 10 or 10P.

[0309] The semiconductor module 10J differs from the semiconductor module 10 or 10P in at least the configurations 16 to 18 shown below. (Configuration 16) Includes a configuration in which the cube chip 100 or 100P in the semiconductor module 10 or 10P, and the stacked chip 30 or 30P in the cube chip 100 or 100P are replaced with the cube chip 100J and the stacked chip 30J in the cube chip 100J. (Configuration 17) The stacked chip 30J has power supply wiring 164 exposed on the second surface 48 of each of the two computing dies 200, one of the two computing dies 200, the SRAM chip 110S connected to the one computing die 200, the two SRAM chips 110S, the other of the two computing dies 200, the SRAM chip 110S connected to the other computing die 200, and the two DRAM chips 110D. (Configuration 18) Includes conductive film 903, conductive film 904, conductive film 907, conductive film 908, heat spreader 909, heat spreader 910, and resin 911.

[0310] The configurations of semiconductor module 10J other than configurations 16 to 18, and configurations other than those related to configurations 16 to 18, are the same as those of semiconductor module 10. Therefore, when describing semiconductor module 10J, configurations that are the same as or similar to those of semiconductor module 10 or 10P will be described as necessary.

[0311] As described in configuration 16, the semiconductor module 10J includes a cube chip 100J. The cube chip 100J includes a stacked chip 30J. Also, as described in configuration 18, the semiconductor module 10J includes a conductive film 903, a conductive film 904, a conductive film 907, a conductive film 908, a heat spreader 909, a heat spreader 910, and a resin 911.

[0312] As described in Configuration 17 and shown in Figure 31, the stacked chip 30J includes the following configuration. In the stacked chip 30J, from left to right in the drawing, the second surface 204 of the computing die 200 within one of the bonded chips 101 is the sixth surface 44, and a grounding wire 165 is exposed on the second surface 48 side of the computing die 200, and a grounding wire 165 is exposed on the second surface 48 side of the SRAM chip 110S adjacent to the computing die 200 within the bonded chip 101, and grounding wires are also provided on the second surface 48 side of each of the two SRAM chips 110S located next to it. The configuration includes a configuration in which a line 165 is exposed, a grounding wire 165 is exposed on the second surface 48 side of two DRAM chips 110D located next to it, a power supply wire 164 is exposed on the second surface 48 side of an SRAM chip 110S adjacent to a computing die 200 in the other bonding chip 101, and the second surface 204 of the computing die 200 in the other bonding chip 101 is the fifth surface 42, and the power supply wire 164 is exposed on the second surface 48 side of the computing die 200.

[0313] Multiple grounding wires 165 exposed on the second surface 48 are electrically connected to the conductive film 907. The heat spreader 909 is electrically connected to the conductive film 908, and through the conductive film 908, is electrically connected to the conductive film 907.

[0314] The sixth surface 44 and the fifth surface 42 of the stacked chip 30J are in contact with the conductive film 903. The sixth surface 44 and the fifth surface 42 of the stacked chip 30J are sandwiched between two conductive films 903. The heat spreader 910 is electrically connected to the conductive film 904 and electrically connected to the conductive film 903 via the conductive film 904.

[0315] Furthermore, the resin 911 is provided in the space 913R formed by the computing die 200 on the sixth surface 44 side, the conductive films 903 and 904 on the sixth surface 44 side, the heat spreader 909, the conductive film 908, the conductive film 907, and the heat spreader 910, as well as in the space 913L formed by the computing die 200 on the fifth surface 42 side, the conductive films 903 and 904 on the fifth surface 42 side, the heat spreader 909, the conductive film 908, the conductive film 907, and the heat spreader 910. Although not shown in the figures, the resin 911 is also provided in the space between the heat spreader 909, the heat spreader 910, the third surface 45, and the fourth surface 47.

[0316] Therefore, the third face 45 (third face 145), fourth face 47 (fourth face 147), fifth face 42 (fifth face 142), and sixth face 44 (sixth face 144) of the stacked chip 30J (cube chip 100J) are surrounded by the heat spreader 910, and the second face 48 (second face 148) of the stacked chip 30J (cube chip 100J) is covered by the heat spreader 909.

[0317] For example, conductive films 903 and 904, and conductive film 907 are formed using the same materials and methods as conductive films 903 and 904 in semiconductor module 10F. Conductive film 908 is formed using the same materials as conductive layers 908L and 908R in semiconductor module 10I. Heat spreaders 909 and 910 may be referred to as thermal conductive members. The semiconductor module 10J may include a heat sink (not shown), and may also include 909 and 910 on which the heat sink is located.

[0318] As described above, the semiconductor module 10J includes a configuration in which the grounding wire 165 and the heat spreader 909 are electrically connected, and the voltage VSS for driving the semiconductor module 10J is supplied to the grounding wire 165 via the heat spreader 909. Also, as described above, the sixth surface 44 and fifth surface 42 of the semiconductor module 10J, on which the computing die 200 is provided, are sandwiched between two conductive films 903 and connected to the heat spreader 910.

[0319] The semiconductor module 10J includes heat spreaders 909 and 910 that cover the second surface 148, third surface 145, fourth surface 147, fifth surface 142, and sixth surface 144 of the cube chip 100J, allowing heat generated within the semiconductor module 10J to be dissipated to the outside. Furthermore, the semiconductor module 10J includes a configuration in which the cube chip 100J is vertically mounted on the semiconductor chip section 300, and has a configuration that has superior heat dissipation characteristics compared to a configuration in which multiple IC chips and logic chips are stacked in parallel.

[0320] Therefore, the semiconductor module 10J has a configuration that can suppress malfunctions due to heat and can operate stably. Furthermore, because malfunctions due to heat are suppressed in the semiconductor module 10J, the thermal design of each component constituting each circuit and element within the semiconductor module 10J can be simplified.

[0321] As described above, the semiconductor module 10J includes the same configuration as semiconductor module 10 or 10P, and therefore provides the same effects and benefits as semiconductor module 10 or 10P. Furthermore, the configuration of semiconductor module 10J may be applied to semiconductor modules 10A, 10B, 10C, 10D, or 10E to the extent that it is applicable without departing from semiconductor modules 10A, 10B, 10C, 10D, or 10E.

[0322] [12. Twelfth Embodiment] A semiconductor module 10K according to the 12th embodiment will be described with reference to Figures 32 to 34. Figure 32 is a perspective view showing the configuration of the semiconductor module 10K. Figure 33 is an end view showing the end cross-sectional structure of the semiconductor module 10K along the line F1-F2 shown in Figure 32. Figure 34 is an end view showing the end cross-sectional structure of the semiconductor module 10K along the line G1-G2 shown in Figure 32. Configurations identical or similar to those in Figures 1 to 31 will be described as necessary.

[0323] As shown in Figure 32, the semiconductor module 10K includes a cube chip 100K, a computing die 600, a bump section 800, an I / O die 700, a bump section 400, and a package substrate 500.

[0324] The computing die 600, bump section 800, IO die 700, bump section 400, and package substrate 500 in the semiconductor module 10K have the same configuration and function as those of the computing die 600, bump section 800, IO die 700, bump section 400, and package substrate 500 in the semiconductor module 10. For example, the IO die 700 in the semiconductor module 10K may include a multilayer wiring structure in which wiring and insulating layers are alternately stacked, and may be an interposer capable of HDI.

[0325] The semiconductor module 10K differs from the semiconductor module 10 or 10P in at least the configurations 19 to 22 shown below. (Configuration 19) Includes a configuration in which the cube chip 100 or 100P in the semiconductor module 10 or 10P, and the stacked chip 30 or 30P in the cube chip 100 or 100P are replaced with the cube chip 100K and the stacked chip 30K in the cube chip 100K. (Configuration 20) The cube chip 100K and the computing die 600 are mounted on the IO die 700 along the third direction D3 and are electrically connected to the IO die 700 using the bump portion 800. (Configuration 21) The IO die 700 is mounted on the package substrate 500 and is electrically connected to the package substrate 500 using the bump portion 400. (Configuration 22) The stacked chip 30K includes multiple IC chips 110, each of which includes four SRAM chips 110S and four DRAM chips 110D.

[0326] The configurations of semiconductor module 10K other than configurations 19 to 22, and configurations other than those related to configurations 19 to 22, are the same as those of semiconductor module 10 or 10P. Therefore, when describing semiconductor module 10K, configurations that are identical or similar to those of semiconductor module 10 or 10P will be described as necessary.

[0327] As described in Configuration 19, the semiconductor module 10K includes cube chips 100K. The cube chips 100K include stacked chips 30K.

[0328] As shown in Figure 33, the cube chip 100K includes metal wiring layers 20B, 20F, and 20D, similar to the cube chip 100. Figure 33 shows the end face of the end cross-sectional structure of the SRAM chip 110S, where the side wirings 180B and 180F of each of the eight IC chips 110 are electrically connected to the wirings 22 and 24 in the outermost metal wiring layers 20B and 20F on the outermost side (third face 145 and fourth face 147) of the cube chip 100K along the second direction D2, and are electrically connected to the wiring 22 in the metal wiring layer 20D on the outermost side (first face 146) along the third direction D3 of the cube chip 100K, and are exposed from the cube chip 100K. Similarly, the side wiring 180D of each of the eight IC chips 110 is electrically connected to the wiring 22 in the outermost (first face 146) metal wiring layer 20D along the third direction D3 of the cube chip 100K, and is exposed from the cube chip 100K.

[0329] As described in configuration 20 and shown in Figure 34, the cube chip 100K is mounted on the IO die 700 along the third direction D3 and is electrically connected to the IO die 700 using bumps 800. More specifically, multiple wirings 22 of the metal wiring layer 20D on the first surface 146 side are electrically connected to the corresponding through-electrode 760 or through-electrode 790 of the IO die 700 via corresponding bumps 801 included in the bumps 800.

[0330] Furthermore, as described in configuration 20 and shown in Figure 34, the computing die 600 is mounted on the IO die 700 along the third direction D3 and is electrically connected to the IO die 700 using bumps 800. More specifically, multiple electrodes 682 exposed on the second surface 604 of the computing die 600 are electrically connected to the corresponding through-electrodes 760 or 790 of the IO die 700 via corresponding bumps 801 included in the bumps 800. In other words, the computing die 600 is face-down mounted on the IO die 700.

[0331] As described in Configuration 21 and shown in Figure 34, the IO die 700 is mounted on the package substrate 500 and electrically connected to the package substrate 500 using bumps 400. More specifically, a plurality of electrodes 782 exposed on the second surface 704 of the IO die 700 are electrically connected to corresponding electrodes 52 provided on the first surface 502 of the package substrate 500 via corresponding bumps 41 included in the bumps 400. In other words, the IO die 700 is face-down mounted on the package substrate 500.

[0332] As described in configuration 22 and shown in Figure 34, the stacked chip 30K includes the following configuration: The stacked chip 30K includes four SRAM chips 110S and four DRAM chips 110D stacked from left to right in the drawing along a first direction D1. Along the first direction D1, the outermost sixth surface 44 has the SRAM chips 110S exposed, and the other outermost fifth surface 42 has the DRAM chips 110D exposed.

[0333] The number of IC chips 110 stacked in the stacked chip 30K is just an example, and the number of IC chips 110 stacked is not limited to 8 (8 layers). Furthermore, the configuration of the multiple IC chips 110 is not limited to 8 IC chips corresponding to 4 SRAM chips 110S and 4 DRAM chips 110D. For example, the multiple IC chips 110 may include SRAM chips 110S, DRAM chips 110D and NVM chips, or SRAM chips 110S and NVM chips, or DRAM chips 110D and NVM chips. Also, the multiple IC chips 110 may consist of only one type of chip (for example, only SRAM chips 110S). The number of stacked IC chips 110 and their configuration may be appropriately selected based on the application, specifications, etc., of the semiconductor module 10K.

[0334] As described above, the semiconductor module 10K includes cube chips 100K vertically mounted on the IO die 700 parallel to the third direction D3 and perpendicular to the first direction D1 and the second direction D2. As a result, the semiconductor module 10K, like the semiconductor module 10 or 10P, has high thermal conductivity and excellent heat dissipation characteristics, thus suppressing malfunctions associated with temperature rise in the semiconductor module. Furthermore, because the semiconductor module 10L has excellent heat dissipation characteristics, the limitation on the number of stacked chips within the cube chip 100K is relaxed compared to a configuration including multiple IC chips stacked parallel to the first direction D1 and the second direction D2.

[0335] Furthermore, the cube chip 100L is vertically mounted on the IO die 700, and multiple wirings within the cube chip 100L are electrically connected to the IO die 700 via the bump section 800 using metal wiring layers 20B, 20F, and 20D.

[0336] As a result, the semiconductor module 10L can shorten the length of the wiring used to transmit signals compared to modules in which logic chips and multiple memory chips are mounted in parallel on a package substrate, modules in which logic chips and multiple memory chips are individually mounted in parallel on a package substrate, and modules in which signals are transmitted by wireless communication. Therefore, the semiconductor module 10K can suppress increases in wiring resistance and parasitic capacitance, suppress increases in power required for signal transmission and reception, suppress energy loss required for signal transmission and reception, and suppress delays in signal transmission and reception.

[0337] [13. 13th Implementation] A semiconductor module 10L according to the 13th embodiment will be described with reference to Figures 35 to 37. Figure 35 is a perspective view showing the configuration of the semiconductor module 10L. Figure 36 is an end view showing the cross-sectional structure of the end of the semiconductor module 10L along the line H1-H2 shown in Figure 35. Figure 37 is an end view showing the cross-sectional structure of the end of the semiconductor module 10L along the line I1-I2 shown in Figure 35. Configurations identical or similar to those in Figures 1 to 34 will be described as necessary.

[0338] As shown in Figure 35, the semiconductor module 10L includes a cube chip 100L, a computing die 600, a memory controller 1100, a bump section 1000, a bump section 800, an I / O die 700, a bump section 400, and a package substrate 500.

[0339] The computing die 600, bump section 800, IO die 700, bump section 400, and package substrate 500 in semiconductor module 10L have the same configuration and function as those of the computing die 600, bump section 800, IO die 700, bump section 40, and package substrate 500 in semiconductor module 10K.

[0340] The semiconductor module 10L differs from the semiconductor module 10K in at least the configurations 23 to 26 shown below. (Configuration 23) Includes a configuration in which the cube chip 100K and the stacked chip 30 in the cube chip 100K of the semiconductor module 10K are replaced with the cube chip 100L and the stacked chip 30L in the cube chip 100L. (Configuration 24) The cube chip 100L is mounted on the memory controller 1100 along the third direction D3 and is electrically connected to the memory controller 1100 using the bump portion 1000. (Configuration 25) The memory controller 1100 and computing die 600, to which the cube chip 100L is electrically connected, are mounted on the IO die 700 along the third direction D3 and are electrically connected to the IO die 700 using bump portions 800. (Configuration 26) The stacked chip 30L includes multiple IC chips 110, and each of the multiple IC chips 110 includes eight DRAM chips 110D.

[0341] The configurations of semiconductor module 10L other than configurations 23 to 26, and configurations other than those related to configurations 23 to 26, are the same as those of semiconductor module 10K. Therefore, when describing semiconductor module 10L, configurations that are the same as or similar to those of semiconductor module 10K will be described as necessary.

[0342] As described in configuration 23, the semiconductor module 10L includes a cube chip 100L. The cube chip 100L includes a stacked chip 30L.

[0343] As shown in Figure 36, the cube chip 100L includes metal wiring layers 20B, 20F, and 20D, similar to the cube chip 100K. Figure 36 shows the end face of the end cross-sectional structure of the DRAM chip 110D along H1-H2 in Figure 35. The side wirings 180B and 180F of each of the eight IC chips 110 are electrically connected to the wirings 22 and 24 in the metal wiring layers 20B and 20F on the outermost side (third side 145 and fourth side 147) of the cube chip 100L along the second direction D2, and are electrically connected to the wiring 22 in the metal wiring layer 20D on the outermost side (first side 146) along the third direction D3 of the cube chip 100L, and are exposed from the cube chip 100L. Similarly, the side wiring 180D of each of the eight IC chips 110 is electrically connected to the wiring 22 in the outermost (first face 146) metal wiring layer 20D along the third direction D3 of the cube chip 100L, and is exposed from the cube chip 100L.

[0344] For example, the memory controller 1100 has a stacked structure similar to that of the computing die 600 shown in Figure 13. For example, the memory controller 1100 includes a first surface 1102, a second surface 1104, a transistor layer 1130, a wiring layer 1150, an electrode 1160, a through electrode 1190, and an electrode 1182, each having a configuration similar to that of the first surface 602, second surface 604, transistor layer 630, wiring layer 650, through electrode 660, through electrode 690, and electrode 682, respectively. Note that electrode 1160 and through electrode 1190 are exposed on the first surface 1102, the through electrode 1190 is electrically connected to electrode 1182, and electrode 1182 is exposed on the second surface 1104. In addition, the memory controller 1100 has the function of controlling the IC chip 110 (here, eight DRAM chips 110D) contained in the cube chip 100L, similar to the memory controller 319.

[0345] As described in configuration 24 and shown in Figures 36 and 37, the cube chip 100L is mounted on the memory controller 1100 along the third direction D3 and is electrically connected to the memory controller 1100 using the bump portion 1000. More specifically, multiple wirings 22 of the metal wiring layer 20D on the first surface 146 side are electrically connected to the corresponding electrodes 1160 or through electrodes 1190 of the memory controller 1100 via the corresponding bumps 1001 included in the bump portion 1000.

[0346] As described in configuration 25 and shown in Figures 36 and 37, the memory controller 1100, to which the cube chip 100L is electrically connected, is mounted on the IO die 700 along the third direction D3 and is electrically connected to the IO die 700 using bumps 800. More specifically, a plurality of electrodes 1182 exposed on the second surface 1104 side are electrically connected to the corresponding through-electrode 760 or through-electrode 790 of the IO die 700 via corresponding bumps 801 included in the bumps 800. In other words, the memory controller 1100 is face-down mounted on the IO die 700.

[0347] Furthermore, as described in configuration 25 and shown in Figure 37, the computing die 600 is mounted on the IO die 700 along the third direction D3 and is electrically connected to the IO die 700 using bumps 800. More specifically, multiple electrodes 682 exposed on the second surface 604 of the computing die 600 are electrically connected to the corresponding through-electrodes 760 or 790 of the IO die 700 via corresponding bumps 801 included in the bumps 800. In other words, the computing die 600 is face-down mounted on the IO die 700.

[0348] As shown in Figure 37, the IO die 700 is mounted on the package substrate 500 and electrically connected to the package substrate 500 using bumps 400. More specifically, a plurality of electrodes 782 exposed on the second surface 704 of the IO die 700 are electrically connected to corresponding electrodes 52 provided on the first surface 502 of the package substrate 500 via corresponding bumps 41 included in the bumps 400. In other words, the IO die 700 is face-down mounted on the package substrate 500.

[0349] As described in configuration 26 and shown in Figure 37, the stacked chip 30L includes the following configuration: The stacked chip 30L includes eight DRAM chips 110D stacked from left to right in the drawing along a first direction D1. The outermost sixth and fifth faces 44 and 42 of the DRAM chips 110D are exposed along the first direction D1.

[0350] The number of IC chips 110 stacked in the stacked chip 30L is just one example, and the number of IC chips 110 stacked is not limited to eight (eight layers). Furthermore, the configuration of the multiple IC chips 110 is not limited to eight IC chips corresponding to eight DRAM chips 110D. Also, for example, the stacking method of the multiple IC chips may be welding, direct silicon bonding, thermal bonding, F2F bonding, F2B bonding, or B2B bonding. The number of IC chips 110 stacked, the bonding method, and the configuration may be appropriately selected based on the application, specifications, etc., of the semiconductor module 10L.

[0351] As described above, the semiconductor module 10L includes a cube chip 100L vertically mounted on the memory controller 1100 parallel to the third direction D3 and perpendicular to the first direction D1 and the second direction D2. As a result, the semiconductor module 10L, like the semiconductor module 10K, has high thermal conductivity and excellent heat dissipation characteristics, thus suppressing malfunctions caused by temperature rise in the semiconductor module. Furthermore, because the semiconductor module 10L has excellent heat dissipation characteristics, the limitation on the number of stacked chips within the cube chip 100L is relaxed compared to a configuration including multiple IC chips stacked parallel to the first direction D1 and the second direction D2.

[0352] Furthermore, the cube chip 100L is vertically mounted on the memory controller 1100, and multiple wirings within the cube chip 100L are electrically connected to the memory controller 1100 via the bump portion 1000 using metal wiring layers 20B, 20F, and 20D.

[0353] As a result, since the cube chip 100L and the memory controller 1100 are electrically connected via the bump portion 1000, the length of the wiring for signal transmission can be shortened compared to modules in which a logic chip and multiple memory chips are mounted in parallel on a package substrate, modules in which a logic chip and multiple memory chips are individually mounted in parallel on a package substrate, and modules in which signals are transmitted by wireless communication. Therefore, the semiconductor module 10L can suppress increases in wiring resistance and parasitic capacitance, suppress increases in power required for signal transmission and reception, suppress energy loss required for signal transmission and reception, and suppress delays in signal transmission and reception. Therefore, the semiconductor module 10L is a module suitable for transmitting high-speed signals (high-frequency signals).

[0354] [14. 14th Embodiment] The semiconductor module 10M according to the 14th embodiment will be described with reference to Figures 38 to 40.

[0355] [14-1. Overview of 10M Semiconductor Module] First, an overview of the semiconductor module 10M will be described with reference to Figures 38 to 40. Figure 38 is a perspective view showing the configuration of the semiconductor module 10M. Figure 39 is a top view showing the configuration of the semiconductor module 10M. Figure 40 is an end view showing the cross-sectional structure of the end of the semiconductor module 10M along J1-J2 shown in Figure 39. Configurations identical or similar to those in Figures 1 to 37 will be described as necessary.

[0356] As shown in Figures 38, 39, or 40, the semiconductor module 10M includes a stacked chip group 1200, a cover 1210, a sealing structure 1230, and a package substrate 500. The semiconductor module 10M may also include a thermal conductive sheet 912 and a conductive film 907. For example, the IO die 700 related to the semiconductor module 10M may include a multilayer wiring structure in which wiring and insulating layers are alternately stacked, and may be an interposer capable of HDI.

[0357] The stacked chip group 1200 includes a first surface 1202 electrically connected to the package substrate 500 in a third direction D3, a second surface 1204 opposite to the first surface 1202 and parallel to the first surface 1202, and multiple chips. As will be described in detail later, for example, as shown in Figure 39 or Figure 40, the stacked chip group 1200 includes multiple cube chips 100L, a first semiconductor chip 1240, multiple support substrates 1300, multiple second semiconductor chips 1250, and bump sections 800. Also, for example, the bump section 800 includes multiple bumps 801. The multiple bumps 801 correspond to the output terminals of the stacked chip group 1200. For example, as shown in Figure 39, the stacked chip group 1200 includes 12 cube chips 100L, 1 first semiconductor chip 1240, 2 support substrates 1300, and 1 second semiconductor chip 1250. The configuration of the stacked chip group 1200 is not limited to the configuration shown in Figure 39. The configuration of the stacked chip group 1200 can be changed as appropriate based on the application or specifications of the semiconductor module 10M. Each of the cube chip 100L, the first semiconductor chip 1240, and the second semiconductor chip 1250 is electrically connected to a plurality of bumps 801 and electrically connected to the package substrate 500.

[0358] The cover 1210 covers the stacked chip group 1200 and is in contact with the first surface 502 of the package substrate 500. For example, the cover 1210 may contain a metallic material and may contain a sealing material. For example, the metallic material may contain gold, nickel, tin, etc., and the sealing material may contain a resin material such as epoxy, a curing agent, a filler, and additives. The cover 1210 has the function of protecting the stacked chip group 1200 from physical impact, contamination, or oxidation due to moisture. The cover 1210 may also function as a heat spreader.

[0359] The sealing structure 1230 surrounds the stacked chip group 1200, is in contact with the stacked chip group 1200, and is also in contact with the first surface 502 of the package substrate 500. For example, the sealing structure 1230 includes a sealing material. For example, the sealing material includes a resin material such as epoxy, a curing agent, a filler, and additives. The sealing structure 1230 has the function of fixing the stacked chip group 1200 to the package substrate 500 and protecting it from physical impact.

[0360] The package substrate 500 is a printed circuit board that includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked, enabling high-density interconnect (HDI). For example, the package substrate 500 includes a first surface 502, a second surface 504, a plurality of electrodes 53, and a plurality of wirings 54, 55, and 56. The plurality of electrodes 53 and the plurality of wirings 54, 55, and 56 are arranged parallel to the first direction D1 and the second direction D2, and are stacked in this order from the first surface 502 toward the second surface 504 along the third direction D3. The plurality of electrodes 53 are exposed on the first surface 502. Each of the plurality of electrodes 53 is electrically connected to each of the corresponding plurality of wirings 54, each of the plurality of wirings 54 is electrically connected to each of the corresponding plurality of wirings 55, and each of the plurality of wirings 55 is electrically connected to each of the corresponding plurality of wirings 56. In Figure 39, the illustration of the insulating layer stacked alternately with the wiring is omitted. Furthermore, the number of layers in the multilayer wiring structure of the package substrate 500 is not limited to the number of layers (4 layers) shown in Figure 39. The number of layers in the multilayer wiring structure of the package substrate 500 can be changed as appropriate based on the application or specifications of the semiconductor module 10M.

[0361] Furthermore, for example, the package substrate 500 has the function of connecting the cube chip 100L, the first semiconductor chip 1240, and the second semiconductor chip 1250 to external devices. The package substrate 500 also includes a plurality of electrodes (not shown) exposed on the second surface 504, which are electrically connected to external devices.

[0362] For example, the conductive film 907 may be provided so as to be in contact with the second surface 1204 of the stacked chip group 1200 along the third direction D3, and the thermal conductive sheet 912 may be provided so as to be in contact between the conductive film 907 and the cover 1210. For example, the conductive film 907 and the thermal conductive sheet 912, together with the cover 1210, have the function of releasing the heat generated by the semiconductor module 10M to the outside of the semiconductor module 10M.

[0363] The semiconductor module 10M includes cube chips 100L mounted vertically on the package substrate 500, parallel to the third direction D3 and perpendicular to the first direction D1 and the second direction D2. As a result, the semiconductor module 10M, like the semiconductor module 10L, has high thermal conductivity and excellent heat dissipation characteristics, thus suppressing malfunctions associated with temperature rise in the semiconductor module.

[0364] Furthermore, since the semiconductor module 10L includes a thermal conductive sheet 912 and has superior heat dissipation characteristics, the limitation on the number of stacked chips in the cube chip 100L is relaxed compared to a configuration that includes multiple IC chips stacked parallel to the first direction D1 and the second direction D2. As a result, for example, the semiconductor module 10L includes a configuration that allows for an increase in the number of stacked DRAM chips 110D, and a configuration that allows for increased memory capacity.

[0365] [14-2. Overview of Cube Chip 100L] The multiple cube chips 100L have the same configuration and function as the cube chips 100L described in the twelfth embodiment. The multiple cube chips 100L are electrically connected to the multiple electrodes 52 of the package substrate 500 via the multiple bumps 801 included in the bump portion 800, which is electrically connected to the multiple wirings 22 exposed on the metal wiring layer 20D.

[0366] Furthermore, at least one of the multiple cube chips 100L is electrically connected to the first semiconductor chip 1240 via electrodes 52 and 53, wirings 54, 55 and 56 of the package substrate 500, and multiple bumps 801. Also, at least one other cube chip 100L is electrically connected to the second semiconductor chip 1250 via electrodes 52 and 53, wirings 54, 55 and 56 of the package substrate 500, and multiple bumps 801.

[0367] Furthermore, the cube chip 100L is vertically mounted on the IO die 700, and multiple wirings within the cube chip 100L are electrically connected to the IO die 700 via the bump portion 800 using metal wiring layers 20B, 20F, and 20D. The cube chip 100L may also include a configuration similar to that of the cube chip 100P, as long as it does not deviate from the configuration of the cube chip 100L. If the cube chip 100L includes a configuration similar to that of the cube chip 100P, multiple wirings within the cube chip 100L may be electrically connected to the IO die 700 via the bump portion 800 using the metal wiring layer 20D.

[0368] [14-3. Overview of the first semiconductor chip 1240] As shown in Figure 39 or Figure 40, the first semiconductor chip 1240 includes a CPU 321, a GPU 320, an IO die 700A, an IO die 700B, and a support substrate 1300.

[0369] The CPU 321 includes multiple IC chips 110C. Each of the multiple IC chips 110C has a stacked structure similar to that of the computing die 600 shown in Figure 13. For example, as shown in Figure 40, the number of stacked IC chips 110C is three (3 layers), and two adjacent IC chips 110C are bonded to each other.

[0370] Of the three IC chips 110C, the IC chip 110C closest to the first surface 1202 is electrically connected to the IO die 700A, and the IC chip 110C furthest from the first surface 1202 is bonded to the support substrate 1300.

[0371] The surface electrically connected to the IO die 700A may be the first surface 602 of the IC chip 110C, or it may be the second surface 604. The surface joined to the support substrate 1300 may be the first surface 602 of the IC chip 110C, or it may be the second surface 604.

[0372] The GPU320 includes multiple IC chips 110G. Similar to the multiple IC chips 110C, each of the multiple IC chips 110G has a stacked structure similar to the computing die 600 shown in Figure 13, with three stacked IC chips 110G (3 layers), and two adjacent IC chips 110G are bonded to each other.

[0373] Of the three IC chips 110G, the IC chip 110G closest to the first surface 1202 is electrically connected to the IO die 700B, and the IC chip 110G furthest from the first surface 1202 is bonded to the support substrate 1300.

[0374] The surface electrically connected to the IO die 700B may be the first surface 602 of the IC chip 110G, or it may be the second surface 604. The surface joined to the support substrate 1300 may be the first surface 602 of the IC chip 110G, or it may be the second surface 604.

[0375] The number of stacked IC chips 110 in the CPU 321 and GPU 320 is just one example, and the number of stacked IC chips 110 is not limited to three (three layers). Also, for example, the stacking method of the support substrate 1300, the multiple IC chips 110C, IO die 700A, the multiple IC chips 110G, and IO die 700B may be welding, direct silicon bonding, thermal bonding, F2F bonding, F2B bonding, or B2B bonding. The number of stacked IC chips 110, bonding method, and configuration may be appropriately selected based on the application and specifications of the semiconductor module 10B.

[0376] [14-4. Overview of the second semiconductor chip 1250] As shown in Figure 39, the second semiconductor chip 1250 includes the GPU 320 and the support substrate 1300. Although not shown in the figure, the second semiconductor chip 1250 also includes an I / O die 700B that is electrically connected to the GPU 320.

[0377] The CPU 321 includes multiple IC chips 110C. Each of the multiple IC chips 110C has a stacked structure similar to that of the computing die 600 shown in Figure 13. For example, as shown in Figure 40, the number of stacked IC chips 110C is three (3 layers), and two adjacent IC chips 110C are bonded to each other.

[0378] Of the three IC chips 110C, the IC chip 110C closest to the first surface 1202 is electrically connected to the IO die 700A, and the IC chip 110C furthest from the first surface 1202 is bonded to the support substrate 1300.

[0379] The surface electrically connected to the IO die 700A may be the first surface 602 of the IC chip 110C, or it may be the second surface 604. The surface joined to the support substrate 1300 may be the first surface 602 of the IC chip 110C, or it may be the second surface 604.

[0380] The GPU320 includes multiple IC chips 110G. Similar to the multiple IC chips 110C, each of the multiple IC chips 110G has a stacked structure similar to the computing die 600 shown in Figure 13, with three stacked IC chips 110G (3 layers), and two adjacent IC chips 110G are bonded to each other.

[0381] Of the three IC chips 110G, the IC chip 110G closest to the first surface 1202 is electrically connected to the IO die 700B, and the IC chip 110G furthest from the first surface 1202 is bonded to the support substrate 1300.

[0382] The surface electrically connected to the IO die 700B may be the first surface 602 of the IC chip 110G, or it may be the second surface 604. The surface joined to the support substrate 1300 may be the first surface 602 of the IC chip 110G, or it may be the second surface 604.

[0383] The number of stacked IC chips 110 in the CPU 321 and GPU 320 is just one example, and the number of stacked IC chips 110 is not limited to three (three layers). Also, for example, the stacking method of the support substrate 1300, the multiple IC chips 110C, IO die 700A, the multiple IC chips 110G, and IO die 700B may be welding, direct silicon bonding, thermal bonding, F2F bonding, F2B bonding, or B2B bonding. The number of stacked IC chips 110, bonding method, and configuration may be appropriately selected based on the application and specifications of the semiconductor module 10B.

[0384] [14-5. Overview of IO-Die 700A and IO-Die 700B] IO die 700A and IO die 700B have a structure similar to IO die 700 shown in Figure 14. Furthermore, IO die 700A and IO die 700B may include multiple IO interfaces 312 and multiple R318, as described in "1-2. Configuration of Semiconductor Module 10".

[0385] For example, the IO die 700A includes a plurality of through-electrodes 790 exposed on the second surface 704, and is electrically connected to the CPU 321 (IC chip 110C) using the plurality of through-electrodes 790. The IO die 700A also includes a plurality of electrodes 782 exposed on the first surface 702, and is electrically connected to a plurality of bumps 81 using the plurality of electrodes 782, and is electrically connected to the package substrate 500 via the bumps 81.

[0386] For example, the IO die 700B, like the IO die 700A, is electrically connected to the GPU 320 (IC chip 110G) using multiple through-electrodes 790, electrically connected to multiple bumps 81 using multiple electrodes 782, and electrically connected to the package substrate 500 via the bumps 81.

[0387] [15. 15th Embodiment] A semiconductor module 10N according to the 15th embodiment will be described with reference to Figure 41. Figure 41 is a perspective view showing the configuration of the semiconductor module N. Figure 42 is an end view showing the cross-sectional structure of the end of the semiconductor module N along the K1-K2 line shown in Figure 41. Figure 43 is a plan view showing a conventional large-scale DRAM mounting example. Configurations identical or similar to those in Figures 1 to 40 will be described as necessary.

[0388] The semiconductor module 10N includes a configuration in which the cube chip 100L in the semiconductor module 10L is replaced with cube chip 100N. Furthermore, cube chip 100N may include a configuration similar to that of cube chip 100P, as long as it does not deviate from the configuration of cube chip 100N. Therefore, in describing the semiconductor module 10N, configurations that are the same as or similar to those of semiconductor modules 10L, 10, or 10P will be described as necessary.

[0389] As shown in Figure 41, the semiconductor module 10N includes a cube chip 100N, a bump section 1000, and a memory controller 1100. Note that in the semiconductor module 10N shown in Figure 41, the computing die 600, bump section 800, IO die 700, bump section 400, and package substrate 500 of the semiconductor module 10L are omitted.

[0390] The bump section 1000, memory controller 1100, computing die 600, bump section 800, IO die 700, bump section 400, and package substrate 500 in semiconductor module 10N have the same configuration and function as the memory controller 1100, computing die 600, bump section 800, IO die 700, bump section 400, and package substrate 500 in semiconductor module 10L.

[0391] The semiconductor module 10N differs from the semiconductor module 10L in at least the configurations 27 and 28 shown below. (Configuration 27) This configuration includes a configuration in which the cube chip 100L and the stacked chip 30L in the semiconductor module 10L are replaced with the cube chip 100N and the stacked chip 30N in the cube chip 100N. (Configuration 28) The stacked chip 30N includes multiple IC chips 110, and each of the multiple IC chips 110 includes four DRAM chips 110DN.

[0392] The configurations of semiconductor module 10N other than configurations 27 and 28, and configurations other than those related to configurations 27 and 28, are the same as those of semiconductor module 10L. Therefore, when describing semiconductor module 10N, configurations that are the same as or similar to those of semiconductor module 10L will be described as necessary.

[0393] As described in configuration 28 and shown in Figure 41, the stacked chip 30N includes the following configuration: The stacked chip 30N includes four DRAM chips 110DN stacked from left to right in the drawing along a first direction D1. The outermost sixth and fifth faces 44 and 42 of the DRAM chips 110DN are exposed along the first direction D1.

[0394] The DRAM chip 110DN has a similar configuration to the DRAM chip 110D described in semiconductor module 10L, but differs from the DRAM chip 110D in the following respects. As shown in Figure 42, the DRAM chip 110DN includes at least four memory banks 2002. For example, the distance between adjacent memory banks 2002, and the distance from memory bank 2002 to the first surface 146, is distance L. For clarity, metal wiring layers 20B, 20F, and 20D are omitted in Figure 42. Note that the number of memory banks in the DRAM chip 110DN is an example, and the number of memory banks is not limited to four.

[0395] The semiconductor module 10N includes a cube chip 100N in which four DRAM chips DN, each containing four memory banks, are bonded (stacked) along the first direction D1. In other words, the semiconductor module 10N includes a cube chip 100N containing 16 memory banks. The cube chip 100N is vertically mounted on the memory controller 1100 parallel to the third direction D3 and perpendicular to the first direction D1 and the second direction D2.

[0396] At this time, similar to the cube chip 100L described with reference to Figures 35 to 37 for semiconductor module 10L, the cube chip 100N is electrically connected to the memory controller 1100 via the bump portion 1000 using metal wiring layers 20B, 20F, and 20D.

[0397] For example, as shown in Figure 43, a conventional large-scale DRAM module 2000 includes a configuration in which 16 memory banks 2002 are arranged on a single substrate along a first direction D1 and a second direction D2. The 16 memory banks 2002 are arranged in a vertical arrangement of eight to eight to eight to a through-electrode region 2004 containing multiple through-electrodes 2006 on a single substrate, along the first direction D1. Each memory bank 2002 is electrically connected to the corresponding multiple through-electrodes 2006 and is also electrically connected to a memory controller (not shown). For example, the distance between adjacent memory banks 2002 is distance L. To read data stored in memory bank 2002A, the data is transmitted to the through-electrode region 2004 over a distance of at least 2L (distance L × 2).

[0398] On the other hand, since the cube chip 100L in the semiconductor module 10N is vertically mounted to the memory controller 1100, in order to read the data stored in the memory bank 2002AN, the data only needs to be transmitted over a distance of at least L.

[0399] As described above, the semiconductor module 10N is mounted vertically on the memory controller 1100 and electrically connected using a metal wiring layer, forming a cube chip 100N with the same memory capacity as a conventional large-scale DRAM module 2000. As a result, the semiconductor module 10N can shorten the signal (data) transmission distance compared to a conventional large-scale DRAM module 2000. Consequently, the semiconductor module 10N can reduce wiring length and parasitic capacitance, thereby reducing power consumption associated with signal transmission.

[0400] Furthermore, the semiconductor module 10N having the configuration described above, like the semiconductor module 10L, has high thermal conductivity and excellent heat dissipation characteristics, thus suppressing malfunctions caused by temperature rise in the semiconductor module. In addition, because the semiconductor module 10N has excellent heat dissipation characteristics, the limitation on the number of stacked chips within the cube chip 100N is relaxed compared to a configuration that includes multiple IC chips stacked parallel to the first direction D1 and the second direction D2.

[0401] Therefore, the semiconductor module 10N can increase the number of stacked IC chips within the cube chip 100N, thereby increasing the memory capacity compared to the conventional large-scale DRAM module 2000.

[0402] The various configurations of the semiconductor modules illustrated as embodiments of the present invention can be combined as appropriate, as long as they do not contradict each other, and technical matters common to each embodiment are included in each embodiment even if not explicitly stated. Furthermore, semiconductor modules disclosed in this specification and drawings, on which a person skilled in the art has added, deleted, or modified components, or added, omitted, or modified processes, are also included in the scope of the present invention, as long as they retain the gist of the present invention.

[0403] Any effects or benefits other than those brought about by the embodiments disclosed herein are to be understood to be brought about by the present invention if they are clear from the description herein or can be easily predicted by a person skilled in the art. [Explanation of Symbols]

[0404] 10: Semiconductor module, 10A: Semiconductor module, 10B: Semiconductor module, 10C: Semiconductor module, 10D: Semiconductor module, 10E: Semiconductor module, 10F: Semiconductor module, 10G: Semiconductor module, 10H: Semiconductor module, 10I: Semiconductor module, 10J: Semiconductor module, 10K: Semiconductor module, 10L: Semiconductor module, 10M: Semiconductor module, 10N: Semiconductor module, 10P: Semiconductor module, 20B: Metal wiring layer, 20BE: End face, 20D: Metal wiring layer, 20F: Metal wiring layer, 20FE : End face, 21: Insulating layer, 22: Wiring, 23: Insulating layer, 24: Wiring, 24BE: End face, 24FE: End face, 25: Insulating layer, 26: Wiring, 30: Multilayer chip, 30B: Multilayer chip, 30D: Multilayer chip, 30E: Multilayer chip, 30F: Multilayer chip, 30I: Multilayer chip, 30J: Multilayer chip, 30K: Multilayer chip, 30L: Multilayer chip, 30N: Multilayer chip, 30P: Multilayer chip, 40: Bump section, 41: Bump, 42: Fifth face, 44: Sixth face, 45: Third face, 46: First face, 47: Fourth face, 48: Second face, 52: Electrode, 53: Electrode, 54: Wiring, 55: Wiring, 56: Wiring, 60: Heatsink, 60L: Heatsink, 60R: Heatsink, 60U: Heatsink, 81: Bump, 100: Cube Chip, 100A: Cube Chip, 100B: Cube Chip, 100C: Cube Chip, 100D: Cube Chip, 100E: Cube Chip, 100F: Cube Chip, 100I: Cube Chip, 100J: Cube Chip, 100K: Cube Chip, 100L: Cube Chip, 100N: Cube Chip, 100P: Cube Chip, 101: Bonding Chip, 101B: Bonding Chip, 101D : Bonding chip, 101E: Bonding chip, 102: First surface, 103: Adhesive layer, 104: Second surface, 110: IC chip, 110C: IC chip, 110D: DRAM chip, 110DN: DRAM chip, 110G: IC chip, 110S: SRAM chip, 110SE: SRAM chip, 111: Memory module, 111D: Memory module, 111S: Memory module, 115: Memory cell array, 130: Transistor layer, 142: Fifth surface, 144: Sixth surface, 145: Third surface, 146: First surface, 147: Fourth surface, 148: Second surface, 150: Wiring layer,160: Through electrode, 162: Wiring, 163: Wiring, 164: Power wiring, 165: Grounding wiring, 166: Signal transmission wiring, 167: Fin, 168: N-type transistor, 169: P-type transistor, 170: Inductor, 173: Substrate, 174: Insulating layer, 175: Gate insulating film, 176: Gate electrode, 177: Insulating layer, 178: Wiring, 179: Insulating layer, 180: Wiring, 180B: Side wiring, 180D: Side wiring, 180F: Side wiring, 181: Insulating layer, 183: Insulating layer, 184: Activation region, 200: Computing die, 200E: Computing die I, 202: First surface, 204: Second surface, 210: Lower wiring layer, 211: Logic module, 212: IO interface, 213: Parallel-to-series conversion circuit, 214: Transceiver circuit, 220: Electrode pad, 221: Electrode pad, 222: Electrode pad, 228: Wiring, 230: Transistor layer, 240: Signal bus, 250: Wiring layer, 251: Latch circuit, 252: Comparator, 252H: Hysteresis comparator, 253: Protection circuit, 254: Injection-synchronous oscillator, 260: Through electrode, 262: Wiring, 263: Wiring, 267: Fin, 268: N-type transistor, 269: P-type transistor, 270: Inductor, 273: Substrate, 274: Insulating layer, 275: Gate insulating film, 276: Gate electrode, 277: Insulating layer, 278: Wiring, 279: Insulating layer, 280: Wiring, 280D: Side wiring, 281: Insulating film, 283: Insulating film, 284: Activation region, 300: Semiconductor chip section, 300B: Semiconductor chip section, 300C: Semiconductor chip section, 300D: Semiconductor chip section, 302: First surface, 304: Second surface, 311: DRAM interface, 312: IO interface, 312a: IO interface, 312b: IO interface Interface, 312c: I / O interface, 312d: I / O interface, 312e: I / O interface, 312k: I / O interface, 313: Parallel / serial conversion circuit, 314: Transceiver circuit, 315: PCIe interface, 317: Network interface, 318: Network router, 318a: Network router, 318b: Network router, 318c: Network router, 318d: Network router, 318e: Network router, 318f: Network router, 318g: Network router,318h: Network router, 318i: Network router, 318j: Network router, 318k: Network router, 318l: Network router, 319: Memory controller, 320: GPU, 321: CPU, 330: Transistor layer, 340: Signal bus, 350: Wiring layer, 351: Latch circuit, 352: Amplifier circuit, 353: Protection circuit, 400: Bump section, 500: Package substrate, 502: First side, 504: Second side, 600: Computing die, 600C: Computing die, 600D: Computing die, 6 02: First surface, 604: Second surface, 608: Wiring layer, 609: Wiring, 610: Lower wiring layer, 611: Wiring, 612: Wiring layer, 613: Wiring, 620: Electrode pad, 621: Electrode pad, 622: Electrode pad, 623: Insulating layer, 624: Through electrode, 625: Through electrode, 626: Through electrode, 627: Insulating layer, 628: Wiring, 629: Insulating layer, 630: Transistor layer, 650: Wiring layer, 660: Through electrode, 662: Wiring, 663: Wiring, 667: Fin, 668: N-type transistor, 669: P-type transistor, 673: Substrate, 674: Insulating layer, 675: Gate insulating layer Edge film, 676: Gate electrode, 677: Insulating layer, 678: Wiring, 679: Insulating layer, 680: Wiring, 681: Insulating layer, 682: Electrode, 683: Insulating layer, 684: Activation region, 690: Through electrode, 700: IO die, 700A: IO die, 700B: IO die, 702: First surface, 704: Second surface, 730: Transistor layer, 750: Wiring layer, 760: Through electrode, 762: Wiring, 763: Wiring, 767: Fin, 768: N-type transistor, 769: P-type transistor, 773: Substrate, 774: Insulating layer, 775: Gate insulating film, 776: Gate electrode, 777: Insulating layer 778: Wiring, 779: Insulating layer, 780: Wiring, 781: Insulating layer, 782: Electrode, 783: Insulating layer, 784: Activation region, 790: Through electrode, 800: Bump section, 801: Bump, 900: Voltage supply section, 901: Support section, 902: Pogo pin, 903: Conductive film, 904: Conductive film, 905: Letter-shaped member, 906: Flexible substrate, 907: Conductive film, 907L: (Configuration 15) Side power wiring, 907L: Side power wiring, 907R: Side ground wiring, 908: Conductive film, 908L: Conductive layer, 908R: Conductive layer, 909: Heat spreader, 909L: Heat spreader,909R: Heat spreader, 910: Heat spreader, 911: Resin, 912: Thermal conductive sheet, 913L: Space, 913R: Space, 1000: Bump section, 1001: Bump, 1100: Memory controller, 1102: First surface, 1104: Second surface, 1130: Transistor layer, 1150: Wiring layer, 1160: Electrode, 1182: Electrode, 1190: Through electrode, 1200: Multiplier Layer chip group, 1202: 1st surface, 1204: 2nd surface, 1210: Cover, 1230: Encapsulation structure, 1240: 1st semiconductor chip, 1250: 2nd semiconductor chip, 1250: 2nd semiconductor chip, 1300: Support substrate, 2000: Module, 2002: Memory bank, 2002A: Memory bank, 2002AN: Memory bank, 2004: Through electrode region, 2006: Through electrode,

Claims

1. A cube chip comprising a stacked chip in which multiple IC chips are stacked along the first direction parallel to a plane formed by a second direction perpendicular to the first direction and a third direction perpendicular to the second direction, and a first metal wiring layer electrically connected to the stacked chip, A semiconductor chip capable of controlling the aforementioned cube chip, A first bump portion electrically connects the semiconductor chip and the first metal wiring layer, It has, The cube chip is vertically positioned on the first bump portion along the third direction. Semiconductor module.

2. The semiconductor module according to claim 1, wherein the first metal wiring layer is a rewiring layer having the function of rearranging the positions of wiring on the laminated chip that are exposed from the side surface of the cube chip.

3. The first bump portion contains solder, The semiconductor module according to claim 1, wherein the first metal wiring layer is a UBM layer having the function of suppressing the diffusion of the solder.

4. The first bump portion contains solder, The semiconductor module according to claim 1, wherein the first metal wiring layer includes a rewiring layer having the function of rearranging the position of wiring on the laminated chip that is exposed from the side surface of the cube chip, and a UBM layer having the function of suppressing the diffusion of the solder.

5. The aforementioned stacked chip is The first surface is one of the outermost surfaces whose normal vector is the third direction, The other outermost surface whose normal vector is the third direction, and which is opposite to the second surface on the side of the first surface, The third surface, which is one of the outermost surfaces, has the second direction as its normal vector, The other outermost surface whose normal vector is the second direction, and the fourth surface opposite to the third surface, The fifth surface, which is one of the outermost surfaces with the first direction as its normal vector, The other outermost surface whose normal vector is the first direction, and the sixth surface opposite to the fifth surface, It has, The first metal wiring layer has a plurality of wirings and is in contact with the first surface, The semiconductor module according to claim 1.

6. Each of the aforementioned plurality of IC chips has a plurality of electrodes exposed on the first surface, The plurality of electrodes are electrically connected to the first bump portion, Some of the aforementioned electrodes are supplied with voltage and control signals for driving the cube chip. The semiconductor module according to claim 5.

7. It further includes a second metal wiring layer in contact with the third surface and a third metal wiring layer in contact with the fourth surface, Each of the second and third metal wiring layers includes a plurality of wirings. The semiconductor module according to claim 5.

8. Each of the plurality of IC chips has a first electrode exposed on the third surface, a second electrode exposed on the fourth surface, and a third electrode exposed on the first surface. The first electrode is electrically connected to a plurality of wirings in the third metal wiring layer using a plurality of wirings in the first metal wiring layer. The second electrode is electrically connected to the plurality of wirings of the third metal wiring layer using the plurality of wirings of the second metal wiring layer. Multiple wirings of the third metal wiring layer are electrically connected to the first bump portion. The semiconductor module according to claim 7.

9. The aforementioned multiple IC chips are A first memory chip on which memory is formed, A first computing die electrically connected to the first memory chip and capable of controlling the first memory chip, A second memory chip on which memory is formed, A second computing die is electrically connected to the second memory chip and capable of controlling the second memory chip, Includes, The first computing die is in contact with the fifth surface, The second computing die is in contact with the sixth surface, The semiconductor module according to claim 5 or claim 8.

10. The aforementioned semiconductor chip is A third computing die capable of controlling the aforementioned cube chip, An input / output die electrically connected to the third computing die, It has, The third computing die has a plurality of circuits, The input / output die has multiple network routers, The cube chip and the plurality of circuits are electrically connected using the plurality of network routers. The semiconductor module according to claim 5 or claim 8.

11. Each of the third computing die and the input / output die includes a substrate, a transistor layer including through-electrodes penetrating the substrate, electrodes exposed on the substrate, and a plurality of transistors, and a wiring layer laminated on the transistor layer and including electrodes exposed on the surface. The electrodes exposed on the surface of the third computing die and the through electrodes of the input / output die are electrically connected. The through-electrode of the third computing die and the electrode exposed to the substrate are electrically connected to the first bump portion. The semiconductor module according to claim 10.

12. The cube chip has a first input / output interface, The aforementioned plurality of circuits have a second input / output interface, The first input / output interface includes a protection circuit electrically connected to the first bump section, and one of a comparator, a hysteresis comparator, or an injection-synchronous oscillator electrically connected to the protection circuit. The second input / output interface includes a protection circuit electrically connected to the first bump section and a comparator electrically connected to the protection circuit. The semiconductor module according to claim 10.

13. Further includes a heatsink, The heat sink has a second surface, a surface opposite to the fifth surface that the first computing die is in contact with, and a surface opposite to the sixth surface that the second computing die is in contact with, The semiconductor module according to claim 9.

14. Each of the third computing die and the input / output die includes a substrate, a transistor layer including through-electrodes penetrating the substrate, electrodes exposed on the substrate, and a plurality of transistors, and a wiring layer laminated on the transistor layer and including electrodes exposed on the surface. The electrodes exposed on the surface of the third computing die and the electrodes exposed on the surface of the input / output die are electrically connected. The through-electrode of the third computing die and the electrode exposed to the substrate are electrically connected to the first bump portion. The semiconductor module according to claim 10.

15. Package substrate and The first bump portion of the semiconductor chip is electrically connected to the opposite side of the side to which it is electrically connected, and the second bump portion is electrically connected to the package substrate. It further possesses, Each of the third computing die and the input / output die includes a substrate, a transistor layer including through-electrodes penetrating the substrate, electrodes exposed on the substrate, and a plurality of transistors, and a wiring layer laminated on the transistor layer and including electrodes exposed on the surface. The third computing die further has a lower wiring layer that is stacked on the side of the transistor layer opposite to the side on which the wiring layer is stacked, and is capable of supplying power. The electrodes exposed on the surface of the input / output die and the electrodes exposed on the surface of the third computing die are electrically connected. The through-electrode of the input / output die and the electrode exposed to the substrate are electrically connected to the first bump portion. The electrodes exposed in the lower wiring layer are electrically connected to the second bump portion. The semiconductor module according to claim 10.

16. Package substrate and The first bump portion of the semiconductor chip is electrically connected to the opposite side of the side to which it is electrically connected, and the second bump portion is electrically connected to the package substrate. It further possesses, The aforementioned semiconductor chip is A transistor layer comprising a substrate, through electrodes penetrating the substrate, electrodes exposed on the substrate, and a plurality of transistors, A wiring layer is stacked on the transistor layer and includes electrodes exposed on the surface, A lower wiring layer capable of supplying power is laminated on the side of the transistor layer opposite to the side on which the wiring layer is laminated, A plurality of circuits capable of controlling the cube chip, which is composed of the transistor layer, the wiring layer, and the lower wiring layer, and a plurality of network routers that electrically connect the cube chip and the plurality of circuits, It has, The through-electrode of the semiconductor chip and the electrode exposed to the substrate are electrically connected to the first bump portion. The electrodes exposed in the lower wiring layer are electrically connected to the second bump portion. The semiconductor module according to claim 5 or claim 8.

17. The aforementioned multiple IC chips are A first memory chip having multiple electrodes exposed on a substrate and having a memory formed on it, A first computing die having multiple electrodes electrically connected to multiple electrodes exposed on the substrate, and capable of controlling the first memory chip, Includes, The first computing die is in contact with the sixth surface, The semiconductor module according to claim 16.

18. The aforementioned multiple IC chips are A first memory chip having a first inductor and a memory formed thereon, A first computing die having a second inductor that can communicate with the first inductor and that can control the first memory chip, Includes, The first computing die is in contact with the sixth surface, The semiconductor module according to claim 16.

19. The plurality of wirings in the first metal wiring layer include a first wiring exposed on the first metal wiring layer. The plurality of wirings in the second metal wiring layer include a second wiring exposed on the second metal wiring layer. A first conductive film is electrically connected to the first wiring and is in contact with the surface of the first metal wiring layer on which the first wiring is exposed. A second conductive film is electrically connected to the second wiring and is in contact with the surface of the second metal wiring layer on which the second wiring is exposed. A first voltage supply unit that is in contact with the first conductive film and capable of supplying voltage to the first conductive film, A second voltage supply unit that is in contact with the second conductive film and capable of supplying voltage to the second conductive film, Further including, The semiconductor module according to claim 8.

20. A first heat spreader capable of dissipating heat and supplying power voltage, A second heat spreader capable of diffusing heat and supplying a reference voltage, A first conductive layer electrically connected to the first heat spreader, A second conductive layer electrically connected to the second heat spreader, It further includes, Each of the aforementioned plurality of IC chips is A fourth electrode exposed on the second surface and electrically connected to the first conductive layer, A fifth electrode exposed on the second surface and electrically connected to the second conductive layer, It further possesses, The semiconductor module according to claim 5 or claim 8.

21. A first heat spreader capable of dissipating heat, A second heat spreader capable of dissipating heat, A first conductive layer electrically connected to the first heat spreader, A second conductive layer electrically connected to the second heat spreader, The space formed by the first heat spreader, the second heat spreader, the first conductive layer, the second conductive layer, and the cube chip, It further includes, Each of the aforementioned plurality of IC chips further has a plurality of fourth electrodes exposed on the second surface, The first conductive layer is electrically connected to a plurality of fourth electrodes, The second conductive layer has a surface opposite to the fifth surface in contact with the first computing die, and a surface opposite to the sixth surface in contact with the second computing die, The semiconductor module according to claim 9.

22. The semiconductor chip and the cube chip are arranged along the first direction and electrically connected upward along the third direction using the first bump portion of the input / output die, Package substrate and A second bump portion is electrically connected between the input / output die and the package substrate, It further possesses, Each of the aforementioned plurality of IC chips is an IC chip on which memory is formed. The semiconductor module according to claim 2 or claim 5.

23. The system further includes a memory controller electrically connected between the semiconductor chip and the first bump portion, The memory controller is electrically connected to the semiconductor chip using a third bump portion, electrically connected to the input / output die using a first bump portion, and configured to control the cube chip. The semiconductor module according to claim 22.

24. The semiconductor chip and the cube chip are arranged along the first direction and electrically connected upward along the third direction using the first bump portion of the package substrate, A conductive layer provided on the side opposite to the package substrate along the third direction and connected to the semiconductor chip and the cube chip, A thermal conductive sheet electrically connected to the conductive layer, The thermal conductive sheet is connected to the lid that covers the semiconductor chip and the cube chip, and is provided on the package substrate. A sealing structure for fixing the semiconductor chip and the cube chip to the package substrate, It further possesses, Each of the aforementioned plurality of IC chips is an IC chip including DRAM, The semiconductor chip comprises a CPU electrically connected to a first input / output die including an input / output interface, a GPU electrically connected to a second input / output die including an input / output interface, and a support substrate supporting the CPU and the GPU. The package substrate has a plurality of electrodes exposed on its surface and a multilayer wiring structure electrically connected to the plurality of electrodes. The semiconductor chip is electrically connected to a plurality of electrodes exposed on the package substrate using a plurality of electrodes exposed on the first input / output die and the second input / output die. The cube chip is electrically connected to the semiconductor chip by the first bump portion, the plurality of electrodes exposed on the surface, the multilayer wiring structure, and the plurality of electrodes exposed on the first input / output die and the second input / output die. The semiconductor module according to claim 5 or claim 8.

25. Each of the aforementioned plurality of IC chips is an IC chip that has multiple memory banks and includes DRAM. The semiconductor module according to claim 5 or claim 8.

Images