Method for manufacturing a semiconductor device and semiconductor device

Abstract

This invention provides a method for manufacturing a semiconductor device and a semiconductor device that utilizes gallium oxide to increase the voltage resistance of the semiconductor device. [Solution] A method for manufacturing a semiconductor device using a gallium oxide single crystal wafer 200 comprises: an electric field relaxation layer formation step S101 in which an electric field relaxation layer 210 is formed on an N-type gallium oxide single crystal wafer 200 in contact with the flat surface 710 of the N-type gallium oxide single crystal wafer 200 to obtain an N-type gallium oxide single crystal wafer 200 with an electric field relaxation layer 210; a lamination step S150 in which inorganic films 600 and 650 having uniform or substantially uniform film thickness are laminated at different timings on the front flat surface 710 and the back flat surface 720 of the N-type gallium oxide single crystal wafer 200 with an electric field relaxation layer 210 to obtain an N-type gallium oxide single crystal wafer 200 with an inorganic film; and a heating step in which the N-type gallium oxide single crystal wafer 200 with the inorganic films 600 and 650 is heated.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a method for forming a high-resistance region in a Ga2O3-based single crystal for forming a high-resistance region by ion implantation in the Ga2O3-based single crystal, as well as a crystal laminated structure and a semiconductor element. As a next-generation switching element capable of achieving high breakdown voltage, low loss and high heat resistance, semiconductor devices using gallium oxide (Ga2O3) with a large energy band gap are attracting attention, and their application to power semiconductor devices such as inverters is expected. FIG. 1 of Patent Document 1 schematically shows a semiconductor element obtained by a method including a step of ion-implanting Mg or Be into a Ga2O3-based single crystal layer, and a step of activating Mg or Be by an annealing treatment at 800°C or higher to form a high-resistance region 15.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

Summary of Invention

Problems to be Solved by the Invention

[0005] A manufacturing method is known for increasing the voltage resistance of semiconductor devices using gallium oxide by introducing argon or nitrogen as an impurity, followed by activation annealing in a nitrogen or oxygen atmosphere. However, a known side effect of this method is that oxygen atoms constituting gallium oxide diffuse outward near the surface, forming oxygen vacancies and other structures, which in turn alters the composition of gallium oxide. In particular, it is suspected that this can lead to an increase in conduction resistance (Ron) in Schottky barrier diodes (SBDs). [Means for solving the problem]

[0006] In a first embodiment of the present invention, a method for manufacturing a semiconductor device using a gallium oxide single crystal wafer comprises: an electric field relaxation layer formation step of forming an electric field relaxation layer in contact with the flat surface of an N-type gallium oxide single crystal wafer to obtain an N-type gallium oxide single crystal wafer with an electric field relaxation layer; a lamination step of laminating inorganic films having uniform or substantially uniform thickness on the front flat surface and the back flat surface of the N-type gallium oxide single crystal wafer with the electric field relaxation layer at different timings to obtain an N-type gallium oxide single crystal wafer with an inorganic film; and a heating step of heating the N-type gallium oxide single crystal wafer with the inorganic film.

[0007] In a second embodiment of the present invention, a semiconductor device comprising an N-type gallium oxide single crystal substrate having an electric field relaxation layer exposed on a part of its surface includes an N-type gallium oxide single crystal substrate with an electric field relaxation layer, in which a part of an inorganic film provided at different timings on the flat surface of the front and the flat surface of the N-type gallium oxide single crystal substrate is in contact with the surface and the electric field relaxation layer during heating to electrically activate the electric field relaxation layer, and an electrode portion provided in contact with the gallium oxide single crystal substrate with the electric field relaxation layer after heating to electrically activate the electric field relaxation layer. [Effects of the Invention]

[0008] According to the present invention, by covering the gallium oxide with an inorganic film, even during activated annealing, the oxygen atoms constituting the gallium oxide are removed, suppressing the generation of oxygen vacancies, and consequently, suppressing the deterioration of the conduction characteristics of the Schottky barrier diode. Furthermore, even when activated annealing is performed in an oxygen atmosphere, it is possible to suppress the existence of a layer with an excess of oxygen near the surface of the gallium oxide crystal substrate.

[0009] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0010] [Figure 1] An example of a method for manufacturing a semiconductor device according to an embodiment of the present invention is schematically shown. [Figure 2] A schematic example of a cross-sectional view of a semiconductor device manufactured according to an embodiment of the present invention is shown. [Figure 3] An example of a gallium oxide single crystal wafer obtained in the electrode formation process according to an embodiment of the present invention is schematically shown. [Figure 4] A schematic example of a method for manufacturing a semiconductor device according to a conventional embodiment is shown. [Figure 5] A schematic example of a cross-sectional view of a semiconductor device manufactured by a conventional embodiment is shown. [Figure 6] A schematic example of a cross-sectional view of a device for stacking inorganic films at the same time is shown. [Modes for carrying out the invention]

[0011] The present invention will be described below through embodiments of the invention, but the following embodiments of the invention are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments of the invention are necessarily essential to the solution provided by the invention.

[0012] Furthermore, the semiconductor device obtained by the manufacturing method of the present invention is assumed to have a size that can be visually recognized by the naked eye. Therefore, the wave nature of electrons, which play an important role in semiconductor devices, is sufficiently spread within the semiconductor device. In particular, although various layers are provided inside a semiconductor substrate typified by a semiconductor base body, it is assumed that the wave nature of electrons is sufficiently spread even in such layers. Electrons are reflected on the inner side surface of the semiconductor base body, that is, on the inner surface of the semiconductor base body. The wave nature of electrons spreads to the outer side surface of the semiconductor base body, that is, to the outer surface of the semiconductor base body.

[0013] The drawings used in the following description are schematic, and the dimensional relationships of the respective elements, the ratios of the respective elements, and the like in the drawings do not necessarily match the actual ones. Further, the dimensional relationships of the respective elements, the ratios of the respective elements, and the like do not necessarily match among a plurality of drawings.

[0014] A part of the manufacturing process of a gallium oxide Schottky barrier diode according to an example of the present invention is shown in Figure 1. Figure 1 does not show all of the manufacturing processes of the gallium oxide Schottky barrier diode.

[0015] Figure 1 schematically shows a part of the cross section of the N-type gallium oxide single crystal wafer 200 before processing and a part of the cross sections of N-type gallium oxide single crystal wafers 250, 260, 270, and 280 obtained by performing the respective processes.

[0016] S101 in Figure 1 corresponds to the electric field relaxation layer forming step for obtaining the N-type gallium oxide single crystal wafer with an electric field relaxation layer according to the first aspect of the present invention described in the Summary of the Invention section. S150 in Figure 1 corresponds to the laminating step for obtaining the N-type gallium oxide single crystal wafer with an inorganic film according to the first aspect of the present invention described in the Summary of the Invention section. Figure 1 does not describe the step corresponding to the heating step of heating the N-type gallium oxide single crystal wafer with an inorganic film according to the first aspect of the present invention described in the Summary of the Invention section.

[0017] Step S100, shown in Figure 1, is a preliminary step for preparing an N-type gallium oxide single crystal wafer 200. This step is the starting point in the embodiment of the present invention. The type of N-type gallium oxide single crystal wafer prepared depends on the semiconductor device to be ultimately obtained. In the embodiment of the present invention, the objective is to ultimately obtain a gallium oxide Schottky barrier diode.

[0018] As indicated by the arrows in Figure 1, the starting step S100 is followed by step S101, which forms an electric field relaxation layer 210 in contact with the flat surface 710 of the N-type gallium oxide single crystal wafer 200. Step S101 is the electric field relaxation layer formation step. This step yields an N-type gallium oxide single crystal wafer 250 with an electric field relaxation layer. The type of electric field relaxation layer 210 formed depends on the semiconductor device that is ultimately to be obtained.

[0019] As indicated by the arrows in Figure 1, step S101, which is the field relaxation layer formation step, is followed by step S150, in which inorganic films 600 and 650, having uniform or substantially uniform film thicknesses, are laminated at the same or different timings onto the flat front surface 710 and the flat back surface 720 of the N-type gallium oxide single crystal wafer 250 with the field relaxation layer. Step S150 is a lamination step. This step yields the N-type gallium oxide single crystal wafer 260 with inorganic films.

[0020] The inorganic films 600 and 650 are formed to make it easier to suppress the outward diffusion of atoms constituting the N-type gallium oxide single crystal wafer 250 with the electric field relaxation layer from the N-type gallium oxide single crystal wafer 260 with the inorganic film during the subsequent heating process.

[0021] Following the lamination process S150, the process continues with heating the inorganic film-coated N-type gallium oxide single crystal wafer 260. This is to electrically activate the field relaxation layer 210.

[0022] As indicated by the arrows in Figure 1, this heating step is followed by step S151, which is a step to remove part or all of the inorganic film used to form the electrode region. Step S151 is an electrode region formation step. This step yields an N-type gallium oxide single crystal wafer 270 from which part or all of the inorganic film used to form the electrode region has been removed.

[0023] As indicated by the arrows in Figure 1, step S151, which is the electrode region formation step, is followed by step S160, which involves providing electrode layers 300 and 400 on the N-type gallium oxide single crystal wafer 270 with an inorganic film. Step S160 is the electrode formation step.

[0024] After step S160, which is an electrode formation process, a dicing process is performed in which the N-type gallium oxide single crystal wafer 280 is diced. As a result, a semiconductor device having a cross-section as shown in Figure 2, namely a gallium oxide Schottky barrier diode 160, is obtained.

[0025] In Figure 1, there are other steps that have been omitted besides heating. These include, for example, the mask formation and mask removal steps for electrode region formation. Other omitted steps include pre-treatment steps such as wafer cleaning.

[0026] The following details describe the N-type gallium oxide single crystal wafer 200, which serves as the starting point for process S100.

[0027] In embodiments of the present invention, the N-type gallium oxide single crystal wafer before processing is not limited to an N-type gallium oxide single crystal wafer consisting of two layers with different electrical conductivity, such as the gallium oxide single crystal wafer 200 shown in the example.

[0028] As an example, the crystal structure of the N-type gallium oxide single crystal wafer 200 according to the embodiment of the present invention is β-type. The crystal structure of the N-type gallium oxide single crystal wafer 200 may also be other crystal structures such as α-type.

[0029] For example, the N-type gallium oxide single crystal wafer 200, like the silicon single crystal wafer, has a roughly disc-like shape consisting of two roughly circular flat surfaces and one side surface. The flat surfaces of the N-type gallium oxide single crystal wafer 200 are the

[0001] surface and its opposite surface. However, due to manufacturing reasons, these surfaces may not be strictly the ideal

[0001] surface and its opposite surface.

[0030] For reference, Figure 3 shows the N-type gallium oxide single crystal wafer 280 obtained in the above process S160, viewed from a direction where the flat surface is visible. The dashed line in Figure 3 is a virtual line that serves as a guide for dicing in the dicing process.

[0031] The thickness of an N-type gallium oxide single crystal wafer 200 is generally very thin compared to the size of its flat surface, similar to a silicon single crystal wafer. For example, the diameter of a roughly circular flat surface of an N-type gallium oxide single crystal wafer 200 is approximately 60 mm. For example, the thickness of an N-type gallium oxide single crystal wafer 200 is approximately 0.6 mm.

[0032] Due to the processing performed in each step, the flat surfaces of N-type gallium oxide single crystal wafers 250, 260, 270, and 280 may not only have irregularities but may also warp overall, resulting in a surface that is no longer ideally flat.

[0033] Similar to silicon single-crystal wafers, the N-type gallium oxide single-crystal wafer 200 is diced after various processing is performed on its flat surface. Since the sides of the N-type gallium oxide single-crystal wafer 200 before processing do not become part of the semiconductor device that is cut out, the sides of the N-type gallium oxide single-crystal wafer 200 are not shown in Figure 1.

[0034] The sides of the N-type gallium oxide single crystal wafer 200 before processing may have various shapes for various purposes, similar to silicon single crystal wafers.

[0035] Gallium oxide single crystals have a unique characteristic compared to other semiconductor materials: they are brittle. Therefore, it is sometimes desirable to design the shape of their sides.

[0036] The N-type gallium oxide single crystal wafer 200 may be manufactured by a third party.

[0037] This is because there is a challenge in reducing the manufacturing cost of semiconductor devices using gallium oxide single crystals.

[0038] The N-type gallium oxide single crystal wafer 200 may be provided with an orientation flat or the like. This is to facilitate the handling of the N-type gallium oxide single crystal wafer 200.

[0039] The N-type gallium oxide single crystal wafer 200 does not have to be disc-shaped. The N-type gallium oxide single crystal wafer 200 may be obtained by cutting a disc-shaped wafer into a rectangular parallelepiped shape by dicing or the like. This is because gallium oxide single crystals have cleavage properties in a certain direction.

[0040] The N-type gallium oxide single crystal wafer 200 may be formed from multiple layers with different dopant concentrations. This may be due to design reasons for the semiconductor device being manufactured.

[0041] As shown in Figure 1, the N-type gallium oxide single crystal wafer 200 according to the example is formed from two layers with different dopant concentrations. Generally, different dopant concentrations result in different electrical conductivity, although this also depends on the activation rate. As an example, N - Gallium oxide layer 201 and N + The approximate dopant concentrations in the gallium oxide layer 202 are 2 × 10⁻⁶ each. 16 cm -3 and 1 × 10 19 cm -3 That is the case.

[0042] The field relaxation layer formation process, described as process S101, will be explained in detail below.

[0043] Step S101, which is a field relaxation layer formation step, is a step in which a field relaxation layer 210 is formed, which is one of the components of the gallium oxide Schottky barrier diode 160, a semiconductor device that is ultimately manufactured. Aspects of the present invention are applicable to methods for manufacturing semiconductor devices using gallium oxide single crystal wafers as materials, specifically those requiring a field relaxation layer formation step. Therefore, step S101, which is the process of forming an electric field relaxation layer, is essential as an example.

[0044] To form the electric field relaxation layer 210, for example, ionized nitrogen atoms (N) are implanted into the N-type gallium oxide single crystal wafer 200 using a principle similar to the ion implantation process used in the normal manufacturing process of semiconductor devices using silicon wafers (Non-Patent Literature 1).

[0045] To implant in a specific region, a mask may be provided to block implantation, using a principle similar to the ion implantation process performed in the normal manufacturing process of semiconductor devices using silicon wafers.

[0046] Nitrogen atoms implanted in a gallium oxide single crystal can form an electric field relaxation layer 210.

[0047] In addition, iron atoms (Fe), beryllium atoms (Be), zinc atoms (Zn), phosphorus atoms (P), oxygen atoms (O), argon atoms (Ar), or magnesium atoms (Mg) may be used instead of nitrogen atoms.

[0048] For nitrogen atoms injected into an N-type gallium oxide single crystal to function as acceptors in a semiconductor device, the nitrogen atoms must be electrically activated. This electrical activation leads to the establishment of specific energy levels within the energy band gap, from the perspective of the electron's energy band structure.

[0049] For this purpose, a high-temperature heating step is provided after the ion implantation step, similar to the manufacturing process of general semiconductor devices. As a result, for example, the electric field relaxation layer 210 after heating may have such high resistance that it is difficult to measure its resistance value, making it close to an insulator.

[0050] In semiconductor devices using gallium oxide single crystals, the heating temperature required to activate nitrogen atoms may be 1000K or higher.

[0051] Conventionally, regardless of whether the gallium oxide single crystal was N-form or P-form, a phenomenon was observed in which constituent atoms diffused outward from within the gallium oxide single crystal during the heating process (Non-Patent Literature 2). As a result, at the atomic level, it was suspected that the crystal structure near the surface of the gallium oxide single crystal wafer would be disordered due to the generation of vacancies, etc., and that the electrical properties of the final semiconductor device would be poor.

[0052] There was a problem in that, although the heating time shortened as the heating temperature for activation increased, the outward diffusion of the constituent atoms became more active, and it was predicted that the electrical properties of the final semiconductor device would deteriorate further.

[0053] Conversely, lowering the heating temperature for activation required longer heating times, resulting in a decrease in the productivity of semiconductor devices. Even when implanting nitrogen atoms, there were challenges in determining the concentration profile and other factors, taking outward diffusion into consideration.

[0054] Consequently, there was a challenge in that the time and cost required to search for the optimal conditions such as injection energy, injection concentration, number of injections, and heating process recipes became enormous.

[0055] Methods for forming the electric field relaxation layer 210 can be considered other than the method of implanting ionized atoms.

[0056] One such method involves creating grooves with a recessed shape on the flat surface of a gallium oxide single crystal wafer by etching or other means, and then filling these grooves with P-type semiconductor material using sputtering or CVD.

[0057] Specific P-type semiconductor materials include materials composed of nickel oxide (NiO)-based materials, copper oxide (CuO, Cu2O)-based materials, or tin oxide (SnO)-based materials, or combinations thereof.

[0058] For example, the groove may be filled using only nickel oxide (NiO)-based material. Alternatively, part of the groove may be filled with nickel oxide (NiO)-based material, and then the remaining part of the groove may be filled with tin oxide (SnO)-based material.

[0059] Alternatively, instead of creating grooves as described above, a method is also possible in which nickel oxide (NiO)-based material, copper oxide (CuO, Cu2O)-based material, or tin oxide (SnO)-based material, or a combination thereof, is laminated onto the flat surface of a gallium oxide single crystal wafer by sputtering or CVD.

[0060] For example, nickel oxide (NiO)-based materials may be laminated only on the flat surface of the wafer. Alternatively, after laminating nickel oxide (NiO)-based materials, tin oxide (SnO)-based materials may be laminated on the flat surface of the wafer. In any case, these stacking processes can result in the flat surface of the gallium oxide single crystal wafer being not strictly flat, but rather having irregularities.

[0061] In all of these cases, as with ion implantation, outward diffusion of gallium oxide and the constituent atoms forming the field relaxation layer is unavoidable due to the heating process performed to electrically activate the field relaxation layer. Therefore, there were challenges such as deterioration of electrical characteristics or decrease in productivity, which in turn led to increased production costs, as well as enormous costs and time required for prototyping to determine the optimal heating conditions.

[0062] To solve the various problems mentioned above, in this embodiment, step S150 is performed after step S101, which is the field relaxation layer formation step.

[0063] Step S150 is a lamination process in which inorganic films 600 and 650, having uniform or substantially uniform film thicknesses, are laminated on the flat front surface 710 and the flat back surface 720 of an N-type gallium oxide single crystal wafer 250 with an electric field relaxation layer, at the same or different timings, to obtain an N-type gallium oxide single crystal wafer 260 with an inorganic film.

[0064] The thickness of the inorganic film 600 or 650 was set to several tens of nanometers to several micrometers. The thickness of the inorganic film 600 or 650 only needs to be above a certain thickness to suppress outward diffusion.

[0065] The thickness of the inorganic film 600 or 650 should preferably be uniform or nearly uniform regardless of its position. This is because the inorganic film-coated N-type gallium oxide single crystal wafer 260 becomes less prone to warping, and handling of the inorganic film-coated N-type gallium oxide single crystal wafer 260 in subsequent processes becomes less difficult.

[0066] The degree of variation in the thickness of inorganic films is difficult to determine numerically because it can vary depending on the specific semiconductor manufacturing technology and equipment used, as well as the type of inorganic film being layered.

[0067] The inorganic film may be formed from silicon oxide (SiO2), aluminum oxide (Al2O3), or carbon (C).

[0068] Silicon oxide, aluminum oxide, and carbon do not react with gallium oxide during the heating process. This has been confirmed by thermodynamic simulations under standard atmospheric pressure of 101325 Pa and a temperature of 1173 K. Needless to say, no other substances are formed at a heating temperature lower than 1173 K, namely 1073 K. In other words, films of silicon oxide, aluminum oxide, or carbon are suitable for suppressing outward diffusion.

[0069] The silicon oxide film according to the embodiment of the present invention is not obtained by heating the underlying semiconductor substrate, and is therefore fundamentally different from a silicon oxide film obtained by heating a silicon substrate in an oxygen atmosphere. A silicon oxide film obtained by heating a silicon substrate in an oxygen atmosphere is also called a thermal oxide film.

[0070] Selecting the constituent atoms for the layer that suppresses outward diffusion is not easy. This is because gallium oxide is composed of gallium atoms and oxygen atoms, resulting in a very large number of reaction combinations. Furthermore, it requires not only a high-temperature heating furnace but also appropriate exhaust gas equipment, which significantly increases the cost and time of the experiment.

[0071] For example, the inorganic film may consist of a single layer made of one type of aluminum oxide film. Alternatively, for example, the inorganic film may consist of two layers made of silicon oxide and aluminum oxide film.

[0072] Silicon may not be used as the material for inorganic film 600 or 650. This is because gallium oxide decomposes to produce gallium (Ga) or silicon oxide (SiO2).

[0073] Silicon nitride may not be used as the material for inorganic film 600 or 650. This is because gallium oxide decomposes to produce gallium nitride (GaN) or silicon oxide (SiO2).

[0074] There may be multiple heating steps for laminating the inorganic film 600 or 650.

[0075] The heating temperature in the heating step for lamination of the inorganic film 600 or 650 may change over time.

[0076] The heating process for laminating inorganic films 600 or 650 does not need to be carried out in an oxygen atmosphere, because gallium oxide gas (GaO or Ga2O) is generated.

[0077] The heating process for laminating inorganic films 600 or 650 does not need to be carried out in a nitrogen atmosphere, because nitrogen oxide gas (NO or N2O) is generated.

[0078] Any of these inorganic films may be formed by a commonly known chemical vapor deposition method.

[0079] This is because various excellent devices have been developed and are being used as film deposition equipment based on chemical vapor deposition.

[0080] The inorganic film shown in step S150 of Figure 1 may be laminated on two flat surfaces 710 and 720 of the N-type gallium oxide single crystal wafer with an electric field relaxation layer at different timings.

[0081] The order in which the inorganic films are layered on the flat surfaces 710 and 720 can vary depending on various conditions. For example, the inorganic film may first be laminated on the flat surface 710 of the N-type gallium oxide single crystal wafer with an electric field relaxation layer, and then laminated on the flat surface 720.

[0082] For example, the inorganic film may first be laminated on the flat surface 720 of the N-type gallium oxide single crystal wafer with an electric field relaxation layer, and then laminated on the flat surface 710.

[0083] The inorganic film may be repeatedly deposited on the flat surfaces 710 and 720 at different timings.

[0084] For example, the inorganic film may be first laminated on the flat surface 710 of an N-type gallium oxide single crystal wafer with an electric field relaxation layer, then laminated on the flat surface 710, then laminated on the flat surface 710, and finally laminated on the flat surface 720.

[0085] The inorganic film shown in step S150 of Figure 1 may be laminated on two flat surfaces 710 and 720 of the N-type gallium oxide single crystal wafer with an electric field relaxation layer at the same time.

[0086] This makes it easier to prevent problems such as wafer cracking caused by the difference in thermal expansion coefficients between inorganic films and gallium oxide single crystals.

[0087] The inorganic film may be laminated onto the flat surfaces 710 and 720 in multiple layers at the same time. As an example, the inorganic film may first be laminated on the flat surfaces 710 and 720 of an N-type gallium oxide single crystal wafer with an electric field relaxation layer, and then further laminated on the flat surfaces 710 and 720.

[0088] Given that gallium oxide single crystals are more brittle than other semiconductor materials, it is more desirable to stack inorganic films on the single crystal wafer at the same time rather than at different times. As an example, when forming an inorganic film using the generally well-known chemical vapor deposition method, there is an example of a device that stacks the inorganic film onto a single-crystal wafer at the same time, as shown in Figure 6.

[0089] Here, the apparatus shown in Figure 6 consists of a support shaft 921, a substrate support part 922, a substrate support part 923, a substrate support part 924, a heating unit 931, a heating unit 932, a first power supply 941, a second power supply 942, a reaction chamber 960, a reaction gas inlet 961, a reaction gas exhaust port 962, and a bellows 963 (Patent Document 2).

[0090] In fact, this invention, which may appear to be merely a process of stacking inorganic films before a high-temperature heating step, does not focus on a stacked structure that can be perceived visually, but rather on the behavior of atoms at the atomic level.

[0091] Therefore, it can be said that the present invention was not made simply for the purpose of providing an insulating part or a protective part, as is often seen in the manufacturing process of conventional semiconductor devices.

[0092] Generally, when manufacturing semiconductor devices using gallium oxide single crystals, it is necessary to further consider the interactions between oxygen atoms, gallium atoms, and atoms added to constitute the N-type and P-type regions.

[0093] In this invention, the complexity increases because the atoms constituting the inorganic film are further added to the atoms that need to be considered, making it essentially different from the manufacturing process of conventional semiconductor devices.

[0094] In this example, the support section that holds the wafer substrate consists of three parts, corresponding to the substrate support sections 922, 923, and 924.

[0095] The wafer substrate is supported by the support portion. The support portion rotates as the support shaft 921 rotates, which in turn causes the wafer substrate to rotate.

[0096] Rotating the wafer substrate makes it easier to improve the uniformity of the thickness of the layered inorganic films.

[0097] The reaction gas 927 is introduced into the reaction chamber 960 from the reaction gas inlet 961 and exits through the reaction gas exhaust port 962 of the reaction chamber 960. At the same time, the reaction gas 927 reacts with the upper surface 911 and the lower surface 912 of the substrate.

[0098] The presence of inorganic films 600 and 650 makes it easier to suppress the outward diffusion of atoms that will subsequently constitute the semiconductor device, even when the electric field relaxation layer 210 is heated for electrical activation. As a result, it becomes easier to achieve a significant improvement in the electrical properties of the manufactured semiconductor device.

[0099] However, determining the structural characteristics of the material is difficult because it requires observation at the atomic level. Even if outward diffusion is suppressed during the heating process, it is possible that certain types of atomic aggregates that have not been observed are formed between the constituent atoms.

[0100] Here, Figure 4 shows an example of a conventional manufacturing method that does not include the lamination process described in the embodiment, such as step S150.

[0101] As can be seen from Figures 4 and 1, the only difference between the manufacturing method of the embodiment according to the present invention and the conventional manufacturing method is the presence or absence of a lamination step, such as S150, which is part of the embodiment of the present invention. In the conventional example shown in Figure 4, there is no lamination step, and therefore there is no equivalent to the inorganic film 601 according to the embodiment of the present invention.

[0102] Figure 5 shows a cross-section of the gallium oxide Schottky barrier diode 120 obtained by the conventional manufacturing method shown in Figure 4.

[0103] The × symbols in Figures 4 and 5 schematically represent outward diffusion of constituent atoms, resulting in the creation of vacancies 500 and 510. It is not well understood, and extremely difficult to determine, exactly which atoms—gallium atoms, oxygen atoms, or atoms forming the electric field relaxation layer—constitute outward diffusion in the gallium oxide single crystal, and in what form. For example, it is unclear whether outward diffusion occurs simply as single atoms.

[0104] Therefore, the above assumption that heating causes specific atoms to diffuse outward and create vacancies may not necessarily be correct. It is also possible that heating causes specific atoms to gather together and form a different aggregate.

[0105] Step S151 is a step of removing the inorganic film in the portion where the electrode layer is to be formed from a gallium oxide single crystal wafer having an activated electric field relaxation layer 210 that has been heated after step S150.

[0106] As shown in S150, a portion of the inorganic film 600 on the side where the electric field relaxation layer is formed is removed by an etching process using the same principle as the etching process used in the manufacturing process of semiconductor devices using silicon wafers. The etching process may be dry or wet.

[0107] Similarly, the entire inorganic film 650 on the side where the electric field relaxation layer is not formed, as shown in S150, is removed using a principle similar to the etching process used in the manufacturing process of semiconductor devices using silicon wafers. The etching process may be dry or wet.

[0108] Step S160 is the electrode formation step.

[0109] Chemical vapor deposition or the like may be used to form the electrodes.

[0110] After the etching process, as shown in S160, the metal material for the electrodes is laminated as a metal layer on the flat surface of the N-type gallium oxide single crystal wafer 280. Then, a portion of the metal layer on the side where the electric field relaxation layer is formed is removed by etching using a principle similar to that used in the manufacturing process of semiconductor devices using silicon wafers. The etching process may be dry or wet.

[0111] Figure 3 schematically shows the N-type gallium oxide single crystal wafer 280 as viewed from the flat surface side when a cross-section as shown in S160 is obtained. The dashed line in Figure 3 is a virtual line for dicing. Along this virtual line, the semiconductor device 160 as shown in Figure 2 is cut out from the gallium oxide single crystal wafer 280.

[0112] Up to this point, embodiments for carrying out the present invention have been described based on examples from the perspective of the manufacturing method, but the features of the present invention can also be described from a different perspective.

[0113] As one of the first specific examples from a different perspective, the semiconductor device 160 shown in Figure 2 is a semiconductor device in which an electric field relaxation layer 210 is exposed on a portion of the surfaces 750 and 760 of an N-type gallium oxide single crystal substrate, and the semiconductor device 160 comprises an N-type gallium oxide single crystal substrate 200 with an electric field relaxation layer, in which a portion of the inorganic film provided on the flat front surface and the flat back surface of the N-type gallium oxide single crystal substrate is in contact with the surfaces 750 and 760 and the electric field relaxation layer 210 at different timings during heating to electrically activate the electric field relaxation layer 210, and electrode portions 300 and 400 provided in contact with the gallium oxide single crystal substrate 200 with an electric field relaxation layer after heating to electrically activate the electric field relaxation layer 210.

[0114] The semiconductor device shown in Figure 2 corresponds to the semiconductor device in the second embodiment of the present invention described in the section on the summary of the invention. Surfaces 750 and 760 of the N-type gallium oxide single crystal substrate correspond to the surface of the N-type gallium oxide single crystal substrate in the second embodiment of the present invention as described in the summary of the invention. The electric field relaxation layer 210 corresponds to the electric field relaxation layer in the second embodiment of the present invention as described in the summary of the invention section. The N-type gallium oxide single crystal substrate 200 corresponds to the N-type gallium oxide single crystal substrate with an electric field relaxation layer in the second aspect of the present invention described in the summary of the invention, in which, during heating to electrically activate the electric field relaxation layer, a portion of the inorganic film provided on the flat surface of the front and the flat surface of the back of the N-type gallium oxide single crystal substrate at different timings is in contact with the surface and the electric field relaxation layer. The electrode portions 300 and 400 correspond to the electrode portions in the second embodiment of the present invention as described in the summary of the invention section.

[0115] The field relaxation layer may consist of a nickel oxide (NiO)-based material, a copper oxide (CuO, Cu2O)-based material, or a tin oxide (SnO)-based material, or a combination thereof. These materials function as P-type semiconductor materials.

[0116] The field relaxation layer may be formed from any of the following: nitrogen atoms (N), iron atoms (Fe), beryllium atoms (Be), zinc atoms (Zn), phosphorus atoms (P), oxygen atoms (O), argon atoms (Ar), or magnesium atoms (Mg). These atoms act as dopant atoms.

[0117] The inorganic film may consist of at least silicon oxide, aluminum oxide, or carbon.

[0118] The silicon oxide film according to the embodiment of the present invention is not obtained by heating the underlying semiconductor substrate, and is therefore fundamentally different from a silicon oxide film obtained by heating a silicon substrate in an oxygen atmosphere. A silicon oxide film obtained by heating a silicon substrate in an oxygen atmosphere is also called a thermal oxide film.

[0119] As a second specific example from a different perspective, a method for manufacturing an N-type gallium oxide single crystal wafer with an inorganic film comprises: an electric field relaxation layer formation step of forming an electric field relaxation layer in contact with the flat surface of an N-type gallium oxide single crystal wafer to obtain an N-type gallium oxide single crystal wafer with an electric field relaxation layer; and a lamination step of laminating an inorganic film having a uniform or substantially uniform thickness on the front flat surface and the back flat surface of the N-type gallium oxide single crystal wafer with the electric field relaxation layer at different timings to obtain an N-type gallium oxide single crystal wafer with an inorganic film.

[0120] This method for manufacturing an inorganic film-coated N-type gallium oxide single crystal wafer can be considered the method for manufacturing an inorganic film-coated N-type gallium oxide single crystal wafer in the third aspect of the present invention, as described in the summary of the invention. This is because a part of the first aspect of the present invention is a method for manufacturing an inorganic film-coated N-type gallium oxide single crystal wafer.

[0121] The field relaxation layer may consist of any of the following: nickel oxide (NiO)-based material, copper oxide (CuO, Cu2O)-based material, or tin oxide (SnO)-based material, or a combination thereof.

[0122] The field relaxation layer may be formed from any of the following: nitrogen atoms (N), iron atoms (Fe), beryllium atoms (Be), zinc atoms (Zn), phosphorus atoms (P), oxygen atoms (O), argon atoms (Ar), or magnesium atoms (Mg).

[0123] The inorganic film may consist of at least silicon oxide, aluminum oxide, or carbon.

[0124] As a third specific example from a different perspective, an N-type gallium oxide single crystal wafer with an inorganic film comprises an N-type gallium oxide single crystal wafer having an electric field relaxation layer in contact with its flat surface, and an inorganic film having a uniform or substantially uniform thickness, which is laminated at different timings on the front and back flat surfaces of the N-type gallium oxide single crystal wafer.

[0125] This inorganic film-coated N-type gallium oxide single crystal wafer can be considered as the inorganic film-coated N-type gallium oxide single crystal wafer in the fourth aspect of the present invention described in the summary of the invention section. This is because the inorganic film-coated N-type gallium oxide single crystal wafer is disclosed in the first aspect of the present invention.

[0126] The field relaxation layer may consist of any of the following: nickel oxide (NiO)-based material, copper oxide (CuO, Cu2O)-based material, or tin oxide (SnO)-based material, or a combination thereof.

[0127] The field relaxation layer may be formed from any of the following: nitrogen atoms (N), iron atoms (Fe), beryllium atoms (Be), zinc atoms (Zn), phosphorus atoms (P), oxygen atoms (O), argon atoms (Ar), or magnesium atoms (Mg).

[0128] The inorganic film may consist of at least silicon oxide, aluminum oxide, or carbon.

[0129] As a fourth specific example from a different perspective, a method for manufacturing an N-type gallium oxide single crystal wafer with an inorganic film comprises a lamination step of laminating an inorganic film having a uniform or substantially uniform thickness onto the flat front surface and the flat back surface of an N-type gallium oxide single crystal wafer at different timings to obtain an N-type gallium oxide single crystal wafer with an inorganic film.

[0130] This method for manufacturing an inorganic film-coated N-type gallium oxide single crystal wafer can be considered the method for manufacturing an inorganic film-coated N-type gallium oxide single crystal wafer in the fifth aspect of the present invention, as described in the summary of the invention. This is because it is part of the first aspect of the present invention and is a method for manufacturing an inorganic film-coated N-type gallium oxide single crystal wafer when there is no field relaxation layer.

[0131] The field relaxation layer may consist of any of the following: nickel oxide (NiO)-based material, copper oxide (CuO, Cu2O)-based material, or tin oxide (SnO)-based material, or a combination thereof.

[0132] The field relaxation layer may be formed from any of the following: nitrogen atoms (N), iron atoms (Fe), beryllium atoms (Be), zinc atoms (Zn), phosphorus atoms (P), oxygen atoms (O), argon atoms (Ar), or magnesium atoms (Mg).

[0133] The inorganic film may consist of at least silicon oxide, aluminum oxide, or carbon.

[0134] As a fifth specific example from a different perspective, an inorganic film-coated N-type gallium oxide single crystal wafer comprises a lamination step of laminating an inorganic film having a uniform or substantially uniform thickness onto the flat front surface and the flat back surface of an N-type gallium oxide single crystal wafer at different timings to obtain an inorganic film-coated N-type gallium oxide single crystal wafer.

[0135] This inorganic film-coated N-type gallium oxide single crystal wafer can be considered as an inorganic film-coated N-type gallium oxide single crystal wafer according to the sixth aspect of the present invention described in the summary of the invention. This is because it is part of the first aspect of the present invention and is an inorganic film-coated N-type gallium oxide single crystal wafer without an electric field relaxation layer.

[0136] The inorganic film may consist of at least silicon oxide, aluminum oxide, or carbon.

[0137] (Note 1) A method for manufacturing a semiconductor device using a gallium oxide single crystal wafer, The aforementioned manufacturing method is A field relaxation layer formation step is performed to form a field relaxation layer in contact with the flat surface of an N-type gallium oxide single crystal wafer, thereby obtaining an N-type gallium oxide single crystal wafer with a field relaxation layer. A lamination step to obtain an N-type gallium oxide single crystal wafer with an inorganic film, wherein an inorganic film having a uniform or substantially uniform thickness is laminated on the flat front surface and the flat back surface of the N-type gallium oxide single crystal wafer with the electric field relaxation layer at different timings, A heating step for heating the N-type gallium oxide single crystal wafer with the inorganic film, A manufacturing method that includes the following features.

[0138] (Note 2) A method for manufacturing a semiconductor device using a gallium oxide single crystal wafer, The field relaxation layer consists of a nickel oxide-based material, a copper oxide-based material, or a tin oxide-based material, or a combination thereof. The manufacturing method described in Appendix 1.

[0139] (Note 3) A method for manufacturing a semiconductor device using a gallium oxide single crystal wafer, The electric field relaxation layer is formed of any one of nitrogen atoms, iron atoms, beryllium atoms, zinc atoms, phosphorus atoms, oxygen atoms, argon atoms, or magnesium atoms. The manufacturing method described in Appendix 1.

[0140] (Note 4) A method for manufacturing a semiconductor device using a gallium oxide single crystal wafer, The inorganic film is made of silicon oxide, aluminum oxide, or carbon. The manufacturing method described in Appendix 1.

[0141] (Note 5) A semiconductor device comprising an N-type gallium oxide single crystal substrate with an electric field relaxation layer exposed on a portion of its surface, The aforementioned semiconductor device is In an N-type gallium oxide single crystal substrate with an electric field relaxation layer, a portion of the inorganic film, which is provided at different timings on the flat surface of the front and the flat surface of the back of the N-type gallium oxide single crystal substrate, is in contact with the surface and the electric field relaxation layer during heating to electrically activate the electric field relaxation layer. After heating to electrically activate the electric field relaxation layer, an electrode portion provided in contact with the gallium oxide single crystal substrate with the electric field relaxation layer, A semiconductor device equipped with a semiconductor device.

[0142] (Note 6) A semiconductor device comprising an N-type gallium oxide single crystal substrate with an electric field relaxation layer exposed on a portion of its surface, The field relaxation layer consists of a nickel oxide-based material, a copper oxide-based material, or a tin oxide-based material, or a combination thereof. Semiconductor device as described in Appendix 5.

[0143] (Note 7) A semiconductor device comprising an N-type gallium oxide single crystal substrate with an electric field relaxation layer exposed on a portion of its surface, The electric field relaxation layer is formed of any one of nitrogen atoms, iron atoms, beryllium atoms, zinc atoms, phosphorus atoms, oxygen atoms, argon atoms, or magnesium atoms. Semiconductor device as described in Appendix 5.

[0144] (Note 8) A semiconductor device comprising an N-type gallium oxide single crystal substrate with an electric field relaxation layer exposed on a portion of its surface, The inorganic film is made of silicon oxide, aluminum oxide, or carbon. Semiconductor device as described in Appendix 5.

[0145] (Note 9) A method for manufacturing an N-type gallium oxide single crystal wafer with an inorganic film, The aforementioned manufacturing method is A field relaxation layer formation step is performed to form a field relaxation layer in contact with the flat surface of an N-type gallium oxide single crystal wafer, thereby obtaining an N-type gallium oxide single crystal wafer with a field relaxation layer. A lamination step to obtain an N-type gallium oxide single crystal wafer with an inorganic film, wherein an inorganic film having a uniform or substantially uniform thickness is laminated on the flat front surface and the flat back surface of the N-type gallium oxide single crystal wafer with the electric field relaxation layer at different timings, A manufacturing method that includes the following features.

[0146] (Note 10) A method for manufacturing an N-type gallium oxide single crystal wafer with an inorganic film, The field relaxation layer consists of a nickel oxide-based material, a copper oxide-based material, or a tin oxide-based material, or a combination thereof. The manufacturing method described in Appendix 9.

[0147] (Note 11) A method for manufacturing an N-type gallium oxide single crystal wafer with an inorganic film, The electric field relaxation layer is formed of any one of nitrogen atoms, iron atoms, beryllium atoms, zinc atoms, phosphorus atoms, oxygen atoms, argon atoms, or magnesium atoms. The manufacturing method described in Appendix 9.

[0148] (Note 12) A method for manufacturing an N-type gallium oxide single crystal wafer with an inorganic film, The inorganic film is made of silicon oxide, aluminum oxide, or carbon. The manufacturing method described in Appendix 9.

[0149] (Note 13) An N-type gallium oxide single crystal wafer with an inorganic film, The aforementioned N-type gallium oxide single crystal wafer with inorganic film is An N-type gallium oxide single crystal wafer having an electric field relaxation layer in contact with its flat surface, An inorganic film, having a uniform or substantially uniform film thickness, is laminated at different timings on the flat surface of the front and the flat surface of the back of the aforementioned N-type gallium oxide single crystal wafer. An N-type gallium oxide single crystal wafer with an inorganic film.

[0150] (Note 14) An N-type gallium oxide single crystal wafer with an inorganic film, The field relaxation layer consists of a nickel oxide-based material, a copper oxide-based material, or a SnO-based material, or a combination thereof. N-type gallium oxide single crystal wafer with inorganic film as described in Appendix 13.

[0151] (Note 15) An N-type gallium oxide single crystal wafer with an inorganic film, The electric field relaxation layer is formed of any one of nitrogen atoms, iron atoms, beryllium atoms, zinc atoms, phosphorus atoms, oxygen atoms, argon atoms, or magnesium atoms. N-type gallium oxide single crystal wafer with inorganic film as described in Appendix 13.

[0152] (Note 16) An N-type gallium oxide single crystal wafer with an inorganic film, The inorganic film is made of silicon oxide, aluminum oxide, or carbon. N-type gallium oxide single crystal wafer with inorganic film as described in Appendix 13.

[0153] (Note 17) A method for manufacturing an N-type gallium oxide single crystal wafer with an inorganic film, The aforementioned manufacturing method is A lamination process to obtain an N-type gallium oxide single crystal wafer with an inorganic film, wherein an inorganic film having a uniform or substantially uniform thickness is laminated on the flat front surface and the flat back surface of an N-type gallium oxide single crystal wafer at different timings, A manufacturing method that includes the following features.

[0154] (Note 18) A method for manufacturing an N-type gallium oxide single crystal wafer with an inorganic film, The inorganic film is made of silicon oxide, aluminum oxide, or carbon. The manufacturing method described in Appendix 17.

[0155] (Note 19) An N-type gallium oxide single crystal wafer with an inorganic film, The aforementioned N-type gallium oxide single crystal wafer with inorganic film is An inorganic film is formed by laminating an inorganic film with a uniform or substantially uniform film thickness onto the flat front surface and the flat back surface of an N-type gallium oxide single crystal wafer at different timings. An N-type gallium oxide single crystal wafer with an inorganic film.

[0156] (Note 20) An N-type gallium oxide single crystal wafer with an inorganic film, The inorganic film is made of silicon oxide, aluminum oxide, or carbon. N-type gallium oxide single crystal wafer with inorganic film as described in Appendix 19.

[0157] As described above, the present invention has been explained using examples, but the technical scope of the present invention is not limited to the embodiments described above. It will be obvious to those skilled in the art that various modifications or improvements can be made to the contents of the above embodiments. It is clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0158] It should be noted that the sequence of apparatus, processes, or the operation of apparatus shown in the claims, specification, and drawings is not explicitly stated as "before," "prior to," etc., and can be implemented in any order unless the results of a previous process are used in a later process. Even if the claims, specification, and the operation of apparatus are described using phrases such as "first," "next," etc., it does not mean that they must be carried out in that order. [Explanation of Symbols]

[0159] 160...Gallium oxide Schottky barrier diode, 200...N-type gallium oxide single crystal wafer, 201...N - Gallium oxide layer, 202···N + Gallium oxide layer, 205...N-type gallium oxide substrate, 206...N-type gallium oxide substrate, 210...Field relaxation layer, 250...N-type gallium oxide single crystal wafer, 260...N-type gallium oxide single crystal wafer, 270...N-type gallium oxide single crystal wafer, 280...N-type gallium oxide single crystal wafer, 300...Metal film, 400...Metal film, 500...Vacancies, 510...Vacancies, 600...Inorganic film, 601...Inorganic film, 650...Inorganic film, 700...Gallium oxide single Crystal wafer, 710...flat surface, 720...flat surface, 750...surface, 760...surface, 911...top surface of substrate, 912...bottom surface of substrate, 921...support shaft, 922...substrate support, 923...substrate support, 924...substrate support, 927...reaction gas, 931...heating section, 932...heating section, 941...first power supply, 942...second power supply, 960...reaction chamber, 961...reaction gas inlet, 962...reaction gas exhaust port, 963...bellows

Claims

1. A method for manufacturing a semiconductor device using a gallium oxide single crystal wafer, The aforementioned manufacturing method is A field relaxation layer formation step is performed to form a field relaxation layer on an N-type gallium oxide single crystal wafer, in contact with the flat surface of the N-type gallium oxide single crystal wafer, in order to obtain an N-type gallium oxide single crystal wafer with a field relaxation layer. A lamination step to obtain an N-type gallium oxide single crystal wafer with an inorganic film, wherein an inorganic film having a uniform or substantially uniform thickness is laminated on the flat front surface and the flat back surface of the N-type gallium oxide single crystal wafer with the electric field relaxation layer at different timings, A heating step for heating the N-type gallium oxide single crystal wafer with the inorganic film, A manufacturing method that includes the following features.

2. A method for manufacturing a semiconductor device using a gallium oxide single crystal wafer, The field relaxation layer consists of a nickel oxide-based material, a copper oxide-based material, or a tin oxide-based material, or a combination thereof. The manufacturing method according to claim 1.

3. A method for manufacturing a semiconductor device using a gallium oxide single crystal wafer, The electric field relaxation layer is formed of any one of nitrogen atoms, iron atoms, beryllium atoms, zinc atoms, phosphorus atoms, oxygen atoms, argon atoms, or magnesium atoms. The manufacturing method according to claim 1.

4. A method for manufacturing a semiconductor device using a gallium oxide single crystal wafer, The inorganic film is made of silicon oxide, aluminum oxide, or carbon. The manufacturing method according to claim 1.

5. A semiconductor device comprising an N-type gallium oxide single crystal substrate with an electric field relaxation layer exposed on a portion of its surface, The aforementioned semiconductor device is In an N-type gallium oxide single crystal substrate with an electric field relaxation layer, a portion of the inorganic film, which is provided at different timings on the flat surface of the front and the flat surface of the back of the N-type gallium oxide single crystal substrate, is in contact with the surface and the electric field relaxation layer during heating to electrically activate the electric field relaxation layer. After heating to electrically activate the electric field relaxation layer, an electrode portion provided in contact with the gallium oxide single crystal substrate with the electric field relaxation layer, A semiconductor device equipped with a semiconductor device.

6. A semiconductor device comprising an N-type gallium oxide single crystal substrate with an electric field relaxation layer exposed on a portion of its surface, The field relaxation layer consists of a nickel oxide-based material, a copper oxide-based material, or a tin oxide-based material, or a combination thereof. The semiconductor device according to claim 5.

7. A semiconductor device comprising an N-type gallium oxide single crystal substrate with an electric field relaxation layer exposed on a portion of its surface, The electric field relaxation layer is formed of any one of nitrogen atoms, iron atoms, beryllium atoms, zinc atoms, phosphorus atoms, oxygen atoms, argon atoms, or magnesium atoms. The semiconductor device according to claim 5.

8. A semiconductor device comprising an N-type gallium oxide single crystal substrate with an electric field relaxation layer exposed on a portion of its surface, The inorganic film is made of silicon oxide, aluminum oxide, or carbon. The semiconductor device according to claim 5.

Images