Semiconductor equipment

Abstract

The present invention provides a semiconductor device that saves external terminals associated with resetting while accelerating the startup of external devices during reset. [Solution] The internal reset generation circuit RSTG asserts a reset request signal REQr when it detects a reset trigger. The pulse generation circuit PLSG generates a reset-out drive pulse signal RODP and controls the switch SW to the ON state / OFF state during its assertion period / negate period. Specifically, the reset-out period setting register REGro holds a count setting value N that represents the length of the assertion period of the reset-out drive pulse signal RODP. The counter CUNT generates the reset-out drive pulse signal RODP by counting the clock signal CLK from the assertion of the reset request signal REQr until the count setting value N is reached.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, for example, to a semiconductor device having a function of resetting an external device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device, specifically an MCU, that can perform recovery from a reset state in a safer state. The MCU includes a CVM and an MCU reset control circuit. The CVM monitors an abnormality of an internal logic circuit, and notifies the MCU reset control circuit of the abnormality when the abnormality occurs. The MCU reset control circuit transitions the MCU to a reset state in response to the abnormality notification from the CVM. Further, the MCU reset control circuit releases the reset of the MCU in response to a terminal reset signal received at an external terminal.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of Invention

Problems to be Solved by the Invention

[0004] For example, systems including a semiconductor device typified by an MCU (Micro Controller Unit) and an external device controlled by the MCU are widely used. In such a system, normally, when the MCU is initialized, it is also necessary to initialize the external device that is the control target thereof. Therefore, the MCU may have a function of outputting a reset signal to the external device. In the present specification, such a function is referred to as reset out.

[0005] A reset-out can be implemented, for example, using the general-purpose I / O pins of an MCU. However, in this case, one general-purpose I / O pin that would normally be freely available to the user is consumed. On the other hand, an MCU usually has a reset pin that receives an external reset signal. Therefore, a method can be considered in which this reset pin is shared for both external reset input and reset-out to an external device. However, in this case, an excessive reset-out period may occur for the external device, potentially delaying its startup.

[0006] The embodiments described later were made in view of these considerations, and other issues and novel features will become clear from the description and accompanying drawings of this specification. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes an external terminal, a switch, an internal reset generation circuit, and a pulse generation circuit. The external terminal is a terminal capable of outputting a reset-out signal to an external device. The switch controls the reset-out signal to an assert level reset voltage by applying a reset voltage to the external terminal during the ON state period. The internal reset generation circuit asserts a reset request signal when it detects a reset trigger. The pulse generation circuit generates a reset-out drive pulse signal and controls the switch to an ON state / OFF state during the assert / negate period of the reset-out drive pulse signal. Here, the pulse generation circuit includes a clock generation circuit, a reset-out period setting register, and a counter. The clock generation circuit generates a clock signal. The reset-out period setting register holds a count setting value representing the length of the assert period of the reset-out drive pulse signal. The counter generates a reset-out drive pulse signal by counting the clock signal from the assertion of the reset request signal until the count setting value is reached. [Effects of the Invention]

[0008] According to the above embodiment, it is possible to save external terminals associated with resetting while speeding up the startup of external devices during reset. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a schematic diagram showing an example of the configuration of a system including a semiconductor device according to the first embodiment. [Figure 2] Figure 2 shows an example of the settings in the reset-out period setting register in Figure 1. [Figure 3] Figure 3 is a timing chart showing a schematic example of the operation of the pulse generation circuit in Figure 1. [Figure 4] Figure 4 is a flowchart showing an example of the operation of the control device shown in Figure 1 when power is turned on. [Figure 5] Figure 5 is a flowchart showing an example of operation when a reset request occurs in the control device shown in Figure 1. [Figure 6] Figure 6 is a timing chart showing an example of the operation during a reset in the system shown in Figure 1. [Figure 7] Figure 7 is a schematic diagram showing an example of the configuration of a system including a semiconductor device according to the second embodiment. [Figure 8] Figure 8 is a flowchart showing an example of the operation of the control device shown in Figure 7 when power is turned on. [Figure 9] Figure 9 is a schematic diagram showing an example configuration of a system including a semiconductor device, which is the first comparative example. [Figure 10] Figure 10 is a schematic diagram showing an example configuration of a system including a semiconductor device, which is a second comparative example. [Figure 11] Figure 11 is a timing chart showing an example of the operation during a reset in the system shown in Figure 10. [Modes for carrying out the invention]

[0010] In the following embodiments, the description will be divided into multiple sections or embodiments where necessary for convenience. However, unless otherwise specified, they are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, when referring to the number of elements (including number, numerical value, quantity, range, etc.), the number is not limited to that specific number unless otherwise specified or when it is clearly limited in principle. In other words, the number of elements may be greater than or less than a specific number.

[0011] Furthermore, in the embodiments, the constituent elements (including element steps) are not necessarily essential unless specifically stated or considered fundamentally essential. Similarly, when referring to the shape, positional relationship, etc., of constituent elements, it includes those that substantially approximate or resemble their shape, etc., unless specifically stated or considered fundamentally not essential. The same applies to the numerical values ​​and ranges mentioned above.

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all drawings used to illustrate the embodiments, the same reference numerals are generally used for identical components, and repeated descriptions of such components will be omitted.

[0013] (First Embodiment) <Overview of Semiconductor Devices> Figure 1 is a schematic diagram showing an example of the configuration of a system including a semiconductor device according to the first embodiment. The system shown in Figure 1 comprises a reset device RDEV, a control device CDEV, and an external device EDEV. For example, the reset device RDEV is a reset IC provided to reset the entire system. The control device CDEV is a semiconductor device, such as an MCU or SoC (System on Chip). The external device EDEV is a device controlled by the control device CDEV.

[0014] As terminals related to reset, the reset device RDEV, the control device CDEV, and the external device EDEV are each provided with an external terminal PNr1, an external terminal PNc1, and an external terminal PNe1, respectively. The reset device RDEV outputs a reset signal RST# from the external terminal PNr1 which is an output terminal to the external terminals PNc1 and PNe1 of the control device CDEV and the external device EDEV.

[0015] The external terminal PNc1 of the control device CDEV receives the reset signal RST# from the reset device RDEV. In addition to this, the external terminal PNc1 is a terminal capable of outputting a reset out signal RO# to the external terminal PNe1 of the external device EDEV. That is, the external terminal PNc1 is a shared terminal for outputting the reset out signal RO# to the external device EDEV and receiving the reset signal RST# from the outside, here the reset device RDEV. By asserting the reset out signal RO#, the control device CDEV can reset the external device EDEV during the assertion period.

[0016] In this example, the assertion level of the reset out signal RO# and the reset signal RST# is the "L" level which is the level of the ground power supply voltage (reset voltage) VSS. For example, the control device CDEV outputs an "L" level from the external terminal PNc1 for a predetermined reset period, and then controls the external terminal PNc1 to a high impedance state. Similarly, the reset device RDEV also outputs an "L" level from the external terminal PNr1 for a predetermined reset period, and then controls the external terminal PNr1 to a high impedance state.

[0017] In response to this high impedance, a pull-up resistor or pull-down resistor is provided to transition the reset-out signal RO# or reset signal RST# to the negate level, in this case the power supply voltage VCC level, which is the "H" level. In this example, a pull-up resistor Rpu is provided with the power supply voltage VCC applied to one end. Thus, the external terminal PNc1 of the control device CDEV is also a terminal to which a pull-up resistor or pull-down resistor can be connected to control the reset-out signal RO# to the negate level.

[0018] The control device CDEV comprises multiple internal circuits and a bus BS that connects the multiple internal circuits to each other. Here, the multiple internal circuits include non-volatile memory NVM, peripheral circuit PERI, volatile memory RAM, and processor PRC. For example, the non-volatile memory NVM may be MRAM (Magnetoresistive Random Access Memory) or flash memory. The volatile memory RAM may be SRAM (Static RAM). The processor PRC includes a CPU (Central Processing Unit) and may also include a GPU (Graphics Processing Unit) or DSP (Digital Signal Processor).

[0019] The peripheral circuitry (PERI) is a circuit that implements various functions required by the control device CDEV. Examples of peripheral circuitry (PERI) include communication interfaces, analog-to-digital converters, digital-to-analog converters, and general-purpose I / O ports. The processor (PRC) executes programs stored in the non-volatile memory (NVM) or copied from the non-volatile memory (NVM) to the volatile memory (RAM). By executing the programs stored in memory, the processor (PRC) can control external devices such as the EDEV via the peripheral circuitry (PERI) and corresponding external terminals.

[0020] Here, the control device CDEV further includes a reset circuit unit RSTU. The reset circuit unit RSTU outputs system reset signals RSTs to one or more internal circuits and a reset out signal RO# to the external terminal PNc1. The reset circuit unit RSTU includes an input buffer IBF, m internal reset generation circuits RSTG[1]-RSTG[m], a power-on reset circuit POR, and a reset control circuit RSTC. In addition, the reset circuit unit RSTU includes a register write circuit WREG, a pulse generation circuit PLSG, and a switch SW.

[0021] The input buffer IBF receives the signal from the external terminal PNC1 and outputs a reset request signal REQr[0]. One way it does this is by receiving the reset signal RST# from the reset device RDEV, buffering it, and then outputting it as the reset request signal REQr[0]. In this example, the reset request signal REQr[0] is an "L" pulse signal with an "L" level as its assertion level. Furthermore, the input buffer IBF is more specifically composed of, for example, a Schmitt trigger circuit.

[0022] The m internal reset generation circuits, RSTG[1]-RSTG[m], detect different reset factors. When each of the m internal reset generation circuits, RSTG[1]-RSTG[m], detects a reset factor, it asserts one of the m reset request signals, REQr[1]-REQr[m]. In this example, the m reset request signals, REQr[1]-REQr[m], are "H" pulse signals with an "H" level as the assertion level. In this specification, each internal reset generation circuit is collectively referred to as the internal reset generation circuit RSTG.

[0023] Specific examples of reset factors include voltage drop detection events targeting the power supply voltage VCC or the internal power supply voltage generated from the power supply voltage VCC. Other examples include rise / fall detection events targeting the ambient temperature detected by the built-in temperature sensor. Furthermore, there are events detecting abnormal operation in the processor PRC and errors in the memory. The internal reset generation circuit RSTG detects various abnormalities occurring within the device, primarily those caused by these reset factors.

[0024] The power-on reset circuit POR detects when power is applied to the control device CDEV and generates a power-on reset signal RSTp upon detection. As is commonly known, the power-on reset signal RSTp is a signal used to initialize the entire control device CDEV when power is applied. In this example, the power-on reset signal RSTp is also an "H" pulse signal with an "H" level as its assertion level.

[0025] The reset control circuit RSTC asserts the system reset signals RSTs to the "H" level in response to the assertion of any of the "m+1" reset request signals REQr[0]-REQr[m] or the power-on reset signal RSTp. The reset control circuit RSTC then maintains this asserted level for a predetermined reset period. The one or more internal circuits described above enter a reset state during the period when the system reset signals RSTs are asserted, i.e., the "H" level period, and release the reset state in response to the transition from the "H" level to the "L" level.

[0026] The reset control circuit RSTC comprises, in detail, three OR gates OR1-OR3 and a reset period compensation circuit RPC. OR gate OR1 performs an OR operation on m reset request signals REQr[1]-REQr[m] from m internal reset generation circuits RSTG and outputs the result as a reset request signal REQr. OR gate OR2 performs an OR operation on the reset request signal REQr from OR gate OR1 and the power-on reset signal RSTp from the power-on reset circuit POR.

[0027] The reset period compensation circuit RPC is located on the signal path from the internal reset generation circuit RSTG to one or more internal circuits, and in this example, it is located between two ore gates OR2 and OR3. The reset period compensation circuit RPC receives the signal from ore gate OR2, in this case an "H" pulse signal, and compensates for the "H" pulse width in the "H" pulse signal. The length of the reset period Tres in one or more internal circuits is determined by the "H" pulse width.

[0028] Therefore, the reset period compensation circuit (RPC) compensates for the length of the reset period Tres required by one or more internal circuits. In other words, the length of the reset period Tres compensated by the reset period compensation circuit (RPC) is determined based on the longest reset period required by one or more internal circuits. The length of the reset period Tres can be, for example, a few milliseconds (m [sec]).

[0029] The OR3 gate performs an OR operation on the "H" pulse signal from the reset period compensation circuit RPC and the inverted "H" pulse signal of the reset request signal REQr[0] from the input buffer IBF. The OR3 gate then outputs the calculation result as a system reset signal RSTs to one or more internal circuits. In this process, the "H" pulse width in the inverted signal of the reset request signal REQr[0] is determined by the reset device RDEV.

[0030] The switch SW applies a reset voltage, the ground power supply voltage VSS, to the external terminal PNc1 during the ON state. This causes the switch SW to control the reset output signal RO#, output from the external terminal PNc1, to an assertion level corresponding to the reset voltage, in this case, the "L" level, during the ON state. The switch SW is composed of, for example, nMOS transistors MNs. Details regarding the pulse generation circuit PLSG and the register writing circuit WREG will be described later.

[0031] <Regarding semiconductor devices (comparative examples) and their problems> Figure 9 is a schematic diagram showing an example configuration of a system including a semiconductor device, which is the first comparative example. Unlike the configuration example shown in Figure 1, the semiconductor device shown in Figure 9, i.e., the control device CDEVx1, outputs a reset out signal RO# to the external device EDEV using the general-purpose I / O port GPIO and the general-purpose I / O terminal PNio. The control device CDEVx1 is equipped with a reset control circuit RSTCx1 which is almost the same as in the case of Figure 1. However, for the sake of simplicity, the input buffer IBF and the power-on reset circuit POR are not shown here.

[0032] Furthermore, the reset control circuit RSTCx1 includes an OR gate OR4. OR gate OR4 performs an OR operation on the reset request signal REQr from OR gate OR1 and the reset request signal REQr[0] from the external terminal PNc1. OR gate OR4 then outputs the result of the operation as a register reset signal RSTa to the general-purpose I / O port GPIO.

[0033] The general-purpose I / O port GPIO is equipped with two registers, REG1 and REG2, and an output buffer OBF. The output buffer OBF outputs a reset out signal RO# to the general-purpose I / O terminal PNio. The output value of the output buffer OBF is determined by the value of register REG2. The output buffer OBF is a ternary buffer whose enable state is controlled by the value of register REG1, and outputs high impedance when the value of register REG1 is at the "L" level.

[0034] In this configuration, for example, when the reset request signal REQr is asserted, the internal circuitry, including the processor PRC, enters a reset state. Furthermore, in parallel with this, the value of register REG1 is also reset to the "L" level via the register reset signal RSTa. As a result, the general-purpose I / O terminal PNio enters a high-impedance state, and the reset out signal RO# enters the "L" level via the pull-down resistor element Rpd. Consequently, the external device EDEV also enters a reset state.

[0035] Subsequently, the reset state of the processor PRC is released after a reset period Tres based on the reset period compensation circuit RPC. Once the reset state is released, the processor PRC writes an "H" level to register REG2 according to the program, and then writes an "H" level to register REG1. As a result, the reset out signal RO# transitions from an "L" level to an "H" level, releasing the reset state of the external device EDEV.

[0036] However, using this method consumes one general-purpose I / O terminal PNio, which is normally available for free use by the user. Therefore, as shown in Figure 10, a method can be considered in which the external terminal PNc1, which is normally the input terminal for the external reset signal RST#, is shared as the output terminal for the reset out signal RO#, similar to the case in Figure 1.

[0037] Figure 10 is a schematic diagram showing an example configuration of a system including a semiconductor device, which is a second comparative example. The control device CDEVx2 shown in Figure 10 has a switch SW similar to that in Figure 1, compared to the configuration example shown in Figure 9. When the switch SW is in the ON state, the reset out signal RO# is asserted to the "L" level by applying the ground power supply voltage VSS to the external terminal PNc1.

[0038] In this case, it is necessary to ensure a reset-out period, which is the "L" level period of the reset-out signal RO#, for a length based on the specifications of the external device EDEV. In Figure 10, this reset-out period length is ensured using the reset-out compensation circuit RPC. Specifically, the reset-out compensation circuit RPC determines the "H" pulse width of the system reset signals RSTs, as well as the "L" pulse width of the reset-out signal RO#. More precisely, the reset-out compensation circuit RPC controls the on / off state of the switch SW by outputting the reset-out drive pulse signal RODP.

[0039] In this case, the length of the reset period TresX based on the reset period compensation circuit RPC is determined based on the specifications of the internal circuitry reset by the system reset signals RSTs and the specifications of the external device EDEV reset by the reset-out signal RO#. Specifically, the length of the reset period TresX is set to the longest length among the lengths based on each specification. However, in this case, there was a risk that the startup of the external device EDEV would be delayed, especially if the reset-out period became excessively long.

[0040] Figure 11 is a timing chart showing an example of operation during reset in the system shown in Figure 10. In Figure 11, the length of the reset-out period TroX is equal to the length of the reset period TresX based on the reset period compensation circuit RPC. The lengths of the reset period TresX and the reset-out period TroX are set to the longest possible lengths, as described above.

[0041] For example, consider a scenario where the control device CDEVx2 can be connected to either an external device (A) requiring a long reset-out period or an external device (B) that only requires a short reset-out period. Furthermore, assume that the reset-out period required by external device (A) is longer than the period required by the internal circuitry within the control device CDEVx2. In this case, the lengths of the reset period TresX and the reset-out period TroX are determined based on the lengths required by external device (A).

[0042] Consequently, as shown in Figure 11, if only an external device (B) that requires a short reset-out period T0 (min) is connected to the control device CDEVx2, an excessive reset-out period Tex1 occurs. As a result, the startup of the external device (B) is delayed, as shown at time t2.

[0043] As another example, consider a case where the expected maximum length is determined based on the internal circuitry within the control device CDEVx2. In this case, the startup of the external device EDEV will be delayed due to the constraints of the internal circuitry. It is desirable for the external device EDEV to start up as quickly as possible. For example, if the external device EDEV is a sensor device, accelerating its startup will enable stable sensing at an earlier stage. Consequently, the control device will also be able to obtain stable sensing results at an earlier stage.

[0044] <Details of the pulse generation circuit and register writing circuit> Therefore, the control device CDEV shown in Figure 1 comprises a pulse generation circuit PLSG and a register writing circuit WREG. The pulse generation circuit PLSG generates a reset-out drive pulse signal RODP. The pulse generation circuit PLSG then controls the switch SW to the ON state / OFF state during the assertion period / negate period of the reset-out drive pulse signal RODP, in this example, the "H" level period / "L" level period.

[0045] The pulse generation circuit PLSG comprises, more specifically, a clock generation circuit CKG, a reset-out period setting register REGro, and a counter CUNT. The clock generation circuit CKG generates the clock signal CLK. Note that the clock generation circuit CKG may be part of the internal clock generator typically provided in the control device CDEV. The reset-out period setting register REGro holds a count setting value N that represents the length of the assert period of the reset-out drive pulse signal RODP.

[0046] The counter CUNT, or timer in other words, receives the reset request signal REQr from the OR gate OR1 as a reset-out request signal REQro. The counter CUNT then counts the clock signal CLK starting from the assertion of the reset-out request signal REQro, and consequently the reset request signal REQr, until it reaches the count set value N. This causes the counter CUNT to generate the reset-out drive pulse signal RODP. The counter CUNT, the clock generation circuit CKG, and the reset-out period setting register REGro are initialized in response to the power-on reset signal RSTp.

[0047] The register writing circuit WREG comprises a non-volatile memory NVMa and a data transfer circuit DTC. The count setting value N, as described above, is pre-stored in the non-volatile memory NVMa. The data transfer circuit DTC transfers the count setting value N stored in the non-volatile memory NVMa to the reset-out period setting register REGro in response to a power-on reset, i.e., the power-on reset signal RSTp.

[0048] Here, the control device CDEV may generally have a reset transfer circuit for performing various initial settings on the entire control device CDEV in response to a power-on reset. Such a reset transfer circuit can be implemented, for example, by a combination of non-volatile memory and a data transfer circuit. For this reason, the register write circuit WREG may be part of the reset transfer circuit.

[0049] Figure 2 shows an example of setting the reset-out period setting register REGro in Figure 1. In Figure 2, one period of the clock signal CLK is defined as "T", and the reset-out period Tro is set from "T" to "(2 n It can be set arbitrarily within the range of -1)T". For example, the count setting value N, which is an n-bit binary, is "000...01" when the reset-out period Tro is set to "T", and "(2 n-1) When set to "T", the value is "111...11". The non-volatile memory NVMa has this count setting value N stored in advance.

[0050] Figure 3 is a timing chart showing a schematic example of the operation of the pulse generation circuit PLSG in Figure 1. As shown in Figure 3, the pulse generation circuit PLSG asserts the reset-out drive pulse signal RODP to the "H" level in response to the assertion of the reset-out request signal REQro, and consequently the reset request signal REQr, to the "H" level. Consequently, when the switch SW is turned on, the reset-out signal RO# transitions from the "H" level to the "L" level, that is, from the level of the power supply voltage VCC to the level of the ground power supply voltage VSS.

[0051] Furthermore, the pulse generation circuit PLSG starts counting in response to the assertion of the reset-out request signal REQro to the "H" level. When the count value reaches the count set value N, the pulse generation circuit PLSG negates the reset-out drive pulse signal RODP to the "L" level. Consequently, the switch SW turns off, causing the reset-out signal RO# to transition from the "L" level to the "H" level by the pull-up resistor element Rpu. The reset-out period Tro is determined by the "L" pulse width of the reset-out signal RO#, and consequently, the "H" pulse width of the reset-out drive pulse signal RODP.

[0052] <Operation of semiconductor device (control device)> Figure 4 is a flowchart showing an example of operation when the control device shown in Figure 1 is powered on. In Figure 4, first, power is supplied to the control device CDEV (step S101). The power-on reset circuit POR detects this power-on and asserts the power-on reset signal RSTp to start initializing the entire system within the device (step S102). As part of this process, the reset control circuit RSTC asserts the system reset signals RSTs.

[0053] Next, the power-on reset circuit POR cancels the power-on reset state by negating the power-on reset signal RSTp (step S103). In response, the data transfer circuit DTC starts transferring data from the non-volatile memory NVMa to the reset-out period setting register REGro (step S104). Also, the clock generation circuit CKG starts supplying the clock signal CLK (step S121).

[0054] Then, once the data transfer in step S104 is complete (step S105), the count setting value N in the reset-out period setting register REGro is determined (step S106). Subsequently, the reset control circuit RSTC releases the system reset state by negating the system reset signal RSTs after a predetermined reset period Tres has elapsed (step S107). In response, the processor PRC is started and operation by the processor PRC begins (step S108).

[0055] Figure 5 is a flowchart showing an example of operation when a reset request occurs in the control device shown in Figure 1. In Figure 5, first, the internal reset generation circuit RSTG asserts the reset request signal REQr when it detects a predetermined reset cause (step S201). In response, the reset control circuit RSTC asserts the system reset signal RSTs (step S202) and also asserts the reset out request signal REQro (step S221).

[0056] The pulse generation circuit PLSG asserts the reset-out drive pulse signal RODP in response to the assertion of the reset-out request signal REQro (step S222). Then, the pulse generation circuit PLSG counts the clock signal CLK until the count value reaches the count setting value N stored in the reset-out period setting register REGro (step S223). When the count value reaches the count setting value N, the pulse generation circuit PLSG negates the reset-out drive pulse signal RODP (step S224). The period from step S222 to step S224 is the reset-out period Tro.

[0057] Meanwhile, the reset control circuit RSTC asserts the system reset signals RSTs in step S202, and then negates the system reset signals RSTs after the reset period Tres based on the reset period compensation circuit RPC has elapsed (step S203). In response, the processor PRC starts up as the reset state is released (step S204).

[0058] Here, we take the example where the reset-out period Tro, based on the count setting value N, is shorter than the reset period Tres, based on the reset period compensation circuit RPC. In this case, the "H" pulse width of the system reset signal RSTs is determined based on the input to the reset period compensation circuit RPC in the OR gate OR3. On the other hand, if the reset-out period Tro, based on the setting, is longer than the reset period Tres, based on the setting, the "H" pulse width of the system reset signal RSTs is determined based on the input to the other side of the OR gate OR3. That is, in this case, the actual reset period Tres is equal to the reset-out period Tro.

[0059] Figure 6 is a timing chart showing an example of operation during reset in the system shown in Figure 1. Figure 6 also shows the timing chart in Figure 11 as a comparative example. In the comparative example, the length of the reset-out period TroX is determined based on the external device (A) with the longest period described in Figure 11. On the other hand, using the method of the embodiment, the length of the reset-out period Tro can be arbitrarily determined according to the specifications of the external device EDEV that is actually connected. Therefore, if an external device (B) that requires a short reset-out period T0 (min), similar to the case in Figure 11, is actually connected, the reset-out period Tro can be set accordingly.

[0060] In the example shown in Figure 6, the length of the reset-out period Tro is set to, for example, the reset-out period T0 (min) plus a margin. The length of the excess reset-out period Tex2 is sufficient with this margin. This significantly reduces the excess reset-out period Tex1 that could occur in the comparative example method. As shown at times t11 and t2, the startup of the external device EDEV can be accelerated by the amount by which the excess reset-out period has been shortened. Also, in this example, as shown at times t12 and t2, the startup of the internal circuitry within the control device CDEV is accelerated compared to the comparative example method.

[0061] <Regarding variations> Figure 1 shows an example where one external device EDEV is connected to external terminal PNc1. However, multiple external devices EDEV may be connected in parallel to external terminal PNc1. In this case, the count setting value N is determined based on the longest length among the multiple reset-out periods required by the multiple external devices EDEV.

[0062] <Main effects of the first embodiment> In the first embodiment described above, a switch is provided for outputting a reset-out signal from an external terminal to which an external device can be connected, and a pulse generation circuit is provided for variably controlling the on-time of the switch based on a count setting value. This allows for saving the external terminal associated with resetting while speeding up the startup of the external device during reset.

[0063] (Second Embodiment) <Overview of Semiconductor Devices> Figure 7 is a schematic diagram showing an example of the configuration of a system including a semiconductor device according to the second embodiment. The system shown in Figure 7 differs from the system shown in Figure 1 in the configuration of the register writing circuit WREG within the control device (semiconductor device) CDEV. In Figure 7, the register writing circuit WREG is implemented by the processor PRC.

[0064] As mentioned above, the processor PRC is reset by the system reset signals RSTs. After being reset by the system reset signals RSTs in response to power-on, i.e., the power-on reset signal RSTp, the processor PRC executes the program stored in memory. Based on the program, the processor PRC writes a count setting value N to the reset-out period setting register REGro, for example, via the bus BS.

[0065] Figure 8 is a flowchart showing an example of operation when the control device shown in Figure 7 is powered on. In Figure 8, the control device CDEV, as in Figure 4, starts the initialization of the entire system by a power-on reset that accompanies power-on, and then releases the power-on reset state (steps S101-S103). In response, the clock generation circuit CKG starts supplying the clock signal CLK (step S121). On the other hand, in Figure 8, unlike in Figure 4, no data transfer (steps S104-S106) occurs in response to the release of the power-on reset state.

[0066] Subsequently, as in the case of Figure 4, the system reset state is released after the reset period Tres has elapsed, the processor PRC starts up, and operation by the processor PRC begins (steps S107, S108). Then, when the processor PRC starts up, it writes the count setting value N to the reset-out period setting register REGro based on the startup program (step S109). This finalizes the count setting value N in the reset-out period setting register REGro (step S110).

[0067] <Main effects of the second embodiment> As described above, by using the method of the second embodiment, the same effects as those described in the first embodiment can be obtained. Furthermore, since the count setting value can be determined by program, for example, the count setting value, i.e., the reset-out period, can be dynamically changed during the normal operation period after power-on.

[0068] On the other hand, unlike the method of the second embodiment, the method of the first embodiment can determine the count setting value before the processor PRC is started. Therefore, for example, even if some reset factor occurs after power-on but before the processor PRC is started, a reset-out signal can be generated. Thus, from the viewpoint of activating the reset-out signal early, the method of the first embodiment is advantageous.

[0069] The present invention has been described in detail above based on embodiments, but the present invention is not limited to the embodiments described above and can be modified in various ways without departing from its essence. For example, the embodiments described above are described in detail in order to explain the present invention in an easy-to-understand manner and are not necessarily limited to those having all the described configurations. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add a configuration from another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with a configuration from another embodiment. [Explanation of Symbols]

[0070] CDEV control device (semiconductor device) CKG Clock Generation Circuit CUNT counter DTC Data Transfer Circuit EDEV External Devices N count setting value NVM (Non-Volatile Memory) PLSG pulse generator circuit PNc1 External terminal PRC Processor REGro Reset-out period setting register REQr Reset Request Signal RO# Reset Out Signal RODP Reset Out Drive Pulse Signal RPC Reset Period Compensation Circuit RSTG Internal Reset Generation Circuit RSTp Power-on reset signal RSTs System Reset Signals Rpu pull-up resistor element SW Switch Tres reset period Tro Resetout Period

Claims

1. An external terminal capable of outputting a reset out signal to an external device, A switch that controls the reset out signal to the reset voltage, which is the assert level, by applying a reset voltage to the external terminal during the ON state period, An internal reset generation circuit that asserts a reset request signal when a reset trigger is detected, A pulse generation circuit that generates a reset-out drive pulse signal and controls the switch to an ON state / OFF state during the assertion period / negate period of the reset-out drive pulse signal, It has, The pulse generation circuit is A clock generation circuit that generates a clock signal, A reset-out period setting register holds a count setting value representing the length of the assert period of the reset-out drive pulse signal, A counter that generates the reset-out drive pulse signal by counting the clock signal starting from the assertion of the reset request signal until the count set value is reached, Equipped with, Semiconductor equipment.

2. In the semiconductor device described in claim 1, The aforementioned external terminal is a terminal that shares the output of the reset out signal to the external device and the input of a reset signal from an external source. Semiconductor equipment.

3. In the semiconductor device described in claim 2, The external terminal is a terminal to which a pull-up resistor or pull-down resistor can be connected to control the reset out signal to a negate level. Semiconductor equipment.

4. In the semiconductor device described in claim 2, A non-volatile memory in which the aforementioned count setting value is stored, A data transfer circuit that transfers the count setting value stored in the non-volatile memory to the reset-out period setting register in response to a power-on reset, Equipped with, Semiconductor equipment.

5. In the semiconductor device described in claim 2, The memory where the program is stored, The processor is reset by the system reset signal, Equipped with, The processor, after being reset by the system reset signal in response to power-on, executes the program to write the count setting value to the reset-out period setting register. Semiconductor equipment.

6. In the semiconductor device according to claim 1, One or more internal circuits that are reset in response to the assertion of the reset request signal, A reset period compensation circuit is provided on the signal path from the internal reset generation circuit to the one or more internal circuits, and compensates for the length of the reset period required by the one or more internal circuits. Equipped with, Semiconductor equipment.

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