Imaging device and its operating method

Abstract

This invention provides a photographic device and a method for operating it. [Solution] An imaging device 10 according to one embodiment includes a pixel array 110 including a plurality of pixels PX, each having a transfer transistor TT that converts incident light into photocharge and transfers the photocharge; a low driver 120 electrically connected to the pixel array 110 and supplying control signals to the plurality of pixels PX; and a compensation driver 180 electrically connected to the pixel array 110 and supplying compensation signals to the plurality of pixels PX, wherein the compensation signals are configured to adjust the effective gate voltage of the transfer transistor TT at each coordinate of the pixel array 110.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an imaging apparatus and an operating method thereof.

BACKGROUND ART

[0002] With the development of the information and communication industry and the digitalization of electronic devices, image sensors with improved performance have been installed in various fields such as digital cameras, video cameras, mobile phones, personal communication systems (PCSs), game consoles, security cameras, and medical micro cameras. In general, an image sensor has a pixel region including photodiodes and a peripheral circuit region. A unit pixel includes a photodiode and a transfer transistor. The transfer transistor is disposed between the photodiode and a floating diffusion region, and transfers charges generated by the photodiode to the floating diffusion region.

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0003] Embodiments of the present disclosure provide an imaging apparatus designed to supply an optimum voltage to a transfer transistor, and an operating method thereof.

[0004] Embodiments of the present disclosure provide an imaging apparatus designed to supply an optimum voltage to a boost control line, and an operating method thereof.

[0005] Embodiments of the present disclosure provide an imaging apparatus capable of securing an optimum driving time (or optimum duration) of a control signal applied to a gate electrode of a transfer transistor, and an operating method thereof.

[0006] Embodiments of the present disclosure provide an imaging apparatus designed to secure an optimum driving time (or optimum duration) of a control signal applied to a boost control line, and an operating method thereof.

[0007] The technical advantages of the embodiments of this disclosure are not limited to those described above and may include additional technical advantages as described in the following detailed description. [Means for solving the problem]

[0008] An imaging apparatus according to one embodiment for solving the above problems includes a pixel array including a plurality of pixels, each equipped with a transfer transistor that converts incident light into photocharge and transfers the photocharge; a row driver electrically connected to the pixel array and supplying control signals to the plurality of pixels; and a compensation driver electrically connected to the pixel array and supplying compensation signals to the plurality of pixels, wherein the compensation signals are configured to adjust the effective gate voltage of the transfer transistor at each coordinate of the pixel array.

[0009] An imaging apparatus according to another embodiment for solving the above problems includes a pixel array having a plurality of pixels, each equipped with a transfer transistor that converts incident light into photocharge and transfers the photocharge; a low driver electrically connected to the pixel array and supplying a control signal having a first duration to the plurality of pixels; and a compensation driver electrically connected to the pixel array and supplying a compensation signal having a second duration to the plurality of pixels, wherein the compensation signal is configured to adjust the effective signal duration of the transfer transistor at each coordinate of the pixel array.

[0010] A method for operating an imaging device according to another embodiment for solving the above problems includes the steps of: evaluating the optimal voltage value of each control signal of a plurality of pixels and storing it in a data memory; outputting the control signal from a low driver; outputting a compensation signal for each of the plurality of pixels in a column unit; and applying the control signal and the compensation signal to each of the plurality of pixels.

[0011] A method for operating an imaging device according to another embodiment for solving the above problems includes the steps of: evaluating the optimal duration of each control signal for a plurality of pixels and storing it in a data memory; outputting the control signal from a low driver; outputting a compensation signal corresponding to the optimal duration for each of the plurality of pixels in a column-by-column unit; and applying the control signal and the compensation signal to each of the plurality of pixels.

[0012] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0013] According to some embodiments, the imaging device may include a low driver that supplies control signals to multiple pixels, and a compensation driver that supplies compensation signals to multiple pixels. Both the control signals and the compensation signals may be applied to the gate electrodes of a transfer transistor. This allows for the provision of an optimal voltage to the transfer transistor.

[0014] According to some embodiments, the imaging device may include a low driver that supplies control signals to multiple pixels, and a compensation driver that supplies compensation signals to multiple pixels. The control signals and compensation signals may be supplied to a boost control line and a compensation line, respectively. The boost control line and the compensation line may each form a capacitance with a floating diffusion electrode (or region). This allows an optimal voltage to be supplied to the boost control line (or floating diffusion electrode).

[0015] According to some embodiments, the imaging device may include a low driver that supplies control signals having a first duration to a plurality of pixels, and a compensation driver that supplies compensation signals having a second duration to a plurality of pixels. Both the control signals and the compensation signals may be applied to the gate electrode of a transfer transistor. This allows the transfer transistor to operate for an optimal drive time (or optimal duration).

[0016] According to some embodiments, the imaging device may include a low driver that supplies control signals having a first duration to a plurality of pixels, and a compensation driver that supplies compensation signals having a second duration to a plurality of pixels. The control signals and compensation signals may be supplied to a boost control line and a compensation line, respectively. The boost control line and the compensation line may each form capacitance with a floating diffusion electrode (or region). This allows the boost control line to operate for an optimal drive time (or optimal duration). [Brief explanation of the drawing]

[0017] [Figure 1] Block diagram showing a shooting system based on one embodiment. [Figure 2] This is a block diagram of an image sensing unit based on one embodiment. [Figure 3] This is a circuit diagram of a pixel in a pixel array based on one embodiment. [Figure 4] This is a schematic diagram showing that an optimal voltage is applied to the pixel transfer transistor according to one embodiment. [Figure 5] This is a timing diagram of a single pixel based on one embodiment. [Figure 6] This figure shows how to store image data output from a single pixel based on one embodiment. [Figure 7] This is a sequence diagram showing the operation method of a photographic device based on one embodiment. [Figure 8] This is a schematic diagram of pixels in a pixel array based on another embodiment. [Figure 9] This is a sequence diagram showing the operation method of a photographic device based on another embodiment. [Figure 10] This timing diagram shows that the pixel transfer transistors, based on other embodiments, operate at their optimal drive time. [Figure 11] This timing diagram shows that the pixel transfer transistors, based on other embodiments, operate at their optimal drive time. [Figure 12]FIG. 20 is a timing diagram showing that a transfer transistor of a pixel according to another embodiment operates at an optimal drive time. [Figure 13] FIG. 13 is a block diagram of an image sensing unit according to another embodiment. [Figure 14] FIG. 3 is a circuit diagram of a pixel in a pixel array according to another embodiment. [Figure 15] FIG. 15 is a schematic cross-sectional view illustrating a floating diffusion electrode, a boost control line, and a compensation line of the image sensing unit of FIG. 14. [Figure 16] FIG. 16 is a timing diagram of a single pixel. [Figure 17] FIG. 17 is a sequence diagram illustrating an operation method of an imaging apparatus according to another embodiment. [Figure 18] FIG. 18 is a sequence diagram illustrating an operation method of an imaging apparatus according to another embodiment. [Figure 19] FIG. 21 is a timing diagram showing that a boost control line of a pixel according to another embodiment operates at an optimal drive time. [Figure 20] FIG. 22 is a timing diagram showing that a boost control line of a pixel according to another embodiment operates at an optimal drive time. [Description of Embodiments]

[0018] Hereinafter, several embodiments of the present technology will be described with reference to the drawings.

[0019] Terms such as first and second are used to distinguish different components, and do not imply any particular order or hierarchical relationship. For example, a first component may be named a second component, and vice versa. In addition, singular expressions include plural expressions unless the context clearly dictates otherwise.

[0020] FIG. 1 is a block diagram illustrating an imaging system according to an embodiment.

[0021] Referring to Figure 1, the shooting system 1 may refer not only to devices such as a digital still camera that takes still images or a digital video camera that takes images, but also to a device that detects motion.

[0022] The imaging system 1 may include an imaging device 10 and a host device 20.

[0023] The imaging device 10 may include an image sensing unit 100, a line memory 200, an ISP (image signal processor) 300, an I / O interface 400, and a data memory 500.

[0024] The image sensing unit 100 may be a CIS (complementary metal oxide semiconductor image sensor) that converts optical signals into electrical signals. The image sensing unit 100 can be controlled by the ISP 300 to control its overall operation, including power supply control (e.g., power on / off), operating mode, operating timing, and sensitivity. Based on the control of the ISP 300, the image sensing unit 100 can transmit the image data obtained by converting the optical signals into electrical signals to the line memory 200.

[0025] The line memory 200 may include volatile memory (e.g., DRAM, SRAM) and / or non-volatile memory (e.g., flash memory).

[0026] The line memory 200 can receive and store image data from the image sensing unit 100, and can transmit the stored image data to the ISP 300 under the control of the ISP 300.

[0027] The ISP300 can perform image signal processing on image data stored in the line memory 200. The ISP300 can reduce noise in the image data and perform image signal processing for image quality improvement, such as gamma correction, color filter array interpolation, color matrix, color correction, color enhancement, and lens distortion correction.

[0028] To generate HDR images, the ISP300 may include a gain processing unit 310 and an image compositing unit 320.

[0029] The gain processing unit 310 can determine the gain to be applied to the image data (for example, multiplication). The gain processing unit 310 can determine the gain based on the difference in conversion gain between the HCG (high conversion gain) mode and the LCG (low conversion gain) mode and provide it to the image synthesis unit 320.

[0030] The image synthesis unit 320 can synthesize an HDR image corresponding to high dynamic range using image data of pixels operating in HCG mode and / or image data of pixels operating in LCG mode.

[0031] The ISP300 can transmit image data (i.e., HDR images) that has undergone image signal processing to the input / output interface 400.

[0032] The input / output interface 400 communicates with the host device 20 and can transmit the image data that has undergone image signal processing to the host device 20.

[0033] The host device 20 may be a processor (e.g., an application processor) that processes the image signal received from the imaging device 10, a memory (e.g., a non-volatile memory) that stores the image data, or a display device (e.g., an LCD (liquid crystal display)) that visually outputs the image data.

[0034] The data memory 500 can store the digital image data Data_PX converted from the analog-to-digital converter 140.

[0035] Figure 2 is a block diagram of an image sensing unit based on one embodiment.

[0036] An image sensing unit 100 based on one embodiment may include a pixel array 110, a timing controller 170, a correlated duplex sampler 130, and an ADC (analog-to-digital converter) 140.

[0037] Referring to Figure 2, the pixel array 110 may include a plurality of pixels PX. The pixels PX may be arranged in a matrix along the row and column directions, but the disclosure is not limited thereto. The pixels PX may include red pixels, green pixels, and blue pixels, but embodiments of the disclosure are not limited thereto and may further include white pixels or infrared pixels.

[0038] Multiple pixels PX may be electrically connected to the low driver 120. Multiple pixels PX may each be electrically connected to a control line extending from the low driver 120. The control line may be the transfer signal line TL or the boost control line shown in Figure 3. In one embodiment, the control line will be described as the transfer signal line TL.

[0039] The low driver 120 can activate the pixel array 110 to perform specific operations on the pixels contained in the low based on commands and control signals supplied by the timing controller 170.

[0040] The correlated dual sampler 130 can transfer the reference signal and image signal of each column to the ADC 140 as correlated dual sampled signals based on the control signal from the timing controller 170.

[0041] The ADC140 can convert the correlated double-sampling signals for each column output from the correlated double-sampler 130 into digital signals and output image data. In one embodiment, the ADC140 can convert the correlated double-sampling signals generated by the correlated double-sampler 130 for each column into digital signals and output them.

[0042] The timing controller 170 can control at least one of the following: the low driver 120, the correlated dual sampler 130, and the ADC 140.

[0043] An image sensing unit 100 according to one embodiment may further include a compensation driver 180. The compensation driver 180 may be controlled by a timing controller 170. One or more compensation lines CPL may extend from the compensation driver 180 to the pixel array 110. Each compensation line CPL is provided to extend along the column direction of the pixel rows of the pixel array 110, and multiple compensation lines CPL may be spaced apart in the row direction. Each of the multiple compensation lines CPL may correspond one-to-one with a pixel row formed by multiple pixels PX extending in the column direction. The compensation lines CPL can play a role in compensating the transfer control signal supplied from the transfer signal line TL.

[0044] Figure 3 is a circuit diagram of a pixel in a pixel array based on one embodiment.

[0045] Referring to Figure 3, the circuit diagram of a pixel can correspond to the equivalent circuit of each pixel PX included in the pixel array (for example, 110 in Figure 2).

[0046] The pixel PX may include a photodetector PD, a transfer transistor TT, a reset transistor RT, a floating diffusion region FA, a driver transistor DT, and a selection transistor ST. In other words, the pixel may have a 4TR (4-transistor) pixel structure.

[0047] A photodetector (PD) can generate and store photocharges corresponding to the intensity of incident light. For example, a photodetector (PD) can be implemented as a photodiode, phototransistor, photogate, pinned photodiode, or a combination thereof.

[0048] The transfer transistor TT may be electrically connected between the photodetector PD and the floating diffusion region FA. The transfer transistor TT turns on or off in response to a transfer control signal TX applied to the gate electrode TG. When the transfer transistor TT is on, it can transfer the photocharge accumulated in the photodetector PD to the floating diffusion region FA. The source electrode of the transfer transistor TT may be electrically connected to the photodetector PD, and the drain electrode may be electrically connected to the floating diffusion region FA.

[0049] The reset transistor RT can reset the voltage of the floating diffusion region FA to the power supply voltage VDD in response to a reset control signal RX applied to the gate electrode RG. The power supply voltage VDD may be applied to the source electrode of the reset transistor RT, and the drain electrode may be electrically connected to the floating diffusion region FA.

[0050] The floating diffusion region FA can accumulate photocharge transferred from the transfer transistor TT. The floating diffusion region FA may be electrically connected to the gate electrode of the driver transistor DT, the drain electrode of the transfer transistor TT, and the drain region of the reset transistor RT. A floating diffusion electrode may be placed in the floating diffusion region FA.

[0051] The driver transistor DT is electrically connected between the power supply voltage VDD and the selection transistor ST, and can amplify the change in the electrical potential of the floating diffusion region FA to which the photocharge accumulated in the photodetector PD has been transferred, and transfer it to the selection transistor ST. The gate electrode of the driver transistor DT may be electrically connected to the floating diffusion region FA, the power supply voltage VDD may be applied to the source electrode, and the drain electrode may be electrically connected to the source electrode of the selection transistor ST.

[0052] The selection transistor ST is electrically connected between the driver transistor DT and the output signal line (or column line), and turns on in response to a low selection control signal SX applied to the gate electrode SG, and can output the electrical signal transferred from the driver transistor DT as the pixel signal Vout. The source electrode of the selection transistor ST may be electrically connected to the drain electrode of the driver transistor DT.

[0053] The floating diffusion region FA (or floating diffusion electrode) can form a capacitance with the boost control line FDBL.

[0054] Each of the control signals provided to the transfer control signal TX, reset control signal RX, low selection control signal SX, and boost control line FDBL may be supplied from the low driver 120, but is not limited thereto.

[0055] A pixel array 110 according to one embodiment may further include a compensation line CPL electrically connected to the gate electrode TG of the transfer transistor TT of each pixel. The compensation line CPL can provide a compensation signal to the gate electrode TG of the transfer transistor TT. The compensation signal may be a compensation signal for a transfer control signal.

[0056] In some embodiments, the pixel PX may further include a first diode OD1 between the transfer signal line TL and the gate electrode TG, and a second diode OD2 between the compensation line CPL and the gate electrode TG. The first diode OD1 and the second diode OD2 may be selectively turned on. The disclosure is not limited thereto, and switches that are turned on / off by other control signals may be provided without using diodes OD1 and OD2.

[0057] Figure 4 is a schematic diagram showing that the optimal voltage is applied to the pixel transfer transistor according to one embodiment.

[0058] Referring to Figure 4, a transfer control signal (also called a first voltage V1) may be applied to the terminal of the first diode OD1 via the transfer signal line TL, and a compensation signal (also called an auxiliary first voltage V1') may be applied to the terminal of the second diode OD2 via the compensation line CPL. In some embodiments, in addition to the first voltage V1 applied via the transfer signal line TL, an auxiliary first voltage V1' can be applied to the gate electrode TG of the transfer transistor TT via the compensation line CPL to enable pixel-level voltage optimization. In some embodiments, the first voltage V1 may be determined based on the average characteristics of all pixels in a particular region, such as a row. Alternatively, it may be applied uniformly to all pixels in that region via the transmission line. In some embodiments, the auxiliary first voltage V1' may be determined based on the individual characteristics of each pixel. By applying it pixel by pixel via the compensation line CPL, the effective gate voltage of the transfer transistor can be adjusted to compensate for variations between pixels. For example, the first voltage V1 may be the lowest of the optimal voltage values ​​for each pixel PX (or the lowest of the optimal voltage values ​​for pixel PX in each pixel row, or the average optimal voltage value for pixel PX in each pixel row). For example, the auxiliary first voltage V1' may be the optimal voltage value for pixel PX at each coordinate. The auxiliary first voltage V1', which is the optimal voltage value, may be different for each pixel PX or may be the same. The method for determining the auxiliary first voltage V1' will be described later. In this specification, the terms “optimized” or “optimal” as used in relation to transfer control signals are used to indicate values ​​or conditions that improve the performance of the image sensor device. In this sense, the terms “optimized” or “optimal” do not necessarily represent the best performance that the image sensor device can achieve.

[0059] Figure 5 is a timing diagram of a single pixel based on one embodiment.

[0060] For the sake of explanation, the reset period will be referred to as Period 1 T1, the light irradiation period as Period 2 T2, and the lead periods as Period 3 T3 and Period 4 T4. Period 3 T3 may be the FD reset period, and Period 4 T4 may be the readout period. Period 1 T1 may be the PD reset period.

[0061] The voltage applied to the gate electrode of the transfer transistor TT may be a first voltage V1, and the transfer transistor TT may be activated or deactivated based on the magnitude of the first voltage V1. An optimal voltage value must be applied to the gate electrode of the transfer transistor TT to ensure proper operation. For each pixel PX shown in Figure 2, the optimal voltage value for turning on the transfer transistor TT may differ from one another. For example, for one pixel PX, the first voltage V1 may be the optimal voltage value, for another pixel PX, a voltage greater than the first voltage V1 may be the optimal voltage value, and for yet another pixel PX, a voltage less than the first voltage V1 may be the optimal voltage value.

[0062] In the case of a single pixel (or first pixel), an optimal voltage value higher than the first voltage (e.g., V1 in Figure 5) can be applied to the transfer transistor to ensure proper operation, and the compensation signal V1' (or auxiliary first voltage) in Figure 4 may be greater than the first voltage V1.

[0063] For other pixels (or second pixels), the optimal voltage value of the transfer transistor may be less than the first voltage (e.g., V1 in Figure 5), and the compensation signal V1' (or auxiliary first voltage) in Figure 4 may be smaller than the first voltage V1. However, in some embodiments, if the diodes OD1 and OD2 in Figure 4 are configured to turn on only when a higher voltage is applied, the first voltage V1 in Figure 5 may be the lowest of the optimal voltage values ​​for all pixels PX. Therefore, in some embodiments, for the second pixel, the compensation signal V1' may be the same magnitude as the first voltage V1. That is, for the second pixel, the first voltage V1 may be the optimal voltage value.

[0064] Furthermore, in the case of other pixels (or a third pixel), the first voltage (for example, V1 in Figure 5) and the optimal voltage value may be the same for the transfer transistor. That is, the compensation signal V1' (or auxiliary first voltage) in Figure 4 may be the same as the first voltage V1.

[0065] Figure 6 shows the storage of image data output from a single pixel based on one embodiment. Figure 6 shows the storage of image data output from each of the first to third pixels described above. Furthermore, Figure 6 shows the transfer of pixel signals S1_PX and S2_PX extracted (or generated) from the third period T3 and fourth period T4 of the pixel to the dual correlation sampler 130.

[0066] Referring to Figure 6, in the third period T3, the first pixel signal S1_PX may be output to the output signal line, and in the fourth period T4, the second pixel signal S2_PX may be output to the output signal line. The output pixel signals S1_PX and S2_PX are transferred to the dual-correlation sampler 130. For example, the first pixel signal S1_PX may represent the pixel signal for the photocharge when the floating diffusion region is reset, and the second pixel signal S2_PX may represent the pixel signal for the photocharge accumulated in the floating diffusion region. As shown in Figure 6, the process of storing the pixel signals S1_PX and S2_PX obtained during the third period T3 and fourth period T4 of the pixel in the data memory 500 may be performed during the wafer test operation.

[0067] Furthermore, the generation of pixel signals S1_PX and S2_PX may be performed in a white environment. However, this embodiment is not limited to this, and the generation of pixel signals S1_PX and S2_PX may also be performed in a black environment. When the generation of pixel signals S1_PX and S2_PX is performed in a black environment where no incident light is present on the pixel array, there may be no photocharge amount due to incident light accumulated in the photoelectric conversion element PD during the second period T2.

[0068] For example, in the case of the third pixel described above, when an optimized voltage is applied to the transfer transistor TT, the first pixel signal S1_PX has a first voltage value, and the second pixel signal S2_PX has a second voltage value. The difference between the first and second voltage values ​​can correspond to the amount of photocharge applied to the photoelectric conversion element PD. The dual-correlation sampler 130 can calculate the difference between the pixel signals S1_PX and S2_PX and transfer it to the ADC 140. Therefore, the ADC 140 can receive a value corresponding to the amount of photocharge applied to the photoelectric conversion element PD (hereinafter referred to as the normal value) and perform digital conversion and offset processing. For example, the ADC 140 converts the normal value provided by the dual-correlation sampler 130 into a digital format and applies an offset to generate image data (Data_PX(Pedestal[LSB])), the value of which may be 64[LSB]. That is, for example, let's assume the normal value is 64[LSB].

[0069] However, in the case of the first pixel, if a voltage smaller than the optimization voltage is applied to the transfer transistor TT, the first pixel signal S1_PX may be a first voltage value, and the second pixel signal S2_PX may have a voltage larger than the second voltage value. Therefore, the ADC140 can receive a voltage value larger than the normal value (hereinafter referred to as the first abnormal value) and perform digital conversion and offset processing. For example, the ADC140 digitally converts and offsets the first abnormal value provided by the dual-correlation sampler 130 to generate image data (Data_PX(Pedestal[LSB])), the value of which may be greater than 64[LSB].

[0070] Furthermore, in the case of the second pixel, if a voltage greater than the optimization voltage is applied to the transfer transistor TT, the first pixel signal S1_PX may be the first voltage value, and the second pixel signal S2_PX may have a voltage smaller than the second voltage value. Therefore, the ADC140 can receive a voltage value smaller than the normal value (hereinafter referred to as the second abnormal value) and perform digital conversion and offset processing. For example, the ADC140 digitally converts and offsets the second abnormal value provided by the dual-correlation sampler 130 to generate image data (Data_PX(Pedestal[LSB])), and its value may be smaller than 64[LSB].

[0071] According to this embodiment, as described above, the size of the image data Data_PX generated from each pixel PX differs depending on whether the transfer control signal applied to the transfer transistor TT of a specific pixel is the optimization voltage, less than the optimization voltage, or greater than the optimization voltage, and the image data Data_PX generated for each pixel PX can be stored in the data memory 500. The data memory 500 can store the image data Data_PX so as to correspond to the pixel PX at each coordinate. In some embodiments, instead of storing the image data Data_PX for each coordinate of the pixel PX, the data memory 500 may store positional information that identifies the pixel PX that needs correction based on the image data Data_PX generated for each coordinate, or a value to be corrected for the pixel PX that needs correction.

[0072] Furthermore, if an optimized voltage is not applied to the transfer transistor TT for each pixel PX (for example, if an image data Data_PX value of 64[LSB] is not generated), the first period T1 to the fourth period T4 in Figure 5 may be repeated during the wafer test (WT) phase while changing the value of the transfer control signal. This allows the optimized voltage value of the transfer control signal to be measured for each pixel PX. Therefore, the data memory 500 can store both the image data Data_PX corresponding to the pixel PX at each coordinate and the optimal voltage value of the transfer control signal for the pixel PX at each coordinate. The optimal voltage values ​​of the transfer control signal for the pixel PX at each coordinate may be different from each other. For example, if the optimal voltage value of the transfer transistor TT for a pixel PX where the image data Data_PX is 64[LSB] is used as the reference optimal voltage value, the optimal voltage value of the transfer transistor TT for a pixel PX where the image data Data_PX is greater than 64[LSB] may be greater than the reference optimal voltage value, and the optimal voltage value of the transfer transistor TT for a pixel PX where the image data Data_PX is less than 64[LSB] may be less than the reference optimal voltage value.

[0073] Therefore, the compensation signal applied to the third pixel (e.g., V1' in Figure 6) may be the same as the first voltage (e.g., V1 in Figure 6), the compensation signal applied to the first pixel (e.g., V1' in Figure 6) may be greater than the first voltage (e.g., V1 in Figure 6), and the compensation signal applied to the second pixel (e.g., V1' in Figure 6) may be less than the first voltage (e.g., V1 in Figure 6). Thus, the compensation signals supplied to the compensation line CPL can be used to adjust the effective gate voltage of the pixel's transfer transistor at each coordinate of the pixel array.

[0074] The operation method of the imaging device will be explained below with reference to Figures 1 to 6. When explaining the sequence diagram in Figure 7, Figures 1 to 6 can also be referred to.

[0075] Figure 7 is a sequence diagram showing the operation method of an imaging device based on one embodiment.

[0076] Referring to Figures 6 and 7, the operation method of the imaging apparatus according to one embodiment includes the step (S10) of evaluating the optimal voltage value of the transfer control signal TX for each pixel and storing it in the data memory 500. In this step, the evaluation may be performed in a black environment or a white environment. As an example, in one embodiment, the evaluation in a white environment will be mainly described. In the step (S10) of evaluating the optimal voltage value of the transfer control signal TX for each pixel and storing it in the data memory 500, the process of storing the pixel signals S1_PX and S2_PX in the data memory 500 is performed during the wafer test operation, and the dual correlation sampler 130 calculates the difference between the pixel signals S1_PX and S2_PX transferred for each pixel and provides it to the ADC 140. Therefore, the ADC 140 receives a value corresponding to the amount of photocharge applied to the photoelectric conversion element PD (hereinafter referred to as the normal value) and can perform digital conversion and offset processing. According to this embodiment, as described above, the size of the image data Data_PX generated from each pixel PX differs depending on whether the transfer control signal applied to the transfer transistor TT is the optimization voltage, less than the optimization voltage, or greater than the optimization voltage, and the image data Data_PX generated for each pixel PX can be stored in the data memory 500. The data memory 500 can store the image data Data_PX so as to correspond to the coordinates of each pixel PX. In some embodiments, instead of storing the image data Data_PX for each coordinate of the pixel PX, the data memory 500 can store positional information that identifies the pixel PX that needs correction based on the image data Data_PX generated for each coordinate, or a value to be corrected for the pixel PX that needs correction.

[0077] Next, the operation method of the imaging device according to one embodiment includes the step (S20) of outputting a pixel transfer control signal TX on a row-by-row basis from a low driver (e.g., 120 in Figure 2). For example, the transfer control signal provided to the pixels on a row-by-row basis (first voltage V1 in Figure 4) may be the average optimal voltage value or the minimum optimal voltage value of the pixels obtained on a row-by-row basis. However, the disclosure is not limited thereto.

[0078] Next, the operation method of the imaging device according to one embodiment includes a step (S30) in which a compensation driver (e.g., 180 in Figure 2) outputs a compensation signal (e.g., V1' in Figure 4) for each pixel in a row. The compensation signal V1' is calculated in step S10 for each pixel (or pixel requiring correction) and may differ for each pixel.

[0079] Next, the operation method of the imaging apparatus according to one embodiment includes the step (S40) of applying an optimal TX voltage value to each pixel. As described in Figure 4, a compensation signal (or auxiliary first voltage V1') may be applied to the terminal of the second diode OD2 via the compensation line CPL.

[0080] Figure 8 is a schematic diagram of pixels in a pixel array based on another embodiment.

[0081] Referring to Figure 8, a pixel array according to another embodiment further includes a compensation line CPL_1, which may be electrically connected to the gate electrode TG_2 of the compensation transistor TT_2 of pixel PX_1. A transfer signal line TL may be electrically connected to the gate electrode TG_1 and first electrode of an auxiliary transfer transistor TT_1. The second electrode of the compensation transistor TT_2 and the second electrode of the auxiliary transfer transistor TT_1 are each electrically connected to the gate electrode TG of the transfer transistor TT, and the second electrode of the transfer transistor TT may be electrically connected to a floating diffusion region FA. The gate electrode TG_2 and first electrode of the compensation transistor TT_2 may be electrically connected to the compensation line CPL_1.

[0082] An auxiliary transfer control signal may be applied to the gate electrode TG_1 of the auxiliary transfer transistor TT_1 via the transfer signal line TL, and a compensation signal may be applied to the gate electrode TG_2 of the compensation transistor TT_2 via the compensation line CPL_2. For example, the auxiliary transfer control signal may be the lowest voltage value among the optimal voltage values ​​of pixel PX_1 at each coordinate (or the lowest voltage value among the optimal voltage values ​​of pixel PX_1 in each pixel row, or the average optimal voltage value of pixel PX_1 in each pixel row), and the compensation signal may be the optimal voltage value of pixel PX at each coordinate. For example, in the case of pixel PX_1 where the image data Data_PX described in Figure 12 is 64 [LSB], the magnitude of the auxiliary transfer control signal and the magnitude of the compensation signal may be the same, in the case of pixel PX_1 where the image data Data_PX is greater than 64 [LSB], the magnitude of the compensation signal may be greater than the magnitude of the auxiliary transfer control signal, and in the case of pixel PX_1 where the image data Data_PX is less than 64 [LSB], the magnitude of the auxiliary transfer control signal may be greater than the magnitude of the compensation signal.

[0083] This allows the transfer signals applied to each transfer transistor TT of pixels PX_1, which have different optimal voltage values, to be optimized via the compensation transistor TT_2 and compensation line CPL_2.

[0084] This has already been explained with reference to Figure 3, so a detailed explanation will be omitted below.

[0085] The following describes a method for compensating the duration of the transfer control signal TX, and the imaging device used for this compensation, with reference to Figures 9 to 12.

[0086] Figure 9 is a sequence diagram showing the operation method of an imaging device based on another embodiment. In the operation method and imaging device shown in Figure 9, a compensation signal is applied via the compensation line CPL described in Figure 2. The magnitude of the compensation signal is the same as the first voltage V1 shown in Figure 4, but the duration of the compensation signal may differ from the transfer control signal TX in order to compensate for the duration of the transfer control signal TX. Therefore, the structure of the imaging device based on this embodiment may be the same as the imaging device described in Figures 2 and 4, or Figure 8.

[0087] The operation method of the imaging device according to this embodiment includes the step (S11) of evaluating the optimal duration of the transfer control signal TX for each pixel and storing it in the data memory 500. In this step, the evaluation may be performed in a black environment or a white environment. As an example, this embodiment will mainly describe the evaluation in a white environment. Since step (S11) is the same as step (S10) described in Figure 7, a redundant explanation will be omitted.

[0088] Next, the operation method of the imaging device according to this embodiment includes the step (S21) of outputting a transfer control signal TX to a pixel from a low driver (e.g., 120 in Figure 2) for a first duration. For example, the first duration of the transfer control signal (first voltage in Figure 4) provided to a row of pixels may be the average optimal duration or minimum optimal duration obtained for pixels on a row-by-row basis, but the disclosure is not limited thereto.

[0089] The operation method of the imaging device according to this embodiment includes the step (S31) of outputting a voltage (or compensation signal) from a compensation driver (e.g., 180 in Figure 2) to compensate for the optimal duration of each pixel in a column-by-column manner. In this embodiment, the compensation signal may be the same as the first voltage, but the disclosure is not limited thereto.

[0090] Next, the operation method of the imaging device according to this embodiment includes the step (S41) of applying a TX voltage to each pixel during the optimal TX duration.

[0091] According to this embodiment, the optimal duration of the transfer control signal TX may differ for each pixel, and the optimal duration of the transfer control signal TX applied to each pixel can be optimized through the duration of the compensation signal output from the compensation driver 180.

[0092] Figure 10 is a timing diagram showing that the pixel transfer transistors based on another embodiment operate at the optimal drive time.

[0093] Referring to Figure 10, in the first period T1, a transfer control signal TX may be applied to the gate electrode for a first duration t1a, and after the transfer control signal TX is applied, a compensation signal may be applied to the gate electrode for a first compensation duration t1a'. The sum of the first duration t1a and the first compensation duration t1a' may be the same as the length of the first period T1. The first duration t1a and the first compensation duration t1a' do not have to overlap.

[0094] Figure 11 is a timing diagram showing that the pixel transfer transistors based on another embodiment operate at the optimal drive time.

[0095] Referring to Figure 11, according to the modified pixel array, in the first period T1, a transfer control signal TX can be applied to the gate electrode for a first duration t1a, and at the same time, a compensation signal can be applied to the gate electrode for a first compensation duration t1a' which is the same length as the first period T1.

[0096] Figure 12 is a timing diagram showing that the pixel transfer transistors based on another embodiment operate at the optimal drive time.

[0097] Referring to Figure 12, during the first period T1, a transfer control signal TX is applied to the gate electrode for a first duration t1b, and the first duration t1b may be longer than the length (or time) of the first period T1. In this case, a higher voltage (or compensation signal) than that of the transfer signal line TL may be applied to the compensation line in Figure 3, and the transfer transistor TT in Figure 8 may be turned off, and only the compensation transistor TT_1 may be turned on, and a compensation signal may be applied to the gate electrode TG_1 of the compensation transistor TT_1. The compensation signal may be applied to the gate electrode for a first compensation duration t1b' which is the same length as the first period T1.

[0098] The following description of the imaging device configured to optimize the boost control signal FDB will be based on Figures 13 to 16.

[0099] Figure 13 is a block diagram of an image sensing unit based on another embodiment.

[0100] Referring to Figure 13, the image sensing unit 100_2 according to this embodiment may include a compensation driver 180_2. The compensation driver 180_2 may be controlled by a timing controller 170. Compensation lines CPL_2 may extend from the compensation driver 180_2. Multiple compensation lines CPL_2 may be provided, extending along the column direction, and each of the multiple compensation lines CPL_2 may be spaced apart in the row direction. Each of the multiple compensation lines CPL_2 may correspond one-to-one with a pixel column formed by a plurality of pixels PX_2 extending in the column direction. In this embodiment, the control line may be a boost control line FDBL.

[0101] Figure 14 is a schematic diagram of a pixel in a pixel array based on another embodiment.

[0102] Referring to Figure 14, the pixel array 110_2 according to this embodiment may further include a compensation line CPL_2. The compensation line CPL_2 can form a capacitance with the floating diffusion region FA. The compensation line CPL_2 can play a role in compensating for the capacitance formed between the boost control line FDBL and the floating diffusion region FA. The compensation line CPL_2 can provide a compensation signal to the floating diffusion region FA. The compensation signal may be a compensation signal for the boost control signal.

[0103] Figure 15 is a schematic cross-sectional view showing the floating diffusion electrode, boost control line, and compensation line of the image sensing unit in Figure 14.

[0104] Referring to Figure 15, the compensation line CPL_2 may overlap with the floating diffusion electrode FD.

[0105] The boost control line FDBL can form a first capacitance C1 with the floating diffusion electrode FD, and the compensation line CPL_2 can form a second capacitance C2 with the floating diffusion electrode FD.

[0106] A boost control signal (or second voltage V2) may be applied to the boost control line FDBL, and a compensation signal (or second voltage V2') may be applied to the compensation line CPL_2. For example, the second voltage V2 is the lowest of the optimal voltage values ​​of pixel PX at each coordinate (or the lowest of the optimal voltage values ​​of pixel PX in each pixel row, or the average optimal voltage value of pixel PX in each pixel row), and the second voltage V2' may be the same voltage value as the difference between the second voltages V2 at the optimal voltage values ​​of pixel PX at each coordinate.

[0107] Figure 16 is a timing diagram for a single pixel.

[0108] Referring to Figure 16, in the first period T1 and fourth period T4 of the pixel according to this embodiment, the boost control signal FDB may have a second voltage V2.

[0109] For a single pixel (or first pixel), for proper operation, an optimal voltage value should be applied to the boost control line FDBL that is higher than the second voltage (e.g., V2 in Figure 15), and the sum of the compensation signal (e.g., V2' in Figure 15) (or second voltage) and the second voltage V2 may be the optimal voltage value.

[0110] The operation method of the imaging device will be explained below with reference to Figures 14 to 16. When explaining the sequence diagram in Figure 17, Figures 14 to 16 can also be referred to.

[0111] Figure 17 is a sequence diagram showing the operation method of an imaging device based on another embodiment.

[0112] Referring to Figures 6 and 17, the operation method of the imaging apparatus according to this embodiment includes the step (S12) of evaluating the optimal voltage value of the boost control signal FDB for each pixel and storing it in the data memory 500. In this step, the evaluation may be performed in a black environment or a white environment. As an example, this embodiment will mainly describe the evaluation in a white environment. In the step (S12) of evaluating the optimal voltage value of the boost control signal FDB for each pixel and storing it in the data memory 500, the process of storing the pixel signals (for example, S1_PX and S2_PX in Figure 6) in the data memory 500 is performed during the wafer test operation, and the dual correlation sampler 130 calculates the difference between the pixel signals S1_PX and S2_PX transferred for each pixel and provides it to the ADC 140. Therefore, the ADC 140 receives a value corresponding to the amount of photocharge applied to the photoelectric conversion element PD (hereinafter referred to as the normal value) and can perform digital conversion and offset processing. According to this embodiment, as described above, the size of the image data Data_PX generated from each pixel PX differs depending on whether the boost control signal applied to the boost control line FDBL is the optimized voltage, less than the optimized voltage, or greater than the optimized voltage, and the image data Data_PX generated for each pixel PX can be stored in the data memory 500. The data memory 500 can store the image data Data_PX according to the coordinates of the pixel PX. In some embodiments, instead of storing the image data Data_PX for each coordinate of the pixel PX, the data memory 500 can store position information that identifies the pixel PX that requires correction, derived based on the image data Data_PX generated for each coordinate, or a value to be corrected for the pixel PX that requires correction.

[0113] Next, the operation method of the imaging device according to this embodiment includes the step (S22) in which a low driver (e.g., 120 in Figure 13) outputs a boost control signal FDB for a pixel. For example, the boost control signal FDB may be provided on a row-by-row basis, and the boost control signal provided to a row-by-row pixel (second voltage V2 in Figure 15) may be the average optimal voltage value or the minimum optimal voltage value for a row-by-row pixel, but the disclosure is not limited thereto.

[0114] Next, the operation method of the imaging device according to this embodiment includes a step (S32) in which a compensation driver (e.g., 180_2 in Figure 13) outputs a compensation signal (e.g., V2' in Figure 15) for each pixel in a row. The compensation signal V2' is calculated in step S12 for each pixel (or pixel requiring correction) and may differ for each pixel.

[0115] Next, the operation method of the imaging apparatus according to this embodiment includes a step (S42) in which an FDB optimal voltage value is applied to each pixel. As described in Figure 15, a compensation signal V2' can be applied via the compensation line CPL_2.

[0116] The following describes a method for compensating the duration of the boost control signal FDB, and the imaging device used for this compensation, with reference to Figures 18 to 20.

[0117] Figure 18 is a sequence diagram showing the operation method of an imaging device according to another embodiment. In the operation method and imaging device shown in Figure 18, a compensation signal is applied via the compensation line CPL_2 described in Figure 13, but the magnitude of the compensation signal may be the same as the second voltage V2 shown in Figure 15. However, the duration of the compensation signal may differ from that of the boost control signal FDB in order to compensate for the duration of the boost control signal FDB. Therefore, the structure of the imaging device according to this embodiment may be the same as that of the imaging device described in Figure 15.

[0118] The operation method of the imaging device according to this embodiment includes the step (S13) of evaluating the optimal duration of the boost control signal FDB for each pixel and storing it in the data memory 500. In this step, the evaluation may be performed in a black environment or a white environment. As an example, this embodiment will mainly describe the evaluation in a white environment. Since the above step (S13) is the same as step (S10) described in Figure 7, a redundant explanation will be omitted.

[0119] Next, the operation method of the imaging device according to this embodiment includes the step (S23) of outputting a boost control signal FDB to the pixels from a low driver (e.g., 120 in Figure 13) for a second duration. For example, the second duration of the boost control signal (second voltage V2 in Figure 15) provided to the pixels on a row-by-row basis may be the average optimal duration or minimum optimal duration obtained for the pixels on a row-by-row basis, but the disclosure is not limited thereto.

[0120] Next, the operation method of the imaging device according to this embodiment includes the step (S33) of outputting a voltage (or compensation signal) from a compensation driver (e.g., 180_2 in Figure 13) to compensate for the optimal duration of each pixel in a column-by-column manner. In this embodiment, the compensation signal may be the same as the second voltage, but the disclosure is not limited thereto.

[0121] Next, the operation method of the imaging device according to this embodiment includes the step (S43) of applying an FDB voltage to each pixel for an optimal FDB duration.

[0122] According to this embodiment, the optimal duration of the boost control signal FDB may differ for each pixel, and the optimal duration of the boost control signal FDB applied to each pixel can be optimized through the duration of the compensation signal output from the compensation driver 180_2.

[0123] Figure 19 is a timing diagram showing that the pixel boost control line based on another embodiment operates with optimal drive time.

[0124] Referring to Figure 19, in the first period T1, a boost control signal FDB may be applied for a second duration t2a, and after the boost control signal FDB is applied, a compensation signal may be applied for a second compensation duration t2a'. The sum of the second duration t2a and the second compensation duration t2a' may be the same as the length of the first period T1. The second duration t2a and the second compensation duration t2a' do not have to overlap.

[0125] Figure 20 is a timing diagram showing that the pixel boost control line based on another embodiment operates with the optimal drive time.

[0126] Referring to Figure 20, during the first period T1, a boost control signal FDB may be applied for a second duration t2a, and at the same time, a compensation signal may be applied for a second compensation duration t2a' which is the same length as the first period T1.

[0127] While some embodiments and examples of the disclosed technology have been described, other embodiments, improvements, modifications, or variations can be made based on what is described and illustrated herein. [Explanation of Symbols]

[0128] 1: Shooting System 10: Imaging device 100: Image Sensing Unit RT: Reset transistor DT: Driver transistor ST: Select Transistor

Claims

1. A pixel array containing multiple pixels, A row driver is electrically connected to the pixel array and supplies control signals to the plurality of pixels. A imaging apparatus comprising a compensation driver electrically connected to the pixel array and supplying compensation signals to the plurality of pixels.

2. The imaging apparatus according to claim 1, wherein each of the plurality of pixels includes a floating diffusion region electrically connected to a photodetector and a transfer transistor, the transfer transistor being electrically connected to the photodetector, and the pixel array further includes a boost control line that forms a first capacitance with the floating diffusion region of each of the plurality of pixels.

3. The imaging apparatus according to claim 2, wherein both the control signal and the compensation signal are applied to the gate electrode of the transfer transistor.

4. The imaging apparatus according to claim 2, wherein the pixel array further includes a transmission line electrically connected to the low driver, a first diode electrically connected between the transmission line and the gate electrode of the transfer transistor, a compensation line electrically connected to the compensation driver, and a second diode electrically connected between the compensation line and the gate electrode of the transfer transistor.

5. The imaging apparatus according to claim 2, wherein the pixel array further includes a transmission line electrically connected to the low driver, a compensation transistor electrically connected to the transfer transistor, and a compensation line electrically connecting the compensation driver to the gate electrode of the compensation transistor.

6. The imaging apparatus according to claim 2, wherein each of the plurality of pixels further includes a compensation line that forms a second capacitance with the floating diffusion region.

7. The imaging apparatus according to claim 6, wherein the control signal is provided to the boost control line and the compensation signal is provided to the compensation line.

8. The imaging apparatus according to claim 2, wherein the optimal voltage value of the control signal for one of the plurality of pixels and the optimal voltage value of the control signal for the other pixels are different from each other.

9. The imaging apparatus according to claim 8, wherein the control signal is applied to the gate electrode of the transfer transistor or to the boost control line.

10. A pixel array containing multiple pixels, A low driver electrically connected to the pixel array and supplying control signals having a first duration to the plurality of pixels, A imaging apparatus comprising: a compensation driver electrically connected to the pixel array and supplying a compensation signal having a second duration to the plurality of pixels.

11. The imaging apparatus according to claim 10, wherein each of the plurality of pixels includes a floating diffusion region electrically connected to a photodetector and a transfer transistor, the transfer transistor being electrically connected to the photodetector, and the pixel array further includes a boost control line forming a first capacitance with the floating diffusion region of each of the plurality of pixels.

12. The imaging apparatus according to claim 11, wherein both the control signal and the compensation signal are applied to the gate electrode of the transfer transistor.

13. The imaging apparatus according to claim 11, wherein each of the plurality of pixels further includes a compensation line that forms a second capacitance with the floating diffusion region.

14. The imaging apparatus according to claim 13, wherein the control signal is provided to the boost control line and the compensation signal is provided to the compensation line.

15. The imaging apparatus according to claim 11, wherein the optimal duration of the control signal for one of the plurality of pixels and the optimal duration of the control signal for the other pixels are different from each other.

16. The imaging apparatus according to claim 15, wherein the control signal is applied to the gate electrode of the transfer transistor or to the boost control line.

17. The steps include evaluating the optimal voltage value of each control signal for multiple pixels in a pixel array and storing it in data memory, The steps include: outputting the control signal from the low driver; A step of outputting a compensation signal for each of the plurality of pixels in a column-by-column unit, A method for operating an imaging device, comprising the steps of applying a control signal and a compensation signal to each of the plurality of pixels.

18. Each of the plurality of pixels includes a photodetector, a transfer transistor electrically connected to the photodetector, and a floating diffusion region electrically connected to the transfer transistor. The method of operating the imaging apparatus according to claim 17, wherein the pixel array further includes a boost control line that forms a first capacitance with the floating diffusion region of the pixels.

19. The method of operating the imaging apparatus according to claim 18, wherein both the control signal and the compensation signal are applied to the gate electrode of the transfer transistor.

20. The method of operating an imaging apparatus according to claim 17, wherein the step of storing the optimal voltage value in the data memory includes storing a value to be corrected for the pixel based on information identifying the pixel that needs correction, or the difference between the pixel signal obtained during the reset period of the floating diffusion region and the pixel signal obtained during the readout period.

21. The method of operating the imaging apparatus according to claim 20, wherein information identifying a pixel that requires correction, or a value to be corrected for the pixel, is stored in the data memory.

22. The steps include evaluating the optimal duration of each control signal for multiple pixels in a pixel array and storing it in data memory, The steps include: outputting the control signal from the low driver; A step of outputting a compensation signal corresponding to the optimal duration for each of multiple pixels in a column, A method for operating an imaging device, comprising the steps of applying a control signal and a compensation signal to each of the plurality of pixels.

23. The method of operating the imaging apparatus according to claim 22, wherein each of the plurality of pixels includes a photodetector, a transfer transistor electrically connected to the photodetector, and a floating diffusion region electrically connected to the transfer transistor.

24. The method of operating the imaging apparatus according to claim 23, wherein the pixel array further includes a boost control line that forms a first capacitance with the floating diffusion region of the pixel.

25. The method of operating the imaging apparatus according to claim 22, wherein both the control signal and the compensation signal are applied to the gate electrode of the transfer transistor.

26. The step of storing the optimal duration in the data memory is: A method for operating an imaging apparatus according to claim 22, comprising storing information that identifies a pixel requiring correction, or a value to be corrected for the pixel, based on the difference between the pixel signal obtained during the reset period of the floating diffusion region and the pixel signal obtained during the readout period.

27. The method of operating the imaging apparatus according to claim 26, wherein information identifying a pixel that requires correction, or a value to be corrected for the pixel, is stored in the data memory.

Images