Communication device

Abstract

To provide a communication device that can achieve high transmission efficiency without incurring overhead. [Solution] The communication device includes a memory 102 in which data is stored, and a communication interface 103 for transmitting data to other devices. The communication interface 103 includes a register that stores a transmit descriptor including the memory read address and the length of the data to be read from before the start of communication, a transmit DMA controller 106 that reads data from memory based on the transmit descriptor and writes it to a transmit buffer when a combined packet is transmitted, and a packet generator that generates a transmit packet including the data in the transmit buffer and an identifier indicating whether it is a combined packet or a single packet.

Description

Technical Field

[0001] The present disclosure relates to a communication apparatus.

Background Art

[0002] In a communication system in which a processor processes packets arriving from a communication path, when small packets with poor transmission efficiency are transmitted at a high frequency, the number of DMA (Direct Memory Access) transfer controls by the processor increases. As a result, there is a problem that the performance of the communication system deteriorates due to the increased load on the processor. Furthermore, since packets are appended with headers necessary for communication in addition to data, there is also a problem that the transmission efficiency of the communication path deteriorates and the communication path becomes congested.

[0003] Patent Document 1 describes that a packet processing apparatus writes a plurality of packets to be transmitted into a packet memory and transmits a combined packet obtained by concatenating the plurality of packets.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In Patent Document 1, the receiving side can restore the packets by being notified in advance that the combined packet has been transmitted. Since the advance notification packet is transmitted, overhead occurs in the communication data.

[0006] An object of the present disclosure is to provide a communication apparatus capable of achieving high transmission efficiency without incurring overhead.

Means for Solving the Problems

[0007] The communication device of this disclosure comprises a memory in which data is stored and a communication interface for transmitting data to another device. The communication interface includes a register that stores a transmit descriptor, which includes the read address of the memory and the length of the data to be read, from before the start of communication; a transmit DMA controller that, when a combined packet is transmitted, reads data from the memory based on the transmit descriptor and writes it to a transmit buffer; and a packet generator that generates a transmit packet, which includes the data in the transmit buffer and an identifier indicating whether it is a combined packet or a single packet. [Effects of the Invention]

[0008] The communication device described herein can achieve high transmission efficiency without incurring overhead. [Brief explanation of the drawing]

[0009] [Figure 1] This is a diagram showing the configuration of the communication system according to Embodiment 1. [Figure 2] This is a diagram representing a PLC (Power Line Communication). [Figure 3] This figure shows an example of data transfer from the CPU unit (device A) 100 to the servo amplifier 230. [Figure 4] This diagram illustrates the procedure for creating transmit descriptors 104 and 114 and receive descriptors 105 and 115. [Figure 5] This diagram shows examples of a transmit descriptor 104 and a receive descriptor 115. [Figure 6] This diagram shows the internal configuration of the communication interface 103 and the transmitting DMA controller 106 involved in packet transmission. [Figure 7] This diagram shows the header (request header) 600 of a transmission packet requesting read data. [Figure 8] This diagram shows an example of a coupled packet generated by DMAC activation. [Figure 9]This is a diagram showing the internal configurations of a communication interface 103 and a reception DMA controller 107 related to packet reception. [Figure 10] This is a diagram for explaining packet transfer according to the second embodiment. [Figure 11] This is a diagram showing the configuration of a request header included in packet 2 (1101) that issues a read request. [Figure 12] This is a diagram showing the configuration of a communication system according to the second embodiment. [Figure 13] This is a diagram showing a complete header 610. [Figure 14] This is a diagram showing an example of an abnormality occurring in an FA system. [Figure 15] This is a diagram showing an example of normal data transfer according to the third embodiment. [Figure 16] This is a diagram showing an example of data transfer when an abnormality occurs in a servo amplifier (B) in the third embodiment. [Figure 17] This is a flowchart showing a communication procedure according to the third embodiment. [Figure 18] (a) to (e) are diagrams showing examples of descriptors in a normal state. [Figure 19] (a) to (c) are diagrams showing examples of descriptors when an abnormality occurs in the servo amplifier (B) 231. [Figure 20] This is a diagram showing a communication sequence when an abnormality occurs in the servo amplifier (B) 231. [Figure 21] This is a diagram showing an example of the FA system recovered from the abnormal state. [Description of Embodiments]

[0010] Hereinafter, embodiments will be described with reference to the drawings.

[0011] First Embodiment.

[0012] Figure 1 is a diagram showing the configuration of the communication system of Embodiment 1. Figure 1 shows an example in which communication data 1, 2, 3, and 4 stored in the memory 102 of device A are transferred to the memory 112 of device B.

[0013] Device A comprises a processor 101, a memory 102, and a communication interface 103. The communication interface 103 comprises a transmit DMA controller 106 and a receive DMA controller 107. Device B comprises a processor 111, a memory 112, and a communication interface 113. The communication interface 113 comprises a transmit DMA controller 116 and a receive DMA controller 117. The processor 111, memory 112, communication interface 113, transmit DMA controller 116, and receive DMA controller 117 have the same configuration as the processor 101, memory 102, communication interface 103, transmit DMA controller 106, and receive DMA controller 107, respectively.

[0014] The processor 101 controls device A by performing actions such as issuing access instructions to memory 102, controlling peripheral circuits such as communication interface 103, and processing data.

[0015] Memory 102 stores data transmitted through the communication interface 103, data received through the communication interface 103, and data processed by the processor 101. Memory 102 is composed of, for example, DRAM (Dynamic Random Access Memory).

[0016] The communication interface 103 exchanges data with external devices such as device B.

[0017] The transmit DMA controller 106 collects data to be transferred to device B from memory 102. The communication interface 103 stores the transmit descriptor 104 before communication begins. The transmit descriptor 104 includes the read address of memory 102 and the length of the data to be read. The transmit descriptor 104 is used by the transmit DMA controller 106 to collect data to be transferred to the opposing device (device B) connected to device A.

[0018] The receiving DMA controller 107 stores the data transferred from device B into memory 102. The communication interface 103 stores the receiving descriptor 105 before communication begins. The receiving descriptor 105 includes the write address of memory 102 and the length of the data to be written. The receiving descriptor 105 is used by the receiving DMA controller 107 to store the data transferred from the opposing device (device B) into memory 102.

[0019] The processor 101, memory 102, and communication interface 103 are connected by a general-purpose communication channel called the internal bus 109. For example, the Advanced Extensible Interface (AXI) bus standard may be used as the internal bus 109.

[0020] Next, we will explain FA (Factory Automation) systems and programmable logic controllers (PLCs).

[0021] Figure 2 shows a PLC. CPU unit 100 in Figure 2 corresponds to device A in Figure 1, and CPU unit 110 in Figure 2 corresponds to device B in Figure 1. The PLC is equipped with multiple CPU units that control factory equipment. Each CPU unit creates coordinate and velocity data for controlling the factory equipment. The number of CPU units installed in the PLC is determined by the size of the factory equipment. Each CPU unit is connected by a general-purpose communication interface such as PCIe (Peripheral Component Interconnect Express), allowing it to transfer processed data to other CPU units and receive data processed by other CPU units. By having each CPU unit perform separate processing, the load can be distributed.

[0022] The CPU unit 110 is connected to the servo amplifier 230 and the motor 240 via a general-purpose communication interface. The servo amplifier 230 can control the motor 240 by converting the control signal from the CPU unit 110 into power for motor control. The servo amplifier 230 also has the same circuit configuration as the CPU units 100 and 110, and is equipped with a processor, a DMAC-equipped communication interface, and memory.

[0023] In Figure 1, the data transferred from memory 102 to memory 112 is, for example, data for controlling the motor 240 in Figure 2.

[0024] Figure 3 shows an example of data transfer from CPU unit (device A) 100 to servo amplifier 230. Figure 3 shows the data stored in memory 102 installed in CPU unit (device A) 100, memory 112 installed in CPU unit (device B) 110, and memory 232 installed in servo amplifier 230.

[0025] In the example shown in Figure 3, CPU unit 100 transfers data (data 1, 2) that controls the motor 240, processed by its processor 101, and processing data (data 3, 4) to CPU unit 110 via the communication channel 120. CPU unit 110 then stores the received data (data 1, 2, 3, 4) in memory 112. Since CPU unit 100 and CPU unit 110 do not share a memory map, the data is stored at different addresses in their respective memories.

[0026] The CPU unit 110 transfers data 1 and 2 to the servo amplifier 230 via the communication channel 222 in order to control the servo amplifier 230. The method of data transfer between the CPU unit 110 and the servo amplifier 230 is the same as the method of data transfer between the CPU unit 100 and the CPU unit 110.

[0027] The servo amplifier 230 operates the motor 240 based on the received data 1 and 2.

[0028] Because FA systems are characterized by handling many small packets, this embodiment is described as an example of its application. However, the communication method of this embodiment can be applied to any system that can improve the transmission efficiency of the communication channel using a processor and DMA.

[0029] Next, we will describe the procedure for creating the transmit descriptor and the receive descriptor. Figure 4 is a diagram illustrating the procedure for creating the transmit descriptors 104 and 114 and the receive descriptors 105 and 115.

[0030] This procedure is performed from the time the FA system starts up until before communication begins. In this embodiment, after the FA system starts up, the descriptor creation procedure is started at step 401, after the network initialization sequence, which includes the detection of devices connected to the network, is completed.

[0031] The CPU unit (device B) 110 detects connected network devices and creates the transmit descriptor 114 and receive descriptor 115 necessary for controlling the servo amplifier 230 (descriptor creation 405).

[0032] The CPU unit (device A) 100 acquires network device information from the CPU unit (device B) 110 to which the communication channel 222 is connected, and creates the transmit descriptor 104 and receive descriptor 105 necessary for controlling the servo amplifier 230 (descriptor creation 404).

[0033] Figure 5 shows an example of a transmit descriptor 104 and a receive descriptor 115.

[0034] A transmit descriptor is used to collect data that a data transfer device (unit) is transferring from memory installed inside the device (unit). For example, in Figure 1, when sending data from CPU unit (device A) 100 to CPU unit (device B) 110, the transmit DMA controller 106 reads the read address and the read data length from the starting address of the transmit descriptor 104, and can then capture data equal to the read data length from the read address in memory 102 into the communication interface 103. The communication interface 103 can combine the captured data to create one large packet (combined packet) and send it to the communication channel 120.

[0035] When the CPU unit (device B) 110 receives a large packet (combined packet), the receiving DMA controller 117 reads the write address and write data length from the receiving descriptor 115 in Figure 5, divides the large packet into units of write data length, and writes each divided packet to the write address in the memory 112.

[0036] As explained above, by transferring and storing descriptors to each unit, for example during initial setup before communication begins, large packets can be exchanged between units without adding the data length and write address of each packet to the combined packet.

[0037] Next, the procedure for forwarding (transmitting) combined packets will be explained. Figure 6 shows the internal configuration of the communication interface 103 and the transmit DMA controller 106 involved in packet transmission.

[0038] The communication interface 103 includes a configuration register 730, a packet generator 740, a transmit DMA controller 106, and a receive DMA controller 107. The transmit DMA controller 106 includes a descriptor FIFO (First In First Out) 750, a buffer generator 720, and a transmit buffer 710.

[0039] The communication interface 103 is controlled by manipulating the value of the setting register 730 via the internal bus 109.

[0040] The configuration register 730 includes a normal packet DMAC activation bit 731, a combined packet DMAC activation bit 732, a destination address 734, a packet identifier 733, device information 735, a transmit descriptor 104, and a receive descriptor 105.

[0041] The transmitting DMA controller 106 collects the transfer data from memory 102 by accessing the coupled packet DMAC activation bit 732 in the configuration register 730.

[0042] The transmit descriptor 104 in the configuration register 730 is transferred to the descriptor FIFO 750.

[0043] The buffer generator 720 reads data from memory 102 based on the transmit descriptor 104 in the descriptor FIFO 750 and writes it to the transmit buffer 710.

[0044] The packet generator 740 generates a transmit packet to be sent to the communication channel 120. Generally, a packet of a general-purpose communication channel protocol consists of a packet header that stores destination and source device information, transfer data, and error correction code. The packet generator 740 creates a packet header from the destination address 734 and device information 735 stored in the configuration register 730. The packet generator 740 adds the packet header to the transfer data stored in the transmit buffer 710. The packet generator 740 creates an error correction code from the packet header and transfer data. The packet generator 740 generates a transmit packet by adding the packet header and error correction code to the transfer data stored in the transmit buffer 710.

[0045] The packet generator 740 writes the packet identifier 733, stored in the configuration register 730, into the packet header of the transmitted packet in order to notify the receiving device whether the transmitted packet is a combined packet or a single packet.

[0046] Figure 7 shows the header (request header) 600 of a transmission packet requesting read access. In Figure 7, the area labeled R is the Reserved area.

[0047] To ensure compliance with the communication channel protocol, the packet identifier 733 is written to bits not used in the protocol specification, such as the Reserved area 603 in the request header 600. In PCIe, the Reserved area is defined as all "0" bits, and the protocol does not use the value of the Reserved area. In this way, by writing the packet identifier 733 to the Reserved area, the packet generator 740 can operate normally even in a communication system where devices other than those of this embodiment (i.e., devices that do not recognize that the packet identifier 733 is written to the Reserved area) are connected to the communication channel. That is, even if the device of this embodiment sends a packet containing the packet identifier 733 and a device other than those of this embodiment receives this packet, the device other than those of this embodiment can prevent the received packet from being recognized as a corrupted packet or a protocol violation. As a result, the entire communication system connected to the communication channel can continue to operate normally.

[0048] Furthermore, if there are multiple bits, such as in the Reserved area 603, multiple types of packet identifiers can be defined to notify the receiving device of combined packets with different combination methods. For example, a packet identifier of "0x0" can indicate that the packet is a normal packet, a packet identifier of "0x1" can indicate that the packet is combined packet 1, a packet identifier of "0x2" can indicate that the packet is combined packet 2, and a packet identifier of "0x4" can indicate that the packet is combined packet 3.

[0049] For protocols where a reserved area is not defined, the packet generator 740 can write the packet identifier 733 to an unused bit in the address bit 602 of the packet header (i.e., a logical reserved area).

[0050] To reduce the processing resources required by the circuitry or software handling the memory map, the memory map utilizes a non-contiguous mapping that includes undefined addresses, making it easier to mask. If there is no reserved area in the packet header, the logical reserved area of ​​the memory map can be used. The ability to add a packet identifier to the reserved area also allows for the design of hardware and software in FA systems at a pre-system operation stage.

[0051] In the communication interface 103 shown in Figure 6, in order to enable the transmission of both normal packets and combined packets, the configuration register 730 is provided with two types of activation registers (normal packet DMAC activation bit 731 and combined packet DMAC activation bit 732) to allow switching between the transmission of the two types of packets.

[0052] When a normal packet is sent, the processor 101 writes the starting address and data length of the data to be sent as a normal packet to the descriptor FIFO 750, and then rewrites the normal packet DMAC activation bit 731 to enable. When the normal packet DMAC activation bit 731 is enabled, a pair of address and data length is input from the descriptor FIFO 750 to the buffer generator 720. The buffer generator 720 reads data from the input address to the input data length in the memory 102 via the internal bus 1091. The buffer generator 720 temporarily stores the read data in the transmit buffer 710. In Figure 6, a dedicated internal bus 1091 is provided, separate from the internal bus 109, to ensure the access speed between the DMA controller and the memory, but it is also possible to access using the internal bus 109 without providing the internal bus 1091.

[0053] When a combined packet is sent, the processor 101 rewrites the combined packet DMAC activation bit 732 to enable. When the combined packet DMAC activation bit 732 is enabled, the address and data length combinations in the transmit descriptor 104 (identical to the transmit descriptor 104 in Figure 1) are input to the buffer generator 720 sequentially from the starting address to the trailing address. For each input, the buffer generator 720 reads the data to be transferred from memory 102 via the internal bus 1091 and stores the data to be transferred to the transmit buffer 710. The transmit descriptor 104 is stored in the setting register 730 so that it can be rewritten via the internal bus 109.

[0054] Figure 8 shows an example of a combined packet generated by the combined packet DMAC activation. The data read by the transmit descriptor 104 is stored in the transmit buffer 710, creating the data payload 800. The packet generator 740 creates the request header 600 from the information in the configuration register 730. The packet generator 740 generates an error correction code 801 from the request header 600 and the data payload 800. This completes the creation of the transmit packet.

[0055] Next, the procedure for processing (receiving) combined packets will be explained. Figure 9 shows the internal configuration of the communication interface 103 and the receiving DMA controller 107 involved in packet reception.

[0056] The communication interface 103 includes a configuration register 730, a packet processor 940, a packet detector 970, a receive DMA controller 107, and a transmit DMA controller 106. The receive DMA controller 107 includes a descriptor FIFO 950, a receive buffer 910, and a buffer processor 920.

[0057] The configuration register 730 includes the receive descriptor 115.

[0058] The receive descriptor 105 in the configuration register 730 is transferred to the descriptor FIFO950.

[0059] The packet processor 940 outputs the received packet to the packet classifier 970 and the receive buffer 910. The packet classifier 970 determines whether the received packet is a normal packet or a combined packet based on the packet identifier 603 stored in the request header 600 within the received packet. The receive buffer 910 temporarily stores the received packet.

[0060] The buffer processor 920, if the received packet is a normal packet, reads a set of write address and write data length from the descriptor FIFO 950, reads the received packet from the receive buffer 910, and writes the data payload 800 of the received packet to an area in memory 102 equal to the write data length, starting from the write address.

[0061] If the received packet is a combined packet, the buffer processor 920 reads the sets of write address and write data length combinations from the descriptor FIFO 950 sequentially from the beginning address to the end address. The buffer processor 920 recovers the data of the combined small single packet (data 1, data 2, ... data N) by taking data equal to the write data length from the data payload 800 of the received packet in the receive buffer 910. The buffer processor 920 writes the recovered data of the small single packet to the write address in memory 102.

[0062] As described above, according to this embodiment, by utilizing the packet identifier 603, the transmit descriptor 104, and the receive descriptor 105, combined packets can be exchanged between multiple devices without increasing the data length of the packets.

[0063] Embodiment 2.

[0064] Figure 10 is a diagram illustrating packet forwarding in Embodiment 2. Device A (1100) forwards packet 2 (1101) (ID=0x1), which requests a read of a combined packet, to device B (1110). Device B (1110) sends back combined packet 2 (1111) (ID=0x1) to device A (1100).

[0065] Figure 11 shows the structure of the request header included in packet 2 (1101) that makes a read request. As shown in Figure 11, the packet identifier 603 is defined, which allows for the determination of whether multiple types of combined packets are being forwarded.

[0066] Figure 12 is a diagram showing the configuration of the communication system of Embodiment 2. As shown in Figure 12, multiple transmit descriptors 104 and multiple receive descriptors 105 are stored so that multiple types of combined packets can be created and decomposed.

[0067] Packet 2 (1101) in Figure 10 is a request to device B (1110) to read a combined packet. The request header of packet 2 (1101) includes a combined packet read 606 with packet identifier 603. Packet 2 (1101) is sent to device B (1110).

[0068] When device A(1100) transmits packet 2(1101), the transmitting DMA controller 106 records the value of the Tag field 601 in the request header 600 of packet 2(1101) to be transmitted into the tag management memory 1102. The value of the Tag field 601 of packet 2(1101) is "0x1", which is the ID of packet 2(1101).

[0069] The combined packet 2(1111) transmitted from the completer device B includes a complete header 610. Figure 13 shows a diagram of the complete header 610. The value of the Tag field 612 of combined packet 2(1111) is also "0x1", which is the ID of combined packet 2(1111).

[0070] In general-purpose standards like PCIe, where a read request protocol is provided and the order in which packets are sent from the completer is not in the same order as the requests, a unique value such as a Tag or ID is added to the complete header 600 so that each completion corresponding to a read request can be identified. The value of the Tag field in a request packet, such as packet 2 (1101), and the value of the Tag field in a completion packet, such as combined packet 2 (1111), are set to be the same.

[0071] The tag management memory 1102 uses the value of the Tag field of the transmitted packet as an index and sets a flag indicating whether or not a combined packet was requested. The flag is set to "true" if a combined packet was requested and to "false" if a combined packet was not requested.

[0072] For example, if packet 2 (1101) is a read request for combined packet 2 (1111), the tag management memory 1102 will set the flag "true" for index "0x1".

[0073] In general-purpose standards that utilize tags, such as PCIe or AXI, the bit width of tags is not large (8 bits to 9 bits to 512 types) in order to simplify the circuit and speed up processing. In addition, the tag management memory 1102 can be used as an index so that the received completion tags can be processed without searching for them.

[0074] Embodiment 3. The CPU unit (device A) 100 and CPU unit (device B) 110 of this embodiment have the same configuration as in embodiments 1 and 2. In this embodiment, if CPU unit (device A) 100 and CPU unit (device B) 110 do not receive a communication acknowledgment from a device connected to them by a communication path, they update the transmit descriptor by deleting the data read address and data read length for that device in the transmit descriptor.

[0075] Figure 14 illustrates an example of an abnormality occurring in an FA system. In Figure 14, an abnormality occurs in the communication path 222 or the servo amplifier (B) 231, making communication between the CPU unit (device A) 110 and the servo amplifier (B) 231 impossible. In the FA system of this embodiment, if a partial communication path is disconnected or a device goes down, the CPU unit (device A) 110 detects the abnormality and, while the system is still operating, disconnects the abnormal location from the network (disconnects it) and rebuilds the network, thereby allowing the system to continue operating.

[0076] Figure 15 shows an example of data transfer under normal conditions in Embodiment 3. Under normal conditions, data is transferred from CPU unit (device A) 100 to servo amplifier (A) 230 and servo amplifier (B) 231. Figure 15 shows the data stored in memory 102 in CPU unit (device A) 100, memory 112 in CPU unit (device B) 110, memory 232 in servo amplifier (A) 230, and memory 233 in servo amplifier (B) 231. Data 1 and 2 are sent from CPU unit (device A) 100 to servo amplifier (A) 230 via CPU unit (device B) 110. Data 3 and 4 are sent from CPU unit (device A) 100 to servo amplifier (B) 231 via CPU unit (device B) 110. Servo amplifier (A) 230 controls the motor based on data 1 and 2. Servo amplifier (B) 231 controls the motor based on data 3 and 4.

[0077] Figure 16 shows an example of data transfer when an abnormality occurs in the servo amplifier (B) in Embodiment 3. Under normal conditions, data is transferred from the CPU unit (device A) 100 to the servo amplifier (A) 230. Data 1 and 2 are sent from the CPU unit (device A) 100 to the servo amplifier (A) 230 via the CPU unit (device B) 110. Data 3 and 4 are not transmitted from the CPU unit (device A) 100 to the CPU unit (device B) 110.

[0078] Figure 17 is a flowchart illustrating the communication procedure in Embodiment 3. After the power is turned on, the master station managing the network is determined (step S810), and the network topology is detected and transmission paths are set (steps S811, S812). Subsequently, the master and slave stations are configured (steps S813, S814), transmit descriptors and receive descriptors are generated and stored in the configuration register (step S815). Packets to drive the FA system are transmitted (step S816), and the network status is checked (step S817). If a network anomaly is detected, an anomaly diagnosis is performed to diagnose the anomaly station (steps S818, S819). If an anomaly is detected in the master station, the process returns to step S810, and if an anomaly is detected in the slave station, the process returns to step S811 (step S819). In step S811, the network configuration is reviewed based on the anomaly diagnosis. Subsequently, the master and slave stations are reconfigured (steps S813, S814), and the transmit descriptor and receive descriptor after decoupling are generated and stored in the configuration register (step S815).

[0079] Figures 18(a) to 18(e) show examples of descriptors under normal conditions. Figure 18(a) shows the transmit descriptor of CPU unit (device A) 100, Figure 18(b) shows the receive descriptor of CPU unit (device B) 110, Figure 18(c) shows the transmit descriptor of CPU unit (device B) 110, Figure 18(d) shows the receive descriptor of servo amplifier (A) 230, and Figure 18(e) shows the receive descriptor of servo amplifier (B) 231.

[0080] Figures 19(a) to 19(c) show examples of the descriptors when the servo amplifier (B) 231 malfunctions. Figure 19(a) shows the transmitting descriptor of CPU unit (device A) 100, Figure 19(b) shows the receiving descriptor of CPU unit (device B) 110, and Figure 19(c) shows the transmitting descriptor of CPU unit (device B) 110.

[0081] Figure 20 shows the communication sequence when a malfunction occurs in the servo amplifier (B) 231. Before the malfunction occurred, the setting register of CPU unit (device A) 100 stored the transmit disk reader shown in Figure 18(a), the setting register of CPU unit (device B) 110 stored the receive disk reader shown in Figure 18(b) and the transmit disk reader shown in Figure 18(c), the setting register of servo amplifier (A) 230 stored the receive disk reader shown in Figure 18(d), and the setting register of servo amplifier (B) 231 stored the receive disk reader shown in Figure 18(e).

[0082] First, CPU unit (device A) 100 sends a network connectivity check instruction to CPU unit (device B) 110. Upon receiving the network connectivity check instruction from CPU unit (device A) 100, CPU unit (device B) 110 sends network connectivity check instructions to servo amplifier (A) 230 and servo amplifier (B) 231. Servo amplifier (A) 230 sends a response to CPU unit (device B) 110 indicating that it is functioning normally. Servo amplifier (B) 231 does not send a response to CPU unit (device B) 110 because an abnormality has occurred. CPU unit (device B) 110 sends a response to CPU unit (device A) 100 indicating that servo amplifier (A) 230 is functioning normally, but servo amplifier (B) 231 is malfunctioning.

[0083] When CPU unit (device A) 100 receives a response from CPU unit (device B) 110, it updates its transmit descriptor as shown in Figure 19(a) and writes it to the setting register. This removes the descriptor for servo amplifier (B) from the transmit descriptor. By removing the descriptor for servo amplifier (B), the data for servo amplifier (B) 231 is excluded from the data transferred via DMA between CPU unit (device A) 100 and CPU unit (device B). Furthermore, CPU unit (device A) 100 sends information to CPU unit (device B) 110 that serves as the source for creating the descriptor for CPU unit (device B) 110 (for example, the updated transmit descriptor information).

[0084] When CPU unit (device B) 110 receives information from CPU unit (device A) 100 to be used as the source for creating the descriptor, it updates the received descriptor of CPU unit (device B) 110 as shown in Figure 19(b) and the transmitted descriptor as shown in Figure 19(c), and writes them to the setting register. As a result, the descriptor for servo amplifier (B) is removed from the transmitted descriptor and the received descriptor. CPU unit (device B) 110 notifies CPU unit (device A) that the descriptor update is complete.

[0085] After this, DMA transfer and data transfer to the servo amplifier are performed. The CPU unit (device A) 100 reads data (data 1, 2) from memory based on the transmit disk reader in the setting register. The CPU unit (device A) 100 generates a combined packet and sends it to the CPU unit (device B) 110.

[0086] CPU unit (device B) 110 receives a packet from CPU unit (device A) 100. Based on the receive descriptor in the configuration register, CPU unit (device B) 110 stores the data (data 1, 2) in the packet in memory. Based on the transmit descriptor in the configuration register, CPU unit (device B) 110 reads the data (data 1, 2) from memory. CPU unit (device B) 110 generates a combined packet and transmits it to servo amplifier (A) 230.

[0087] As a result of the above sequence, the CPU unit (device A) 100 can DMA transfer the combined packet, with the data for the servo amplifier (B) excluded, to the CPU unit (device B) 110.

[0088] In Embodiment 3, the CPU unit (device B) 110 updated the receiving descriptor and transmitting descriptor based on descriptor source information from the CPU unit (device A) 100, but it is not limited to this. The CPU unit (device B) 110 may also update the receiving descriptor and transmitting descriptor based on the communication status of the servo amplifier (A) and servo amplifier (B) collected by the CPU unit (device A) 110.

[0089] Embodiment 4. The CPU unit (device A) 100 and CPU unit (device B) 110 in this embodiment have the same configuration as in embodiments 1 to 3. In this embodiment, CPU unit (device A) 100 and CPU unit (device B) 110 update their transmit descriptors when they do not receive a communication acknowledgment from a device, and then update their transmit descriptors again when they receive a communication acknowledgment from that device by storing the data read address and the length of the data to be read back into the transmit descriptor.

[0090] Figure 21 shows an example of an FA system that has recovered from an abnormal state. It illustrates a double-row configuration in which the communication abnormality of the disconnected servo amplifier (B) 231 is recovered and it rejoins the network. After communication of servo amplifier (B) 231 is recovered, when the CPU unit (device A) 100 and CPU unit (device B) 110 perform a network connectivity check, a connectivity confirmation response is returned from servo amplifier (B) to CPU unit (device B) 110.

[0091] As a result, the transmit descriptor of CPU unit (device A) 100 is updated as shown in Figure 18(a), the receive descriptor of CPU unit (device B) 110 is updated as shown in Figure 18(b), and the transmit descriptor of CPU unit (device B) 110 is updated as shown in Figure 18(c). This enables DMA transfer including data (data 3, 4) to servo amplifier (B) 231.

[0092] Modification 1 of Embodiment 4. In this modified example, when CPU unit (device A) 100 and CPU unit (device B) 110 receive a communication acknowledgment from a new device connected to them via a communication channel, they update the transmit descriptor by storing the data read address and data length for that device in the transmit descriptor.

[0093] The various aspects of this disclosure are summarized below as an appendix. (Note 1) The memory where the data is stored, The system includes a communication interface for transmitting the aforementioned data to another device, The aforementioned communication interface is A register that stores a transmit descriptor including the read address of the aforementioned memory and the length of the read data, before the start of communication, A transmit DMA controller reads data from the memory based on the transmit descriptor and writes it to the transmit buffer when transmitting a combined packet. A communication device comprising: a packet generator that generates a transmit packet containing data in the transmit buffer and an identifier indicating whether it is a combined packet or a single packet.

[0094] (Note 2) The packet generator is a communication device as described in Appendix 1, which writes the identifier to the reserved area in the header of the transmitted packet.

[0095] (Note 3) The packet generator is a communication device as described in Appendix 1 or 2, which writes the identifier to an unused bit in the address bits of the header of the transmitted packet.

[0096] (Note 4) The aforementioned identifier is represented by multiple bits, The register is a communication device according to any one of the appendices 1 to 3, which stores a plurality of the transmit descriptors.

[0097] (Note 5) The aforementioned communication interface receives data from other devices. The register stores a receive descriptor, including the write address of the memory and the length of the data to be written, from before the start of communication. The aforementioned communication interface is A packet determination device that determines whether the received packet is the combined packet or the single packet based on the identifier contained in the received packet, A communication device according to any one of the appendices 1 to 4, comprising: a receive DMA controller that temporarily stores the received packet in a receive buffer, and, if the received packet is the combined packet, retrieves data from the received packet stored in the receive buffer based on the receive descriptor and writes it to the memory.

[0098] (Note 6) The communication device according to Appendix 5, comprising a tag management memory that stores the correspondence between the value of a tag in the header of the transmitted packet and a flag indicating whether the transmitted packet is the single packet or the combined packet.

[0099] (Note 7) The aforementioned identifier is represented by multiple bits, The register is a communication device according to appendix 5 or 6, which stores a plurality of the received descriptors.

[0100] (Note 8) The communication device described in any one of the appendices 1 to 7, wherein if the communication device does not receive a communication acknowledgment from a device connected to the communication device by a communication path, the communication device updates the transmission descriptor by deleting the data read address and data read length for the device in the transmission descriptor.

[0101] (Note 9) The communication device described in Appendix 8 updates the transmission descriptor again after updating the transmission descriptor and receiving a communication acknowledgment from the device by storing the data read address and the length of the data to be read back into the transmission descriptor.

[0102] (Note 10) The communication device described in any one of the appendices 1 to 9, wherein when the communication device receives a communication acknowledgment from a new device connected to the communication device by a communication path, it updates the transmission disk printer by storing the data read address and the length of the data to be read to the device in the transmission disk printer.

[0103] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the present invention is indicated by the claims rather than by the foregoing description, and all modifications within the meaning and scope equivalent to the claims are intended to be included. [Explanation of Symbols]

[0104] 100,110 Device (unit), 101,111 Processor, 102,112,232 Memory, 103,113 Communication interface, 104,114 Transmit descriptor, 105,115 Receive descriptor, 106,116 Transmit DMA controller, 107,117 Receive DMA controller, 109,1091 Internal bus, 120,222 Communication channel, 230 Servo amplifier, 240 Motor, 710 Transmit buffer, 720 Buffer generator, 730 Configuration register, 740 Packet generator, 910 Receive buffer, 920 Buffer processor, 940 Packet processor, 970 Packet detector, 1102 Tag management memory, 750,950 Descriptor FIFO.

Claims

1. The memory where the data is stored, The system includes a communication interface for transmitting the aforementioned data to another device, The aforementioned communication interface is A register that stores a transmit descriptor including the read address of the aforementioned memory and the length of the read data, before the start of communication, A transmit DMA controller reads data from the memory based on the transmit descriptor and writes it to the transmit buffer when transmitting a combined packet, A communication device comprising: a packet generator that generates a transmit packet containing data in the transmit buffer and an identifier indicating whether it is a combined packet or a single packet.

2. The communication device according to claim 1, wherein the packet generator writes the identifier to the reserved area in the header of the transmitted packet.

3. The communication device according to claim 1, wherein the packet generator writes the identifier to an unused bit in the address bits of the header of the transmitted packet.

4. The aforementioned identifier is represented by multiple bits, The communication device according to claim 1, wherein the register stores a plurality of the transmit descriptors.

5. The aforementioned communication interface receives data from other devices. The register stores a receive descriptor, including the write address of the memory and the length of the data to be written, from before the start of communication. The aforementioned communication interface is A packet determination device that determines whether the received packet is the combined packet or the single packet based on the identifier contained in the received packet, The communication device according to claim 1, further comprising: a receive DMA controller that temporarily stores the received packet in a receive buffer, and, if the received packet is the combined packet, retrieves data from the received packet stored in the receive buffer based on the receive descriptor and writes it to the memory.

6. The communication device according to claim 5, further comprising a tag management memory that stores a correspondence between the value of a tag in the header of the transmitted packet and a flag indicating that the transmitted packet is the single packet or the combined packet.

7. The aforementioned identifier is represented by multiple bits, The communication device according to claim 6, wherein the register stores a plurality of the received descriptors.

8. The communication device according to claim 1, wherein if the communication device does not receive a communication acknowledgment from a device connected to the communication device by a communication path, the communication device updates the transmission descriptor by deleting the data read address and data read length for the device in the transmission descriptor.

9. The communication device according to claim 8, wherein, after updating the transmitting disk, when it receives a communication acknowledgment from the device, it updates the transmitting disk again by storing the data read address and the length of the data to be read back into the transmitting disk.

10. The communication device according to claim 1, wherein when the communication device receives a communication acknowledgment from a new device connected to the communication device by a communication path, it updates the transmission disk printer by storing the data read address and the length of the data to be read to the device in the transmission disk printer.

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