Address determination circuit and semiconductor device

Abstract

This invention provides an address determination circuit and semiconductor device that improve the accuracy of address determination with a simple circuit configuration. [Solution] The address determination circuit 10 is a serial communication address determination circuit, and includes an SA terminal short-circuit determination circuit 40 that determines the SA signal is an SCL signal if the condition that the SDA signal is at the first level when the SA signal rises and the SDA signal is at the second level when the SA signal falls (hereinafter, first proposition) is false, and the condition that the SCL signal is at the first level when the SA signal rises and the SCL signal is at the second level when the SA signal falls (hereinafter, second proposition) is false, and determines the SA signal is an SDA signal if the condition that the SCL signal is at the first level when the SA signal rises and the SCL signal is at the second level when the SA signal falls (hereinafter, second proposition) is false, and determines the power supply voltage corresponding to the voltage of the SA signal when both the first and second propositions are true.

Description

TECHNICAL FIELD

[0001] The present invention relates to an address determination circuit and a semiconductor device.

BACKGROUND ART

[0002] A plurality of modules inside and outside a computer may be connected via a common path for data exchange for use (bus connection). In such a bus connection, a unique address is set for each module, and a master, which is a control module, transmits a command including the address of a slave, which is a controlled module. On the slave side, the received controlled address is compared with its own preset address, and a response is made only to a command whose controlled address matches the own address.

[0003] In recent years, communication systems may use an I 2 C (Inter Integrated Circuit) serial transfer bus provided with two signal lines for a serial data signal (SDA signal) and a serial clock signal (SCL signal) that comply with communication protocols.

[0004] I 2 When it is desired to use a plurality of modules that function as slaves in C communication or the like, addresses must be individually set. As a method for a user to easily set addresses, a method is used in which individual address input terminals (SA terminals) are provided, and an address is selected according to the input level of the SA terminal. The method of detecting two values by using the SA terminal as a digital input is the simplest, but in order to connect more modules to the communication bus, it is necessary to increase the number of SA terminals, and in products that frequently use packages with a small number of terminals, it is difficult to dedicate many terminals to address input.

[0005] Accordingly, from the viewpoint of enabling modules connected to a bus to be applied to packages with a small number of terminals, various techniques capable of setting the address of a slave module with a simple circuit configuration have been studied (for example, refer to Patent Document 1).

PRIOR ART DOCUMENTS

[0006] [Patent Document 1] Japanese Patent Publication No. 2010-212989 [Overview of the project] [Problems that the invention aims to solve]

[0007] The conventional address determination circuits and semiconductor devices described above can sometimes misidentify addresses, indicating room for improvement.

[0008] One aspect of the present invention aims to provide an address determination circuit and a semiconductor device that improve the accuracy of address determination with a simple circuit configuration. [Means for solving the problem]

[0009] At least one aspect of the present invention is a circuit for determining the address of serial communication that transmits and receives a start signal, a data signal, and an end signal over a communication line, comprising: an address selection signal input terminal; a serial data input terminal; a serial clock input terminal; a first determination signal based on the result of latching the level of the serial data signal supplied to the serial data input terminal at a first edge timing when the address selection signal supplied to the address selection signal input terminal transitions from a first power supply voltage to a second power supply voltage, and at a second edge timing when the address selection signal transitions from the second power supply voltage to the first power supply voltage; and at the first edge timing and the second edge timing, the serial The address selection signal determination circuit includes an address selection signal determination circuit that receives a second determination signal based on the result of latching the level of a serial clock signal supplied to a serial clock input terminal, wherein the address selection signal determination circuit determines that the address selection signal is the serial clock signal when the first determination signal is at a signal level corresponding to false, determines that the address selection signal is the serial data signal when the second determination signal is at a signal level corresponding to false, and determines that the address selection signal is either the first power supply voltage or the second power supply voltage based on the voltage of the address selection signal when both the first and second determination signals are at signal levels corresponding to true. [Effects of the Invention]

[0010] According to one aspect of the present invention, the accuracy of address determination can be improved with a simple circuit configuration. [Brief explanation of the drawing]

[0011] [Figure 1] This is a schematic diagram showing an example configuration of the address determination circuit and semiconductor device according to this embodiment. [Figure 2] This circuit diagram shows an example configuration of the SDA short-circuit detection signal generation circuit in the address determination circuit according to this embodiment. [Figure 3] This circuit diagram shows an example configuration of the SCL short-circuit detection signal generation circuit in the address determination circuit according to this embodiment. [Figure 4] In the address determination circuit according to this embodiment, (A) is a timing chart showing the case when the SA terminal is shorted to the SCL line, and (B) is a timing chart showing the case when the SA terminal is shorted to the SDA line. [Figure 5] This is a truth table showing the operation of the SA terminal short-circuit detection circuit included in the address determination circuit according to this embodiment. [Figure 6] This is a schematic diagram showing an example configuration of an address determination circuit related to a reference example. [Figure 7] (A) and (B) are timing charts showing the first and second examples of address misdetermination in the address determination circuit related to the reference example, respectively. [Figure 8] This is a schematic diagram showing a first modified example (second configuration example) of the address determination circuit and semiconductor device according to this embodiment. [Figure 9] This is a circuit diagram showing a first modified example (second configuration example) of the SDA short-circuit detection signal generation circuit in the address determination circuit according to this embodiment. [Figure 10] This is a circuit diagram showing a first modified example (second configuration example) of the SCL short-circuit detection signal generation circuit in the address determination circuit according to this embodiment. [Figure 11] This is a circuit diagram showing a second modified example (third configuration example) of the SDA short-circuit detection signal generation circuit in the address determination circuit according to this embodiment. [Figure 12] This is a schematic diagram showing a second modified example (third configuration example) of the address determination circuit and semiconductor device according to this embodiment. [Figure 13] This is a circuit diagram showing a third modified example (fourth configuration example) of the SDA short-circuit detection signal generation circuit in the address determination circuit according to this embodiment. [Figure 14] This is a circuit diagram showing a third modified example (fourth configuration example) of the SCL short-circuit detection signal generation circuit in the address determination circuit according to this embodiment. [Figure 15] This is a timing chart showing the case where the SA terminal is shorted to the SCL line in the address determination circuit according to the second modified example. [Mode for Carrying Out the Invention]

[0012] Hereinafter, an address determination circuit and a semiconductor device according to embodiments of the present invention will be described with reference to the drawings. In the present embodiment, "high level" and "low level" in a bit signal are synonymous with "1" and "0" of the bit signal, respectively.

[0013] Figure 1 is a schematic diagram showing a configuration example of an address determination circuit 10 which is an example of the address determination circuit according to the present embodiment, and a semiconductor device 50 which is an example of the semiconductor device according to the present embodiment.

[0014] The address determination circuit 10 is a circuit that determines an address for serial communication in which a transmission start signal, a data signal, and a transmission end signal are transmitted and received via a communication line, and includes, for example, an SDA terminal 11, an SA terminal 12, an SCL terminal 13, an output terminal 14, a delay element 16 that delays an input signal by a predetermined time and outputs the delayed signal, an SDA short determination signal generation circuit 20, an SCL short determination signal generation circuit 30, and an SA terminal short determination circuit 40.

[0015] The SDA terminal 11 serving as a serial data input terminal is connected to a serial data line (hereinafter referred to as "SDA line", not shown) to which a serial data signal (hereinafter referred to as "SDA signal") is supplied.

[0016] The SCL terminal 13 serving as a serial clock input terminal is connected to a serial clock line (hereinafter referred to as "SCL line", not shown) to which a serial clock signal (hereinafter referred to as "SCL signal") is supplied.

[0017] The SA terminal 12, which serves as an address selection signal input terminal, is supplied with an address selection signal (hereinafter referred to as the "SA signal") to which four different addresses are set, and is selectively connected to four power sources. The four locations to which the SA terminal 12 is connected, that is, the locations to which the SA terminal 12 is shorted, are the SDA line, the SCL line, the VSS line which supplies the voltage Vss as the first power supply voltage, and the VDD line which supplies the voltage Vdd as the second power supply voltage.

[0018] The SDA short-circuit detection signal generation circuit 20 is configured to generate a signal that includes a signal level corresponding to the result of determining the condition for determining whether the short-circuit target of the SA terminal 12 is not the SDA line, based on the SDA signal and the SA signal SA_DLY (see Figure 4), which is an SA signal delayed by a predetermined time. The SCL short-circuit detection signal generation circuit 30 is configured to generate a signal that includes a signal level corresponding to the result of determining the condition for determining whether the short-circuit target of the SA terminal 12 is not the SCL line, based on the SCL signal and the SA_DLY (see Figure 4).

[0019] The SA terminal short detection circuit 40, which serves as an address selection signal determination circuit, includes a first input node that receives an SDA short detection signal, a second input node that receives an SA signal, a third input node that receives an SCL short detection signal, and an output node that outputs a 2-bit signal corresponding to the connection destination of the SA terminal 12.

[0020] The SA terminal short detection circuit 40 determines which terminal is shorted by the SA terminal 12 based on the SDA short detection signal, SA signal, and SCL short detection signal supplied from the first node to the third node, and outputs a 2-bit signal corresponding to the determined shorted terminal, i.e., the connection destination. The 2-bit signal output from the SA terminal short detection circuit 40 is supplied to the output terminal 14, and from the output terminal 14 it is supplied to a subsequent circuit (not shown).

[0021] Here, the principle of address determination in the address determination circuit 10 will be explained. The address determination circuit 10 compares the SA signal supplied from the SA terminal 12 with the signal SA_DLY, which is the SA signal delayed by a predetermined time to ensure the setup / hold time of the FF circuit. By determining the contrapositive of a proposition with clear truth value between the address selection signal and the signal SA_DLY, it is determined that the address selection signal is neither an SCL signal nor an SDA signal.

[0022] To explain in more detail, if the SA signal is the SCL signal, then the SCL signal is "1" when the SA_DLY signal is rising and "0" when the SA_DLY signal is falling. Similarly, if the address selection signal is the SDA signal, then the SDA signal is "1" when the SA_DLY signal is rising and "0" when the SA_DLY signal is falling.

[0023] In short, the following two propositions Proposition 1: "If the address selection signal is the SCL signal, then the SCL signal is '1' when the SA_DLY signal is rising edge, and '0' when the SA_DLY signal is falling edge." The second proposition states: "If the address selection signal is the SDA signal, then the SDA signal is '1' when the SA_DLY signal is rising edge and '0' when the SA_DLY signal is falling edge." It is clear that both statements are true.

[0024] In the address determination circuit 10, the third proposition is the contrapositive of the first proposition, and the fourth proposition is the contrapositive of the second proposition, that is, Third Proposition: "If the SCL signal is not '1' when the SA_DLY signal is rising edge, and not '0' when the SA_DLY signal is falling edge, then the address selection signal is not the SCL signal." Proposition 4: "If the SDA signal is not '1' when the SA_DLY signal is rising edge and not '0' when the SA_DLY signal is falling edge, then the address selection signal is not the SDA signal." By utilizing the fact that both conditions are true, it is determined whether the address selection signal is neither an SCL signal nor an SDA signal.

[0025] Next, we will describe an example configuration of the SDA short-circuit detection signal generation circuit 20 as the first signal generation circuit and the SCL short-circuit detection signal generation circuit 30 as the second signal generation circuit.

[0026] Figures 2 and 3 are circuit diagrams showing example configurations of the SDA short-circuit detection signal generation circuit 20 and the SCL short-circuit detection signal generation circuit 30, respectively.

[0027] The SDA short-circuit detection signal generation circuit 20 includes, for example, a D flip-flop circuit (hereinafter referred to as "D-FF circuit") 210 that operates on the rising edge of the clock and retains information until the next rising edge of the clock, an AND circuit 211, a D-FF circuit 220, an OR circuit 221, inverters 222 and 223, and an AND circuit 25. The SDA short-circuit detection signal generation circuit 20 also includes a first input node 21 connected to the SDA terminal 11, a second input node 22 connected to the output node of the delay element 16, and an output node 23 connected to the output terminal 253 of the AND circuit 25.

[0028] The AND circuit 211 has a first input terminal connected to the output terminal Q of the D-FF circuit 210, a second input terminal connected to the first input node 21, and an output terminal that calculates the logical AND of the output signal of the D-FF circuit 210 and the SDA signal and outputs an output signal corresponding to the calculation result.

[0029] The D-FF circuit 210 has an input terminal D that receives the output signal from the AND circuit 211, a clock input terminal CK that receives the signal SA_DLY, and an output terminal Q, and its initial value is 1.

[0030] The D-FF circuit 220 has an input terminal D that receives the output signal from the OR circuit 221, a clock input terminal CK that receives the signal SA_DLY inverted by the inverter 222, and an output terminal Q, and its initial value is 0.

[0031] The OR circuit 221 has a first input terminal connected to the output terminal Q of the D-FF circuit 220, a second input terminal connected to the first input node 21, and an output terminal that calculates the logical OR of the output signal of the D-FF circuit 220 and the SDA signal and outputs an output signal corresponding to the calculation result.

[0032] The AND circuit 25 has a first input terminal 251 connected to the output terminal of the D-FF circuit 210, a second input terminal 252 connected to the output terminal of the D-FF circuit 220 via the inverter 223, and an output terminal 253. The AND circuit 25 supplies an SDA short-circuit determination signal, which is a first determination signal containing a signal level corresponding to the result of the logical AND operation of the signals input to the first input terminal 251 and the second input terminal 252, to the output node 23 from the output terminal 253.

[0033] Here, the AND gate 211 and the D-FF gate 210 constitute the first logic circuit in the SDA short-circuit detection signal generation circuit 20. The OR gate 221 and the D-FF gate 220 constitute the second logic circuit in the SDA short-circuit detection signal generation circuit 20. Here, the output signal of the D-FF gate 210 corresponds to the output signal of the first logic circuit, and the output signal of the D-FF gate 220 corresponds to the output signal of the second logic circuit.

[0034] The SDA short-circuit detection signal generation circuit 20 determines that the signal level of the SDA signal is not "1", i.e., "0", when the voltage of the signal SA_DLY, which is obtained by delaying the SA signal for a predetermined time using the AND circuit 211 and the D-FF circuit 210, rises from voltage Vss to voltage Vdd, and outputs a signal including the signal level corresponding to that determination result to the first input terminal 251 of the AND circuit 25.

[0035] When the AND gate 211's calculation result is "false," i.e., "0," the D-FF circuit 210 receives an input signal with a signal level of "0" at input terminal D, and therefore outputs an output signal with a signal level of "0." Once the D-FF circuit 210 outputs an output signal with a signal level of "0," the output signal of the D-FF circuit 210 remains fixed at a signal level of "0" thereafter.

[0036] Furthermore, the SDA short-circuit detection signal generation circuit 20 determines that the signal level of the SDA signal is not "0", i.e., "1", when the voltage of the signal SA_DLY, which is obtained by delaying the SA signal for a predetermined time using the OR circuit 221 and the D-FF circuit 220, falls from voltage Vdd to voltage Vss. The inverter 223 inverts the signal containing the signal level corresponding to the determination result and outputs it to the second input terminal 252 of the AND circuit 25.

[0037] When the OR gate 221 calculates to "true," i.e., "1," the D-FF circuit 220 receives an input signal of signal level "1" at input terminal D, and outputs an output signal of signal level "1." Once the D-FF circuit 220 outputs an output signal of signal level "1," the output signal of the D-FF circuit 220 remains fixed at signal level "1" thereafter.

[0038] The AND circuit 25 outputs an SDA short-circuit determination signal from the output terminal 253, which includes a signal level corresponding to the result of the logical AND operation of the signals input to the first input terminal 251 and the second input terminal 252. The output signal of the AND circuit 25 indicates the truth value determination result of whether the first condition, "the SDA signal is '1' when the SA_DLY signal is rising edge and the SDA signal is '0' when the SA_DLY signal is falling edge," is met (true) or not met (false). The signal levels of "0" and "1" in the output signal of the AND circuit 25 correspond to the first condition not being met (false) and being met (true), respectively.

[0039] The SCL short-circuit detection signal generation circuit 30 includes, for example, a D flip-flop circuit (hereinafter referred to as "D-FF circuit") 310 that operates at the rising edge of the clock, an AND circuit 311, a D-FF circuit 320, an OR circuit 321, inverters 322 and 323, and an AND circuit 35. The SCL short-circuit detection signal generation circuit 30 also includes a first input node 31 connected to the SCL terminal 13, a second input node 32 connected to the output node of the delay element 16, and an output node 33 connected to the output terminal 353 of the AND circuit 35.

[0040] The AND circuit 311 has a first input terminal connected to the output terminal Q of the D-FF circuit 310, a second input terminal connected to the first input node 31, and an output terminal that calculates the logical AND of the output signal of the D-FF circuit 310 and the SCL signal and outputs an output signal corresponding to the calculation result.

[0041] The D-FF circuit 310 has an input terminal D that receives the output signal from the AND circuit 311, a clock input terminal CK that receives the signal SA_DLY, and an output terminal Q.

[0042] The D-FF circuit 320 has an input terminal D that receives the output signal from the OR circuit 321, a clock input terminal CK that receives the signal SA_DLY inverted by the inverter 322, and an output terminal Q.

[0043] The OR circuit 321 has a first input terminal connected to the output terminal Q of the D-FF circuit 320, a second input terminal connected to the first input node 31, and an output terminal that calculates the logical OR of the output signal of the D-FF circuit 320 and the SCL signal and outputs an output signal corresponding to the calculation result.

[0044] The AND circuit 35 has a first input terminal 351 connected to the output terminal of the D-FF circuit 310, a second input terminal 352 connected to the output terminal of the D-FF circuit 320 via an inverter 323, and an output terminal 353. The AND circuit 35 supplies an SCL short-circuit determination signal, which is a second determination signal containing a signal level corresponding to the result of the logical AND operation of the signals input to the first input terminal 351 and the second input terminal 352, to the output node 33 from the output terminal 353.

[0045] Here, the AND circuit 311 and the D-FF circuit 310 constitute the first logic circuit in the SCL short-circuit detection signal generation circuit 30. The OR circuit 321 and the D-FF circuit 320 constitute the second logic circuit in the SCL short-circuit detection signal generation circuit 30. Here, the output signal of the D-FF circuit 310 corresponds to the output signal of the first logic circuit, and the output signal of the D-FF circuit 320 corresponds to the output signal of the second logic circuit.

[0046] The SCL short-circuit detection signal generation circuit 30 determines that the signal level of the SCL signal is not "1", i.e., "0", when the voltage of the signal SA_DLY, which is obtained by delaying the SA signal for a predetermined time using the AND circuit 311 and the D-FF circuit 310, rises from voltage Vss to voltage Vdd, and outputs a signal including the signal level corresponding to that determination result to the first input terminal 351 of the AND circuit 35.

[0047] When the AND gate 311's calculation result is "false," i.e., "0," the D-FF circuit 310 receives an input signal with a signal level of "0" at input terminal D, and outputs an output signal with a signal level of "0." Subsequently, the output signal of the D-FF circuit 310 is fixed at a signal level of "0."

[0048] Furthermore, the SCL short-circuit detection signal generation circuit 30 determines that the signal level of the SCL signal is not "0", i.e., "1", when the voltage of the signal SA_DLY, which is obtained by delaying the SA signal for a predetermined time using the OR circuit 321 and the D-FF circuit 320, falls from voltage Vdd to voltage Vss. The inverter 323 inverts the signal containing the signal level corresponding to the determination result and outputs it to the second input terminal 352 of the AND circuit 35.

[0049] When the OR gate 321 calculates to "true," i.e., "1," the D-FF circuit 320 receives an input signal of signal level "1" at input terminal D, and outputs an output signal of signal level "1." Subsequently, the output signal of the D-FF circuit 320 is fixed at signal level "1."

[0050] The AND circuit 35 outputs an SCL short-circuit determination signal from the output terminal 353, which includes a signal level corresponding to the result of the logical AND operation of the signals input to the first input terminal 351 and the second input terminal 352. The output signal of the AND circuit 35 indicates the truth value determination result of whether the second condition, "SCL signal is '1' when signal SA_DLY is rising edge and SCL signal is '0' when signal SA_DLY is falling edge," is met (true) or not met (false). The signal levels of "0" and "1" in the output signal of the AND circuit 35 correspond to the second condition not being met (false) and being met (true), respectively.

[0051] Next, regarding the address determination operation of the address determination circuit 10, I 2 This explanation will use the case of C communication as an example.

[0052] Figure 4(A) is a timing chart showing the case where SA terminal 12 is shorted to the SCL line (not shown), and Figure 4(B) is a timing chart showing the case where SA terminal 12 is shorted to the SDA line (not shown).

[0053] In the address determination circuit 10, as described above, the SDA short-circuit determination signal generation circuit 20 (see Figure 2) determines whether the first condition, "the SDA signal is '1' when the SA_DLY signal is rising and the SDA signal is '0' when the SA_DLY signal is falling", is met (true) or not (false), and the SCL short-circuit determination signal generation circuit 30 (see Figure 3) determines whether the second condition, "the SCL signal is '1' when the SA_DLY signal is rising and the SCL signal is '0' when the SA_DLY signal is falling", is met (true) or not (false).

[0054] When the SA terminal 12 is shorted to the SCL line (not shown) (see Figure 4(A)), according to Figure 4(A), the SCL signal is "1" on the rising edge of signal SA_DLY and "0" on the falling edge of signal SA_DLY for any pulse. On the other hand, the SDA signal is "0" on the rising edge of the second pulse of signal SA_DLY (indicated by the downward dashed arrow) and "0" on the falling edge of signal SA_DLY, according to the operation of the SDA short-circuit determination signal generation circuit 20 described above. Therefore, the fourth proposition is true, and it is determined that the address selection signal is not the SDA signal. Furthermore, when the SA terminal 12 is shorted to the VDD line or VSS line, the address selection signal remains "1" or "0" and there is no change in the signal level. Therefore, if the signal level of signal SA_DLY is changing, it is determined that the address selection signal is the remaining SCL signal.

[0055] When the SA terminal 12 is shorted to the SDA line (not shown) (see Figure 4(B)), according to Figure 4(B), the SDA signal is "1" on the rising edge of the SA_DLY signal and "0" on the falling edge of the SA_DLY signal for any pulse. On the other hand, the SCL signal is "0" on the rising edge of the SA_DLY pulse (indicated by the downward dashed arrow) and "0" on the falling edge of the SA_DLY signal, according to the operation of the SCL short-circuit determination signal generation circuit 30 described above. Therefore, the third proposition is true, and it is determined that the address selection signal is not the SCL signal. Furthermore, when the SA terminal 12 is shorted to the VDD line or VSS line, the address selection signal remains "1" or "0" and there is no change in the signal level. Therefore, if the signal level of the SA_DLY signal is changing, it is determined that the address selection signal is the remaining SDA signal.

[0056] Figure 5 is a truth table showing the operation of the SA terminal short detection circuit 40 provided in the address detection circuit 10. In Figure 5, the SDA short detection signal and the SCL short detection signal are denoted as sa_short_sda and sa_short_scl, respectively, and the detection points that serve as the basis for determining the short-circuit partner (connection destination) of the SA terminal 12 are indicated in uppercase letters.

[0057] The SA terminal short detection circuit 40 determines the four possible short-circuit partners of the SA terminal 12 based on the SDA short detection signal (sa_short_sda) supplied to the first input node from the SDA short detection signal generation circuit 20, the address selection signal supplied to the second input node from the SA terminal 12, and the SCL short detection signal (sa_short_scl) supplied to the third input node from the SCL short detection signal generation circuit 30.

[0058] To explain in more detail, the SA terminal short-circuit detection circuit 40 determines that there is no short circuit with the SDA line, i.e., a short circuit with the SCL line, if the result of the first condition indicated by the SDA short-circuit detection signal (sa_short_sda) is "FALSE". Also, if the result of the second condition indicated by the SCL short-circuit detection signal (sa_short_scl) is "FALSE", it determines that there is no short circuit with the SCL line, i.e., a short circuit with the SDA line.

[0059] The SA terminal short detection circuit 40 cannot make a definitive determination using only the SDA short detection signal (sa_short_sda) and the SCL short detection signal (sa_short_scl) if the result of both the first and second conditions is "true". However, since it is clear that the short-circuited object of the SA terminal 12 is not the SDA line or the SCL line, if the voltage of the SA terminal 12 is known to be either voltage Vdd or voltage Vss, it is possible to determine whether it is shorted to the VDD line or the VSS line.

[0060] Therefore, the SA terminal short detection circuit 40 determines that there is a short to the VDD line if the voltage of the SA terminal 12 is at a high level corresponding to voltage Vdd, and determines that there is a short to the VSS line if the voltage of the SA terminal 12 is at a low level corresponding to voltage Vss. The SA terminal short detection circuit 40 outputs a signal corresponding to the above-mentioned determination result to the outside from the output terminal 14 in 2 bits (00b, 01b, 10b, 11b). In the example shown in Figure 5, 00b corresponds to the VSS line, 01b to the VDD line, 10b to the SDA line, and 11b to the SCL line.

[0061] Next, the accuracy of address determination in the address determination circuit according to this embodiment will be explained using an example of a conventional address determination circuit as a reference.

[0062] Figure 6 is a schematic diagram showing an example configuration of an address determination circuit 500, which is an address determination circuit related to a reference example.

[0063] The address determination circuit 500 is a circuit corresponding to Figure 4 described in Patent Document 1. The address determination circuit 500 comprises an EXOR circuit 512, an OR circuit 513, a D-FF circuit 511, and an output decoder 530. The EXOR circuit 512 receives the SDA signal and the SA signal as inputs, calculates their exclusive OR, and outputs it to the OR circuit 513. The OR circuit 513 receives the output signal of the D-FF circuit 511 and the output signal of the EXOR circuit 512 as inputs, calculates their logical OR, and outputs it to the D-FF circuit 511.

[0064] The output signal of the OR circuit 513 is input to the input terminal D of the D-FF circuit 511, and the SCL signal is input as a clock signal to the clock input terminal. When the D-FF circuit 511 receives a start signal at the CLR terminal, it is initialized (cleared). In addition, the address determination circuit 500 pre-processes the SA signal by shifting its timing forward or backward to ensure the setup / hold time of the D-FF circuit 511 before supplying it to the D-FF circuit 511.

[0065] Figures 7(A) and 7(B) are I 2 These are timing charts illustrating examples of data transmission according to the C communication protocol, showing the first and second examples of address misjudgment by the address determination circuit 500, respectively.

[0066] Figure 7(A) shows, from top to bottom, the waveforms of the SCL signal, the SDA signal, and the SA signal when the SA signal is the SCL signal, but with its timing slightly earlier than the SCL and SDA signals. In each signal waveform, a higher signal level is represented as "1" and a lower signal level as "0".

[0067] As shown in Figure 7(A), the SDA signal transitions from "0" to "1" after the start condition is reached, and then remains "1". According to the timing chart shown in Figure 7(A), at time t1, which is the first rising edge of the SCL signal after the start condition, the SDA signal is "1" and the SA signal is "1". When the address determination circuit 500 receives an SDA signal of "1" and an SA signal of "1", the output signal of the EXOR circuit 512 becomes "0", the output signal of the OR circuit 513 becomes "0", and the output signal sda_b of the D-FF circuit 511 becomes "0".

[0068] In this case, the output decoder 530 determines that it has the highest priority (top in the diagram) and that the short-circuit target of the SA terminal is the SDA line. As mentioned above, the first example shown in Figure 7(A) is when the SA signal is the SCL signal, but the address determination circuit 500 mistakenly determines that the SA signal is the SDA signal.

[0069] On the other hand, the address determination circuit 10 detects the SDA signal "1" at the falling edge of the SA signal at time t2, and determines that the first condition "the SDA signal is "1" when the SA_DLY signal is rising and the SDA signal is "0" when the SA_DLY signal is falling" is not met. Therefore, based on the first condition being FALSE, it determines that the SA terminal 12 is shorted to the SCL line. In other words, the address determination circuit 10 does not make an incorrect determination like the address determination circuit 500, even when the timing progresses according to the timing shown in Figure 7(A).

[0070] Figure 7(B) shows, from top to bottom, the waveforms of the SCL signal, the SDA signal, and the SA signal when the SA signal is the SCL signal, but with its timing slightly delayed relative to the SCL and SDA signals. In each signal waveform, a higher signal level is represented as "1" and a lower signal level as "0".

[0071] As shown in Figure 7(B), the SDA signal remains "0" after transitioning to the start condition. According to the timing chart shown in Figure 7(B), at time t1, which is the first rising edge of the SCL signal after the start condition, the SDA signal is "0" and the SA signal is "0". When the address determination circuit 500 receives the SDA signal as "0" and the SA signal as "0", the output signal of the EXOR circuit 512 becomes "0", the output signal of the OR circuit 513 becomes "0", and the output signal sda_b of the D-FF circuit 511 becomes "0".

[0072] Even at the timing shown in Figure 7(B), just like at the timing shown in Figure 7(A) above, the output decoder 530 incorrectly determines that the SA terminal has the highest priority (top of the diagram) and mistakenly identifies the SDA line as the short-circuit target.

[0073] On the other hand, the address determination circuit 10 detects the SDA signal "0" at the rising edge of the SA signal at time t3, and determines that the first condition "the SDA signal is "1" at the rising edge of the SA_DLY signal and the SDA signal is "0" at the falling edge of the SA_DLY signal" is not met. Therefore, based on the first condition being FALSE, it determines that the SA terminal 12 is shorted to the SCL line. In other words, the address determination circuit 10 does not make an incorrect determination like the address determination circuit 500, even when the timing progresses according to the timing shown in Figure 7(B).

[0074] Next, I will briefly explain the countermeasures for avoiding Metastable in the address determination circuit 10. In the address determination circuit 10, the four possible short partners of the SA terminal 12 are determined based on the truth value determination of the SDA short determination signal and the SCL short determination signal. If Metastable occurs and the SDA short determination signal or SCL short determination signal is incorrectly judged as "FALSE", the short partner of the SA terminal 12 will be incorrectly determined. However, the address determination circuit 10 has measures in place to avoid Metastable or to prevent a final incorrect determination even if Metastable occurs. Specifically, these measures are as follows.

[0075] If the SA terminal 12 is shorted to the VDD line or VSS line, the SDA short detection signal or the SCL short detection signal remains at its initial value, so a false short detection of the SA terminal 12 due to metastable events cannot occur. Metastable events occur when the setup / hold time of the FF circuit is insufficient for the rising or falling edge of the signal waveform. However, the address detection circuit 10 takes measures to prevent metastable events by inserting noise filters into the SDA terminal 11 and SCL terminal 13, and by supplying the SA_DLY signal (a delayed SA signal) to the D-FF circuits 210, 220, 310, and 320, so that the setup / hold time of the FF circuit is not insufficient. Therefore, the SDA short detection signal generation circuit 20 and the SCL short detection signal generation circuit 30 are designed to prevent metastable events.

[0076] It should be noted that the present invention is not limited to the embodiments described above, and in practice, it can be implemented in various forms other than those described above, and various omissions, additions, substitutions, or modifications can be made without departing from the spirit of the invention. Next, several modifications of the address determination circuit and semiconductor device will be described from among several possible forms.

[0077] Figure 8 is a schematic diagram showing the configuration of the address determination circuit 10A and semiconductor device 50A, which are first modified examples (second configuration examples) of the address determination circuit and semiconductor device according to this embodiment. Figures 9 and 10 are circuit diagrams showing first modified examples (second configuration examples) of the SDA short-circuit detection signal generation circuit and the SCL short-circuit detection signal generation circuit, respectively, in the address determination circuit according to this embodiment. Figure 11 is a circuit diagram showing a second modified example (third configuration example) of the SDA short-circuit detection signal generation circuit in the address determination circuit according to this embodiment.

[0078] The address determination circuit 10A is configured to generate an SDA short-circuit determination signal and an SCL short-circuit determination signal using an SA signal that is advanced by a predetermined time relative to the SDA signal and the SCL signal, in relation to the address determination circuit 10. In other words, in the address determination circuit 10A, the forward and backward relationship (advance and delay) between the SDA signal and the SA signal, and the forward and backward relationship (advance and delay) between the SCL signal and the SA signal are reversed relative to the address determination circuit 10.

[0079] The address determination circuit 10A and the semiconductor device 50A differ from the address determination circuit 10 in that they have an SDA short-circuit detection signal generation circuit 20A instead of the SDA short-circuit detection signal generation circuit 20, and an SCL short-circuit detection signal generation circuit 30A instead of the SCL short-circuit detection signal generation circuit 30, and in the location where the delay element 16 is connected, but otherwise they are substantially the same. In the address determination circuit 10A, the delay element 16 is connected between the SDA terminal 11 and the SDA short-circuit detection signal generation circuit 20A, and between the SCL terminal 13 and the SCL short-circuit detection signal generation circuit 30A, while the delay element 16 is not connected between the SA terminal 12 and the SDA short-circuit detection signal generation circuit 20A and the SCL short-circuit detection signal generation circuit 30A.

[0080] The SDA short-circuit detection signal generation circuit 20A differs from the SDA short-circuit detection signal generation circuit 20 in that an inverter 212 is connected between the first input node 21 and the second input terminal of the AND circuit 211 and the second input terminal of the OR circuit 221, but otherwise it is substantially the same. Similarly, the SCL short-circuit detection signal generation circuit 30A differs from the SCL short-circuit detection signal generation circuit 30 in that an inverter 312 is connected between the first input node 31 and the second input terminal of the AND circuit 311 and the second input terminal of the OR circuit 321, but otherwise it is substantially the same.

[0081] The reason for further configurations including inverters 212 and 312 is that when using signal SA_FWD, which is an SA signal advanced by a predetermined time relative to the SDA signal and SCL signal, the signal levels in the first and second propositions described above are reversed. Specifically, in the address determination circuit 10A, The following Propositions 1A and 2A Proposition 1A: "If the address selection signal is the SCL signal, then the SCL signal is '0' when the SA_FWD signal is rising edge, and '1' when the SA_FWD signal is falling edge." Proposition 2A: "If the address selection signal is the SDA signal, then the SDA signal is '0' when the SA_FWD signal is rising edge and '1' when the SA_FWD signal is falling edge." Both are true.

[0082] Therefore, the contrapositive of Proposition 1A, which is Proposition 3A, and the contrapositive of Proposition 2A, which is Proposition 4A, are Proposition 3A: "If the SCL signal is not '0' when the SA_FWD signal is rising edge, and not '1' when the SA_FWD signal is falling edge, then the address selection signal is not the SCL signal." Proposition 4A: "If the SDA signal is not '0' when the SA_FWD signal is rising and not '1' when the SA_FWD signal is falling, then the address selection signal is not the SDA signal." It will become.

[0083] In the SDA short-circuit detection signal generation circuit 20A illustrated in Figure 9, the inverter 212 is connected between the first input node 21 and the second input terminal of the AND circuit 211 and the second input terminal of the OR circuit 221. However, for the SDA short-circuit detection signal generation circuit 20 (see Figure 2), the inverter 212 may be connected between the second input node 22 and the clock input terminal CK of the D-FF circuit 210 and the input terminal of the inverter 222. Furthermore, as shown in the SDA short-circuit detection signal generation circuit 20A1 illustrated in Figure 11, the series connection of inverters 212 and 222 may be simplified, and instead of inverter 212, inverter 214 may be connected between the connection point of the second input node 22 and the clock input terminal CK of the D-FF circuit 220 and the clock input terminal CK of the D-FF circuit 210. Although the second modified example (third configuration example) of the SCL short-circuit detection signal generation circuit 30A is not shown in the diagram, the SCL short-circuit detection signal generation circuit 30A may also be modified in the same way as the SDA short-circuit detection signal generation circuit 20A.

[0084] Next, we will explain the second variation (third configuration example). Figure 12 is a schematic diagram showing the configuration of the address determination circuit 10B and semiconductor device 50B, which are a second modified example (third configuration example) of the address determination circuit and semiconductor device according to this embodiment. Figures 13 and 14 are circuit diagrams showing the configurations of the SDA short-circuit determination signal generation circuit 20B and the SCL short-circuit determination signal generation circuit 30B in the third configuration example, respectively.

[0085] The address determination circuit 10B differs from the address determination circuit 10 in that it has multiple delay elements 16, replaces the SDA short-circuit determination signal generation circuit 20 with an SDA short-circuit determination signal generation circuit 20B, and includes an SCL short-circuit determination signal generation circuit 30B, but otherwise is substantially the same. Therefore, when describing the address determination circuit 10B and the semiconductor device 50B, the same reference numeral is used for overlapping components and their descriptions are omitted.

[0086] In the address determination circuit 10B, at least one delay element 16 is connected in series to each of the SDA terminal 11, SA terminal 12, and SCL terminal 13. More specifically, one delay element 16 is connected between the SDA terminal 11 and the input side of the SDA short-circuit detection signal generation circuit 20B, two delay elements 16 are connected in series between the SA terminal 12 and the input side of the SDA short-circuit detection signal generation circuit 20B and the input side of the SCL short-circuit detection signal generation circuit 30B, and one delay element 16 is connected between the SCL terminal 13 and the input side of the SCL short-circuit detection signal generation circuit 30B.

[0087] In the address determination circuit 10B, node N1 is supplied with a signal that has been delayed by one step from the SDA terminal 11. Node N2 is supplied with a signal (without delay) that has been supplied from the SA terminal 12. Node N3 is supplied with a signal that has been delayed by one step from the SA terminal 12. Node N4 is supplied with a signal that has been delayed by two steps from the SA terminal 12. Node N5 is supplied with a signal that has been delayed by one step from the SCL terminal 13.

[0088] The SDA short-circuit detection signal generation circuit 20B receives a signal supplied from the SDA terminal 11 with a one-step delay, a signal supplied from the SA terminal 12 (without delay), and a signal supplied from the SA terminal 12 with a two-step delay. The SCL short-circuit detection signal generation circuit 30B receives a signal supplied from the SCL terminal 13 with a one-step delay, a signal supplied from the SA terminal 12 (without delay), and a signal supplied from the SA terminal 12 with a two-step delay.

[0089] The SDA short-circuit detection signal generation circuit 20B comprises four D-FF circuits 210_1, 220_1, 210_2, and 220_2, four inverters 214, 222, and 223, and an AND circuit 26 that performs a logical AND operation on the signals input from the four input terminals 261 to 264. The SDA short-circuit detection signal generation circuit 20B is equivalent to a logic circuit that outputs the logical AND of the output signals of two SDA short-circuit detection signal generation circuits 20 and 20A1 (see Figures 2 and 11).

[0090] Furthermore, the SDA short-circuit detection signal generation circuit 20B includes a first input node 21B whose input terminal is connected to the output terminal of a delay element 16 whose input terminal is connected to the SDA terminal 11, forming node N1; a second input node 22B whose input terminal is connected to the output terminals of two delay elements 16 whose input terminals are connected in series with the SA terminal 12, forming node N4; a third input node 24B which is directly connected to the SA terminal 12; and an output node 23 which is connected to the output terminal of the AND circuit 26. The inverter 214 is connected between the third input node 24B and the clock input terminal CK of the D-FF circuit 210_2.

[0091] The SCL short-circuit detection signal generation circuit 30B has the same configuration as the SDA short-circuit detection signal generation circuit 20B. The SCL short-circuit detection signal generation circuit 30B includes four D-FF circuits 310_1, 320_1, 310_2, and 320_2, four inverters 314, 322, and 323, and an AND circuit 36 ​​that performs a logical AND operation on the signals input from four input terminals 361 to 364. The SCL short-circuit detection signal generation circuit 30B is equivalent to a logic circuit that outputs the logical AND of the output signals of two SCL short-circuit detection signal generation circuits 30 and a modified version of the SCL short-circuit detection signal generation circuit 30A (equivalent to the SDA short-circuit detection signal generation circuit 20A1: see Figure 11).

[0092] Furthermore, the SCL short-circuit detection signal generation circuit 30B includes a first input node 31B connected to the SCL terminal 13 via a delay element 16, a second input node 32B connected to the SA terminal 12 via two delay elements 16, a third input node 34B directly connected to the SA terminal 12, and an output node 33 connected to the output terminal of the AND circuit 36. The inverter 314 is connected between the third input node 34B and the clock input terminal CK of the D-FF circuit 310_2.

[0093] The operation of the SDA short-circuit detection signal generation circuit 20B, the SCL short-circuit detection signal generation circuit 30B, and the SA terminal short-circuit detection circuit 40 in the operation of the address detection circuit 10B will be explained.

[0094] The SDA short-circuit detection signal generation circuit 20B uses the timing of the SDA signal as a reference and not only determines the signal level at the rising and falling edges of the SA signal that are delayed by a predetermined time relative to that timing, but also determines the signal level at the rising and falling edges of the SA signal that are advanced by a predetermined time relative to the timing of the SDA signal. Therefore, since the truth value of the "first condition" is determined at more observation points than the SDA short-circuit detection signal generation circuit 20, the accuracy of address determination can be further improved.

[0095] The SCL short-circuit detection signal generation circuit 30B uses the timing of the SCL signal as a reference and not only determines the signal level at the rising and falling edges of the SA signal that are delayed by a predetermined time relative to that timing, but also determines the signal level at the rising and falling edges of the SA signal that are advanced by a predetermined time relative to the timing of the SCL signal. Therefore, the truth value of the "second condition" can be determined at more observation points than the SCL short-circuit detection signal generation circuit 30, further improving the accuracy of address determination.

[0096] The SA terminal short-circuit detection circuit 40 in the address determination circuit 10B is substantially the same in operation as the SA terminal short-circuit detection circuit 40 in the address determination circuit 10 or the address determination circuit 10A. That is, the SA terminal short-circuit detection circuit 40 determines the connection destination of the SA terminal 12 according to the logic compliant with the truth table illustrated in Figure 5. However, in the address determination circuit 10B, the SDA short-circuit detection signal and the SCL short-circuit detection signal obtained by conditional determination at more observation points than in the address determination circuit 10 or the address determination circuit 10A can be applied, thereby further improving the accuracy of address determination.

[0097] Figure 15 is a timing chart showing the case where the SA terminal 12 is shorted to the SCL line in the address determination circuit 10B.

[0098] Figure 15 shows, from top to bottom, the SCL signal, the SDA signal, the SA signal, the SA_DLY0 signal (=SA signal), which is the SA signal with no delay relative to the SA signal, the SCL_DLY signal, which is the SCL signal with one stage delay, the SA_DLY2 signal, which is the SA signal with two stages delay, and the SDA_DLY signal, which is the SDA signal with one stage delay. The SDA signal exemplified in Figure 15 changes so that it falls simultaneously with or slightly after the falling edge of the SCL signal (the level change of the SDA signal is prohibited when the SCL signal is at a high level).

[0099] In the address determination circuit 10B, the SCL_DLY signal and SDA_DLY signal are determined at two observation points (times t11, t12): the SA_DLY0 signal, which is one step ahead (no delay), and the SA_DLY2 signal, which is one step behind (two-step delay). By using two observation points, even in special cases where the SDA short-circuit determination signal (sa_short_sda) fails to detect the condition as false (incorrectly outputs true) at one observation point (time t11), it can be correctly detected at the other observation point (time t12).

[0100] As described above, according to one aspect of the present invention, the address determination circuits 10, 10A, 10B and semiconductor devices 50, 50A, 50B, in which four addresses are set for one SA terminal, can be configured with a simple circuit configuration and higher accuracy in address determination. Furthermore, according to one aspect of the present invention, since the address determination is performed based on the SA signal and the SDA short-circuit determination signal and SCL short-circuit determination signal generated based on the SA signal and at least one signal that is shifted by a predetermined time, for example by delaying it by a predetermined time, the accuracy of address determination can be improved.

[0101] Furthermore, although the address determination circuits 10, 10A, and 10B described above are examples with one SA terminal 12, multiple SA terminals 12 may be used. In address determination circuits 10, 10A, and 10B equipped with multiple SA terminals 12 (k in total), the set address is 4 k Up to a certain number of addresses can be determined. In addition, although the case where the second input terminal of the SA terminal short detection circuit 40 is connected to the SA terminal 12 has been described, it may also be connected to the output terminal of the delay element 16 (node ​​N3 or node N4 in the address detection circuit 10B) instead of the SA terminal 12.

[0102] Furthermore, in the SDA short-circuit detection signal generation circuit 20B (see Figure 13), the portion corresponding to the SDA short-circuit detection signal generation circuit 20A1 (see Figure 11) may be replaced with the SDA short-circuit detection signal generation circuit 20A (see Figure 9). Similarly, the SCL short-circuit detection signal generation circuit 30B (see Figure 14) may be modified in the same way as the SDA short-circuit detection signal generation circuit 20B. These embodiments and their modifications are included in the scope and essence of the invention, as well as in the scope of the invention and its equivalents as described in the claims. [Explanation of Symbols]

[0103] 10, 10A, 10B Address determination circuit 20, 20A, 20B SDA Short Circuit Detection Signal Generation Circuit 30, 30A, 30B SCL short-circuit detection signal generation circuit 40 SA terminal short-circuit detection circuit (address selection signal detection circuit) 50, 50A, 50B Semiconductor Equipment

Claims

1. A circuit for determining the address of serial communication that sends and receives a start signal, a data signal, and an end signal over a communication line, The system includes an address selection signal input terminal, a serial data input terminal, a serial clock input terminal, and an address selection signal determination circuit that receives a first determination signal based on the result of latching the level of the serial data signal supplied to the serial data input terminal at a first edge timing when the address selection signal supplied to the address selection signal input terminal transitions from a first power supply voltage to a second power supply voltage, and a second determination signal based on the result of latching the level of the serial clock signal supplied to the serial clock input terminal at the first edge timing and the second edge timing. The address selection signal determination circuit is characterized in that it determines the address selection signal is the serial clock signal when the first determination signal is at a signal level corresponding to false, determines the address selection signal is the serial data signal when the second determination signal is at a signal level corresponding to false, and determines either the first power supply voltage or the second power supply voltage based on the voltage of the address selection signal when both the first and second determination signals are at signal levels corresponding to true.

2. The system comprises at least one delay element that delays at least one of the serial data signal, the serial clock signal, and the address selection signal, The address determination circuit according to claim 1, wherein the first edge timing and the second edge timing include a plurality of signal edges with different delay times generated by the delay element.

3. A first signal generation circuit that generates the first determination signal, The system comprises a second signal generation circuit that generates the second determination signal, The first signal generation circuit and the second signal generation circuit each include a plurality of flip-flop circuits that latch an input signal in response to at least one of the rising edge and falling edge of the address selection signal, The address determination circuit according to claim 1 or 2, further comprising a logic gate that calculates the logical AND of the output signals of the plurality of flip-flop circuits.

4. A semiconductor device comprising an address determination circuit as described in claim 1 or 2.

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