Substrate structure for electronic devices and method for manufacturing electronic devices

Abstract

This invention provides a substrate structure and manufacturing method for an electronic device that controls the particle size of the conductive material formed in through holes by adjusting the current density and electroplating time in the electroplating process. [Solution] The substrate structure 100 of the electronic device comprises a substrate 10, a plurality of through holes VH penetrating the substrate, and a conductive member 30 disposed in at least one of the plurality of through holes. The pitch between two adjacent through holes of the plurality of through holes is 200 μm or less. In a cross-sectional view of the substrate structure, the conductive member has a bridge 20B, a first portion 30a, a second portion 30b, and a third portion 30c arranged sequentially along the normal direction of the substrate. The bridge is adjacent to at least one side wall of the plurality of through holes. The first portion is adjacent to the side wall of the bridge, and the average particle size of the first portion is 5 μm or less.

Description

Technical Field

[0001] This application claims the priority benefit of U.S. Provisional Application No. 63 / 781,387, filed on April 1, 2025, the content of which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates to an electronic device, and more particularly, to a design of an electronic device having a substrate structure and a method of manufacturing the same.

Background Art

[0003] In the manufacturing process of electronic devices, an electroplating process is used to form a conductive member in a through hole of a substrate, so as to form a substrate structure. However, the material of the conductive member formed by the existing electroplating process may have relatively large crystal grain sizes or variations in crystallinity. In the manufacturing process of electronic devices, the substrate structure is prone to cracking after heat treatment. This may cause abnormal signal transmission in the manufactured electronic device, and further reduce the reliability of the electronic device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

[0005] This disclosure relates to a substrate structure for an electronic device. An electronic device including this substrate structure can have relatively high reliability.

[0006] According to some embodiments of the present disclosure, the substrate structure of an electronic device comprises a substrate, a plurality of through holes, and a conductive member. The plurality of through holes penetrate the substrate, and the pitch between two adjacent through holes is 200 μm or less. The conductive member is located in at least one of the plurality of through holes. In a cross-sectional view of the substrate structure, the conductive member has a bridge, a first portion, a second portion, and a third portion arranged sequentially along the normal direction of the substrate. The bridge is adjacent to the side wall of at least one of the plurality of through holes. The first portion is adjacent to the side wall of the bridge, and the average particle size of the first portion is 5 μm or less.

[0007] This disclosure relates to a method for manufacturing electronic devices. Electronic devices manufactured by this method can have relatively high reliability.

[0008] According to some embodiments of the present disclosure, a method for manufacturing an electronic device includes the following steps. A substrate structure is provided, which includes the following steps. A substrate having a plurality of through holes is provided. An electroplating process is performed to form a conductive member in at least one of the plurality of through holes, and this process includes performing a first electroplating process for forming a bridge in at least one of the plurality of through holes, wherein the bridge is adjacent to a side wall of at least one of the plurality of through holes, and thereafter performing a second electroplating process for forming the rest portion of the conductive member connected to the bridge in at least one of the plurality of through holes. In a cross-sectional view of the substrate structure, the rest portion of the conductive member has a first portion, a second portion, and a third portion sequentially arranged along the normal direction of the substrate. The first portion is adjacent to the side wall of the bridge, and the average grain size of the first portion is 5 μm or less. The pitch between two adjacent through holes among the plurality of through holes is 200 μm or less. At least one process is performed to form an electronic device. The current density and electroplating time used in the first electroplating process are greater than the current density and electroplating time used in the second electroplating process. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a deeper understanding of the present disclosure, are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. [Figure 1] 1 is a schematic flowchart of a method for manufacturing an electronic device according to an embodiment of the present disclosure. [Figure 2] 2 is a schematic cross-sectional view of a substrate structure of an electronic device according to an embodiment of the present disclosure. [Figure 3A] 3 is a scanning electron micrograph of an embodiment of region R1 in FIG. 2. [Figure 3B] 4 is a scanning electron micrograph of an embodiment of region R2 in FIG. 2. [Figure 4]This is a schematic top view of a portion of the substrate structure of an electronic device according to one embodiment of the present disclosure. [Figure 5] This is a schematic cross-sectional view of an electronic device according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0010] The embodiments of this disclosure shown in the attached drawings will be described in detail below. Wherever possible, the same reference numerals will be used in the drawings and description to refer to identical or similar parts.

[0011] This disclosure can be understood by referring to the following detailed description in conjunction with the attached drawings. For the sake of readability and conciseness, many of the drawings in this disclosure show only a portion of the electronic device, and certain elements in the drawings are not depicted to actual size. Furthermore, the quantities and sizes of elements in the drawings are for illustrative purposes only and do not limit the scope of this disclosure.

[0012] Throughout this specification and the accompanying claims, certain terms are used to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may refer to the same component by different names. This specification is not intended to distinguish between components that have the same function but different names. In the following description and claims, terms such as “include,” “contain,” and “have” are unrestrictive terms, i.e., “include, but not limited to.” So where the terms “include,” “contain,” and / or “have” are used in the description of this disclosure, they specify the presence of a corresponding feature, area, step, operation, and / or component, and do not exclude the presence of one or more other corresponding features, areas, steps, operations, and / or components.

[0013] The terms indicating direction, such as “up,” “down,” “front,” “back,” “left,” and “right,” as used herein are merely for reference to the orientation of the accompanying drawings. Therefore, these directional terms are illustrative and do not limit the disclosure. In the drawings, each figure illustrates the general characteristics of the methods, structures, and / or materials used in a particular embodiment. However, these drawings are not construed as defining or limiting the scope or nature of these embodiments.

[0014] When a corresponding component (e.g., a film layer or region) is described as being "on another component," it may be directly on that component, or other components may exist between them. On the other hand, when a component is described as being "directly on another component," there are no components between them. Furthermore, when a component is described as being "on another component," they are in an up-and-down relationship in the top-down view, and this component may be above or below the other component, and this up-and-down relationship is determined by the orientation of the device.

[0015] The terms “equal to” or “same,” “substantially” or “about” are generally interpreted to mean within 20% of a particular value or range, or within 10%, 5%, or 0.5% of a particular value or range.

[0016] Ordinal numbers such as "first," "second," etc., used in the specification and claims are used to modify elements and do not in themselves suggest or indicate that an element has a preceding ordinal number, nor do they indicate the order of one element to another, or the order in a manufacturing method. The use of these ordinal numbers is used solely to clearly distinguish an element with a particular name from another element with the same name. The same terminology is not necessarily used in the claims and the specification. Therefore, a first element in the specification may be a second element in the claims.

[0017] Features in multiple different embodiments are substitutable to complete other embodiments without departing from the spirit of this disclosure. Features in various embodiments can be combined in any way, provided they do not contradict or conflict with the spirit of this disclosure.

[0018] The electrical connections or couplings described herein may be either direct or indirect. In a direct connection, the terminals of the two circuit elements are either directly connected or connected to each other by a conductive wire segment. In an indirect connection, there is another suitable element between the terminals of the two circuit elements.

[0019] In this disclosure, the definitions of thickness, length, width, area, and roughness can be determined by observation using an optical microscope, scanning electron microscope, or transmission electron microscope. For uneven surfaces, the difference in distance between the peaks and valleys of the surface irregularities can be defined as the roughness of the uneven surface. The state of the surface irregularities is observed with a microscope at appropriate magnification, and the range of roughness is determined by comparing the state of irregularities of a unit length (e.g., 10 micrometers) of the sample. Here, "appropriate magnification" means that at least one surface roughness (Rz) or mean roughness (Ra) can be observed with at least 10 peaks of irregularities within the field of view at that magnification.

[0020] The manufacturing methods for the electronic devices of this disclosure can be provided, for example, by a wafer-level packaging (WLP) process or a panel-level packaging (PLP) process, which may be a chip-first process or a chip-last / RDL-first process.

[0021] The electronic devices of this disclosure can be applied to, but are not limited to, power modules, semiconductor packaging devices, display devices, light-emitting devices, backlight devices, antenna devices, sensing devices, or tiling devices. These electronic devices may include peripheral systems such as drive systems, control systems, and light source systems to support display devices, antenna devices, wearable devices, automotive devices, or tiling devices. These electronic devices may include, but are not limited to, high-bandwidth memory (HBM) packages, chip-on-wafer-on-substrate (CoWoS) package structures, system-on-a-chip (SoC), system-in-package (SiP), antenna-in-package (AiP), co-packaged optics (CPO), or various combinations of the above devices.

[0022] Refer to Figures 1 and 2 simultaneously. In this embodiment, the electronic device 10c and the substrate structure of the electronic device 10c can be formed by performing the following steps, but the disclosure is not limited thereto.

[0023] Step (1) is performed to form multiple through-holes VH that penetrate the substrate 10.

[0024] The material of the substrate 10 may be, for example, a suitable ceramic material. For example, the material of the substrate 10 may be a transparent material, glass, alkali-free glass, or quartz glass. In this embodiment, the substrate 10 is a glass substrate and has two surfaces 10s1 and 10s2 that face each other in the Z direction (normal direction of the substrate 10). By performing a corresponding etching process and / or laser process on the substrate 10, a plurality of through-holes VH penetrating the substrate 10 can be formed.

[0025] Step (2) is performed, in which a seed layer 20 is formed in multiple through holes VH of the substrate 10.

[0026] The seed layer 20 can be formed by electroless plating, electroplating, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination thereof. In this embodiment, the seed layer 20 may have a multilayer structure. The seed layer 20 can also be formed on surfaces 10s1 and 10s2 of the substrate 10.

[0027] Step (3) is performed, which involves executing a preprocessing process on the seed layer 20.

[0028] In some embodiments, the pretreatment process performed on the seed layer 20 may include a cleaning process, a micro-etching process, and / or heat treatment. For example, a first cleaning process may be performed to remove seams and / or holes that occur where adjacent seed layers 20 join within the through-hole VH. Subsequently, a micro-etching process may be performed on the seed layer 20 to roughen its surface and improve the bonding strength with the later-formed film layer. Next, a second cleaning process may be performed to remove impurities generated by the aforementioned micro-etching process. After the pretreatment process on the seed layer 20 is complete, the continuity of the seed layer may be improved by selectively repeating step (2) to form another seed layer.

[0029] Step (4) is performed, which involves carrying out a first electroplating process to form a bridge 20B of the conductive member 30.

[0030] In this embodiment, the first electroplating process is a pulsed periodic reversal (PPR) electroplating process. Specifically, a bridge 20B can be formed between adjacent seed layers 20 located within the through-hole VH by independently adjusting the current on time, current off time (electroplating time), and / or current density. After performing the first electroplating process, process (4-1), namely the annealing process, can be selectively performed.

[0031] Perform the first inspection process, step (5).

[0032] In this embodiment, the first inspection process includes (a) confirming whether a bridge 20B is formed and (b) confirming the location of the bridge 20B. If it is confirmed in step (a) that a bridge 20B is not formed, the process returns to step (3). If it is confirmed that a bridge 20B is formed, step (b) is performed to confirm whether the bridge 20B is located in a region extending from the surface 10s1 of the substrate 10 in the Z direction in a range of 0.25 to 0.75 times the thickness t of the substrate 10. If it is confirmed that a bridge 20B is not formed in the above region, the process returns to step (3) and performs another pretreatment process on the seed layer 20, for example, removing the oxide layer of the seed layer 20 by an appropriate process.

[0033] In some embodiments, the condition of the bridge 20B can be confirmed by an optical inspection system or a scanning electron microscope, but the disclosure is not limited thereto. A cleaning process may be performed before the first inspection process.

[0034] Step (6) is performed to complete the conductive member 30 by performing a second electroplating process to form the other parts of the conductive member 30 connected to the bridge 20B.

[0035] The second electroplating process is, for example, a multi-stage DC electroplating process. Specifically, the conductive member 30, which includes a first portion 30a, a second portion 30b, and a third portion 30c, can be formed by performing a three-stage DC electroplating process, and the first portion 30a, the second portion 30b, and the third portion 30c can be arranged sequentially. Here, "arranged sequentially" means that the first portion 30a, the second portion 30b, and the third portion 30c are arranged sequentially along a direction (X or Y direction) perpendicular to the normal direction (Z direction) of the substrate, and the first portion 30a is adjacent to the side wall of the bridge 20b. In this embodiment, the first portion 30a and the second portion 30b are conformally formed within the through-hole VH, and the third portion 30c is filled within the through-hole VH. In other words, the bridge 20B is used as a base for filling the through-hole VH, completing the fabrication of the conductive member 30. The current density and electroplating time used in the first and second electroplating processes are different. In this embodiment, the current density and electroplating time of the first electroplating process are greater than those of the second electroplating process. In some embodiments, the average particle size of the third portion 30c is greater than or equal to the average particle size of the bridge 20B. Technical solutions regarding particle size are described in detail in the following embodiments.

[0036] In this embodiment, in a three-stage DC electroplating process, the current density increases sequentially and the electroplating time decreases sequentially. Specifically, the current density in the DC electroplating process forming the first portion 30a is lower than the current density in the DC electroplating process forming the second portion 30b, and the current density in the DC electroplating process forming the second portion 30b is lower than the current density in the DC electroplating process forming the third portion 30c. Furthermore, the plating time in the DC electroplating process forming the first portion 30a is longer than the plating time in the DC electroplating process forming the second portion 30b, and the plating time in the DC electroplating process forming the second portion 30b is longer than the plating time in the DC electroplating process forming the third portion 30c.

[0037] In the three-stage DC electroplating process, the crystallization conditions in the first section 30a, the second section 30b, and the third section 30c can be individually adjusted by varying the current density and electroplating time. This reduces the stress caused by differences in the thermal expansion coefficients between layers in the subsequent back-end process, thereby reducing the possibility of crack formation in the conductive member 30 formed within the through hole VH. After the second electroplating process, step (6-1), i.e., the annealing process, can be selectively performed to reduce the internal stress of the conductive member 30 and / or alter the microstructure of the conductive member 30.

[0038] In some embodiments, the materials of the bridge 20B and the conductive member 30 may be copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tungsten (W), platinum (Pt), nickel (Ni), gold (Au), silver (Ag), or a combination thereof.

[0039] After the second electroplating process, a surface planarization step can be performed so that the surface of the conductive member 30 is substantially coplanar with the surface of the substrate 10. That is, in the Z direction, the distance between the surface of the conductive member 30 and the surface of the substrate 10 is 10 micrometers or less. See Figure 3A. After the planarization step, in a cross-sectional region extending 50 μm in the Z direction from the surface 30s1 of the conductive member 30, the average particle size of the conductive member 30 is 5 μm or less, and the maximum particle size is 20 μm or less. This was measured using appropriate equipment in the cross-sectional region enclosed by the circle in Figure 3A (its surface area is the product of the diameter W and 50 μm). See Figure 4. In the upper surface region in the Z direction of the surface 30s1 of the conductive member 30, and in the upper surface region in the Z direction of the surface 30s2 of the conductive member 30 (not shown), the average particle size of the conductive member 30 is 6 μm or less. See Figure 3B, which shows the cross-sectional region near the center of the conductive member 30. According to some embodiments, the maximum particle size in the cross-sectional region and the upper surface region is 20 μm or less, or 15 μm or less.

[0040] At this point, the fabrication of the substrate structure 100 is complete.

[0041] Perform the second inspection process, step (7).

[0042] In this embodiment, the second inspection step includes (c) confirming whether the average particle size of the conductive member 30 in a cross-sectional region extending 50 μm in the Z direction from the surface 30s1 of the conductive member 30 is 5 μm or less, and (d) confirming whether the average particle size of the conductive member 30 in the surface regions of the top view in the Z direction of the surfaces 30s1 and 30s2 of the conductive member 30 is 6 μm or less. If at least one of the parameters defined in steps (c) and (d) is not met or is outside the specifications, it is considered to return to step (6-1) or discard the substrate structure.

[0043] In some embodiments, whether the multiple through-holes VH satisfy the parameters defined in step (c) and step (d) can be verified by an optical inspection system or a scanning electron microscope, but the disclosure is not limited thereto.

[0044] After performing the second inspection process, the substrate structure 100 can be applied to a backend process to form the corresponding electronic device. According to some embodiments, the disclosure may further include a separation step of dividing the substrate structure 100 into a plurality of sub-substrates by dicing or laser grooving. For example, as shown in Figure 5, step (8) can be performed, in which at least one process is performed on the substrate structure 100 to form the electronic device 10c.

[0045] In this embodiment, at least one corresponding process can be performed on the substrate structure 100 to form an electronic device 10c, which may include, but is not limited to, a process for forming a circuit structure ES on the substrate structure 100 and a process for forming an electronic component 2.

[0046] Refer to Figure 5. In this embodiment, the circuit structure ES is positioned on the surface 10s1 of the substrate 10 and at least partially overlaps with a plurality of through holes VH. In some embodiments, the circuit structure ES comprises at least one insulating layer IL and at least one conductive layer M. The material of the insulating layer IL may be Ajinomoto build-up film (ABF), photosensitive polyimide (PSPI), polyimide (PI), epoxy resin, or other suitable insulating material. The conductive layer M may be composed of a suitable conductive material similar to that of the conductive member 30.

[0047] The thickness t of the substrate 10 is 0.6 mm to 2 mm, and the coefficient of thermal expansion of the substrate 10 is 1 ppm / K to 10 ppm / K. In the X direction, the minimum opening diameter d of one of the multiple through holes VH is 90 μm to 110 μm, the aspect ratio (AR) of the multiple through holes VH is 8 to 20, and the aspect ratio = substrate thickness t / minimum opening diameter d of one of the multiple through holes VH (AR = t / d). In the X direction, the pitch P between two adjacent through holes VH is 200 μm or less. In this disclosure, the terms “adjacent” or “contacting” mean that two of the multiple elements (e.g., multiple through holes VH) are arranged along one direction and these two elements have a minimum distance or minimum pitch.

[0048] Refer to Figure 2. Before the annealing process, the average particle size of the conductive member 30 in a cross-sectional region extending 50 micrometers in the Z direction from surface 30s1 of the conductive member 30 (or in the opposite direction from surface 30s2) is 5 μm or less. Here, the average particle size of the bridge 20B and the first portion 30a is 5 μm or less, the average particle size of the second portion 30b may be larger than the average particle size of the first portion 30a, and the average particle size of the third portion 30c may be larger than the average particle size of the first portion 30a. In some embodiments, after the annealing process or after the formation of the circuit structure ES, the average particle size of the third portion 30c of the conductive member 30 is 2 μm or more and less than or equal to one-fifth of the minimum opening diameter d of one of the multiple through holes VH, thereby reducing the risk of crack formation in the substrate 10. The bridge 20B referred to in this disclosure is a conductive member 30 having a continuous structure adjacent to the side wall of the through hole VH at the center of the through hole VH (the portion where the width of the through hole VH is smallest). The first portion 30a is located within 10 μm in the X direction from the side wall of the bridge 20B, the second portion 30b is located within 15 μm in the X direction from the side wall of the first portion 30a, and the remainder is the third portion 30c.

[0049] In this embodiment, the multilayer conductive layer M of the circuit structure ES comprises contact pads PAD1 and PAD2. Contact pad PAD1 is located, for example, on one side of the surface 10s1 of the substrate 10 and is the part of the multilayer conductive layer M furthest from the surface 10s1 of the substrate 10, and is exposed by a multilayer insulating layer IL. Contact pad PAD2 is located, for example, on one side of the surface 10s2 of the substrate 10. In this embodiment, at least a portion of the multilayer conductive layer M is arranged in a plurality of through holes VH, forming an electrical connection path between contact pads PAD1 and PAD2.

[0050] In this embodiment, the circuit structure ES includes a rewiring structure that can be used for rewiring and / or expanding the fan-out area of ​​the wiring. The purpose of providing the rewiring structure is to extend connections to a wider pitch or to rewiring connections to other connections of a different pitch. This allows identical or different electronic components 2 to be placed on the circuit structure ES and electrically connected. External components CB can be placed on the surface 10s2 of the substrate 10 and electrically connected to the circuit structure ES through through holes VH, thereby allowing electronic components 2 to be electrically connected to the external components CB via the circuit structure ES. The external components CB may be a circuit board, an IC board, or other suitable component. Methods for forming the circuit structure ES include electroplating, electroless plating, etching, laser, photolithography, annealing steps, or other suitable methods.

[0051] In this embodiment, the electronic device 10c further comprises a buffer layer BF. The material of the buffer layer BF may be a suitable organic and / or inorganic material. The material of the buffer layer BF may be, but is not limited to, polyimide, parylene, benzocyclobutene (BCB) resin, epoxy resin, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-containing compounds, or a combination thereof. In some embodiments, the buffer layer BF may be a multilayer structure of inorganic / organic / inorganic layers. In some embodiments, the buffer layer BF may cover the sides of the substrate 10 and the sidewalls of through holes VH, filling pits, irregularities, or microcracks that occur on the corresponding surface of the substrate 10 during the manufacturing process, thereby reducing cracks in the substrate 10.

[0052] For example, a plurality of electronic components 2 are arranged on a circuit structure ES and electrically connected to the circuit structure ES. In this embodiment, the plurality of electronic components 2 include two electronic components 2a and 2b, but the disclosure is not limited to this number. The electronic components 2a and 2b may be, for example, high-bandwidth memory, dynamic random access memory (DRAM), static random access memory (SRAM), cache memory, image processing unit (GPU), central processing unit (CPU), digital signal processor (DSP), or application-specific integrated circuit (ASIC), but the disclosure is not limited to these. Electronic component 2a may be electrically connected to the circuit structure ES via a contact pad PAD3 and at least a portion of a plurality of connection units CU1, and electronic component 2b may be electrically connected to the circuit structure ES via at least another portion of the plurality of connection units CU1.

[0053] In this embodiment, the electronic device 10c further comprises a plurality of connection units CU1 arranged on the circuit structure ES, thereby electrically connecting the circuit structure ES to the electronic components 20 via the plurality of connection units CU1. The material of the plurality of connection units CU1 may be tin, copper, nickel, silver, gold, gallium, or other suitable material.

[0054] In this embodiment, the electronic device 10c further comprises a sealing layer MC that surrounds the substrate 10 and the plurality of electronic components 2. In this embodiment, the sealing layer MC may expose a portion of the plurality of electronic components 2. Specifically, the upper surface of the sealing layer MC may be aligned with the inactive surfaces of the plurality of electronic components 2, but the disclosure is not limited thereto.

[0055] In this embodiment, the electronic device 10c further comprises an underfill layer UF1 positioned between the substrate 10 and the electronic component 2, filling the space between adjacent connecting elements CU1. In some embodiments, the underfill layer UF1 may be surrounded by a sealing layer MC.

[0056] In this embodiment, the electronic device 10c further comprises a plurality of connection units CU2 disposed on one side of the surface 10s2 of the substrate 10 and electrically connected to a contact pad PAD2 in the circuit structure ES, thereby the circuit structure ES may be electrically connected to an external component CB via the plurality of connection units CU2. In some embodiments, the connection to the external component CB may be electrically connected via alignment marks AM in the substrate 10. The material of the plurality of connection units CU2 may be the same as or similar to the material of the plurality of connection units CU1.

[0057] In this embodiment, the electronic device 10c further comprises an underfill layer UF2 positioned between the substrate 10 and the external component CB, filling the space between adjacent connecting elements CU2. In some embodiments, the underfill layer UF2 may be in contact with the sidewall of the sealing layer MC. The materials of the sealing layer MC, the underfill layer UF1, and the underfill layer UF2 may be suitable inorganic or organic materials.

[0058] In this embodiment, the electronic device 10c further comprises an interposer INP including, for example, a core layer CL, vias V, an insulating layer IL1', a conductive layer M1', an insulating layer IL2', and a conductive layer M2'. The material of the core layer CL may be, for example, silicon, glass, or an organic material. In some embodiments, the edges of the core layer CL may have chamfered or rounded corners, but this disclosure is not limited thereto. Multiple vias V are arranged, for example, to penetrate the core layer CL. In some embodiments, the vias V may also be provided with a filler FI arranged on the sidewall of the via V. The insulating layer IL1' and the conductive layer M1' are arranged, for example, above the core layer CL and located between the core layer CL and the substrate structure 100 in the Z direction. The insulating layer IL1' and the conductive layer M1' may be combined to form a redistribution structure, thereby allowing conductive members 30 in the substrate structure 100 to be electrically connected to vias V in the core layer CL. The insulating layer IL2' and the conductive layer M2' are located between the core layer CL and the external component CB in the Z direction. The insulating layer IL2' and the conductive layer M2' may be combined to form a rewiring structure, thereby allowing the external component CB to be electrically connected to vias V in the core layer CL via a connection unit CU3. According to some embodiments, multiple electronic components 2 may be electrically connected to the circuit board CB via an interposer INP. Here, the method for forming vias V may be the same as the method for forming conductive member 30. That is, after the annealing process, the average particle size of the third portion of via V is 2 μm or more and is less than or equal to one-fifth of the minimum opening diameter of the multiple through-holes in the interposer INP, thereby reducing the risk of crack formation.

[0059] In some embodiments, the interposer INP may include an embedded die ED located in a recess RE of the core layer CL, which may be electrically connected to a via V in the core layer CL via a conductive layer M1'.

[0060] In this embodiment, the electronic device 10c further comprises a plurality of connection units CU3 located below the interposer INP and electrically connected to the conductive layer M2' within the interposer INP, thereby electrically connecting the interposer INP to an external component CB via the plurality of connection units CU3.

[0061] In summary, in a method for manufacturing electronic devices provided by some embodiments of the present disclosure, the particle size of the conductive material formed in through holes can be controlled by adjusting the current density and / or electroplating time in the electroplating process. This reduces the likelihood of crack formation in the substrate structure after heat treatment and improves the manufacturing yield of electronic devices.

Claims

1. A substrate structure for an electronic device, circuit board and A plurality of through holes penetrating the substrate, wherein the pitch between two adjacent through holes is 200 μm or less, and A conductive member is disposed in at least one of the plurality of through holes, and in a cross-sectional view of the substrate structure, the conductive member has a bridge, a first portion, a second portion, and a third portion arranged sequentially along the normal direction of the substrate, the bridge is adjacent to the side wall of at least one of the plurality of through holes, the first portion is adjacent to the side wall of the bridge, and the average particle size of the first portion is 5 μm or less. A substrate structure for an electronic device, comprising the following features.

2. The substrate structure for an electronic device according to claim 1, wherein the average particle size of the second portion is 5 μm or less.

3. The substrate structure for an electronic device according to claim 1, wherein the substrate is a glass substrate.

4. The substrate structure for an electronic device according to claim 1, wherein the thickness of the substrate is 0.6 mm to 1 mm, and the minimum aperture diameter of one of the plurality of through holes is 90 μm to 110 μm.

5. The substrate structure for an electronic device according to claim 4, wherein the average particle size of the third portion is greater than 2 μm and is less than or equal to one-fifth of the minimum opening diameter of one of the plurality of through holes.

6. The substrate structure for an electronic device according to claim 1, wherein the thermal expansion coefficient of the substrate is 1 ppm / K to 10 ppm / K.

7. The substrate structure for an electronic device according to claim 1, wherein the aspect ratio of the plurality of through holes is 8 to 20.

8. A method for manufacturing an electronic device, which includes providing a substrate structure, To provide the aforementioned substrate structure, To provide a substrate having multiple through holes, Performing an electroplating process to form a conductive member in at least one of the multiple through holes, Performing at least one process on the substrate structure in order to form the electronic device Includes, Performing the aforementioned electroplating process means Performing a first electroplating process to form a bridge of the conductive member in at least one of the multiple through holes, Performing a second electroplating process to form the other portion of the conductive member connected to the bridge in at least one of the multiple through holes. Includes, In a cross-sectional view of the substrate structure, the other portion of the conductive member has a first portion, a second portion, and a third portion arranged sequentially along the normal direction of the substrate, the first portion is adjacent to the side wall of the bridge, the average particle size of the first portion is 5 μm or less, and the pitch between two adjacent through holes of the plurality of through holes is 200 μm or less. A method for manufacturing an electronic device, wherein the current density and electroplating time used in the first electroplating process are greater than the current density and electroplating time used in the second electroplating process.

9. The method for manufacturing an electronic device according to claim 8, wherein the first electroplating process includes a pulse periodic reversal electroplating process, and the second electroplating process includes a multi-stage DC electroplating process.

10. The method for manufacturing an electronic device according to claim 9, wherein the second electroplating process comprises a three-stage DC electroplating process, the current density is sequentially increased through the three-stage DC electroplating process, and the electroplating time is sequentially decreased through the three-stage DC electroplating process.

11. Furthermore, the method for manufacturing an electronic device according to claim 8, comprising forming a seed layer in at least one of the multiple through holes before forming a bridge in the multiple through holes.

12. Furthermore, the method for manufacturing an electronic device according to claim 11, further comprising performing a pretreatment process on the seed layer.

13. Furthermore, the method for manufacturing an electronic device according to claim 8, comprising performing a first inspection step after forming a bridge in at least one of the plurality of through holes.

14. The first inspection process described above is: To confirm whether the aforementioned bridge is formed, To confirm the formation position of the aforementioned bridge. A method for manufacturing an electronic device according to claim 13, including the method described in claim 13.

15. A method for manufacturing an electronic device according to claim 14, wherein if the bridge is not formed after performing the first inspection process, another pre-processing process is performed on the seed layer.

16. A method for manufacturing an electronic device according to claim 14, wherein, after performing the first inspection process, if no bridge is formed in a region extending from the first surface of the substrate in the direction normal to the substrate in a range of 0.25 to 0.75 times the thickness of the substrate, another pre-treatment process is performed on the seed layer.

17. Furthermore, the method for manufacturing an electronic device according to claim 8, comprising performing an annealing process after forming the conductive member in at least one of the plurality of through holes.

18. Furthermore, the method for manufacturing an electronic device according to claim 17, comprising performing a second inspection process after performing the annealing process.

19. The second inspection process described above is: To confirm whether the average particle size of the conductive member in a cross-sectional region extending 50 μm in the direction normal to the first surface of the conductive member is 5 μm or less, To confirm whether the average particle size of the conductive member in the surface region of the top view in the normal direction of the first surface and the second surface of the conductive member is 6 μm or less. A method for manufacturing an electronic device according to claim 18, including the method described in claim 18.

20. A method for manufacturing an electronic device according to claim 19, wherein, after performing the second inspection process, if at least one of the requirements for the average particle size of the conductive member is outside the specifications, another annealing process is performed.

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