Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor that suppresses the occurrence of cracks within the laminate due to electrostriction when a high voltage is applied. [Solution] The multilayer ceramic capacitor 10 has a laminate 12 including an inner layer portion 16 formed by alternately stacking a plurality of dielectric layers 14 and a plurality of internal electrode layers 20, and outer layer portions 18a and 18b arranged to sandwich the inner layer portion from the first main surface side and the second main surface side, and a first external electrode 30a arranged on the first end surface 12e and a second external electrode 30b arranged on the second end surface 12f. The inner layer portion consists of an internal dielectric layer 14a from among the plurality of dielectric layers arranged in the inner layer portion, and the internal dielectric layer contains voids, and has a longitudinal central dielectric layer arranged in the longitudinal center of the inner layer portion and a longitudinal end dielectric layer arranged at the longitudinal end of the inner layer portion, and the amount of voids contained in the longitudinal end dielectric layer is less than the amount of voids in the longitudinal central dielectric layer.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] Conventionally, a multilayer ceramic capacitor is constituted by a capacitor body of a ceramic sintered body made of a dielectric such as barium titanate, and inside this capacitor body, internal electrodes made of a noble metal material such as Ag or Ag-Pd alloy or a base metal material such as Ni are arranged via ceramic layers (dielectric layers) so as to be led out alternately to one end face and the other end face. The internal electrodes at one potential are electrically conductively connected to an external electrode, and the internal electrodes at the other potential are electrically conductively connected to another external electrode, respectively (see Patent Document 1).

[0003] The multilayer ceramic capacitor described in Patent Document 1 uses a metal material as internal electrodes, and in the multilayer ceramic capacitor in which the external electrodes are composed of a plurality of metal components containing a metal that is the same as or can be alloyed with the internal electrode metal and a glass component, the external electrodes are adhered to a wiring substrate via a conductive resin adhesive, and the area occupancy (porosity) of the metal component with respect to the cross-sectional area of the external electrode is 60 to 95%. Thereby, this multilayer ceramic capacitor can be mounted on a wiring substrate at low cost and with high reliability without using solder.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in multilayer ceramic capacitors with a general structure like that described in Patent Document 1, electrostriction occurs when a voltage is applied. This stress due to electrostriction is concentrated at the effective ends in the length and width directions of the multilayer ceramic capacitor, and at the halfway point in the height direction. When a high voltage is applied, cracks occur starting from the aforementioned stress concentration points. Although cracks due to electrostriction are difficult to screen out, they lead to deterioration of high-temperature load reliability and moisture resistance, thus posing a risk of problems in the market.

[0006] Therefore, while there are several methods to reduce cracks caused by electrostriction, a typical measure is to set the applied voltage during screening low enough to prevent electrostriction. However, when the voltage at which electrostriction occurs is low, the voltage necessary for screening cannot be applied, which presents a problem as the screening effect is reduced.

[0007] Therefore, the main objective of this invention is to provide a multilayer ceramic capacitor that can suppress the occurrence of cracks in the laminate due to electrostriction when a high voltage is applied. [Means for solving the problem]

[0008] The multilayer ceramic capacitor according to this invention includes a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, and includes a laminated body comprising: an inner layer portion in which the dielectric layers and internal electrode layers are alternately stacked, an outer layer portion arranged to sandwich the inner layer portion from the first main surface side and the second main surface side, and a laminated body comprising: an inner layer portion in which the dielectric layers and internal electrode layers are alternately stacked, an outer layer portion arranged to sandwich the inner layer portion from the first main surface side and the second main surface side, and a laminated body disposed on the first end surface. A multilayer ceramic capacitor having a first external electrode and a second external electrode disposed on a second end face, wherein the inner layer is composed of an internal dielectric layer among a plurality of dielectric layers disposed in the inner layer, the internal dielectric layer contains voids, and the internal dielectric layer has a longitudinal central dielectric layer disposed in the central region in the longitudinal direction of the inner layer and a longitudinal end dielectric layer disposed in the longitudinal end region of the inner layer, the amount of voids contained in the longitudinal end dielectric layer is less than the amount of voids in the longitudinal central dielectric layer.

[0009] When voids exist in the dielectric layer, the mechanical strength is lower compared to regions where the dielectric layer is filled with ceramic. Therefore, if voids exist at points of electrostrictive stress concentration, electrostrictive cracks will occur in the dielectric layer starting from these voids. Electrostriction is more likely to occur at the longitudinal ends of the dielectric layer located within the inner layers of the laminate. According to the multilayer ceramic capacitor of the present invention, by reducing the amount of voids near the longitudinal ends of the dielectric layer located within the inner layers of the laminate, where electrostrictive stress is concentrated, compared to the longitudinal center, it is possible to reduce the occurrence of electrostrictive cracks. Furthermore, by reducing the amount of voids in the dielectric layer at the longitudinal ends, the sinterability of the ceramic is improved, and the shrinkage rate at the longitudinal ends is improved, increasing the exposure of the internal electrode layer and improving contact with the external electrode. [Effects of the Invention]

[0010] This invention provides a multilayer ceramic capacitor that can suppress the occurrence of cracks inside the laminate due to electrostriction when a high voltage is applied.

[0011] The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings. [Brief explanation of the drawing]

[0012] [Figure 1] This is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of this invention. [Figure 2] This is a cross-sectional view along line II-II in Figure 1. [Figure 3] This is a cross-sectional view along line III-III in Figure 1. [Figure 4] (a) is a schematic cross-sectional view showing the internal dielectric layer along line II-II in Figure 1, and (b) is a schematic cross-sectional view showing the internal dielectric layer along line III-III in Figure 1. [Figure 5] (a) is a cross-sectional view along line III-III in Figure 1 showing a structure in which the counter electrode portion of the internal electrode layer of a multilayer ceramic capacitor according to an embodiment of the present invention is divided into two parts; (b) is a cross-sectional view along line III-III in Figure 1 showing a structure in which the counter electrode portion of the internal electrode layer of a multilayer ceramic capacitor according to the present invention is divided into three parts; and (c) is a cross-sectional view along line III-III in Figure 1 showing a structure in which the counter electrode portion of the internal electrode layer of a multilayer ceramic capacitor according to the present invention is divided into four parts. [Modes for carrying out the invention]

[0013] 1. Multilayer ceramic capacitor A multilayer ceramic capacitor according to an embodiment of this invention will be described.

[0014] Figure 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 2 is a cross-sectional view taken along line II-II in Figure 1. Figure 3 is a cross-sectional view taken along line III-III in Figure 1. Figure 4(a) is a schematic cross-sectional view showing the internal dielectric layer along line II-II in Figure 1, and Figure 4(b) is a schematic cross-sectional view showing the internal dielectric layer along line III-III in Figure 1.

[0015] As shown in Figures 1 to 3, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped laminate 12 and external electrodes 30 positioned at both ends of the laminate 12.

[0016] The laminate 12 comprises a plurality of stacked dielectric layers 14 and a plurality of internal electrode layers 20 stacked on the dielectric layers 14. Furthermore, the laminate 12 has a first main surface 12a and a second main surface 12b opposite to the height direction x, a first side surface 12c and a second side surface 12d opposite to the width direction y which is perpendicular to the height direction x, and a first end surface 12e and a second end surface 12f opposite to the length direction z which is perpendicular to the height direction x and the width direction y. The corners and edges of this laminate 12 are rounded.

[0017] A corner refers to the point where three adjacent faces of the laminate 12 intersect, and a ridge refers to the point where two adjacent faces of the laminate 12 intersect. Furthermore, the term "rectangular parallelepiped" refers to any member having a first main surface 12a and a second main surface 12b, a first side surface 12c and a second side surface 12d, and a first end surface 12e and a second end surface 12f. In addition, some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f may have irregularities or other features formed on them. The dielectric layer 14 and the internal electrode layer 20 are laminated in the height direction x.

[0018] As shown in Figure 2 and Figure 3, in the height direction x connecting the first main surface 12a and the second main surface 12b, the laminate 12 has an inner layer portion 16 formed by alternately laminating dielectric layers 14 and internal electrode layers 20, a first outer layer portion 18a formed of a plurality of dielectric layers 14 located between the internal electrode layer 20 positioned closest to the first main surface 12a side and the first main surface 12a, and a second outer layer portion 18b formed of a plurality of dielectric layers 14 located between the internal electrode layer 20 positioned closest to the second main surface 12b side and the second main surface 12b.

[0019] The inner layer portion 16 is constituted by a plurality of internal dielectric layers 14a among the plurality of dielectric layers 14. That is, the inner layer portion 16 is arranged such that the plurality of internal electrode layers 20 face each other with the internal dielectric layers 14a interposed therebetween. Voids are contained inside the internal dielectric layers 14a.

[0020] Further, as shown in Figure 4(a), the internal dielectric layer 14a further includes a lengthwise central portion side dielectric layer 14a1 arranged in the central region in the length direction z of the inner layer portion 16, and a lengthwise end portion side dielectric layer 14a2 arranged in the end region in the length direction z of the inner layer portion 16. The amount of voids contained in the lengthwise end portion side dielectric layer 14a2 is preferably smaller than the amount of voids contained in the lengthwise central portion side dielectric layer 14a1. In addition, illustration of the internal electrode layers 20 is omitted in Figure 4(a).

[0021] The difference between the void area occupancy PCL in the LT cross section of the lengthwise central portion side dielectric layer 14a1 and the void area occupancy PEL in the LT cross section of the lengthwise end portion side dielectric layer 14a2 is preferably 2.0% or more and 8.0% or less.

[0022] Region LA, in which the amount of voids in the dielectric layer 14a2 at the longitudinal end is less than the amount of voids in the dielectric layer 14a1 at the longitudinal center, is located in the region inside the longitudinal z of the inner layer 16, from both ends in the longitudinal z direction. Preferably, the length z dimension l1 of region LA, in which the amount of voids in the dielectric layer 14a2 at the longitudinal end is less than the amount of voids in the dielectric layer 14a1 at the longitudinal center, is 10% or less of the length z dimension l0 of the inner layer 16.

[0023] Furthermore, as shown in Figure 4(b), the internal dielectric layer 14a has a central dielectric layer 14a3 located in the central region of the inner layer 16 in the width direction y, and an end dielectric layer 14a4 located in the end region of the inner layer 16 in the width direction y. The amount of voids contained in the end dielectric layer 14a4 is less than the amount of voids contained in the central dielectric layer 14a3. Note that the internal electrode layer 20 is not shown in Figure 4(b).

[0024] The difference between the area occupancy PCW of the voids in the WT cross-section of the dielectric layer 14a3 on the width central side and the area occupancy PEW of the voids in the WT cross-section of the dielectric layer 14a4 on the width edge side is preferably 0.5% or more and 8.0% or less.

[0025] Region WA, in which the amount of voids in the dielectric layer 14a4 at the widthwise end is less than the amount of voids in the dielectric layer 14a3 at the widthwise center, is located in the interior region of the inner layer 16 from both ends in the widthwise y direction. Preferably, the dimension w1 in the widthwise y direction of region WA, in which the amount of voids in the dielectric layer 14a4 at the widthwise end is less than the amount of voids in the dielectric layer 14a3 at the widthwise center, is 15% or less of the dimension w0 in the widthwise y direction of the inner layer 16.

[0026] The method for measuring voids is as follows. A cross-sectional image of the laminate 12 is acquired using a scanning electron microscope (SEM), and the ceramic filling and void areas are binarized. The porosity is then defined as the ratio of the area occupied by the voids to the total area of ​​the binarized image.

[0027] The first outer layer 18a is located on the side of the first main surface 12a of the laminate 12 and is an assembly of multiple outer dielectric layers 14b, which are multiple dielectric layers 14 located between the first main surface 12a and the internal electrode layer 20 closest to the first main surface 12a. The second outer layer 18b is located on the second main surface 12b side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b, which are multiple dielectric layers 14 located between the second main surface 12b and the internal electrode layer 20 closest to the second main surface 12b. The region sandwiched between the first outer layer 18a and the second outer layer 18b is the inner layer 16.

[0028] The dimensions of the laminate 12 are not particularly limited, but it is preferable that the length z dimension is 0.95 mm or more and 3.1 mm or less, the width y dimension is 0.49 mm or more and 2.47 mm or less, and the height x dimension is 0.49 mm or more and 2.47 mm or less.

[0029] The dielectric layer 14 can be formed from, for example, a dielectric material. As the dielectric material, for example, a dielectric ceramic containing a main component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 can be used. When the above dielectric material is included as the main component, depending on the desired properties of the laminate 12, a material with a lower content of minor components than the main component, such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds, may be used.

[0030] The thickness of the dielectric layer 14 after firing is preferably 0.5 μm or more and 10 μm or less.

[0031] The number of dielectric layers 14 to be stacked is preferably 50 to 1000.

[0032] The first internal electrode layer 20a is arranged on a plurality of dielectric layers 14 and is located inside the laminate 12. The first internal electrode layer 20a has a first opposing electrode portion 22a facing the second internal electrode layer 20b, and a first leading electrode portion 24a located on one end side of the first internal electrode layer 20a, extending from the first opposing electrode portion 22a to the first end face 12e of the laminate 12. The end of the first leading electrode portion 24a is led out to the surface of the first end face 12e and exposed from the laminate 12. In other words, the end of the first leading electrode portion 24a is not exposed to the first main surface 12a and the second main surface 12b, the second end face 12f, and the first side surface 12c and the second side surface 12d. In detail, the end of the first internal electrode layer 20a is slightly recessed from the second end face 12f.

[0033] The shape of the first opposing electrode portion 22a of the first internal electrode layer 20a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0034] The shape of the first lead-out electrode portion 24a of the first internal electrode layer 20a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0035] The width of the first opposing electrode portion 22a of the first internal electrode layer 20a and the width of the first leading electrode portion 24a of the first internal electrode layer 20a may be the same, or one of them may be narrower.

[0036] The second internal electrode layer 20b is arranged on a plurality of dielectric layers 14 and is located inside the laminate 12. The second internal electrode layer 20b has a second opposing electrode portion 22b facing the first internal electrode layer 20a, and a second leading electrode portion 24b located on one end side of the second internal electrode layer 20b, extending from the second opposing electrode portion 22b to the second end face 12f of the laminate 12. The end of the second leading electrode portion 24b is drawn out to the surface of the second end face 12f and exposed from the laminate 12. In other words, the end of the first leading electrode portion 24a is not exposed to the first main surface 12a and the second main surface 12b, the first end face 12e, and the first side surface 12c and the second side surface 12d. In detail, the end of the second internal electrode layer 20b is slightly recessed from the first end face 12e.

[0037] The shape of the second opposing electrode portion 22b of the second internal electrode layer 20b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0038] The shape of the second lead-out electrode portion 24b of the second internal electrode layer 20b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0039] The width of the second opposing electrode portion 22b of the second internal electrode layer 20b and the width of the second leading electrode portion 24b of the second internal electrode layer 20b may be the same, or one of them may be narrower.

[0040] The laminate 12 includes a side portion of the laminate 12 (hereinafter referred to as the "W gap") 26a formed between one end in the width direction y of the first opposing electrode portion 22a and the second opposing electrode portion 22b and the first side surface 12c, and between the other end in the width direction y of the first opposing electrode portion 22a and the second opposing electrode portion 22b and the second side surface 12d. Furthermore, the laminate 12 includes an end portion of the laminate 12 (hereinafter referred to as the "L gap") 26b formed between the end of the first internal electrode layer 20a opposite to the first extraction electrode portion 24a and the second end surface 12f, and between the end of the second internal electrode layer 20b opposite to the second extraction electrode portion 24b and the first end surface 12e.

[0041] The internal electrode layer 20 can be made of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. The internal electrode layer 20 may further contain dielectric particles of the same composition as the ceramics contained in the dielectric layer 14.

[0042] The thickness of the internal electrode layer 20 is preferably 0.2 μm or more and 2.0 μm or less.

[0043] Furthermore, it is preferable that the total number of the first internal electrode layer 20a and the second internal electrode layer 20b is between 50 and 1000.

[0044] Furthermore, the laminated body 12 shown in Figure 1, as shown in Figure 5, is provided with a floating internal electrode layer 20c that is not extended from either the first end face 12e or the second end face 12f, in addition to the first internal electrode layer 20a and the second internal electrode layer 20b, and the floating internal electrode layer 20c divides the opposing electrode portion 22 into multiple parts. For example, there is a two-unit structure as shown in Figure 5(a), a three-unit structure as shown in Figure 5(b), and a four-unit structure as shown in Figure 5(c), and it goes without saying that structures with four or more units are also possible. By dividing the opposing electrode portion 22 into multiple parts in this way, multiple capacitor components are formed between the opposing first internal electrode layer 20a, the second internal electrode layer 20b, and the floating internal electrode layer 20c, and these capacitor components are connected in series. As a result, the voltage applied to each capacitor component becomes lower, and the voltage withstand capability of the multilayer ceramic capacitor 10 can be increased.

[0045] Furthermore, the floating internal electrode layer 20c, like the first internal electrode layer 20a and the second internal electrode layer 20b, can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0046] External electrodes 30 are arranged on the first end face 12e and the second end face 12f of the laminate 12, as shown in Figures 1 to 3.

[0047] The external electrode 30 includes a base electrode layer 32 containing a metal component and glass, and a plating layer 34 disposed on the surface of the base electrode layer 32.

[0048] The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

[0049] The first external electrode 30a is connected to the first internal electrode layer 20a and is positioned on at least the surface of the first end face 12e. The first external electrode 30a also extends from the first end face 12e of the laminate 12 and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first lead-out electrode portion 24a of the first internal electrode layer 20a.

[0050] The second external electrode 30b is connected to the second internal electrode layer 20b and is positioned on at least the surface of the second end face 12f. The second external electrode 30b also extends from the second end face 12f of the laminate 12 and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second lead-out electrode portion 24b of the second internal electrode layer 20b.

[0051] Within the laminate 12, capacitance is formed when the first opposing electrode portion 22a of the first internal electrode layer 20a and the second opposing electrode portion 22b of the second internal electrode layer 20b face each other via the dielectric layer 14. As a result, capacitance can be obtained between the first external electrode 30a to which the first internal electrode layer 20a is connected and the second external electrode 30b to which the second internal electrode layer 20b is connected, and the characteristics of a capacitor are exhibited.

[0052] The base electrode layer 32 has a first base electrode layer 32a and a second base electrode layer 32b.

[0053] The first base electrode layer 32a is connected to the first internal electrode layer 20a and is positioned on the surface of the first end face 12e. The first base electrode layer 32a also extends from the first end face 12e and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the first base electrode layer 32a is electrically connected to the first lead-out electrode portion 24a of the first internal electrode layer 20a.

[0054] The second base electrode layer 32b is connected to the second internal electrode layer 20b and is positioned on the surface of the second end face 12f. The second base electrode layer 32b also extends from the second end face 12f and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the second base electrode layer 32b is electrically connected to the second lead-out electrode portion 24b of the second internal electrode layer 20b.

[0055] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, and a thin film layer, etc.

[0056] The following describes the configurations when the base electrode layer 32 is the baked layer, conductive resin layer, and thin film layer described above.

[0057] (In the case of a baked-on layer) The baked layer contains a metal component and glass. The metal component of the baked layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer is formed by applying a conductive paste containing glass and metal to a laminate and baking it. The baked layer is formed by simultaneously baking a laminated chip having an internal electrode layer 20 and a dielectric layer 14 and the conductive paste applied to the laminated chip, but it may also be baked after baking the laminated chip having the internal electrode layer 20 and the dielectric layer 14. The baked layer may consist of multiple layers.

[0058] The thickness in the longitudinal direction z connecting the first end face 12e and the second end face 12f at the center of the first base electrode layer 32a located at the first end face 12e in the height direction x is preferably, for example, 10 μm or more and 150 μm or less.

[0059] The thickness of the second base electrode layer 32b located at the second end face 12f in the length direction z connecting the first end face 12e and the second end face 12f at the center of the height direction x is preferably, for example, 10 μm or more and 150 μm or less.

[0060] The thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center of the length direction z connecting the first end surface 12e and the second end surface 12f of the first underlay electrode layer 32a, which is located in a part of the first main surface 12a and the second main surface 12b, is preferably, for example, 10 μm or more and 100 μm or less.

[0061] Furthermore, the thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center of the length direction z connecting the first end surface 12e and the second end surface 12f of the second underlay electrode layer 32b, which is located in a part of the first main surface 12a and the second main surface 12b, is preferably, for example, 10 μm or more and 100 μm or less.

[0062] The thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z connecting the first end surface 12e and the second end surface 12f of the first underlay electrode layer 32a, which is located in a part of the first side surface 12c and the second side surface 12d, is preferably, for example, 10 μm or more and 100 μm or less.

[0063] Furthermore, the thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z connecting the first end surface 12e and the second end surface 12f of the second underlay electrode layer 32b located in a part of the first side surface 12c and the second side surface 12d is preferably, for example, 10 μm or more and 100 μm or less.

[0064] (In the case of a conductive resin layer) The conductive resin layer comprises a first conductive resin layer and a second conductive resin layer.

[0065] Preferably, the first conductive resin layer is arranged as a first base electrode layer 32a, further covering other layers such as a baking layer, and preferably, the second conductive resin layer is arranged as a second base electrode layer 32b, further covering other layers such as a baking layer.

[0066] Specifically, it is preferable that the first conductive resin layer and the second conductive resin layer are arranged as the first base electrode layer 32a and the second base electrode layer 32b, respectively, on top of other layers such as baking layers located on the first end face 12e and the second end face 12f, and also extend onto other layers such as baking layers located on the first main surface 12a and the second main surface 12b, as well as the first side surface 12c and the second side surface 12d. However, the first conductive resin layer and the second conductive resin layer may be arranged only on other layers such as baking layers located on the first end face 12e and the second end face 12f.

[0067] The thickness of the first conductive resin layer and the second conductive resin layer is preferably, for example, 10 μm to 200 μm.

[0068] The first conductive resin layer and the second conductive resin layer each contain a thermosetting resin and a metal component.

[0069] Because the first and second conductive resin layers contain thermosetting resins, they are more flexible than, for example, the base electrode layer 32 which is made of a plated film or a fired conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layers function as buffer layers, preventing cracks in the multilayer ceramic capacitor 10.

[0070] Specific examples of thermosetting resins include various known thermosetting resins such as epoxy resins, phenolic resins, urethane resins, silicone resins, and polyimide resins. Among these, epoxy resins, which have excellent heat resistance, moisture resistance, and adhesion, are among the most suitable resins.

[0071] The first conductive resin layer and the second conductive resin layer preferably contain a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, and imidazole compounds can be used as curing agents for the epoxy resin.

[0072] The metals contained in the first and second conductive resin layers can be Ag, Cu, or alloys thereof. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating on its surface, it is preferable to use Cu or Ni as the metal powder.

[0073] Alternatively, copper treated with an anti-oxidation process can be used. The reason for using an Ag-coated metal is that it allows for the use of a less expensive base metal while maintaining the aforementioned properties of Ag.

[0074] Preferably, the metal contained in the first conductive resin layer and the second conductive resin layer is present in an amount of 35 vol% to 75 vol% relative to the total volume of the conductive resin.

[0075] The shape of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited. The conductive filler may be spherical, flattened, or the like.

[0076] The average particle size of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, 0.3 μm to 10 μm.

[0077] The metals contained in the first and second conductive resin layers are primarily responsible for the conductivity of the conductive resin layers. Specifically, conductive paths are formed within the conductive resin layers through contact between the conductive fillers.

[0078] The metals contained in the first conductive resin layer and the second conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical metal powder and flattened metal powder.

[0079] The conductive resin layer may be formed directly on the laminate without forming a baking layer.

[0080] Next, the first plating layer 34a and the second plating layer 34b, which are plating layers 34 placed on the base electrode layer 32, will be described with reference to Figures 2 and 3.

[0081] The first plating layer 34a and the second plating layer 34b include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0082] The first plating layer 34a is positioned to completely cover the first underlay electrode layer 32a. The second plating layer 34b is positioned to completely cover the second under electrode layer 32b.

[0083] The first plating layer 34a and the second plating layer 34b may be formed from multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of a lower plating layer (Ni plating layer) formed on the base electrode layer 32 using Ni plating, and an upper plating layer (Sn plating layer) formed on the lower plating layer using Sn plating. In other words, in this case, the first plating layer 34a has a first lower plating layer 36a and a first upper plating layer 38a located on the surface of the first lower plating layer 36a. Furthermore, the second plating layer 34b has a second lower plating layer 36b and a second upper plating layer 38b located on the surface of the second lower plating layer 36b.

[0084] The lower plating layer 36 made of Ni is used to prevent the underlying electrode layer 32 from being corroded by the solder when mounting the multilayer ceramic capacitor 10, and the upper plating layer 38 made of Sn is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, making it easier to mount. The thickness of each plating layer of the lower plating layer 36 and the upper plating layer 38 is preferably 1.0 μm or more and 15.0 μm or less.

[0085] The length z dimension of the multilayer ceramic capacitor 10, including the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension L. The height x dimension of the multilayer ceramic capacitor 10, including the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension T. The width y dimension of the multilayer ceramic capacitor 10, including the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are as follows: the length (L) in the z direction is 1.0 mm to 3.2 mm; the width (W) in the y direction is 0.5 mm to 2.5 mm; and the height (T) in the x direction is 0.5 mm to 2.5 mm. Furthermore, the dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0086] If voids exist in the dielectric layer 14, the mechanical strength is lower compared to the region where ceramic is filled within the dielectric layer 14. Therefore, if voids exist at locations where electrostrictive stress is concentrated, electrostrictive cracks will occur in the dielectric layer 14 starting from these voids. Electrostriction is most likely to occur at the edges of the dielectric layer 14 in the width direction y within the inner layer portion 16 of the laminate 12.

[0087] In the multilayer ceramic capacitor 10 shown in Figure 1, the amount of voids near the ends of the dielectric layer 14 in the longitudinal direction z, which are located within the inner layer 16 of the laminate 12 where electrostrictive stress is concentrated, is reduced compared to the amount of voids in the central part of the longitudinal direction z. Specifically, the amount of voids contained in the dielectric layer 14a2 on the longitudinal end side is less than the amount of voids contained in the dielectric layer 14a1 on the longitudinal central side. This makes it possible to reduce the occurrence of electrostrictive cracks.

[0088] Furthermore, in the multilayer ceramic capacitor 10 shown in Figure 1, the amount of voids contained in the dielectric layer 14a2 at the longitudinal end is less than the amount of voids contained in the dielectric layer 14a1 at the longitudinal center. This improves the sinterability of the ceramic, and the shrinkage rate of the dielectric layer 14a2 at the longitudinal end increases the amount of exposure of the internal electrode layer 20, thereby improving contact with the external electrode 30. This significantly reduces the occurrence of electrostrictive cracks.

[0089] Furthermore, in the multilayer ceramic capacitor 10 shown in Figure 1, if the difference between the area occupancy ratio PCL of the voids in the LT cross-section of the dielectric layer 14a1 on the longitudinal central side and the area occupancy ratio PEL of the voids in the LT cross-section of the dielectric layer 14a2 on the longitudinal end side is between 2.0% and 8.0%, the occurrence of electrostrictive cracks can be further reduced.

[0090] Furthermore, in the multilayer ceramic capacitor 10 shown in Figure 1, if the amount of voids contained in the dielectric layer 14a4 on the widthwise end side is less than the amount of voids contained in the dielectric layer 14a3 on the widthwise central side, a significant effect of reducing the occurrence of electrostrictive cracks can be obtained.

[0091] Furthermore, in the multilayer ceramic capacitor 10 shown in Figure 1, if the difference between the area occupancy rate PCW of the voids in the WT cross-section of the dielectric layer 14a3 on the width central side and the area occupancy rate PEW of the voids in the WT cross-section of the dielectric layer 14a4 on the width edge side is between 0.5% and 8.0%, the effect of reducing the occurrence of electrostrictive cracks can be obtained more significantly.

[0092] 2. Manufacturing method of multilayer ceramic capacitors Next, we will explain the manufacturing method of multilayer ceramic capacitors.

[0093] First, a ceramic green sheet for the dielectric layer and a conductive paste for the internal electrode layer are prepared. The ceramic green sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and solvent may be known.

[0094] Then, a conductive paste for the internal electrode layer is printed on the ceramic green sheet for the dielectric layer in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a ceramic green sheet with the pattern for the first internal electrode layer formed on it, and a ceramic green sheet with the pattern for the second internal electrode layer formed on it.

[0095] (Process for obtaining laminated sheets) Next, a predetermined number of ceramic green sheets for the outer layer, which do not have the pattern of the internal electrode layer printed on them, are laminated to form a second outer layer portion on the second main surface side. Then, a ceramic green sheet with the pattern of the first internal electrode layer printed on it, and a ceramic green sheet with the pattern of the second internal electrode layer printed on it, are sequentially laminated on the second outer layer portion in a manner consistent with the structure of the present invention to form an inner layer portion. A predetermined number of ceramic green sheets for the outer layer, which do not have the pattern of the internal electrode layer printed on it, are laminated on this inner layer portion to form a first outer layer portion on the first main surface side. This completes the production of the laminated sheet.

[0096] (Process for obtaining laminated blocks) Next, a laminated block is produced by pressing the laminated sheets in the lamination direction using means such as a hydrostatic press.

[0097] (Process for obtaining stacked chips) Then, the laminated block is cut to a predetermined size, thereby producing laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0098] (Process for obtaining a laminate) Next, the laminated chips are fired to create a laminate. At this time, the heat distribution of the firing furnace during heat treatment is adjusted so that the amount of heat applied to the center of the laminated chip in the longitudinal direction z is less than the amount of heat applied to the ends of the laminated chip in the longitudinal direction z. In this way, the ceramic filling density is higher at the ends of the laminate in the longitudinal direction z than at the center of the laminate in the longitudinal direction z, and the amount of voids at the ends of the laminate in the longitudinal direction z can be made smaller than the amount of voids at the center of the laminate in the longitudinal direction z. The firing temperature depends on the temperature of the dielectric layer and the internal electrode layer, but it is preferably between 900°C and 1400°C.

[0099] Next, a conductive paste for the base electrode layer, containing metal and glass components, is prepared.

[0100] (Process for forming external electrodes) A conductive paste, which will serve as the base electrode layer, is applied to both ends of the laminate to form the base electrode layer. Methods such as dipping or screen printing can be used to apply the conductive paste to both ends of the laminate. The temperature during this baking process is preferably between 700°C and 900°C.

[0101] Next, if necessary, plating is applied to the surface of the base electrode layer to form a plating layer. In this embodiment, two plating layers are formed on the surface of the base electrode layer. Specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by a barrel plating method.

[0102] As described above, the multilayer ceramic capacitor 10 according to this embodiment is manufactured.

[0103] According to the manufacturing method of a multilayer ceramic capacitor according to the present invention, the ceramic filling density is higher at the ends of the multilayer in the longitudinal direction z than at the center of the multilayer in the longitudinal direction z, and the amount of voids at the ends of the multilayer in the longitudinal direction z can be reduced to less than the amount of voids at the center of the multilayer in the longitudinal direction z. As a result, a multilayer ceramic capacitor can be obtained that can reduce the crack occurrence rate of electrostrictive cracks.

[0104] 3. Experimental Examples Next, in order to confirm the effect of the multilayer ceramic capacitor according to the present invention described above, a multilayer ceramic capacitor sample was prepared according to the manufacturing method described above, and an experiment was conducted to check for the presence or absence of cracks due to electrostriction.

[0105] (1) Specification of the sample in the experimental example First, according to the manufacturing method of the multilayer ceramic capacitor described above, samples of multilayer ceramic capacitors according to Examples 1 to 10 and the Comparative Example were prepared with the following specifications.

[0106] (Specifications of multilayer ceramic capacitors) • Dimensions of the multilayer ceramic capacitor (design value): L × W × T = 1.6 mm × 0.8 mm × 0.8 mm • Main component of the dielectric layer: Ceramic material: BaTiO3 ·Capacity: 22μF • Rated voltage: 16V • Material of the internal electrode layer: Ni • Structure of the external electrode: conductive metal (Cu) and glass component • Film thickness at the center of the height direction of the first and second end faces of the external electrode: approximately 90 μm • Plating layer Formation of a two-layer structure consisting of a Ni plating layer and a Sn plating layer. Ni plating layer thickness: approximately 3 μm Sn plating layer thickness: approximately 5 μm

[0107] (2) Method for evaluating crack occurrence Electrostrictive testing of each multilayer ceramic capacitor sample was performed using a breakdown voltage measuring device. The detailed conditions for the breakdown voltage measuring device were that the voltage was boosted to DC 150V at a boosting rate of 100V / sec. This evaluation involved observing the presence or absence of cracks using an ultrasonic flaw detection device. Specifically, first, the multilayer ceramic capacitor samples were aligned so that their main surfaces faced upwards. Next, ultrasonic waves were irradiated onto the upper surfaces of the aligned multilayer ceramic capacitors using an ultrasonic probe, and scanning was performed. The reflected waves of the ultrasonic waves were observed, and the presence or absence of cracks was confirmed by detecting the reflected waves that returned earlier than the bottom waves. Here, samples in which cracks were confirmed were counted as electrostrictive defects, and the crack occurrence rate was calculated. For each example and comparative example, 100 samples were prepared, and the crack occurrence rate was measured. The crack occurrence rate was defined as the percentage of the total number of samples measured (100) and the number of cracks. The criteria for judging the crack occurrence rate were as follows: 0% to 10% was marked "◎", 11% to 30% was marked "〇", 31% to 50% was marked "△", and 51% to 100% was marked "×".

[0108] (3) Results Table 1 shows the crack occurrence rates of the dielectric layers of the laminates for Examples 1 to 10 and the comparative examples.

[0109] [Table 1]

[0110] According to Table 1, in each of the samples from Examples 1 to 10, the amount of voids contained in the dielectric layer on the longitudinal end side was less than the amount of voids contained in the dielectric layer on the longitudinal center side, resulting in a good crack occurrence rate of 50% or less.

[0111] Furthermore, in each of the samples from Examples 2 to 5, the difference between the area occupancy ratio PCL of the voids in the LT cross-section of the dielectric layer on the longitudinal central side and the area occupancy ratio PEL of the voids in the LT cross-section of the dielectric layer on the longitudinal end side was between 2.0% and 8.0%, resulting in a better crack occurrence rate of between 11% and 30%.

[0112] Furthermore, in each sample from Example 7 to Example 10, the difference between the area occupancy PCW of voids in the WT cross-section of the dielectric layer on the widthwise central side and the area occupancy PEW of voids in the WT cross-section of the dielectric layer on the widthwise edge side was between 0.5% and 8.0%, resulting in an even better crack occurrence rate of 10% or less.

[0113] On the other hand, in the comparative example, the amount of voids contained in the dielectric layer at the longitudinal end was greater than the amount of voids contained in the dielectric layer at the longitudinal center, resulting in a crack occurrence rate of 72%.

[0114] From the above results, it is suggested that in the present invention, the inner layer of the laminate is composed of an internal dielectric layer, which contains voids, and the amount of voids contained in the dielectric layer at the longitudinal end, where the internal dielectric layer is located in the longitudinal central region of the inner layer, is less than the amount of voids contained in the dielectric layer at the longitudinal central region. This reduces the amount of voids near the longitudinal ends of the dielectric layer within the inner layer of the laminate, which are areas where electrostrictive stress is concentrated, and thus reduces the occurrence of electrostrictive cracks.

[0115] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto.

[0116] In other words, various modifications can be made to the embodiments described above with respect to the mechanism, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and objectives of the present invention, and these modifications are included in the present invention. [Explanation of symbols]

[0117] 10 Multilayer ceramic capacitors 12-layer structure 12a First main surface 12b Second main surface 12c First side 12d Second aspect 12e First end face 12f Second end face 14 Dielectric layer 14a Internal dielectric layer 14a1 Dielectric layer on the central side in the longitudinal direction 14a2 End-side dielectric layer in the longitudinal direction 14a3 Dielectric layer in the central part in the width direction 14a4 End-side dielectric layer in the width direction 14b External dielectric layer 16 Inner layer 18a First outer layer 18b Second outer layer 20 Internal electrode layer 20a First internal electrode layer 20b Second internal electrode layer 20c floating internal electrode layer 22 Counter electrode section 22a First counter electrode portion 22b Second counter electrode section 24a First extraction electrode section 24b Second extraction electrode section 26a Side (W gap) 26b End (L gap) 30 External electrode 30a First external electrode 30b Second external electrode 32 Base electrode layer 32a First underlay electrode layer 32b Second base electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 36 Lower plating layer 36a First lower plating layer 36b Second lower plating layer 38 Upper plating layer 38a First upper plating layer 38b Second upper plating layer Region where voids are located within the dielectric layer at the widthwise end. Region where voids are located in the dielectric layer at the longitudinal end of LA. x Height direction (Stacking direction) y width direction z-length direction

Claims

1. It includes multiple stacked dielectric layers and multiple stacked internal electrode layers, The plurality of dielectric layers include a first main surface and a second main surface facing each other in the height direction, which is the stacking direction of the plurality of dielectric layers; a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction; and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction. An inner layer portion formed by alternately stacking the dielectric layer and the internal electrode layer, A laminate including an outer layer portion arranged to sandwich the inner layer portion from the first main surface side and the second main surface side, A first external electrode disposed on the first end face, A second external electrode disposed on the second end face, In a multilayer ceramic capacitor having, The inner layer is composed of an internal dielectric layer among a plurality of dielectric layers arranged in the inner layer. The aforementioned internal dielectric layer contains voids, The internal dielectric layer comprises a dielectric layer located in the central region in the longitudinal direction of the inner layer, and a dielectric layer located in the end region in the longitudinal direction of the inner layer, It has, A multilayer ceramic capacitor in which the amount of voids contained in the dielectric layer on the longitudinal end side is less than the amount of voids in the dielectric layer on the longitudinal central side.

2. The multilayer ceramic capacitor according to claim 1, wherein the difference between the area occupancy ratio PCL of the voids in the LT cross-section of the dielectric layer on the longitudinal central side and the area occupancy ratio PEL of the voids in the LT cross-section of the dielectric layer on the longitudinal end side is 2.0% or more and 8.0% or less.

3. The internal dielectric layer further comprises a dielectric layer located in the central region in the width direction of the inner layer, and a dielectric layer located in the end region in the width direction of the inner layer, The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the amount of voids in the dielectric layer on the widthwise end side is less than the amount of voids in the dielectric layer on the widthwise central side side.

4. The multilayer ceramic capacitor according to claim 3, wherein the difference between the area occupancy PCW of the voids in the WT cross-section of the dielectric layer on the width central side and the area occupancy PEW of the voids in the WT cross-section of the dielectric layer on the width edge side is 0.5% or more and 8.0% or less.

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