Manufacturing method of wiring boards
Patent Information
- Application Number
- JP2025061722
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2026-10-16
Smart Images

Figure 2026168557000001_ABST
Abstract
Description
Technical Field
[0001] The technology disclosed in the present specification relates to a method for manufacturing a wiring board.
Background Art
[0002] Patent Document 1 discloses a method for manufacturing a heat-resistant board-embedded circuit wiring board that incorporates a heat-resistant board. Patent Document 1 manufactures a heat-resistant board that includes a core substrate made of Si, through-hole conductors penetrating the core substrate, and conductor circuits and an insulating layer formed on the core substrate. In Patent Document 1, the heat-resistant board is attached to a support. Thereafter, Patent Document 1 forms an interlayer resin insulating layer on the heat-resistant board and on the support exposed from the heat-resistant board.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
[0004] [Problem of Patent Document 1] In Patent Document 1, the heat-resistant board is composed of a core substrate made of Si, and through-hole conductors, conductor circuits, and an insulating layer formed of members other than Si. The heat-resistant board is formed of different members. The core substrate in the heat-resistant board is considered to be prone to warping. When the heat-resistant board is attached to the support, the core substrate is considered to receive a large force. As a result, the core substrate in the heat-resistant board is considered to be prone to cracking.
Means for Solving the Problem
[0005] The present invention provides a method for manufacturing a wiring board, comprising: preparing a support; forming a metal layer on the support; forming a fourth conductor layer on the metal layer; forming a resin insulating layer having a third surface and a fourth surface opposite to the third surface on the fourth conductor layer and the metal layer such that the fourth surface and the fourth conductor layer face each other; forming a glass layer having a first surface and a second surface opposite to the first surface on the resin insulating layer such that the second surface and the third surface face each other; forming an opening for a via conductor that penetrates the glass layer and the resin insulating layer and exposes the fourth conductor layer; and forming a via conductor that connects to the fourth conductor layer within the opening for the via conductor. [Brief explanation of the drawing]
[0006] [Figure 1] A schematic cross-sectional view showing the wiring board of the embodiment. [Figure 2A] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2B] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2C] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2D] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2E] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2F] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2G] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2H] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Modes for carrying out the invention]
[0007] [Embodiment] Figure 1 is a cross-sectional view showing a wiring board 2 of an embodiment. As shown in Figure 1, the wiring board 2 has a core board 4 and a build-up portion 300 on the core board 4.
[0008] The core substrate 4 has a glass layer 30, a resin insulating layer 20, a resin 50, a first conductor layer 60, a fourth conductor layer 10, and a via conductor 70. The glass layer 30 has a first surface 32 and a second surface 34 opposite to the first surface 32. The glass layer 30 is made of glass. The resin insulating layer 20 has a third surface 22 and a fourth surface 24 opposite to the third surface 22. The resin insulating layer 20 is formed on the second surface 34 of the glass layer 30 such that the third surface 22 and the second surface 34 face each other. The third surface 22 is in contact with the second surface 34. The resin insulating layer 20 is made of resin and a large number of inorganic particles dispersed within the resin. The resin is an epoxy resin. Examples of resins are thermosetting resins and photocurable resins. Examples of inorganic particles are silica and alumina.
[0009] The resin 50 is in contact with the side surface of the glass layer 30 and the side surface of the resin insulating layer 20, and surrounds the glass layer 30 and the resin insulating layer 20. The resin 50 has a fifth surface 52 and a sixth surface 54 opposite to the fifth surface 52. The fifth surface 52 is substantially coplanar with the first surface 32 of the glass layer 30. The fifth surface 52 and the first surface 32 form a substantially coplanar plane. The sixth surface 54 is substantially coplanar with the fourth surface 24 of the resin insulating layer 20. The sixth surface 54 and the fourth surface 24 form a substantially coplanar plane. The resin 50 is not formed on the first surface 32 of the glass layer 30. The resin 50 is not formed on the fourth surface 24 of the resin insulating layer 20. The resin 50 is an epoxy resin. Examples of resin 50 are thermosetting resins and photocurable resins. The resin 50 does not contain fibrous reinforcing materials. The resin 50 does not contain inorganic particles. Alternatively, the resin 50 may contain inorganic particles. Examples of inorganic particles are silica and alumina.
[0010] The first conductor layer 60 is formed on the first surface 32 of the glass layer 30. The first conductor layer 60 is formed of a seed layer 60a and an electroplating layer 60b on the seed layer 60a.
[0011] The fourth conductor layer 10 is formed on the fourth surface 24 of the resin insulating layer 20. The fourth conductor layer 10 is embedded in the resin insulating layer 20. The fourth conductor layer 10 is formed of an electrolytic plating layer 10b. The fourth conductor layer 10 is the outermost conductor layer on the mounting side. The fourth conductor layer 10 includes electrodes for mounting electronic components.
[0012] The via conductor 70 is formed within a via conductor opening 40 that simultaneously penetrates the glass layer 30 and the resin insulating layer 20. The via conductor 70 connects the first conductor layer 60 and the fourth conductor layer 10. The via conductor 70 is formed of a seed layer 60a and an electroplating layer 60b on the seed layer 60a. The seed layer 60a forming the via conductor 70 and the seed layer 60a forming the first conductor layer 60 are common. The electroplating layer 60b forming the via conductor 70 and the electroplating layer 60b forming the first conductor layer 60 are common. The seed layer 60a forming the via conductor 70 is formed on the inner wall surface of the via conductor opening 40 and on the fourth conductor layer 10 exposed from the via conductor opening 40. The electroplating layer 60b forming the via conductor 70 fills the via conductor opening 40. When the via conductor 70 is formed by the bottom-up method, the seed layer 60a may be omitted. When the via conductor 70 is formed by the bottom-up method, the via conductor 70 is formed only of the electroplating layer 60b. When the via conductor 70 is formed by the bottom-up method, the first conductor layer 60 is formed only of the electroplating layer 60b. The first conductor layer 60 does not include the seed layer 60a.
[0013] The build-up portion 300 is formed on the first surface 32 of the glass layer 30, the fifth surface 52 of the resin 50, and the first conductor layer 60. The build-up portion 300 has a first build-up portion 100 formed on the first surface 32, the fifth surface 52, and the first conductor layer 60, and a second build-up portion 200 formed on the first build-up portion 100.
[0014] The first build-up section 100 has resin insulating layers 110, 140, conductor layers 120, 150, and via conductors 130, 160. The first build-up section 100 in Figure 1 has two resin insulating layers 110, 140, two conductor layers 120, 150, and via conductors 130, 160 that penetrate each of the resin insulating layers 110, 140. The number of resin insulating layers in the first build-up section 100 may be one or three or more. The number of conductor layers in the first build-up section 100 may be one or three or more. The resin insulating layer 110 is formed on the first surface 32, the fifth surface 52, and the first conductor layer 60. The resin insulating layer 110 is formed using a thermosetting resin. An example of a thermosetting resin is epoxy resin. The resin insulating layer 110 contains inorganic particles such as silica. The resin insulating layer 110 does not contain reinforcing materials made of fibers. The conductor layer 120 is formed on the resin insulating layer 110. The via conductor 130 is formed within an opening that penetrates the resin insulating layer 110. The via conductor 130 connects the first conductor layer 60 and the conductor layer 120. The embodiment does not require the formation of the first conductor layer 60. In that case, the embodiment does not have the first conductor layer 60. The via conductor 130 is directly connected to the via conductor 70. The via conductor 130 connects the via conductor 70 and the conductor layer 120. The conductor layer 120 and the via conductor 130 are formed from a common seed layer 120a and electroplating layer 120b. The resin insulating layer 140 is formed on the resin insulating layer 110 and the conductor layer 120. The resin insulating layer 140 is formed from the same material as the resin insulating layer 110. The conductor layer 150 is formed on the resin insulating layer 140. The via conductor 160 is formed within an opening that penetrates the resin insulating layer 140. The via conductor 160 connects the conductor layer 120 and the conductor layer 150. The conductor layer 150 and the via conductor 160 are formed from a common seed layer 150a and electroplating layer 150b.
[0015] The second build-up section 200 has resin insulating layers 210, 240, conductor layers 220, 250, and via conductors 230, 260. The second build-up section 200 in Figure 1 has two resin insulating layers 210, 240, two conductor layers 220, 250, and via conductors 230, 260 that penetrate each of the resin insulating layers 210, 240. The number of resin insulating layers in the second build-up section 200 may be one or three or more. The number of conductor layers in the second build-up section 200 may be one or three or more. The resin insulating layer 210 is formed on the resin insulating layer 140 and conductor layer 150 in the first build-up section 100. The resin insulating layer 210 is formed using a thermosetting resin. An example of a thermosetting resin is epoxy resin. The resin insulating layer 210 includes a reinforcing material made of fibers. An example of a reinforcing material is glass cloth. The resin insulating layer 210 may also include inorganic particles such as silica. The conductor layer 220 is formed on the resin insulating layer 210. The via conductor 230 is formed in an opening that penetrates the resin insulating layer 210. The via conductor 230 connects the conductor layer 150 and the conductor layer 220 in the first build-up section 100. The conductor layer 220 and the via conductor 230 are formed of a common seed layer 220a and electroplating layer 220b. The resin insulating layer 240 is formed on the resin insulating layer 210 and the conductor layer 220. The resin insulating layer 240 is made of the same material as the resin insulating layer 210. The conductor layer 250 is formed on the resin insulating layer 240. The conductor layer 250 is the outermost conductor layer on the side opposite to the mounting surface. The conductor layer 250 has electrodes for connecting to a printed circuit board or package substrate. The via conductor 260 is formed in an opening that penetrates the resin insulating layer 240. The via conductor 260 connects the conductor layer 220 and the conductor layer 250. The conductor layer 250 and the via conductor 260 are formed from a common seed layer 250a and electroplating layer 250b.
[0016] The thickness of the resin insulating layers 210, 240 in the second build-up section 200 is greater than the thickness of the resin insulating layers 110, 140 in the first build-up section 100. The thickness of each resin insulating layer corresponds to the distance between adjacent conductor layers. The thickness of the conductor layers 220, 250 in the second build-up section 200 is greater than the thickness of the conductor layers 120, 150 in the first build-up section 100. When the number of via conductors penetrating one resin insulating layer in the first build-up section 100 and the number of via conductors penetrating one resin insulating layer in the second build-up section 200 are compared, the number of via conductors 230, 260 in the second build-up section 200 is less than the number of via conductors 130, 160 in the first build-up section 100. The diameter of the openings for via conductors in the first build-up section 100 is smaller than the diameter of the openings for via conductors in the second build-up section 200.
[0017] In the wiring board of the embodiment, the first surface 32 of the glass layer 30 and the fifth surface 52 of the resin 50 form substantially the same plane. In the embodiment, the build-up section 300 is formed on the substantial plane formed by the first surface 32 and the fifth surface 52. Therefore, the embodiment can form fine wiring in the build-up section 300. Cracks are less likely to occur in the resin insulating layer in the build-up section 300.
[0018] [Method for manufacturing the wiring board 2 of the embodiment] (FIG. 2A to FIG. 2H show the method for manufacturing the wiring board 2 of the embodiment. FIG. 2A to FIG. 2H are cross-sectional views. A support 6 is prepared. A metal layer 8 is formed on the support 6. A support member composed of the support 6 and the metal layer 8 on the support 6 is prepared. The support 6 is a glass plate. The metal layer 8 is, for example, a copper foil. A plating resist is formed on the metal layer 8. An electrolytic plating layer 10b is formed by electrolytic copper plating on the metal layer 8 exposed from the plating resist. The plating resist is removed. A fourth conductor layer 10 is formed. The fourth conductor layer 10 is formed by the electrolytic plating layer 10b. As shown in FIG. 2A, a resin insulating layer 20 is formed on the metal layer 8 and the fourth conductor layer 10. The resin insulating layer 20 has a third surface 22 and a fourth surface 24 opposite to the third surface 22. The fourth surface 24 of the resin insulating layer 20 faces the fourth conductor layer 10. The fourth conductor layer 10 is embedded in the resin insulating layer 20. As shown in FIG. 2A, in this embodiment, a plurality of products are formed on the support member. FIG. 2A shows a first product area A1, a second product area A2, and a third product area A3. One product (the wiring board 2 of the embodiment) is manufactured in one product area. A gap exists between adjacent product areas. No product is formed in the gap between products. The gap between products may be referred to as a non-product area. The resin insulating layer is present in the non-product area. There is no conductor circuit for forming a conductor layer in the non-product area.
[0019] As shown in FIG. 2B, a glass layer 30 is formed on the third surface 22 of the resin insulating layer 20. The glass layer 30 has a first surface 32 and a second surface 34 opposite to the first surface 32. One glass layer 30 is laminated over the product areas and the non-product area. The glass layer 30 is formed on the third surface 22 of the resin insulating layer 20 so that all the product areas and all the non-product area are covered by the single glass layer 30. The second surface 34 of the glass layer 30 faces the third surface 22 of the resin insulating layer 20.
[0020] As shown in FIG. 2C, a metal mask 80 is formed on the first surface 32 of the glass layer 30. The metal mask 80 has openings for forming the via conductor openings 40 and the inter-product grooves 42 shown in FIG. 2D.
[0021] Reactive ion etching is performed. As shown in Figure 2D, via conductor openings 40 and inter-product grooves 42 are formed, penetrating the glass layer 30 and the resin insulating layer 20. The via conductor openings 40 expose the fourth conductor layer 10. The inter-product grooves 42 expose the metal layer 8. The via conductor openings 40 are formed within each product area A1 to A3. The inter-product grooves 42 are formed within the non-product areas. The metal mask 80 is removed.
[0022] As shown in Figure 2E, resin 50 is filled into the inter-product groove 42. The resin 50 is formed in the inter-product groove 42 that simultaneously penetrates the glass layer 30 and the resin insulating layer 20. The resin 50 does not have reinforcing materials made of fibers. The resin 50 contains inorganic particles such as silica. The resin 50 is in contact with the side surfaces of the glass layer 30 and the resin insulating layer 20, surrounding the glass layer 30 and the resin insulating layer 20. The first surface 32 of the glass layer 30 and the fifth surface 52 of the resin 50 are substantially coplanar. The fourth surface 24 of the resin insulating layer 20 and the sixth surface 54 of the resin 50 are substantially coplanar. The resin 50 is not formed on the first surface 32 of the glass layer 30. Adjacent glass layers 30 are connected by the resin 50. Glass layers 30 in adjacent products are connected by the resin 50. The glass layer 30 and resin insulating layer 20 in a single product are surrounded by the resin 50. Within a single product, the glass layer 30 and the resin insulating layer 20 are completely surrounded by resin 50.
[0023] A seed layer 60a is formed on the first surface 32 of the glass layer 30 and the fifth surface 52 of the resin 50. A seed layer 60a is formed on the inner wall surface of the via conductor opening 40 and on the fourth conductor layer 10 exposed from the via conductor opening 40. The seed layer 60a is formed of an electroless copper plating film. A plating resist is formed on the seed layer 60a. The plating resist has openings for forming the first conductor layer 60 and via conductors 70. An electrolytic plating layer 60b is formed on the seed layer 60a exposed from the plating resist by electrolytic copper plating. The electrolytic plating layer 60b fills the via conductor opening 40. The electrolytic plating layer 60b is formed of an electrolytic copper plating film. The plating resist is removed. The seed layer 60a exposed from the electrolytic plating layer 60b is removed. As shown in Figure 2F, the first conductor layer 60 and the via conductor 70 are formed simultaneously. A core substrate 4 is formed on a support member. The first conductor layer 60 and the via conductor 70 may be formed by a bottom-up method. In that case, the seed layer 60a may be omitted.
[0024] As shown in Figure 2G, a first build-up section 100 is formed on the first surface 32 of the glass layer 30, the fifth surface 52 of the resin 50, and the first conductor layer 60. The first build-up section 100 has resin insulating layers 110, 140, conductor layers 120, 150, and via conductors 130, 160. A second build-up section 200 is formed on the first build-up section 100. The second build-up section 200 has resin insulating layers 210, 240, conductor layers 220, 250, and via conductors 230, 260. Wiring boards 2 are formed in each product area A1 to A3 on the support member. A product group 3 consisting of multiple wiring boards 2 is formed on the support member. In product group 3, resin 50 is formed between adjacent wiring boards 2, and the glass layers 30 of adjacent wiring boards 2 are connected by the resin 50. In product group 3, the multiple wiring boards 2 are arranged side by side so that the resin 50 is located in a straight line.
[0025] As shown in Figure 2H, the support 6 and the metal layer 8 are removed. The product group 3 is separated from the support 6. The fourth conductor layer 10 and the fourth surface 24 of the resin insulating layer 20 are exposed.
[0026] Product group 3 is cut. The resin 50 and resin insulating layers 110, 140, 210, and 240 in the non-product area are cut. The resin 50 connecting the glass layers 30 of adjacent wiring boards 2 is cut. The product group is divided into individual wiring boards 2. Multiple wiring boards 2 are formed. The wiring board 2 in Figure 1 is, for example, a wiring board 2 formed in the first product area A1.
[0027] In the wiring board 2 of this embodiment, the first surface 32 of the glass layer 30 and the fifth surface 52 of the resin 50 form substantially the same plane. The build-up portion 300 is formed on the substantially flat surface formed by the first surface 32 and the fifth surface 52. Therefore, in this embodiment, fine wiring can be formed within the build-up portion 300. Cracks are less likely to occur in the resin insulating layer within the build-up portion 300.
[0028] In the manufacturing method of the wiring board 2 of this embodiment, a glass layer 30 is laminated on the third surface 22 of the resin insulating layer 20. The second surface 34 of the glass layer 30 faces the third surface 22 of the resin insulating layer 20. The glass layer 30 does not have any other insulating layers or conductors. Therefore, the flatness of the glass layer 30 is high. A nearly flat glass layer 30 is attached to the resin insulating layer 20. In this embodiment, the glass layer 30 can be attached to the resin insulating layer 20 with weak force. Therefore, in this embodiment, cracking of the glass layer 30 can be prevented.
[0029] When the product group is cut, the embodiment does not cut the glass layer 30. Therefore, the embodiment can prevent cracking of the glass layer 30. When the product group is cut, the support member may be bonded to the product group. In that case, the support member is removed after cutting. [Explanation of Symbols]
[0030] 2: Wiring board 3:Product group 4: Core board 6:Support 8: Metal layer 10: Fourth Conductor Layer 20: Resin insulating layer 22:Side 3 24:Side 4 30: Glass layer 32: 1st page 34:Second side 40: Opening for via conductor 42: Grooves between products 52:Side 5 54:Side 6 60: First Conductor Layer 70: Via conductor 100: First Build-up Department 200: Second Build-up Department 300: Build-up Department
Claims
1. Preparing the support structure, Forming a metal layer on the aforementioned support, Forming a fourth conductive layer on the aforementioned metal layer, A resin insulating layer having a third surface and a fourth surface opposite to the third surface is formed on the fourth conductor layer and the metal layer such that the fourth surface and the fourth conductor layer face each other. A glass layer having a first surface and a second surface opposite to the first surface is formed on the resin insulating layer such that the second surface and the third surface face each other. To form a via conductor opening that penetrates the glass layer and the resin insulating layer and exposes the fourth conductor layer, A method for manufacturing a wiring board, comprising forming a via conductor in the via conductor opening to connect to the fourth conductor layer.
2. A method for manufacturing a wiring board according to claim 1, further comprising forming a first conductor layer on the first surface, wherein the via conductor connects the first conductor layer and the fourth conductor layer.
3. A method for manufacturing a wiring board according to claim 1, wherein the fourth conductor layer is embedded in the resin insulating layer.
4. A method for manufacturing a wiring board according to claim 1, further comprising forming a groove between products that penetrates the glass layer and the resin insulating layer to expose the metal layer, and filling the groove between products with resin, wherein the resin is in contact with the side surface of the glass layer and the side surface of the resin insulating layer and surrounds the glass layer and the resin insulating layer.
5. A method for manufacturing a wiring board according to claim 4, wherein the resin is not formed on the first surface of the glass layer.
6. A method for manufacturing a wiring board according to claim 4, wherein the resin has a fifth surface and a sixth surface opposite to the fifth surface, and the fifth surface and the first surface are substantially located on the same plane.
7. A method for manufacturing a wiring board according to claim 6, further comprising forming a build-up portion on the first surface and the fifth surface.
8. A method for manufacturing a wiring board according to claim 4, further comprising cutting the resin in the groove between products.
Citation Information
Patent Citations
Circuit wiring board incorporating heat resistant substrate
WO2007129545A1