Signal transmission line and organic interposer equipped therewith

Abstract

We provide signal transmission lines that offer excellent connection reliability and durability, as well as flexible design, and organic interposers equipped with these lines that can be interconnected at high density and scaled up to large areas. [Solution] Multiple holes 14 are formed in the ground layers 11 and 15 to create a porous mesh structure, thereby mitigating stress caused by the difference in thermal expansion between the organic material and the metal material, suppressing thermal deformation, improving adhesion between the dielectric layers 12 and 16 and the signal layer 13 and the ground layers 11 and 15, and preventing peeling and breakage of the signal line 13, and peeling and cracking of the ground layers 11 and 15.

Description

Technical Field

[0001] The present invention relates to a signal transmission line that has excellent connection reliability and durability and allows flexible design, and an organic interposer and the like that is equipped with the signal transmission line, enables high-density interconnection, and can be increased in area.

Background Art

[0002] The introduction of generative AI applications such as ChatGPT has led to the explosive popularization of AI technology, but the increase in the number of parameters used in generative AI learning models requires further improvements in the core count of semiconductor packages, memory performance, and bandwidth between dies. To meet the demand for deep learning and AI, HBM (High Bandwidth Memory), which is a three-dimensional stacked memory technology, has been adopted.

[0003] Regarding the packaging of HBM modules, advanced packaging approaches such as Embedded Multi-die Interconnect Bridge (EMIB) that realize high-density interconnection between dies are becoming mainstream. In terms of advanced packaging, silicon interposers and organic interposers have been proposed. Organic interposers are attracting attention because they can be increased in area and are low in cost.

[0004] As the interlayer insulating layer of the organic interposer, a low dielectric constant polymer that can improve propagation speed and suppress dielectric loss is used. However, low dielectric constant polymers have a higher coefficient of thermal linear expansion than metal materials, and stress is generated from the difference in the coefficient of thermal linear expansion between the organic dielectric layer and the metal wiring layer and electrode layer, which reduces adhesion. In conventional manufacturing by photolithography, the adhesion between the organic dielectric layer of the redistribution layer (RDL) and the metal wiring layer and electrode layer has become a problem.

[0005] Furthermore, low dielectric polymers have low capacitance, which reduces crosstalk, and dielectric layers made of low dielectric polymers have good surface smoothness because they do not contain fillers. However, the smooth surface of the low dielectric polymer layer weakens the mechanical bonding (anchor effect) at the lamination interface, reducing adhesion. From this point of view, the adhesion between the organic dielectric layer and the metal wiring layer and electrode layer is a problem.

[0006] Therefore, methods have been proposed to improve the adhesion between a dielectric layer made of organic material and a wiring layer and electrode layer made of metal material, as well as to prevent delamination and cracking at the lamination interface between them.

[0007] A common technique involves surface roughening at the laminate interface. Roughening the surface of the organic dielectric layer improves the anchoring effect and thus the adhesion to the metal wiring layer. Another technique involves introducing an adhesive layer made of an interfacial molecular binder to the laminate interface. Chemically modifying the surface of the organic dielectric layer at the molecular level improves the adhesion to the metal wiring layer.

[0008] Furthermore, Patent Document 1 discloses a method for preventing cracks in the insulating film formed on a silicon wafer by forming a multilayer laminated structure of low dielectric constant insulating layers, forming each insulating layer with a thickness of less than 500 nm, and applying heat treatment each time an insulating layer is formed to create a compressive stress state. According to this method, a laminated structure consisting of a metal layer exhibiting tensile stress and a dielectric layer exhibiting compressive stress can be constructed, thereby preventing cracks caused by tensile stress that tend to occur in insulating films formed on silicon wafers. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] U.S. Patent Publication No. 6,232,658 [Patent Document 2] Japanese Patent Publication No. 2001-94011 [Patent Document 3] U.S. Patent Publication No. 2009-308649 [Patent Document 4] Japanese Patent Publication No. 2009-81534 [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] However, surface roughening of the laminate interface requires surface roughening with a surface roughening agent and a subsequent removal and cleaning process, increasing costs. Furthermore, the unevenness of the laminate interface and the skin effect increase conductor loss at higher frequencies. Additionally, introducing an adhesive layer to the laminate interface requires a process of applying an adhesive layer made of an interfacial molecular binder, increasing costs. Moreover, the method described in Patent Document 1 involves multiple steps in the process of forming the insulating layer and heat treatment, increasing costs and environmental impact.

[0011] As described above, conventional methods for improving adhesion between organic dielectric layers, metal wiring layers, and electrode layers, and for suppressing delamination and cracking at their lamination interfaces, have been insufficient from the standpoint of transmission characteristics and manufacturing costs. Currently, there is no signal transmission line that solves these problems, offers excellent connection reliability and durability, low transmission loss, and can be manufactured at low cost with a simple structure.

[0012] The present invention has been made in view of the above problems, and aims to provide a signal transmission line that improves the adhesion between the dielectric layer, signal layer and ground layer by making the ground layer a porous mesh structure, thereby providing excellent connection reliability and durability, flexible design, and low-cost manufacturing. Furthermore, it aims to provide an organic interposer and a resin multilayer substrate equipped with such a signal transmission line that have low interference between signal lines, enable high-density interconnection, can be made in large area, and can be manufactured at low cost.

[0013] Here, Patent Document 2 discloses a semiconductor integrated circuit having a signal transmission line with a microstrip structure that reduces the capacitance between wirings in the signal transmission line and increases the characteristic impedance by drilling holes in the signal line or ground plate, thereby reducing coupling between multiple signal lines.

[0014] Furthermore, Patent Document 3 discloses a printed circuit board that includes a periodically patterned reference plane (ground plane), which is oriented on the printed circuit board at an optimal angle with respect to the signal conduction path to reduce signal distortion, thereby reducing distortion during high-frequency signal transmission exceeding 1 GHz.

[0015] Furthermore, Patent Document 4 discloses a microstrip transmission line that includes a ground wiring layer having a mesh pattern, and in which the wiring density in the region facing the signal line is higher than the wiring density in other regions, thereby reducing signal loss due to wiring resistance when transmitting high-frequency signals.

[0016] However, all of these transmission line structures aim to improve specific transmission characteristics, such as those of microstrip transmission lines, by creating a specific mesh pattern by providing multiple holes in the signal line or ground layer. They do not aim to improve connection reliability or durability by improving the adhesion between the organic dielectric layer and the metal signal layer and ground layer, as is the case with the present invention.

[0017] The inventors have discovered that by forming multiple holes in the metal ground layer to create a porous mesh structure, stress caused by the difference in thermal expansion between the metal ground layer and the organic dielectric layer can be absorbed, suppressing thermal deformation, improving adhesion between the dielectric layer, the ground layer, and the signal layer, and preventing delamination and cracking at the lamination interface. Furthermore, they have found that by optimizing the size and arrangement of holes in the ground layer, and the width and arrangement of signal lines, transmission loss and interference between signal lines can be suppressed, thereby improving the performance of the signal transmission line. As a result of further research, the present invention has been completed.

[0018] In other words, the present invention relates to a microstrip line type signal transmission line comprising a first ground layer, a first dielectric layer, and a signal layer on which at least one signal line is formed, wherein these layers are stacked in this order, the first dielectric layer being made of an organic material, and in a plan view, a plurality of rows of holes consisting of a plurality of holes are formed in parallel in at least one direction in the first ground layer, the signal line extends in the same direction as the row of holes, and in a cross-sectional view perpendicular to the longitudinal centerlines of the signal line and the row of holes and passing through the center of the holes, the width of the signal line is formed to be smaller than the width of the holes, and some or all of the signal line is arranged to be located inside the holes.

[0019] Furthermore, the present invention relates to a coplanar signal transmission line comprising a first ground layer, a first dielectric layer, a signal layer on which at least one signal line is formed, and a pair of second ground layers located on the same plane as the signal layer and spaced apart on both sides of the signal line, wherein each of these layers is stacked in this order, the first dielectric layer being made of an organic material, and in a plan view, a plurality of rows of holes consisting of a plurality of holes are formed in parallel in at least one direction in the first ground layer, the signal line extends in the same direction as the row of holes, and in a cross-sectional view perpendicular to the longitudinal centerlines of the signal line and the row of holes and passing through the center of the holes, the width of the signal line is formed to be smaller than the width of the holes, and some or all of the signal line is arranged to be located inside the holes.

[0020] Further, the present invention is a stripline-type signal transmission line comprising a first ground layer, a first dielectric layer, a signal layer on which at least one signal line is formed, a second dielectric layer, and a second ground layer, wherein these layers are laminated in this order, the first and second dielectric layers are made of an organic material, a plurality of hole arrays each composed of a plurality of holes are formed in the first and second ground layers in parallel in at least one direction in a plan view, the signal line extends in the same direction as the hole arrays, in a cross-sectional view orthogonal to the longitudinal center lines of the signal line and the hole arrays and passing through the centers of the holes, the width of the signal line is formed to be smaller than the width of the holes, and part or all of the signal line is arranged to be positioned inside the holes.

[0021] In the signal transmission line of the present invention, a plurality of holes are formed in the ground layer made of a metal material to form a porous mesh structure, so that the dielectric layer made of an organic material is bonded to the ground layer via the large number of holes. By replacing part of the ground layer with the dielectric layer, stress caused by the difference in thermal linear expansion between the dielectric layer and the ground layer can be relieved, and thermal deformation of the laminate can be suppressed. The adhesion between the dielectric layer and the signal layer as well as the ground layer can be improved, so that peeling or disconnection of the signal line and peeling or cracking of the ground layer at the lamination interface can be prevented.

[0022] In addition, by adjusting the hole shape, the number of holes and the arrangement pattern of the ground layer while keeping the width of the signal line constant, the impedance and the corresponding insertion loss can be controlled more strictly, and more flexible structural design becomes possible. Furthermore, a plurality of recesses can be formed toward the holes of the lower ground layer in the longitudinal direction of the signal line, so that the signal line can have redundancy against tensile and compressive stress. In the stripline type, vias penetrating through the holes of the upper and lower ground layers can be provided, and the signal line can be connected to other signal lines and external wirings.

[0023] Furthermore, one embodiment of the present invention is a multilayer stripline-type signal transmission line, which includes the above stripline-type signal transmission line as a repeating structure, a plurality of the repeating structures are stacked, and between two adjacent repeating structures, the second ground layer of one repeating structure constitutes the first ground layer of the other repeating structure.

[0024] In the multilayer stripline type, the upper and lower dielectric layers are bonded to the ground layer via a plurality of holes, and the upper and lower dielectric layers are further bonded to each other with the ground layer sandwiched therebetween. With this configuration, the stress caused by the difference in thermal linear expansion can be more effectively relieved to suppress thermal deformation of the laminate, the mechanical coupling between the dielectric layer and the ground layer is improved, and the adhesion between the dielectric layer and the signal layer as well as the ground layer can be further enhanced. In addition, the upper and lower signal lines can be connected by vias penetrating the holes in the upper and lower ground layers, so that a desired three-dimensional fine wiring network can be constructed.

[0025] Furthermore, one embodiment of the present invention is the signal transmission line, wherein the holes are substantially circular, elliptical, or polygonal with four or more sides.

[0026] Furthermore, one embodiment of the present invention is the signal transmission line, wherein the holes are substantially circular with a diameter of 2.5 μm or more, elliptical with an average of the minor axis and the major axis of 2.5 μm or more, or polygonal with four or more sides and a diagonal distance of 3 μm or more.

[0027] By configuring the holes in the above form, a high-precision mesh pattern can be stably manufactured at low cost using an existing photolithography process. The stress caused by the difference in linear expansion between the dielectric layer and the ground layer can be sufficiently absorbed, and the adhesion between the dielectric layer and the signal layer as well as the ground layer can be further improved.

[0028] Furthermore, one embodiment of the present invention is the signal transmission line, wherein the thickness of the ground layer on which the hole arrays are formed is 0.5 μm or more.

[0029] By increasing the thickness of the ground layer to 0.5 μm or more, the porous mesh structure can adequately absorb stress caused by differences in linear expansion while maintaining its function as a reference electrode. In the case of a multilayer stripline type, interference between signal lines arranged vertically can be reduced.

[0030] Furthermore, one embodiment of the present invention is a signal transmission line in which the area occupied by the metal material per unit area of ​​the ground layer in which the row of holes is formed is in the range of 35 to 95%.

[0031] The ratio of the area occupied by metal material per unit area of ​​the ground layer (filling density) is set considering factors such as the effect of suppressing thermal deformation due to stress relaxation, the function and reliability as a reference electrode, and the processing accuracy and stability of the photolithography process. Within the above range, a suitable balance can be achieved between improved adhesion at the laminate interface, prevention of delamination and disconnection, excellent transmission characteristics and connection reliability, and quality stability and manufacturing costs.

[0032] Furthermore, one embodiment of the present invention is a signal transmission line in which the longitudinal centerlines of some or all of the signal lines and the longitudinal centerlines of the hole rows are arranged to substantially coincide.

[0033] Furthermore, one embodiment of the present invention is a signal transmission line in which, in a cross-sectional view along the longitudinal centerline of the signal line, a plurality of recesses are formed on the signal line toward a plurality of holes formed in the first ground layer.

[0034] With the above configuration, wide and deep recesses can be formed in the signal lines, and the entire signal line extending in the same direction as the row of holes can be given a wavy shape. By providing sufficient elasticity in the front-to-back and up-and-down directions of the signal lines, tensile and compressive stresses caused by differences in thermal expansion can be absorbed more effectively, further improving the reliability and durability of the connection. In the stripline type, vias can be easily provided that penetrate the holes in the upper and lower ground layers.

[0035] Furthermore, in one embodiment of the present invention, in a plan view, at least two adjacent rows of holes are formed offset from each other such that the holes in one row of holes are located between adjacent holes in the other row of holes, and in one repeating structure, the longitudinal centerlines of some or all of the signal lines are arranged to substantially coincide with the longitudinal centerlines of the one row of holes, and in the other repeating structure, the longitudinal centerlines of some or all of the signal lines are arranged to substantially coincide with the longitudinal centerlines of the other row of holes, and in a cross-sectional view, some or all of the signal lines of the one repeating structure and some or all of the signal lines of the other repeating structure are arranged alternately with the second or first ground layer in between, the signal transmission line.

[0036] Furthermore, one embodiment of the present invention is a signal transmission line further comprising vias provided through the holes formed in the first and second ground layers, for electrically connecting the signal line with external wiring and / or other signal lines.

[0037] The above configuration reduces interference between signal lines arranged vertically, thereby improving crosstalk. Furthermore, the vertically arranged signal lines can be connected by vias that penetrate holes in the upper and lower ground layers. This allows for the construction of a desired three-dimensional fine wiring network with improved transmission performance and connection reliability.

[0038] Furthermore, the present invention relates to an organic interposer or resin multilayer substrate equipped with the aforementioned signal transmission line.

[0039] The signal transmission lines of the present invention can be manufactured using existing physical or chemical vapor deposition methods, spin coating, dry film methods, photolithography, damascene methods, etc., and can be manufactured over large areas at low cost. They also enable the construction of fine wiring networks with excellent adhesion between the organic dielectric layer, the metal signal layer, and the ground layer. Resin multilayer substrates such as organic interposers, package substrates, and printed circuit boards equipped with the signal transmission lines of the present invention have excellent connection reliability and transmission characteristics and are suitable for 3D mounting of semiconductor chiplets and the like. [Effects of the Invention]

[0040] The signal transmission line of the present invention, with its simple configuration of forming multiple holes in the ground layer, absorbs stress caused by the difference in thermal expansion between the organic dielectric layer and the signal layer, thereby suppressing thermal deformation, improving adhesion between the dielectric layer and the signal and ground layers, and preventing delamination and disconnection at the interface. It offers excellent connection reliability and durability and can be manufactured at low cost using existing processes.

[0041] Furthermore, the organic interposer or resin multilayer substrate of the present invention has a structure in which the signal transmission lines of the present invention are stacked, and can be interconnected at high density by a fine wiring network with excellent connection reliability. It can be manufactured in large area using existing processes and at low cost. [Brief explanation of the drawing]

[0042] [Figure 1a] This is a top view of the microstrip line type of the first embodiment. [Figure 1b] This is a cross-sectional view of line AA in Figure 1a (a cross-sectional view using the ZX plane). [Figure 2a] This is a top view of the coplanar type of the second embodiment. [Figure 2b] This is a cross-sectional view of line AA in Figure 2a (a cross-sectional view using the ZX plane). [Figure 3a] This is a top view of the stripline type of the third embodiment. [Figure 3b] This is a cross-sectional view of line AA in Figure 3a (a cross-sectional view using the ZX plane). [Figure 3c] Figure 3a shows a cross-sectional view of line BB (cross-sectional view in the YZ plane), and a partially enlarged view of portion P in the figure. [Figure 4] This graph shows the relationship between frequency and impedance in impedance measurements of porous mesh ground layers with varying packing density. [Figure 5]This graph shows the relationship between frequency and insertion loss when measuring insertion loss with varying packing density of a porous mesh ground layer. [Figure 6] This is a cross-sectional view in the ZX plane showing the structure of a signal transmission line in which crosstalk between signal lines (horizontal pairs) arranged on the left and right sides was measured. [Figure 7] This graph shows the relationship between frequency and near-end crosstalk (NEXT) in crosstalk measurements where the spacing between signal lines arranged on the left and right sides is varied. [Figure 8] This graph shows the relationship between frequency and near-end crosstalk (NEXT) and far-end crosstalk (FEXT) in crosstalk measurements where the lengths of signal lines placed on the left and right sides are varied.

[0043] [Figure 9] This is a cross-sectional view of the fourth embodiment of a multilayer stripline type as shown in the ZX plane. [Figure 10] This image shows the distribution of warpage in the thickness direction (Z direction) in a thermal analysis simulation of a reference configuration with a solid ground (without holes). [Figure 11] This image shows the distribution of warpage in the thickness direction (Z direction) in a thermal analysis simulation of the fourth embodiment equipped with a porous mesh ground. [Figure 12] This graph shows the relationship between the distance from the center and the curvature in thermal analysis simulations with varying ground shapes (with or without holes). [Figure 13] This graph shows the relationship between distance from the center and stress in thermal analysis simulations with varying ground shapes (with or without holes). [Figure 14] This graph shows the relationship between ground thickness and warping in thermal analysis simulations with varying ground shapes (presence or absence of holes and hole shape). [Figure 15] This image shows the distribution of warpage in the thickness direction (Z direction) in a thermal analysis simulation of a reference configuration (φ300 wafer substrate) equipped with a solid ground (no holes). [Figure 16]This image shows the distribution of warpage in the thickness direction (Z direction) in a thermal analysis simulation (φ300 wafer substrate) of the fourth embodiment equipped with a porous mesh ground. [Figure 17] This graph shows the relationship between the distance from the center and warpage in thermal analysis simulations (φ300 wafer substrate) with varying ground shape (presence or absence of holes). [Figure 18] This is a cross-sectional view in the ZX plane showing the structure of a signal transmission line in which crosstalk between signal lines (diagonal pairs) arranged vertically was measured. [Figure 19] This graph shows the relationship between frequency and near-end crosstalk (NEXT) and far-end crosstalk (FEXT) in crosstalk measurements where the lengths of signal lines arranged vertically are varied.

[0044] [Figure 20a] This is a top view of the multilayer stripline type (staggered arrangement pattern) of the fourth embodiment. [Figure 20b] This is a cross-sectional view of line AA in Figure 20a (a cross-sectional view using the ZX plane). [Figure 20c] This is a cross-sectional view of the CC line in Figure 20a (a cross-sectional view using the ZX plane). [Figure 20d] This is a top view of the multilayer stripline type (honeycomb pattern) of the fourth embodiment. [Figure 21] This is a cross-sectional view of the fifth embodiment of a multilayer stripline type (interlayer via connection) in the ZX plane. [Modes for carrying out the invention]

[0045] The signal transmission line of the present invention and the organic interposer equipped therewith will be described in detail below. Note that the material composition, shape and structure, manufacturing method, etc., which are not described here, may be the same as or substantially the same as those known to those skilled in the art.

[0046] In the descriptions, left / right, front / back, and up / down are defined relative to the coordinate axes in each drawing. Specifically, the +X direction is defined as the right direction, the -X direction as the left direction, the +Y direction as the back direction, the -Y direction as the front direction, the +Z direction as the up direction, and the -Z direction as the down direction. Furthermore, the horizontal plane is defined as the XY plane, and the vertical planes are defined as the YZ plane and the ZX plane.

[0047] Since each plan view and cross-sectional view is a conceptual diagram showing a part of the signal transmission line of the present invention, some features may be omitted or exaggerated. Therefore, some components may not be shown, and the form and dimensions of each component may be shown at different scales.

[0048] Furthermore, in this specification, "consisting of" means essentially or substantially consisting of the compound or material in question, and allows for the inclusion of trace amounts of other compounds or components.

[0049] The term "approximately" is not limited to cases where the shape is strictly identical, but rather includes errors or modifications that do not result in a loss of identity. For example, "approximately circular" is not limited to cases where the shape is strictly circular, but includes shapes that can be considered equivalent to a circle from the perspective of their function and effect.

[0050] <First Embodiment> First, a microstrip line type signal transmission line 1, which is a first embodiment of the present invention, will be described with reference to Figures 1a and 1b. The microstrip line type signal transmission line 1 is constructed by stacking a first ground layer 11, a first dielectric layer 12, and a signal layer in which signal lines 13 are formed, in this order on a substrate 10 such as a silicon substrate or a silicon substrate on which predetermined dielectric layers are laminated. Each layer only needs to be arranged in this order in the vertical direction, and other layers may be provided between each layer. For example, a barrier layer may be provided between the first dielectric layer 12 and the signal layer on which the signal lines 13 are formed. Furthermore, an insulating cover layer may be provided as the uppermost layer.

[0051] [Ground layer] The first ground layer 11 constitutes a reference electrode that provides a reference potential. As shown in Figures 1a and 1b, the first ground layer 11 has multiple rows of holes, each consisting of multiple substantially circular holes 14, formed in parallel in the X and Y directions. It is formed from a conductive metallic material such as copper, copper alloys (TiCu, TiCuFe), aluminum, aluminum alloys (AlSi, AlCu, AlSiCu), gold, gold alloys, niobium, and niobium alloys. The film is formed by physical vapor deposition methods such as vapor deposition and sputtering, chemical vapor deposition methods such as CVD, or electrolytic or electroless wet plating methods.

[0052] The thickness of the ground layer is not limited as long as it can perform its intended function, but a certain thickness is required to ensure sufficient thermal stress relaxation due to the porous mesh structure and to guarantee its function and reliability as a reference electrode. A thickness of 0.5 μm or more is preferred, and 2.5 μm or more is more preferred. On the other hand, in interposer applications, minute sizes are required for the signal layer and interlayer connection vias in the formation of a fine wiring network, and a thin electrode layer is also desirable. From the viewpoint of balancing stress relaxation with miniaturization and multilayering, a range of 0.5 to 50 μm is preferred, and a range of 2.5 to 25 μm is more preferred.

[0053] Multiple linear hole rows, each composed of multiple holes 14, are formed in parallel in at least one direction, as signal lines 13 are positioned above them. A linear hole row refers to an arrangement of holes where the line connecting the centers of the multiple holes is approximately a straight line. In this embodiment, a parallel pattern is formed in which the holes are aligned at the shortest possible distance and with equal pitch in the X and Y directions, but the arrangement pattern is not limited as long as it achieves the desired effect. Examples include parallel arrangements with holes aligned in two directions, horizontal and vertical; a 45° staggered arrangement with holes aligned in two directions with a 45° inclination angle that intersects at 90°; and a 60° staggered arrangement with holes aligned in two directions with a 60° inclination angle that intersects at 60°. The porous mesh pattern is formed on a metal layer laminated on a substrate 10 through a series of photolithography processes such as resist coating, exposure, development, and etching.

[0054] The shape of the pores 14 is preferably approximately circular, elliptical, or a polygon with four or more sides from the viewpoint of thermal stress relaxation effect and high-precision, low-cost manufacturing. More preferably, the pores are approximately circular, elliptical, a polygon with four or more sides with rounded corners, or a point-symmetric polygon with six or more sides to prevent stress concentration at the corners from causing cracks or delamination in the ground layer. In this invention, elliptical means a circular shape with a minor axis / major axis (ellipticity) of 0.95 or less. The diameter of these pores is not limited as long as they can perform the predetermined function, and is set considering the thermal stress relaxation effect, control of electrical characteristics such as impedance, and high-precision, low-cost manufacturing. The diameter of approximately circular pores and the average diameter of the minor and major axes of elliptical pores are preferably 2.5 μm or more, and more preferably 5 μm or more. The diagonal distance of polygons with four or more sides is preferably 3 μm or more, and more preferably 6 μm or more. In applications where miniaturization is required, the diameter of approximately circular pores and the average diameter of the minor and major axes of elliptical pores are preferably in the range of 2.5 to 50 μm, and more preferably in the range of 5 to 25 μm. The diagonal distance of polygons with four or more sides is preferably in the range of 3 to 60 μm, and more preferably in the range of 6 to 30 μm.

[0055] In a plan view, the ratio of the area occupied by metal material per unit area of ​​the ground layer with multiple through holes (filling density) is not limited as long as it can perform the desired function. It is set considering factors such as the effect of mitigating thermal stress, the function and reliability as a reference electrode, the control of electrical characteristics such as impedance, and high-precision, low-cost manufacturing. If the thickness of the ground layer is the same, a smaller filling density can be expected to have a greater stress-relaxing effect, and a larger density results in superior performance as a reference electrode. Furthermore, there is a structural limit to the lower limit of the filling density due to the mechanical strength of the ground layer, and there are manufacturing limits to the lower limits of the hole diameter and hole pitch depending on the exposure equipment used in the photolithography process.

[0056] The packing rate can be calculated using known methods based on the area, hole shape, hole diameter, number of holes, and hole pitch of the repeating units constituting the porous mesh pattern. A packing rate of 35 to 95% is preferred, 45 to 85% is more preferred, and 50 to 80% is even more preferred. For example, in the parallel pattern of circular holes with equal pitch shown in Figure 3a, the packing rate (%) is calculated by the following formula, depending only on the hole diameter (2r) and hole pitch (p) of the repeating units shown in section R. Filling rate (%)=(1-πr 2 / p 2 ) × 100

[0057] [Dielectric layer] The first dielectric layer 12 constitutes an interlayer insulating film. Since the signal propagation speed in semiconductor devices is inversely proportional to the relative permittivity of the insulating material, an insulating material with a low relative permittivity is desirable. Furthermore, since the dielectric loss during signal propagation is proportional to the relative permittivity and dielectric loss tangent of the insulating material, an insulating material with a low dielectric loss tangent is desirable. The dielectric layer of the present invention is composed of an organic material such as an organic polymer that has excellent physical properties in these respects. The relative permittivity is preferably 4 or less, and more preferably 3 or less. The dielectric loss tangent is preferably 0.02 or less, and more preferably 0.01 or less. Polyimide resin, modified polyimide resin, epoxy resin, acrylic resin, liquid crystal polymer, and the like are preferred examples. In this embodiment, polyimide resin is used.

[0058] The first dielectric layer 12 is formed after the porous mesh pattern of the first ground layer by coating methods such as spin coating and slit coating using liquid resin materials, printing methods such as screen printing and inkjet printing, or dry film methods using film-like resin materials. Its thickness is not limited as long as it performs the desired function, but a certain thickness is required to ensure the function and reliability of the interlayer insulating film. On the other hand, in interposer applications, a thin interlayer insulating film is desirable for the formation of a fine wiring network. From the viewpoint of balancing reliability with miniaturization and multilayering, a range of 1 to 50 μm is preferred, and a range of 5 to 25 μm is more preferred.

[0059] [Signal layer] One or more signal lines 13 are formed in the signal layer, constituting a transmission line for high-frequency signals. In interposer applications, they constitute a fine wiring network connecting chiplets to package substrates and to chiplets themselves. As shown in Figure 1a, the signal lines 13 extend in the Y direction, in the same direction as the row of holes 14 formed in the first ground layer 11. Furthermore, as shown in Figure 1b, in a cross-sectional view perpendicular to the longitudinal centerline of the row of holes consisting of the signal lines 13 and holes 14, and passing through the center of the holes 14, the width of the signal lines 13 in the short direction is formed to be smaller than the diameter of the holes 14, and the signal lines 13 are positioned radially inward of the holes 14.

[0060] In a configuration in which multiple signal lines 13 are formed, some or all of them are arranged to be located radially inward of the hole 14. Considering the provision of redundancy to the signal lines and connections by vias, which will be described later, it is preferable to arrange most or all of the signal lines to be located radially inward of the hole 14. A part of the signal lines means less than 50% of the total number of signal lines, more specifically less than 25%, and most of the signal lines means 50% or more of the total number of signal lines, more specifically 75% or more. Specifically, the ratio of the number of signal lines arranged to be located inside the hole to the total number of signal lines is preferably 25% or more, more preferably 50% or more, and even more preferably 75% or more.

[0061] The signal layer is formed from the same metallic material as the ground layer and is similarly deposited by physical vapor deposition, chemical vapor deposition (CVD), or electrolytic or electroless wet plating. Furthermore, signal lines and wiring patterns consisting of multiple signal lines are formed through a series of photolithography processes, insulating layer pattern formation, Cu plating, and single or dual damascene processes such as chemical mechanical polishing (CMP).

[0062] The thickness of the signal layer (signal lines) is not limited as long as it can perform its intended function, but a certain thickness is required to ensure the function and reliability of the signal transmission line. A thickness of 0.5 μm or more is preferred, and 2.5 μm or more is more preferred. On the other hand, from the viewpoint of balancing reliability with miniaturization and multilayering depending on the application, a range of 0.5 to 50 μm is preferred, and a range of 2.5 to 25 μm is more preferred. The width of the signal lines and the spacing between signal lines are preferably in the range of 1 to 50 μm, and a range of 2.5 to 25 μm is more preferred.

[0063] <Second Embodiment> Next, a coplanar signal transmission line 2, which is a second embodiment of the present invention, will be described with reference to Figures 2a and 2b. In the coplanar signal transmission line 2, a pair of second ground layers 15 are arranged on both sides of the signal line 13 with a gap between them. These second ground layers 15 are stacked on the upper surface of the first dielectric layer 12, which is in the same plane as the signal layer on which the signal line 13 is formed.

[0064] A pair of second ground layers 15 constitute a reference electrode that provides a reference potential. As shown in Figures 2a and 2b, the second ground layers 15 have multiple rows of holes, each consisting of multiple substantially circular holes 14, formed in parallel in the X and Y directions. The distance between the signal line 13 and the pair of second ground layers 15 is preferably in the range of 1 to 50 μm, and more preferably in the range of 2.5 to 25 μm, similar to the distance between signal lines. The material composition, shape structure, manufacturing method, etc., of the other components are the same as in the first embodiment.

[0065] <Third Embodiment> Next, a stripline type signal transmission line 3, which is a third embodiment of the present invention, will be described with reference to Figures 3a to 3c. In the stripline type signal transmission line 3, a second dielectric layer 16 and a second ground layer 15 are stacked in this order on a signal layer on which the signal line 13 is formed. Each layer only needs to be arranged in this order in the vertical direction, and other layers may be provided between each layer. For example, an adhesive layer may be provided between the signal layer on which the signal line 13 is formed and the second dielectric layer 16.

[0066] The second ground layer 15 constitutes a reference electrode that provides a reference potential. As shown in Figures 3a to 3c, the second ground layer 15 has multiple rows of holes, each consisting of multiple substantially circular holes 14, formed in parallel in the X and Y directions. The shape of the porous mesh pattern formed on the first ground layer 11 and the second ground layer 15 is identical to that of the first ground layer 15. Note that in Figure 3a, the uppermost insulating cover layer is omitted from the illustration. The material composition, shape structure, manufacturing method, etc. of the other components are the same as in the first embodiment.

[0067] The shape of the holes, hole diameter, number of holes, hole pitch, and arrangement pattern of each mesh pattern formed in the first and second ground layers are not limited as long as they can achieve the predetermined effects of the present invention, and may be the same or different. Considering the provision of redundancy to the signal lines and connections by vias, as described later, in a plan view, it is preferable that the centers of the holes 14 formed in the first ground layer 11 and the centers of the holes 14 formed in the second ground layer 15 opposite each other across the signal line 13 are partially or completely coincident, and more preferably that most or completely coincide. Partially coincident holes mean less than 50% of the total number of holes, more specifically less than 25%, and most coincident holes mean 50% or more of the total number of holes, more specifically 75% or more. Specifically, the ratio of the number of holes with coincident centers to the total number of holes in each of the first and second ground layers is preferably 25% or more, more preferably 50% or more, and even more preferably 75% or more.

[0068] Figure 3c is a cross-sectional view of line BB in Figure 3a (cross-sectional view in the YZ plane). As shown in the enlarged portion of section P, the first dielectric layer 12 deposited on the hole 14 is recessed toward the hole 14, and the signal line 13 deposited on top of it is also recessed. Therefore, in a plan view, by arranging the signal line 13 so that its longitudinal centerline and the longitudinal centerline of the hole row consisting of the hole 14 substantially coincide, multiple recesses 17 can be formed in the signal line 13, and a undulation can be formed in the longitudinal direction of the signal line 13. This provides redundancy as wiring in the longitudinal direction of the signal line 13, effectively absorbing tensile and compressive stresses caused by differences in thermal expansion at the laminate interface, suppressing breakage and peeling of the signal line, and improving the reliability and durability of the connection.

[0069] By arranging the signal line 13 so that its longitudinal centerline and the longitudinal centerline of the hole row consisting of holes 14 substantially coincide, and by forming the signal line 13 with a width in the short direction smaller than the width of the holes 14, the recess 17 can be formed to be wide and deep. The inclination angle θ and depth h of the inclined surface of the recess 17 formed in the signal line 13 vary depending on the hole diameter of the holes 14 and the thickness of the lower first ground layer 11. An example of an inclination angle θ with respect to the lower surface of the first dielectric layer 12 or the first ground layer 11 (upper surface of the substrate) is 10° or less. Also, an example of a depth h of the recess 17 with respect to the upper surface of the signal line 13 (signal layer) is 1 / 3 or less of the thickness of the first ground layer 11. In the multilayer stripline type described later, a tendency was observed for the width (wavelength) of the undulation of the upper signal line 13 to increase as the number of layers increased.

[0070] [Measurement of impedance and insertion loss] In the third embodiment, signal transmission lines with solid grounds (100% filling rate) for the first and second ground layers and signal transmission lines with porous mesh grounds (74% or 50% filling rate) were fabricated, and the impedance and corresponding insertion loss were measured. A 1 μm thick polyimide dielectric layer, a 0.5 μm thick Cu ground layer, a 1 μm thick polyimide dielectric layer, a 0.5 μm thick Cu signal line, a 1 μm thick polyimide dielectric layer, a 0.5 μm thick Cu ground layer, and a 1 μm thick polyimide dielectric layer were stacked on a Si substrate in that order. The width of the signal line was 6 μm and the length was 1 mm. The filling rate of the porous mesh ground was adjusted by changing the hole diameter with a hole pitch of 25 μm. Figure 4 shows the relationship between frequency and impedance, and Figure 5 shows the relationship between frequency and insertion loss.

[0071] As shown in Figure 4, the porous mesh ground exhibits smaller impedance changes over a wide frequency range up to 10 GHz compared to a solid ground, and these changes can be further reduced by lowering the packing density of the porous mesh pattern. This means that more precise impedance control is possible. As a result, as shown in Figure 5, the corresponding insertion loss can be reduced. By adjusting the mesh hole size while keeping the signal line width constant, impedance control becomes possible, allowing for more flexible structural design.

[0072] [Measurement of crosstalk] In a third embodiment with five signal lines, near-end crosstalk (NEXT) and far-end crosstalk (FEXT) were measured when the second and third signal lines were connected horizontally. The width of the signal lines was varied to 2 μm, and the spacing between signal lines was varied to 2, 5, or 8 μm. The length of the signal lines was designed to 1 or 2 mm for advanced packaging according to the UCIe 1.1 specification. Figure 6 shows the structure of the evaluated signal transmission line. Figure 7 shows the relationship between frequency and near-end crosstalk (NEXT) for 1 mm signal lines. Figure 8 shows the relationship between frequency and near-end crosstalk (NEXT) and far-end crosstalk (FEXT) for 2 μm spacing.

[0073] The results in Figure 7 show that the NEXT at 10 GHz between a pair of 1 mm signal lines, (2) and (3), with a width of 2 μm, is improved to approximately -21 dB at a 2 μm spacing (4 μm pitch), approximately -29 dB at a 5 μm spacing (7 μm pitch), and approximately -36 dB at an 8 μm spacing (10 μm pitch). The insertion loss of the 1 mm signal line is within -5 dB at 10 GHz, which meets the loss specifications of the UCIe 2.0 specification.

[0074] Furthermore, the results in Figure 8 confirm that for 2mm signal lines, the NEXT at 10GHz decreases to -19.5dB with a spacing of 2μm (4μm pitch). For interconnecting horizontally arranged 2mm signal lines, a larger pitch is required, and it is considered that at least a spacing of 5μm (7μm pitch) or more is necessary.

[0075] <Fourth Embodiment> Next, a multilayer stripline type signal transmission line 4A of the fourth embodiment of the present invention will be described with reference to Figure 9. In the multilayer stripline type signal transmission line 4A, the stacked structure from the first ground layer to the second ground layer of the stripline type signal transmission line 3 of the third embodiment is used as a repeating unit, and this is repeated twice. Between these two adjacent repeating structures, the second ground layer 15L of the lower repeating structure 18L constitutes the first ground layer 11U of the upper repeating structure 18U. The material composition, shape structure, manufacturing method, etc., of each layer are the same as in the first and third embodiments. In an organic interposer equipped with the multilayer stripline type signal transmission line of the present invention, a thick, three-dimensional fine wiring network can be constructed by stacking this repeating structure several to more than ten times, more specifically, about four to ten times.

[0076] [Thermal Analysis Simulation] In the fourth embodiment, a stacked model was assumed in which each ground layer was either a solid ground without holes or a porous mesh ground. Thermal analysis simulation software (ANSYS Inc.) was used to analyze the magnitude of warping and stress due to temperature changes. The temperature change conditions were from the mounting temperature of the organic interposer (280°C) to the operating temperature of the CPU (90°C). A 0.5 μm thick Cu ground layer, a 1 μm thick polyimide dielectric layer, a 0.5 μm thick Cu signal layer, a 1 μm thick polyimide dielectric layer, and a 0.5 μm thick Cu ground layer were stacked in that order on a 100 μm thick Si substrate, and this stacked structure was repeated twice. The porous mesh ground had circular holes, a hole diameter of 15 μm, a hole pitch of 25 μm, and a packing rate of 72%.

[0077] Figures 10 and 11 show the distribution of warpage in the thickness direction along the diagonal from the center of the stacked model up to approximately 500 μm. Figures 12 and 13 show the relationship between the distance from the center and the magnitude of warpage and stress, respectively. From the results in Figure 12, it can be seen that in the porous mesh ground, the magnitude of warpage decreases by approximately 24% at a distance of approximately 520 μm from the center, indicating that thermal deformation can be reduced by suppressing the difference in thermal expansion between the metallic material and the organic material through the porous mesh structure. Furthermore, from the results in Figure 13, it can be considered that the stress level remains almost the same.

[0078] Furthermore, thermal analysis was performed under the same conditions as above, except that the gland layer thickness was set to three levels: 0.5, 2, and 5 μm, and a porous mesh gland with square pores was added. The added square-pore mesh gland had a side length of 13.3 μm and a pore pitch of 25 μm, and was adjusted to the same packing density of 72% as the circular-pore mesh gland. Figure 14 shows the relationship between the thickness of the mesh gland and the magnitude of warping.

[0079] Figure 14 shows that the effect of the porous mesh structure on reducing warpage increases with increasing ground layer thickness, reaching a maximum reduction of approximately 28%. No difference in effect was observed depending on the pore shape, suggesting that the warpage reduction effect is at the same level for mesh structures of the same volume (same packing density and same thickness).

[0080] Furthermore, thermal analysis was performed under the same conditions as above, except that the substrate size was increased to a 300mm diameter Si wafer to expand the area of ​​the stacked model. Figures 15 and 16 show the distribution of the warpage magnitude in the thickness direction from the wafer center to 150mm, and Figure 17 shows the relationship between the distance from the wafer center and the warpage magnitude. From the results in Figure 17, it can be seen that the effect of reducing warpage in a 300mm Si wafer by using a porous mesh structure is up to approximately 46%.

[0081] [Measurement of crosstalk] In the fourth embodiment, which has 10 signal lines (5 on each of the upper and lower transmission lines), near-end crosstalk (NEXT) and far-end crosstalk (FEXT) were measured when the 2nd and 8th signal lines were connected in an oblique vertical direction. The signal lines were spaced 2 μm apart (4 μm pitch), and the signal lines were designed to be 1 or 2 mm in diameter for advanced packaging according to the UCIe 1.1 specification. Figure 18 shows the structure of the evaluated signal transmission line, and Figure 19 shows the relationship between frequency and near-end crosstalk (NEXT) and far-end crosstalk (FEXT).

[0082] As shown in Figure 19, for a signal line of length 2 mm, the NEXT between signal lines (2) and (8) located diagonally opposite each other was approximately -24 dB at 10 GHz. It can be seen that the signal pair arranged diagonally vertically showed an improvement of approximately -4 dB compared to the signal pair arranged horizontally. This is thought to be due to a reduction in capacitive coupling caused by the porous mesh ground present between the signal lines.

[0083] [Improved crosstalk] To improve crosstalk, it is conceivable to reduce interference between signal lines by arranging the upper and lower signal lines in alternating positions. In the multilayer stripline type signal transmission line 4B, as shown in Figures 20a to 20c, a porous mesh pattern in a 45° staggered arrangement is formed in the first and second ground layers, with circular holes 14L and 14U arranged in two directions with a 45° inclination angle that intersect at 90°, and arranged at the shortest and equal pitch. Note that in Figure 20a, the uppermost cover layer and the holes located on the four sides are omitted from the illustration. Looking at the Y direction in which the signal lines 13L and 13U extend, in two adjacent rows of holes, the holes 14L of one row of holes are positioned between adjacent holes 14U of the other row of holes, and are arranged in a staggered pattern offset from each other. In this 45° staggered arrangement pattern of circular holes, the filling rate (%) is calculated by the following formula, depending only on the hole diameter (2r) and the hole pitch (p) of the repeating unit shown in section R. Filling rate (%)=(1-2·πr 2 / p 2 ) × 100

[0084] As shown in Figure 20b, in the lower first repeating structure 18L, the center line of the signal line 13L is positioned to substantially coincide with the center line of one of two adjacent hole rows (the hole row consisting of hole 14L) formed in the first and second ground layers. Also, as shown in Figure 20c, in the upper second repeating structure 18U, the center line of the signal line 13U is positioned to substantially coincide with the center line of the other of two adjacent hole rows (the hole row consisting of hole 14U) formed in the first and second ground layers.

[0085] In this way, by arranging the signal lines 13L of the first repeating structure 18L and the signal lines 13U of the second repeating unit 18U in a staggered pattern, offset from each other across the first ground layer (second ground layer), in a cross-sectional view of the AA line passing through the center of the hole 14L and the CC line passing through the center of the hole 14U, perpendicular to their longitudinal centerlines, interference between the upper and lower signal lines can be reduced and crosstalk improved while arranging the signal lines at high density. Furthermore, vias can be provided to connect the upper and lower signal lines by passing through holes in the upper and lower ground layers, enabling the construction of a three-dimensional fine wiring network. In addition, multiple recesses can be formed in the signal lines toward multiple holes formed in the lower first ground layer, providing redundancy against tensile and compressive stresses to the signal lines.

[0086] Figure 20d shows another configuration in which the upper and lower signal lines are arranged alternately with the ground layer in between. In this multilayer stripline type signal transmission line 4C, a porous mesh pattern in a 60° staggered arrangement is formed in the first and second ground layers, with regular hexagonal holes 14L,U arranged at the shortest and equal pitch in two directions with a 60° inclination angle that intersect at 60°. The other configurations are the same as those of the signal transmission line 4B described above. In this 60° staggered arrangement pattern of regular hexagonal holes (honeycomb pattern), the packing rate (%) is calculated by the following formula, depending only on the side length (a) or diagonal distance (2a) and the inter-hole pitch (p) of the repeating unit of regular hexagonal holes shown in section R. Filling rate (%)=(1-3·a 2 / p 2 ) × 100

[0087] <Fifth Embodiment> Next, a multilayer stripline type transmission line 5 according to the fifth embodiment of the present invention will be described with reference to Figure 21. In this embodiment, in the multilayer stripline transmission line 4 of the fourth embodiment, vias 19 for interlayer connection are formed, which are connected to the upper and lower signal lines 13 and penetrate the upper and lower first ground layers 11 and second ground layers 15. Pads or lands may be provided on the upper part of the via 19 for connection to semiconductor chips or the like. The via may be formed as a through electrode for connection between multiple chips or components, and bumps may be provided below it for connection to a package substrate or the like.

[0088] By electrically connecting the signal line 13 to external wiring and / or other signal lines, a three-dimensional and more complex fine wiring network can be constructed. Vias are formed through a series of processes, such as photolithography, single or dual damascene, similar to signal lines. From the viewpoint of balancing reliability with miniaturization and multilayering depending on the application, the via diameter is preferably in the range of 5 to 50 μm, and more preferably in the range of 10 to 25 μm. The land diameter is preferably in the range of 10 to 100 μm, and more preferably in the range of 20 to 50 μm.

[0089] The fine wiring network through which signals are transmitted consists of wiring patterns drawn in a planar direction and vias arranged vertically. Focusing on the relationship between the substrate material and the transmission characteristics of the vias, the transmission loss of the vias increases with increasing frequency and with increasing land diameter. This is thought to be because the magnitude of the parasitic reactance component changes with the land diameter, causing a phase shift. Reducing parasitic capacitance is effective in reducing the transmission loss of vias.

[0090] The capacitance C of a parallel plate capacitor is expressed by the following formula. To reduce C, it is considered effective to (a) reduce the relative permittivity of the material, (b) reduce the electrode area, and (c) increase the distance between electrodes. C[F]=ε r ·ε0·S / d ε r : relative permittivity of the material, ε0: permittivity of vacuum (constant), S: electrode area, d: distance between electrodes

[0091] The electrodes for the parasitic capacitance of the via are considered to be via 19 and ground layers 11 and 15. Therefore, for (b), reducing the land diameter B and via diameter D of the via is considered effective, and for (c), increasing the thickness of the insulating layer between the front and back layers where the land is formed and the inner layer where the ground layer is located, and increasing the pore diameter H of the ground layer are considered effective. Thus, it is considered possible to reduce the transmission loss of the via by optimizing the land diameter B and via diameter D of via 19, the pore diameter H of the pores 14 in ground layers 11 and 15, etc.

[0092] Although preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications are possible within the scope of achieving the operation and effects of the present invention. For example, the porous mesh patterns formed on the first and second ground layers may be changed from identical patterns to different patterns. Furthermore, the first and second ground layers and the first and second dielectric layers may be formed to different thicknesses or made of different materials. [Industrial applicability]

[0093] The signal transmission line of the present invention, with its simple configuration of forming multiple holes in the ground layer to create a porous mesh structure, can alleviate stress caused by the difference in linear expansion between the organic dielectric layer and the ground layer, suppress thermal deformation, improve adhesion between the organic dielectric layer and the ground layer, and prevent delamination and cracking at the interface. It offers excellent connectivity, reliability, and durability, and can be manufactured at low cost using existing processes such as physical or chemical vapor deposition, spin coating, dry film deposition, photolithography, and damascene.

[0094] Furthermore, the organic interposer of the present invention has a stacked configuration of the signal transmission lines of the present invention, which offer excellent connectivity and reliability, enabling highly reliable, high-density interconnection between chiplets and dies in 2.5D / 3D mounting of semiconductor packages, etc. Similarly, it can be scaled up to a large area using existing processes and manufactured at low cost.

[0095] The signal transmission line of the present invention is important as a technology to improve interlayer connectivity and reliability in realizing multilayer organic materials. The organic interposer or resin multilayer substrate of the present invention can construct a fine wiring network with excellent connectivity reliability and can be scaled up to a large area. Therefore, it is particularly important in the field of semiconductor devices and their manufacturing that require high-density interconnections, and in the field of portable electronic devices such as smartphones and mobile PCs. [Explanation of Symbols]

[0096] 1...Microstrip line type, 2...Coplanar type, 3...Strip line type, 4A,4B,4C...Multilayer strip line type, 5...Via-connected multilayer strip line type, 10...Substrate, 11,11L,11U...First ground layer, 12...First dielectric layer, 13,13L,13U...Signal lines (signal layer), 14,14L,14U...Holes, 15,15L,15U...Second ground layer, 16...Second dielectric layer, 17...Recess, 18L,18U...Repeating structure, 19...Via, 20...Pattern.

Claims

1. A microstrip line type signal transmission line comprising a first ground layer, a first dielectric layer, and a signal layer on which at least one signal line is formed, wherein these layers are stacked in this order, The first dielectric layer is made of an organic material, In a plan view, the first ground layer has multiple rows of holes arranged in parallel in at least one direction, and the signal line extends in the same direction as the row of holes. In a cross-sectional view perpendicular to the longitudinal centerlines of the signal lines and the row of holes and passing through the center of the holes, the width of the signal lines is formed to be smaller than the width of the holes, and some or all of the signal lines are arranged to be located inside the holes. Microstrip line type signal transmission line.

2. A coplanar signal transmission line comprising a first ground layer, a first dielectric layer, a signal layer on which at least one signal line is formed, and a pair of second ground layers located coplanar with the signal layer and spaced apart on both sides of the signal line, wherein these layers are stacked in this order, The first dielectric layer is made of an organic material, In a plan view, the first ground layer has multiple rows of holes arranged in parallel in at least one direction, and the signal line extends in the same direction as the row of holes. In a cross-sectional view perpendicular to the longitudinal centerlines of the signal lines and the row of holes and passing through the center of the holes, the width of the signal lines is formed to be smaller than the width of the holes, and some or all of the signal lines are arranged to be located inside the holes. Coplanar signal transmission line.

3. A stripline type signal transmission line comprising a first ground layer, a first dielectric layer, a signal layer on which at least one signal line is formed, a second dielectric layer, and a second ground layer, wherein these layers are stacked in this order, The first and second dielectric layers are made of organic material, In a plan view, the first and second ground layers have multiple rows of holes arranged in parallel in at least one direction, and the signal lines extend in the same direction as the rows of holes. In a cross-sectional view perpendicular to the longitudinal centerlines of the signal lines and the row of holes and passing through the center of the holes, the width of the signal lines is formed to be smaller than the width of the holes, and some or all of the signal lines are arranged to be located inside the holes. Stripline type signal transmission line.

4. A multilayer stripline type signal transmission line comprising the signal transmission line described in claim 3 as a repeating structure, wherein a plurality of these repeating structures are stacked, and between two adjacent repeating structures, the second ground layer of one repeating structure constitutes the first ground layer of the other repeating structure.

5. The signal transmission line according to any one of claims 1 to 4, wherein the hole is substantially circular, elliptical, or a polygon with four or more sides.

6. The signal transmission line according to claim 5, wherein the hole is substantially circular with a diameter of 2.5 μm or more, elliptical with an average diameter of 2.5 μm or more between its minor and major axes, or a polygon with four or more sides and a diagonal distance of 3 μm or more.

7. The signal transmission line according to any one of claims 1 to 4, wherein the thickness of the ground layer in which the pore row is formed is 0.5 μm or more.

8. The signal transmission line according to any one of claims 1 to 4, wherein the proportion of the area occupied by the metal material per unit area of ​​the ground layer in which the row of holes is formed is in the range of 35 to 95%.

9. A signal transmission line according to any one of claims 1 to 4, wherein the longitudinal centerlines of some or all of the signal lines are arranged to substantially coincide with the longitudinal centerlines of the hole rows.

10. The signal transmission line according to any one of claims 1 to 4, wherein, in a cross-sectional view along the longitudinal center line of the signal line, a plurality of recesses are formed in the signal line toward a plurality of holes formed in the first ground layer.

11. In a plan view, at least two adjacent rows of holes are formed offset from each other such that the holes in one row of holes are located between the adjacent holes in the other row of holes. In the aforementioned repeating structure, the longitudinal centerlines of some or all of the signal lines are arranged to substantially coincide with the longitudinal centerline of the one row of holes. In the other repeating structure, the longitudinal centerlines of some or all of the signal lines and the longitudinal centerlines of the other row of holes are arranged to coincide substantially. The signal transmission line according to claim 4, wherein, in the cross-sectional view, some or all of the signal lines of one repeating structure and some or all of the signal lines of the other repeating structure are arranged alternately with the second or first ground layer in between.

12. The signal transmission line according to claim 4 or 11, further comprising vias provided through the holes formed in the first and second ground layers for electrically connecting the signal line to external wiring and / or other signal lines.

13. An organic interposer or resin multilayer substrate comprising the signal transmission line according to claim 4 or 11.

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