Wiring board and method for manufacturing a wiring board

Abstract

Improving the manufacturing quality of circuit boards. [Solution] The wiring board of the present disclosure includes a first conductor layer having a predetermined wiring pattern, an insulating layer covering the first conductor layer, a second conductor layer formed on the insulating layer, and a connecting conductor penetrating the insulating layer to connect the first conductor layer and the second conductor layer, wherein the first conductor layer includes a conductor pad in contact with the connecting conductor and a wiring pattern covered by the insulating layer, the surface of the conductor pad is roughened by a first surface roughness, and the surface of the wiring pattern is roughened by a second surface roughness smaller than the first surface roughness and is covered with an organic coating to improve adhesion with the insulating layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a wiring board and a method for manufacturing the wiring board. BACKGROUND ART

[0002] Patent Document 1 discloses a printed wiring board in which a chemical conversion film is formed on the surface of a low-roughened or non-roughened metal wiring layer, and an insulating resin layer is formed on the metal wiring layer via the chemical conversion film. PRIOR ART DOCUMENTS PATENT DOCUMENTS

[0003] PATENT DOCUMENT 1 Japanese Patent Laid-Open No. 2018-172759 SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0004] In the printed wiring board disclosed in Patent Document 1, the adhesion between the metal wiring layer and the insulating resin layer is ensured by an organic film such as a chemical conversion film. However, the organic film may be degraded by heat, and the function of bringing the conductor layer such as the metal wiring layer into close contact with the insulating layer such as the insulating resin layer may be reduced. Therefore, for example, even if a conductor pad connected to a connection conductor such as a via conductor that connects different conductor layers is covered with an organic film, the effect of the organic film may not be sufficiently obtained due to the heat of the laser when forming the conductor pad. As a result, the adhesion between the side surface of the conductor pad and the insulating layer is lowered, and delamination may occur in some cases.

[0005] In order to prevent such delamination between the side surface of the conductor pad and the insulating layer, a method of improving the adhesion with the insulating layer by roughening the surface of the conductor pad to increase the surface roughness has been proposed. However, if the wiring pattern in the same conductor layer is also roughened when the conductor pad is roughened, a problem that the transmission characteristics of high-frequency signals in the wiring pattern are deteriorated may occur. [Means for solving the problem]

[0006] The wiring board of this disclosure comprises a first conductor layer including a predetermined wiring pattern, An insulating layer covering the first conductor layer, A second conductor layer formed on the insulating layer, A connecting conductor that penetrates the insulating layer and connects the first conductor layer and the second conductor layer, A wiring board including, The first conductor layer includes a conductor pad in contact with the connecting conductor and a wiring pattern covered by the insulating layer. The surface of the conductor pad is roughened by a first surface roughness, The surface of the wiring pattern is roughened with a second surface roughness lower than the first surface roughness and is covered with an organic coating to improve adhesion with the insulating layer.

[0007] The method for manufacturing a wiring board according to the present disclosure involves forming a first conductor layer having a conductor pad and a wiring pattern that penetrates an insulating layer and contacts a connecting conductor for connecting different conductor layers, Forming a resist film to cover the aforementioned wiring pattern, The surface of the conductor pad is roughened by roughening the exposed surface of the first conductor layer, Removing the aforementioned resist film, The surface of the wiring pattern is roughened by roughening the exposed surface of the first conductor layer to a second surface roughness smaller than the first surface roughness, This includes covering the surface of the wiring pattern with an organic coating by providing an organic coating on part or all of the exposed surface of the first conductor layer to improve adhesion with the insulating layer.

[0008] According to the technology disclosed herein, it is possible to prevent delamination between the wiring pattern and the conductor pad and the insulating layer while preventing deterioration of the transmission characteristics of high-frequency signals in the wiring pattern. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view of a wiring board according to one embodiment of the present disclosure. [Figure 2] This is a magnified view of region 100 in Figure 1. [Figure 3A] This is a cross-sectional view showing an example of the manufacturing process of a wiring board according to one embodiment of the present disclosure. [Figure 3B] This is a cross-sectional view showing an example of the manufacturing process of a wiring board according to one embodiment of the present disclosure. [Figure 3C] This is a cross-sectional view showing an example of the manufacturing process of a wiring board according to one embodiment of the present disclosure. [Figure 3D] This is a cross-sectional view showing an example of the manufacturing process of a wiring board according to one embodiment of the present disclosure. [Figure 3E] This is a cross-sectional view showing an example of the manufacturing process of a wiring board according to one embodiment of the present disclosure. [Figure 3F] This is a cross-sectional view showing an example of the manufacturing process of a wiring board according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0010] Next, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0011] Figure 1 is a cross-sectional view of a wiring board 10 according to one embodiment of the present disclosure.

[0012] The wiring board 10 of this embodiment includes a core substrate 20 having a first surface (top surface or front side) and a second surface (bottom surface or back side) opposite to the first surface, a build-up portion 21 formed on the first surface side of the core substrate 20, and a build-up portion 22 formed on the second surface side of the core substrate 20.

[0013] Here, the top surface or the surface refers to the upper surface in the drawing among the two surfaces constituting the core substrate 20, and the bottom surface or the back surface refers to the lower surface in the drawing among the two surfaces constituting the core substrate 20. Further, in the following description, the side farther from the core substrate 20 in the thickness direction of the wiring board 10 is referred to as the upper side, the upward direction, or up, and the side closer to the core substrate 20 is referred to as the lower side, the downward direction, or down for description.

[0014] Each of the build-up portions 21 and 22 includes a plurality of laminated interlayer insulating layers 51 to 54, a plurality of conductor layers formed between the plurality of interlayer insulating layers 51 to 54, a plurality of via conductors 60, an interlayer insulating film 41, and a wiring pattern 81. The plurality of via conductors 60 are each formed so as to penetrate through the interlayer insulating layers 51 to 54. The interlayer insulating films 41 are respectively formed on the first surface of the insulating substrate 30 and the second surface opposite to the first surface. Each of the plurality of conductor layers includes a predetermined wiring pattern 58. With such a configuration, in the wiring board 10 of the present embodiment, a certain conductor layer is covered by any one of the interlayer insulating layers 51 to 54, and another conductor layer is formed on this interlayer insulating layer. The via conductor 60 is a connection conductor that penetrates through the interlayer insulating layers 51 to 54 to connect different conductor layers.

[0015] The core substrate 20 includes an insulating substrate 30 and through-hole conductors 36 formed in the insulating substrate 30.

[0016] The through-hole conductor 36 is formed by filling a through-hole formed in the insulating substrate 30 with plating. The through-hole conductor 36 can also be formed by performing an electroless plating treatment and an electrolytic plating treatment on the through-hole formed in the insulating substrate 30.

[0017] The conductor layer covered by the interlayer insulating layer 51 includes a conductor pad 61 in contact with the via conductor 60, and a wiring pattern 81 covered by the interlayer insulating layer 51.

[0018] Next, Figure 2 shows an enlarged view of region 100 in Figure 1.

[0019] Here, the conductor pad 61 shown in Figure 2 is a conductor pad for connecting to multiple via conductors 60 stacked in three or more layers on the upper side, as can be seen by referring to Figure 1.

[0020] As shown in Figure 2, the surface of the conductor pad 61 is roughened to a first surface roughness by, for example, micro-etching. This roughening creates irregularities on the surface of the conductor pad 61, improving adhesion with the interlayer insulating layer 51. The surface of the wiring pattern 81 is then roughened to a second surface roughness, which is lower than the first surface roughness of the conductor pad 61, by, for example, another method such as micro-etching.

[0021] These surface roughnesses can be quantified, for example, as surface roughness as defined in ISO 25178. For example, the arithmetic mean roughness (Ra) can be used as a parameter to indicate surface roughness. For example, the arithmetic mean roughness (Ra) of the surface of the conductor pad 61 with the first surface roughness is 0.3 μm or more and 0.6 μm or less, and the arithmetic mean roughness (Ra) of the surface of the wiring pattern 81 with the second surface roughness is greater than 0.15 μm and 0.22 μm or less.

[0022] As shown in Figure 2, the surface of the wiring pattern 81 is covered with an organic coating 70 to improve adhesion with the interlayer insulating layer 51. The surface of the conductor pad 61 facing the interlayer insulating layer 51 is also covered with the organic coating 70. However, the conductor pad 61 and the via conductor 60 are in direct contact without the organic coating 70 in between.

[0023] The organic coating 70 improves the adhesion between the conductor layer, which includes the wiring pattern 81 and the conductor pad 61, and the interlayer insulating layer 51. The organic coating 70 is formed from a material that can bond with both an organic material, such as a resin constituting the interlayer insulating layer 51, and an inorganic material, such as a metal constituting the conductor layer. The organic coating 70 is formed from a material that includes both reactive groups that can chemically bond with organic materials and reactive groups that can chemically bond with inorganic materials. In the art of this disclosure, the organic coating 70 is particularly formed from an azole compound. Examples of azole compounds include silane coupling agents containing azolesilane compounds such as triazole compounds. The material of the organic coating 70 is not limited to silane coupling agents, as long as it can increase the adhesion strength between the conductor layer and the interlayer insulating layer compared to the case where the interlayer insulating layer is directly formed on the conductor layer. The organic coating 70 allows the conductor layer and the interlayer insulating layer to adhere with greater strength compared to the case where the interlayer insulating layer is directly formed on the conductor layer.

[0024] Furthermore, in the wiring board 10 of this embodiment, the surface roughness (first surface roughness) of the conductor pad 61 is greater than the surface roughness (second surface roughness) of the wiring pattern 81. Therefore, a sufficient anchoring effect is obtained between the conductor pad 61 and the interlayer insulating layer 51. As a result, it is considered that delamination at the interface between the conductor pad 61 and the interlayer insulating layer 51 is unlikely to occur. Moreover, unintended intrusion of liquid into the interface between the conductor pad 61 and the interlayer insulating layer 51 is prevented by the surface irregularities of the conductor pad 61, which has a relatively large first surface roughness. As a result, delamination between the conductor pad 61 and the interlayer insulating layer 51 that could be caused by such liquid intrusion is also suppressed.

[0025] More specifically, in the manufacturing process of the wiring board 10, the inner walls of the through-holes provided in the interlayer insulating layer 51 for the formation of via conductors 60 may be exposed to various processing solutions and plating solutions. These liquids may then penetrate from the inner walls of the through-holes into the interface between the conductor pad 61 and the interlayer insulating layer 51, potentially causing delamination between the conductor pad 61 and the interlayer insulating layer 51. However, in this embodiment, such unintended liquid intrusion that could cause delamination is prevented by the surface irregularities of the conductor pad 61, which have a relatively large surface roughness (first surface roughness).

[0026] Furthermore, when forming through holes in the interlayer insulating layer 51 using a laser to create via conductors 60, the heat from this laser may degrade the function of the organic coating 70 described above. As a result, it may be difficult to ensure sufficient adhesion between the conductor pad 61 and the interlayer insulating layer 51 using the organic coating 70. In particular, the adhesion between the side surface of the conductor pad 61 and the layer 51 may deteriorate, leading to delamination. Even if you try

[0027] Therefore, in the wiring board 10 of this embodiment, the surface roughness (first surface roughness) of the conductor pad 61 is made relatively large to ensure good adhesion between the surface of the conductor pad 61 and the layer 51.

[0028] On the other hand, the surface roughness (second surface roughness) of the wiring pattern 81 is smaller than the surface roughness (first surface roughness) of the conductor pad 61. The reason why the surface roughness (second surface roughness) of the wiring pattern 81 is smaller than that of the conductor pad 61 is explained below.

[0029] In wiring patterns with roughened surfaces, the transmission characteristics of high-frequency signals may deteriorate due to the skin effect, which increases the effective impedance and reduces insertion loss. Furthermore, in fine wiring patterns, such as those with a wiring width of 10 μm or less and a wiring spacing of 10 μm or less, if the surface is roughened to a high degree of surface roughness, the desired shape may not be obtained after roughening relative to the design wiring width and thickness. On the other hand, in conductor pads 61 for connecting to via conductors 60, the problem of deterioration of high-frequency signal transmission characteristics is unlikely to occur. Therefore, as described above, the surface roughness (first surface roughness) of the conductor pad 61 is made relatively large, prioritizing adhesion with the interlayer insulating layer 51.

[0030] Furthermore, if sufficient adhesion between the surface of the wiring pattern 81 and the interlayer insulating layer 51 can be ensured solely by the organic coating 70, it is not necessary to roughen the surface of the wiring pattern 81. However, wiring patterns 81 located near conductor pads 61 may be affected by heat from the laser during the formation of via conductors 60. As mentioned above, if the organic coating 70 deteriorates due to heat from the laser, it may not be possible to ensure sufficient adhesion between it and the interlayer insulating layer 51. Therefore, in the wiring substrate 10 of this embodiment, the surface of the wiring pattern 81 is roughened to a degree that does not affect the transmission characteristics of the high-frequency signals of the wiring pattern 81. As a result, delamination between the wiring pattern 81 and the conductor pads 61 and the interlayer insulating layer 51 is prevented while preventing deterioration of the transmission characteristics of the high-frequency signals in the wiring pattern 81.

[0031] Next, the manufacturing method of the wiring board 10 shown in Figures 1 and 2 will be explained with reference to Figures 3A to 3F.

[0032] First, as shown in Figure 3A, a conductor layer is formed having conductor pads 61 and wiring patterns 81 that contact via conductors, which are connecting conductors that penetrate the insulating layer to connect different conductor layers. Figure 3A shows the state after the conductor pads 61 and wiring patterns 81 have been formed on the conductor layer.

[0033] Next, as shown in Figure 3B, a resist film 90 is formed that has an opening in the area of ​​the conductor pad 61 and covers the wiring pattern 81. The resist film 90 is made of, for example, DFR (dry film resist).

[0034] Next, as shown in Figure 3C, the surface of the conductor pad 61 is roughened to a first surface roughness by, for example, micro-etching, by roughening the exposed surface of the conductor layer. This roughening process is called the normal roughening process, and the surface of the conductor pad 61 is roughened to a relatively large surface roughness. However, in this normal roughening process, the wiring pattern 81 is covered by the resist film 90, so its surface is not roughened.

[0035] Then, after the usual roughening process is performed, the resist film 90 is removed, for example, by using an alkaline solvent, as shown in Figure 3D.

[0036] Next, as shown in Figure 3E, the surface of the wiring pattern 81 is roughened to a second surface roughness, which is lower than the first surface roughness, by roughening the exposed surface of the conductor layer, for example, by another micro-etching process. This roughening process is called a micro-roughening process, and the surface of the wiring pattern 81 is roughened to a surface roughness lower than the surface roughness of the conductor pad 61. In this micro-roughening process, the surface of the conductor pad 61 is also roughened, but since the surface of the conductor pad 61 is already roughened to the first surface roughness, the surface roughness does not change significantly.

[0037] Finally, as shown in Figure 3F, an organic coating 70 is provided on part or all of the exposed surface of the conductor layer to improve adhesion with the interlayer insulating layer 51, thereby covering the surface of the wiring pattern 81 and the surface of the conductor pad 61 with the organic coating.

[0038] Subsequently, an interlayer insulating layer 51 is formed on the conductor layer, and via conductors 60 are formed on the conductor pads 61.

[0039] Furthermore, when the via conductor 60 is formed on the conductor pad 61, the organic coating 70 in contact with the via conductor 60 is removed. While a laser beam can be used to remove the organic coating 70, it may also be removed by, for example, plasma treatment.

[0040] The wiring boards of the technology of this disclosure are not limited to the structures illustrated in the drawings, nor to the structures, shapes, and materials illustrated herein. As stated above, the wiring boards of embodiments of this disclosure may have any lamination structure. For example, the wiring boards of embodiments of this disclosure may include any number of conductor layers and interlayer insulating layers.

[0041] Furthermore, the method for manufacturing the core substrate of the technology of this disclosure is not limited to the method described with reference to the drawings. For example, the interlayer insulating film 41 and interlayer insulating layers 51-54 are not limited to film-like resins, but can be formed using any form of resin. In addition, the method for manufacturing the wiring substrate of the embodiment of this disclosure may include additional steps other than those described above, and some of the described steps may be omitted. [Explanation of Symbols]

[0042] 10 Wiring board 20 core boards 21, 22 Build-up section 30 Insulating substrate 36 Through-hole conductors 41 Interlayer insulating film 51-54 Interlayer insulating layer 58 Wiring Patterns 60 via conductors 61, 62 Conductor pads 70 Organic coating 81 Wiring Patterns 90 Resist film 100 areas

Claims

1. A first conductor layer including a predetermined wiring pattern, An insulating layer covering the above first conductor layer, A second conductor layer formed on the insulating layer, A connecting conductor that penetrates the insulating layer and connects the first conductor layer and the second conductor layer, A wiring board including, The first conductor layer includes a conductor pad in contact with the connecting conductor and a wiring pattern covered by the insulating layer. The surface of the conductor pad is roughened by a first surface roughness, The surface of the wiring pattern is roughened with a second surface roughness lower than the first surface roughness and is covered with an organic coating to improve adhesion with the insulating layer.

2. A wiring board according to claim 1, wherein the arithmetic mean roughness of the surface of the conductor pad in the first surface roughness is 0.3 μm or more and 0.6 μm or less, and the arithmetic mean roughness of the surface of the wiring pattern in the second surface roughness is greater than 0.15 μm and 0.22 μm or less.

3. A wiring board according to claim 1, wherein the conductor pad is a conductor pad for connecting to a plurality of connecting conductors stacked in three or more layers on the upper side.

4. The wiring board according to claim 1, wherein the surface of the conductor pad facing the insulating layer is covered with the organic coating, and the conductor pad and the connecting conductor are in direct contact without the organic coating in between.

5. A first conductor layer is formed having a conductor pad and wiring pattern that contacts a connecting conductor for penetrating the insulating layer and connecting different conductor layers, Forming a resist film to cover the aforementioned wiring pattern, The surface of the conductor pad is roughened by roughening the exposed surface of the first conductor layer, Removing the aforementioned resist film, The surface of the wiring pattern is roughened by roughening the exposed surface of the first conductor layer to a second surface roughness smaller than the first surface roughness, By providing an organic coating on part or all of the exposed surface of the first conductor layer to improve adhesion with the insulating layer, the surface of the wiring pattern is covered with the organic coating. A method for manufacturing a wiring board that includes [the specified component].

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