Semiconductor equipment

Abstract

To provide a semiconductor device that suppresses the degradation of connection reliability. [Solution] The semiconductor device comprises a semiconductor chip, a terminal 50, and a second solder 92. The terminal is aligned with the semiconductor chip in the Z direction. The second solder is interposed between the second main surface of the semiconductor chip and the lower surface 50a of the terminal in the Z direction, connecting the two. The second solder has a joint 92a and a plurality of temporary joints 92b, which have a higher oxygen content than the joint. The joint is located in both the central part 50d on the lower surface and the annular end 50e around it. The temporary joints are located only in the end of the central part and the end. The plurality of temporary joints are aligned in a planar direction perpendicular to the Z direction, with the central part in between.

Description

Technical Field

[0001] The disclosure described in the present specification relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a pre-soldering process for a lead frame. In such process, a solder foil is placed on a die pad of the lead frame, a laser beam is irradiated to a plurality of locations on the peripheral edge of the solder foil, and the solder foil is temporarily fixed and bonded onto the die pad.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of Invention

Problems to be Solved by the Invention

[0004] In the pre-soldering process for a lead frame shown in Patent Document 1, the irradiation positions of the laser beam are not specified. Depending on the irradiation positions, part of the solder foil may be displaced, or uneven distribution of oxidized portions generated in the solder foil by laser irradiation may occur. Therefore, when this solder foil is melted to connect the lead frame and the semiconductor chip, there is a risk that the connection reliability between the two will decrease.

[0005] An object of the present disclosure is to provide a semiconductor device in which a decrease in connection reliability is suppressed.

Means for Solving the Problems

[0006] A semiconductor device according to the disclosed aspect is: a semiconductor chip (10), and a conductor (50) arranged side by side with the semiconductor chip in the stacking direction, The device comprises a solder (92) interposed between the first surface (10b) of the semiconductor chip and the second surface (50a) of the conductor in the stacking direction, connecting the first surface and the second surface, The solder has a joint (92a) and a plurality of temporary joints (92b) that have a higher oxygen content than the joint. The joint is located at both the central part (50d) on the central side of the opposing region between the first and second surfaces in the stacking direction, and at the surrounding annular end (50e). The temporary joint is located only at the end of the central part and the end. Multiple temporary joints are aligned in a planar direction perpendicular to the lamination direction, with a central portion in between.

[0007] According to this, a decrease in connection reliability between the conductor (50) and the semiconductor chip (10) is suppressed.

[0008] The reference numbers in parentheses above merely indicate the correspondence with the configurations described in the embodiments below, and do not limit the technical scope in any way. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view of a semiconductor device. [Figure 2] This is a plan view of a semiconductor chip. [Figure 3] This is a cross-sectional view of the terminal. [Figure 4] This is a floor plan of the terminal. [Figure 5] This graph shows the energy-dispersive X-ray analysis of the central region. [Figure 6] This graph shows the energy-dispersive X-ray analysis of the edges. [Figure 7] This is a floor plan of the terminal. [Figure 8] This is a floor plan of the terminal. [Figure 9] This is a floor plan of the terminal. [Figure 10] This is a floor plan of the terminal. [Figure 11] This is a cross-sectional view of the terminal. [Figure 12] This is a plan view of a terminal. [Figure 13] This is a cross-sectional view showing a connection state between a terminal and a semiconductor chip. [Figure 14] This is a cross-sectional view showing a connection state between a terminal and a semiconductor chip. [Mode for Carrying Out the Invention]

[0010] Embodiments for implementing the present disclosure will be described with reference to the drawings. Portions corresponding to matters described in the previous embodiments may be denoted by the same reference numerals in subsequent embodiments, and redundant descriptions may be omitted. When only a part of the configuration is described in each embodiment, the description of the previous embodiment can be applied to the other parts of the configuration.

[0011] Combinations of portions that are explicitly indicated to be specifically combinable in each embodiment are possible. Unless there is a particular hindrance to the combination, a plurality of embodiments, an embodiment and a modified example, or a plurality of modified examples can also be partially combined even if it is not explicitly indicated that the combination is possible.

[0012] In the following, three directions that are orthogonal to each other are referred to as the X direction, the Y direction, and the Z direction. The X direction, Y direction, and Z direction are linear directions. In the drawings, the description of "direction" is omitted, and they are simply illustrated as X, Y, and Z.

[0013] When the present disclosure is mounted on a vehicle, the X direction extends along the left-right direction of the vehicle. The Y direction extends along the forward-rearward direction of the vehicle. The Z direction extends along the vertical direction of the vehicle. When the vehicle is stopped on a horizontal plane, the plane defined by the X direction and the Y direction extends along the horizontal direction. The Z direction extends along the vertical direction. In the following, the embodiments will be described on the premise that the plane defined by the X direction and the Y direction extends along the horizontal direction, and the Z direction extends along the vertical direction. The Z direction corresponds to the stacking direction. The direction orthogonal to the Z direction corresponds to the planar direction.

[0014] <First Embodiment> <Semiconductor Device> The semiconductor device 100 is a power card applied to power conversion apparatuses such as inverters and converters. The semiconductor device 100 has a flat shape with a small thickness in the Z direction. The semiconductor device 100 includes an active element and a passive element. These active element and passive element generate heat when energized. To suppress temperature rise caused by such heat generation, the semiconductor device 100 is provided in the cooler 200 shown in FIG. 1.

[0015] <Cooler> The cooler 200 internally has a first cooling part 210 and a second cooling part 220 through which a coolant flows. The first cooling part 210 and the second cooling part 220 are arranged spaced apart from each other in the Z direction. The semiconductor device 100 is provided between the first cooling part 210 and the second cooling part 220.

[0016] Heat transfer parts 230 excellent in thermal conductivity and electrical insulation are provided on the inner surfaces of the first cooling part 210 and the second cooling part 220 on the semiconductor device 100 side. The heat transfer parts 230 are in a gel form or a sheet form. The semiconductor device 100 is positioned between the heat transfer part 230 provided on the inner surface of the first cooling part 210 and the heat transfer part 230 provided on the inner surface of the second cooling part 220. These two heat transfer parts 230 are in contact with the semiconductor device 100.

[0017] A spring force that causes the first cooling part 210 and the second cooling part 220 to approach each other in the Z direction is applied to the cooler 200 from a spring body (not illustrated). This spring force increases the contact area between the semiconductor device 100 and the heat transfer parts 230 provided between the first cooling part 210 and the second cooling part 220. The thermal resistance between the semiconductor device 100 and the heat transfer parts 230 is reduced.

[0018] Due to this mechanical configuration, the heat generated in the semiconductor device 100 is actively transferred to the coolant flowing inside the first cooling unit 210 via the heat transfer unit 230 and the first cooling unit 210. The heat generated in the semiconductor device 100 is also actively transferred to the coolant flowing inside the second cooling unit 220 via the heat transfer unit 230 and the second cooling unit 220. In this way, the semiconductor device 100 is cooled on both sides. This suppresses the temperature rise of the semiconductor device 100.

[0019] As shown above, the cooler 200 shown in Figure 1 has a so-called double-sided cooling configuration. However, the configuration of the cooler 200 is not limited to the above example. For example, a single-sided cooling configuration can also be adopted for the cooler 200.

[0020] <Semiconductor device> As shown in Figure 1, the semiconductor device 100 includes a semiconductor chip 10, a terminal 50, a main conductive part 60, a conductive terminal 70, a signal terminal 80, and a sealing resin 90. The terminal 50 corresponds to a conductor.

[0021] The main conductive portion 60, conductive terminals 70, and signal terminals 80 are contained within a lead frame (not shown). The semiconductor chip 10 and terminals 50 are connected to this lead frame. These are then partially covered with a sealing resin 90. A portion of the lead frame exposed outside the sealing resin 90 is selectively removed. This forms the main conductive portion 60, conductive terminals 70, and signal terminals 80. The semiconductor device 100 is manufactured in this manner. Note that a portion of the main conductive portion 60, conductive terminals 70, and signal terminals 80 may be composed of a metal plate separate from the lead frame.

[0022] As shown in Figure 1, the main conductive part 60 has a lower conductive part 61 and an upper conductive part 62. The conductive terminal 70 has a lower conductive terminal 71 and an upper conductive terminal 72. The lower conductive terminal 71 and the lower conductive part 61 are integrally connected. The upper conductive terminal 72 and the upper conductive part 62 are integrally connected.

[0023] The lower conductive portion 61 and the upper conductive portion 62 are separated in a manner that they face each other in the Z direction. The semiconductor chip 10 and the terminal 50 are located between these lower conductive portion 61 and upper conductive portion 62.

[0024] The semiconductor chip 10 has a first main surface 10a and a second main surface 10b aligned in the Z direction. The first main surface 10a side of the semiconductor chip 10 is mechanically and electrically connected to the lower conductive part 61. The second main surface 10b side of the semiconductor chip 10 is mechanically and electrically connected to the upper conductive part 62 via the terminal 50. The first main surface 10a corresponds to the first back surface. The second main surface 10b corresponds to the first surface.

[0025] The tips of the lower conductive terminal 71 and the upper conductive terminal 72 are exposed to the outside of the sealing resin 90. The tips of these lower conductive terminal 71 and upper conductive terminal 72 are connected to conductive busbars that constitute the current path of the power converter. As a result, the current from the power converter flows between the lower conductive terminal 71 and the upper conductive terminal 72 to the semiconductor chip 10, terminal 50, and main conductive part 60.

[0026] The semiconductor chip 10 is connected to a signal terminal 80 via a wire 81. Part of the signal terminal 80 and the wire 81 are covered with a sealing resin 90. The tip of the signal terminal 80 is exposed outside the sealing resin 90. This tip of the signal terminal 80 is connected to a driver board that controls the operation of the power converter.

[0027] The semiconductor device 100 may have more than one semiconductor chip 10. Furthermore, the semiconductor device 100 may have terminals 50, main conductive parts 60, conductive terminals 70, and signal terminals 80 corresponding to multiple semiconductor chips 10. However, the semiconductor device 100 may share some of the terminals 50, main conductive parts 60, conductive terminals 70, and signal terminals 80 corresponding to multiple semiconductor chips 10. The components of the semiconductor device 100 will now be described individually.

[0028] <Semiconductor chips> The semiconductor chip 10 comprises a semiconductor substrate and semiconductor elements formed on the semiconductor substrate. The external shape of the semiconductor chip 10 is generally equivalent to that of the semiconductor substrate.

[0029] The semiconductor substrate is made of semiconductor material such as Si, SiC, or GaN. The semiconductor substrate has a thin, flat shape in the Z direction. The semiconductor substrate has two main surfaces aligned in the Z direction. One of these two main surfaces corresponds to the first main surface 10a described above. The other of the two main surfaces corresponds to the second main surface 10b. A semiconductor element is formed inside the space between the first main surface 10a and the second main surface 10b of this semiconductor substrate.

[0030] The semiconductor element is an RC (Reverse Conducting) IGBT, which constitutes part of the circuit of the power conversion device. The IGBT and freewheeling diode included in the RC-IGBT have a vertical structure in which current flows between the first main surface 10a and the second main surface 10b of the semiconductor substrate.

[0031] A collector electrode 20 is formed on the first main surface 10a, and an emitter electrode 21 is formed on the second main surface 10b. Although not shown in the figure, a gate electrode is also formed on the second main surface 10b. The IGBT and the freewheeling diode are connected in parallel between the collector electrode 20 and the emitter electrode 21.

[0032] In addition to the IGBT and freewheeling diode, the semiconductor substrate also has sensor elements such as a temperature-sensitive diode that detects the temperature of the semiconductor substrate. A MOSFET may be formed on the semiconductor substrate instead of the IGBT.

[0033] As shown in Figure 1, the collector electrode 20 is formed over the entire first main surface 10a. In contrast, as shown in Figures 1 and 2, the emitter electrode 21 is partially formed on the second main surface 10b. The emitter electrode 21 has a smaller area than the collector electrode 20.

[0034] The IGBT and freewheeling diode are formed directly beneath the emitter electrode 21. Therefore, the current-carrying region of the IGBT and freewheeling diode is mainly directly beneath the emitter electrode 21. Due to electrical resistance, current tends to flow more easily towards the center of the emitter electrode 21.

[0035] As shown in Figure 2, in addition to the emitter electrode 21, electrode pads 22 are formed on the second main surface 10b. In this embodiment, electrode pads 22 for the following five purposes are formed on the second main surface 10b. Specifically, electrode pads 22 for the gate electrode of the IGBT, for the Kelvin emitter that detects the potential of the emitter electrode 21, for current sensing, for the anode potential of the temperature-sensitive diode, and for its cathode potential are formed on the second main surface 10b.

[0036] These five electrode pads 22 are spaced apart in the X direction. At the same time, the five electrode pads 22 are spaced apart from the emitter electrode 21 in the Y direction. The terminal 50 described above is electrically connected to the emitter electrode 21 in a manner that it faces the Z direction.

[0037] <Terminal> Terminal 50 electrically and thermally connects the semiconductor chip 10 and the upper conductive part 62. Terminal 50 is made of a metallic material such as Cu or its alloy that has electrical and thermal conductivity. The surface of terminal 50 is nickel-plated.

[0038] Terminal 50 has a roughly rectangular parallelepiped shape. Terminal 50 has a lower surface 50a and an upper surface 50b aligned in the Z direction, and an annular side surface 50c located between them in the Z direction and connecting them. The lower surface 50a and the upper surface 50b are identical in the X direction. The lower surface 50a and the upper surface 50b are identical in the Y direction. The annular side surface 50c extends in the Z direction.

[0039] The terminal 50 is provided between the semiconductor chip 10 and the upper conductive portion 62 in the Z direction. The lower surface 50a of the terminal 50 is positioned opposite the emitter electrode 21 of the semiconductor chip 10 in the Z direction. The upper surface 50b of the terminal 50 is positioned opposite the second connection surface 62a of the upper conductive portion 62 in the Z direction. The lower surface 50a corresponds to the second surface. The upper surface 50b corresponds to the second back surface.

[0040] <Main conductive part> The main conductive part 60 functions to electrically relay the semiconductor chip 10 and the conductive terminal 70. At the same time, the main conductive part 60 also functions to dissipate the heat generated in the semiconductor chip 10. The main conductive part 60 is made of a metallic material such as Cu or its alloy that has electrical conductivity and thermal conductivity.

[0041] As described above, the main conductive part 60 has a lower conductive part 61 and an upper conductive part 62. The lower conductive part 61 has a first connection surface 61a and a first heat dissipation surface 61b aligned in the Z direction. The upper conductive part 62 has a second connection surface 62a and a second heat dissipation surface 62b aligned in the Z direction. The lower conductive part 61 corresponds to the first frame. The upper conductive part 62 corresponds to the second frame.

[0042] As shown in Figure 1, the lower conductive portion 61 and the upper conductive portion 62 are arranged such that the first connection surface 61a and the second connection surface 62a are separated in the Z direction and face each other. A semiconductor chip 10 and a terminal 50 are provided between the lower conductive portion 61 and the upper conductive portion 62. The semiconductor chip 10 is provided on the lower conductive portion 61 side. The terminal 50 is provided on the upper conductive portion 62 side.

[0043] The first connection surface 61a of the lower conductive portion 61 and the collector electrode 20 of the semiconductor chip 10 are spaced apart in the Z direction. A first solder 91 is interposed between them. The lower conductive portion 61 and the collector electrode 20 are mechanically and electrically connected via the first solder 91. The first connection surface 61a corresponds to the third surface.

[0044] The emitter electrode 21 of the semiconductor chip 10 and the lower surface 50a of the terminal 50 are spaced apart in the Z direction. A second solder 92 is interposed between them. The emitter electrode 21 and the terminal 50 are mechanically and electrically connected via the second solder 92. The second solder 92 corresponds to solder.

[0045] The upper surface 50b of terminal 50 and the second connection surface 62a of the upper conductive part 62 are spaced apart in the Z direction. A third solder 93 is interposed between them. Terminal 50 and the upper conductive part 62 are mechanically and electrically connected via the third solder 93. The third solder 93 corresponds to the second solder. The second connection surface 62a corresponds to the fourth surface.

[0046] With the connection configuration described above, the semiconductor elements of the semiconductor chip 10 are electrically connected to the upper conductive part 62 and the lower conductive part 61.

[0047] As shown in Figure 1, the first connection surface 61a side of the lower conductive portion 61 to which the semiconductor chip 10 is connected, and the second connection surface 62a side of the upper conductive portion 62 to which the terminal 50 is connected are covered with sealing resin 90. However, the first heat dissipation surface 61b of the lower conductive portion 61 and the second heat dissipation surface 62b of the upper conductive portion 62 are exposed from the sealing resin 90.

[0048] The heat transfer section 230 comes into contact with the first heat dissipation surface 61b and the second heat dissipation surface 62b exposed from the sealing resin 90. Due to this configuration, Joule heat generated in the semiconductor device 100 due to the energization is actively conducted to the cooler 200 via the heat transfer section 230.

[0049] <Conductive terminals> The conductive terminal 70 functions as a connection terminal to the busbar that constitutes the current path of the power conversion circuit. Current flows through the conductive terminal 70 between the emitter and collector of the IGBT and between the anode and cathode of the freewheeling diode.

[0050] As described above, the conductive terminal 70 has a lower conductive terminal 71 and an upper conductive terminal 72. As shown in Figure 1, the lower conductive terminal 71 is integrally connected to the lower conductive part 61. The upper conductive terminal 72 is integrally connected to the upper conductive part 62. The connection side of these multiple conductive terminals to the conductive part is covered with sealing resin 90. The tip sides of the multiple conductive terminals are exposed from the sealing resin 90. Busbars that constitute the current path of the power conversion device described above are connected to the tip sides of these conductive terminals by laser welding or the like.

[0051] <Signal terminals> The signal terminal 80 functions as a connection terminal to the driver board. As described above, the semiconductor chip 10 has five electrode pads 22 formed on it. The semiconductor device 100 has five signal terminals 80 corresponding to these five electrode pads 22. These five electrode pads 22 and the five signal terminals 80 are electrically connected via wire 81.

[0052] The connection side of the wire 81 at the signal terminal 80 is covered with sealing resin 90. The tip of the signal terminal 80 is exposed from the sealing resin 90. This tip of the signal terminal 80 is connected to the driver board by solder or the like.

[0053] <Sealing resin> The sealing resin 90 is made of, for example, an epoxy resin. The sealing resin 90 is molded, for example, by a transfer molding method. As shown in Figure 1, the sealing resin 90 has one surface 90a and one back surface 90b aligned in the Z direction, and an annular side surface 90c located between them in the Z direction and connecting them.

[0054] The first heat dissipation surface 61b of the lower conductive portion 61 exposed from the sealing resin 90 is flush with one surface 90a of the sealing resin 90. The heat transfer portion 230 on the first cooling portion 210 side is in contact with this first heat dissipation surface 61b and one surface 90a.

[0055] Similarly, the second heat dissipation surface 62b of the upper conductive portion 62 exposed from the sealing resin 90 is flush with the back surface 90b of the sealing resin 90. The heat transfer portion 230 on the second cooling portion 220 side is in contact with this second heat dissipation surface 62b and the back surface 90b.

[0056] Furthermore, the tips of the conductive terminal 70 and the signal terminal 80 are exposed from the side surface 90c of the sealing resin 90. The exposed surfaces of the conductive terminal 70 and the signal terminal 80 on the side surface 90c are separated in the Y direction. The tips of the conductive terminal 70 and the signal terminal 80 extend in the Y direction in such a manner that they are separated from each other from the sealing resin 90. It is also possible to adopt a configuration in which a portion of the exposed surface of the conductive terminal 70 and the exposed surface of the signal terminal 80 on the side surface 90c are the same, and these are aligned in the X direction.

[0057] <Manufacturing method for semiconductor devices> First, a lower lead frame is prepared, including a lower conductive part 61, a lower conductive terminal 71, and a signal terminal 80. The constituent materials for the first solder 91 are applied to this lower lead frame, and the semiconductor chip 10 is placed on top of it. A terminal 50, which has the constituent materials for the second solder 92 and the third solder 93, is also provided on the semiconductor chip 10. This forms the first laminate. This first laminate is transported to a reflow oven. This connects the lower lead frame and the semiconductor chip 10 with the first solder 91. The semiconductor chip 10 and the terminal 50 are connected with the second solder 92. This completes the first reflow process.

[0058] After the first reflow process, the lower lead frame and the semiconductor chip 10 are electrically connected via wire 81. This completes the bonding process.

[0059] After the bonding process, an upper lead frame including the upper conductive part 62 and the upper conductive terminal 72 is prepared. This upper lead frame is placed on the third solder 93 of the terminal 50. This forms the second laminate. This second laminate is transported to a reflow oven. This connects the upper lead frame and the terminal 50 with the third solder 93. This completes the second reflow process.

[0060] After the second reflow process, the soldered lower lead frame, semiconductor chip 10, terminal 50, and upper lead frame are partially covered with sealing resin 90. This completes the molding process.

[0061] After the molding process, the main conductive portion 60, conductive terminals 70, and signal terminals 80 are formed by selectively removing the lower lead frame and a portion of the upper lead frame that are exposed outside the sealing resin 90. The semiconductor device 100 is manufactured through these steps.

[0062] <Solder foil> As described above, in the first reflow process, a terminal 50 containing the constituent materials of the second solder 92 and the third solder 93 is provided on the semiconductor chip 10. The constituent material of the second solder 92 is the first solder foil 101. The constituent material of the third solder 93 is the second solder foil 102.

[0063] As shown in Figure 3, the first solder foil 101 and the second solder foil 102 are in the form of thin sheets. Before performing the first reflow process, the first solder foil 101 is temporarily bonded to the lower surface 50a of the terminal 50 by laser. The second solder foil 102 is simply placed on the upper surface 50b of the terminal 50.

[0064] As shown in Figure 4, the lower surface 50a of terminal 50 is rectangular in shape. Therefore, the lower surface 50a has four corners. The intersection of the diagonals connecting these four corners is the geometric center GC of the lower surface 50a.

[0065] Naturally, the geometric center GC is included in the central part 50d on the middle side of the bottom surface 50a. The four corners are included in the end portions 50e, which are located in a ring around the middle side of the bottom surface 50a. The bottom surface 50a is the current path, but due to the difference in shape, the central part 50d has lower electrical resistance than the end portion 50e. In other words, the end portion 50e has higher electrical resistance than the central part 50d. The first solder foil 101 is temporarily joined to this end portion 50e with higher electrical resistance. In Figures 3 and 4, the boundary between the central part 50d and the end portion 50e is shown by a dashed line.

[0066] The first solder foil 101 is interposed between the second main surface 10b on which the emitter electrode 21 is formed on the semiconductor chip 10 and the lower surface 50a of the terminal 50. The first solder foil 101 is located in the opposing region between the second main surface 10b and the lower surface 50a in the Z direction. The shape of the plane perpendicular to the Z direction in this opposing region is equivalent to that of the lower surface 50a. The central part 50d is included in the central region of this opposing region, and the end part 50e is included in the edge region of the opposing region. In Figure 2, the region included in the central side of the opposing region on the second main surface 10b is shown enclosed by a dashed line.

[0067] Figure 4 shows the state after the first reflow process, where the first solder foil 101 has spread over the lower surface 50a of the terminal 50. It also shows the state where the second solder 92 is connected to the lower surface 50a.

[0068] As shown by the hatching in Figure 4, the area of ​​the second solder 92 that is temporarily joined to the lower surface 50a (temporary joint 92b) is located at two of the four corners. The area of ​​the second solder 92 excluding the temporary joint 92b (joint 92a) is located at the central part 50d and the end part 50e.

[0069] The two temporary joints 92b are located on one of the two diagonals. The two temporary joints 92b are aligned via the central portion 50d. More specifically, the two temporary joints 92b are aligned via the geometric center GC. The central portion 50d and the geometric center GC are located between the two temporary joints 92b. In Figures 2 and 3, the positions of the temporary joints 92b are indicated by etching, and each position is also labeled with a sign.

[0070] <Oxygen content> The first solder foil 101 is placed on the lower surface 50a of the terminal 50, and a laser is shone onto the first solder foil 101 in the Z direction, from the lower surface 50a to the upper surface 50b. This temporarily bonds the first solder foil 101 to the lower surface 50a. This laser irradiation oxidizes the constituent material of the first solder foil 101, and the oxide is scattered into the surroundings. In addition, there is a risk that some of the Ni plating covering the surface of the terminal 50 will peel off and be scattered into the surroundings.

[0071] The effects of the oxide and Ni scattering remain in the second solder 92, which is formed after the first reflow process when the first solder foil 101 is molten. The results are shown in Figures 5 and 6.

[0072] Figures 5 and 6 show the results of energy-dispersive X-ray analysis performed on the second solder 92 of the semiconductor device 100. Figure 5 shows the energy-dispersive X-ray analysis results for the central portion 50d where only the joint 92a is located. Figure 6 shows the energy-dispersive X-ray analysis results for the end portion 50e where both the joint 92a and the temporary joint 92b are located.

[0073] Figures 5 and 6 show multiple peaks indicating the elements contained in the second solder 92. However, Figure 6 shows more peaks than Figure 5. In particular, the peak enclosed by the dashed line in Figure 6 is significantly different from that in Figure 5. This peak indicates oxygen. From these analysis results, it can be seen that the oxygen content per unit volume of the second solder 92 is higher at the edges 50e than at the center 50d.

[0074] <Void> The presence of the aforementioned oxide makes it difficult for the solder to wet and spread. This oxide is concentrated in the temporary joint 92b. As a result, gas tends to remain in the temporary joint 92b instead of solder. In other words, voids tend to be concentrated in the temporary joint 92b.

[0075] Such voids can be observed using ultrasonic testing (SAT). Alternatively, they can be observed by cutting the semiconductor device 100 and observing the cross-section of the second solder 92 with a microscope.

[0076] <Effects and Effects> As explained above, the first solder foil 101 is temporarily joined to the terminal 50. The two temporarily joined regions (temporary joint 92b) are aligned with the central portion 50d in between.

[0077] According to this, misalignment of the first solder foil 101 relative to the terminal 50 and the semiconductor chip 10 during the first reflow process is suppressed. As a result, a decrease in the reliability of the connection between the terminal 50 and the semiconductor chip 10 is suppressed.

[0078] In particular, in this embodiment, the two temporary joints 92b are aligned via a geometric center GC. This effectively suppresses misalignment of the first solder foil 101 relative to the terminals 50 and the semiconductor chip 10 during the first reflow process.

[0079] Furthermore, with the above configuration, the oxide generated during temporary bonding is concentrated in the high-resistance end portion 50e rather than the low-resistance central portion 50d. This suppresses the formation of voids in the second solder 92 in the central portion 50d due to the oxide. This also suppresses an increase in electrical resistance between the terminal 50 and the semiconductor chip 10.

[0080] <Second Embodiment> This embodiment will be described primarily in terms of its differences from the first embodiment. In subsequent embodiments, the differences from the previously described embodiment will also be described primarily in terms of their differences. Configurations, operations, and effects not specifically described in other embodiments are the same as those described in the previously described embodiment.

[0081] In the first embodiment, as shown in Figure 4, an example was shown in which the planar shape of the temporary joint 92b perpendicular to the Z direction is circular. In contrast, in this embodiment, as shown in Figure 7, the planar shape of the temporary joint 92b is elliptical.

[0082] In particular, in this embodiment, the long axes of the two temporary joints 92b are aligned in the X direction, and the short axes of the two temporary joints 92b are aligned in the Y direction. This suppresses misalignment of the first solder foil 101 relative to the terminal 50 and the semiconductor chip 10.

[0083] <Third Embodiment> In the first embodiment, an example was shown in which the temporary joints 92b are provided at two opposing corners of the four corners of the lower surface 50a. In contrast, in this embodiment, as shown in Figure 8, the temporary joints 92b are provided on the central side of two opposing sides of the four sides of the lower surface 50a.

[0084] <Fourth Embodiment> In the first embodiment, an example was shown in which the planar shape of the temporary joint 92b was circular. In contrast, in this embodiment, as shown in Figure 9, the planar shape of the temporary joint 92b is an L-shape extended in the X and Y directions. This suppresses misalignment of the first solder foil 101 with respect to the terminal 50 and the semiconductor chip 10. The planar shape of the temporary joint 92b may also be C-shaped.

[0085] <Fifth Embodiment> In the first embodiment, an example was shown in which the temporary joint portion 92b is provided at a part of the four corners of the lower surface 50a. In contrast, in this embodiment, as shown in Figure 10, the temporary joint portion 92b is provided at all four corners of the lower surface 50a.

[0086] <Sixth Embodiment> In the first embodiment, an example was shown in which the first solder foil 101 was temporarily bonded to the terminal 50 by laser before the first reflow process was performed. In contrast, in this embodiment, as shown in Figure 11, both the first solder foil 101 and the second solder foil 102 are temporarily bonded to the terminal 50 by laser before the first reflow process is performed. In Figure 11, the position of the upper temporary bond portion 93b, which will be described later, is indicated by etching and labeled with a reference numeral.

[0087] The upper surface 50b of terminal 50 is rectangular in shape, similar to the lower surface 50a. The upper surface 50b has an upper central portion 50f on the central side and an upper end portion 50g that is located in an annular shape around it. The second solder foil 102 is temporarily joined to the upper end portion 50g, which has a higher electrical resistance than the upper central portion 50f. In Figures 11 and 12, the boundary between the upper central portion 50f and the upper end portion 50g is shown by a dashed line.

[0088] Figure 12 shows the state after the first reflow process, where the second solder foil 102 has spread over the upper surface 50b of the terminal 50. It also shows the state where the third solder 93 is connected to the upper surface 50b. As shown by the hatching in Figure 12, the area of ​​the third solder 93 that is temporarily joined to the upper surface 50b (upper temporary joint 93b) is located at two of the four corners. The area of ​​the third solder 93 excluding the upper temporary joint 93b (upper joint 93a) is located at the upper central part 50f and the upper end part 50g.

[0089] The two upper temporary joints 93b are located on one of the two diagonals on the upper surface 50b. The two upper temporary joints 93b are aligned via the upper central portion 50f.

[0090] The third solder 93 is interposed between the upper surface 50b of the terminal 50 and the second connection surface 62a of the upper conductive portion 62 during the second reflow process. The third solder 93 is located in the opposing region between the upper surface 50b and the second connection surface 62a in the Z direction. The shape of the plane perpendicular to the Z direction in this opposing region is equivalent to that of the upper surface 50b. The central region of this opposing region includes the upper central portion 50f, and the edge region of this opposing region includes the upper end portion 50g.

[0091] <Seventh Embodiment> In the first embodiment, an example was shown in which the terminal 50 has a rectangular parallelepiped shape. In contrast, in this embodiment, as shown in Figure 13, the terminal 50 has a shape that is convex in the Z direction. The lower surface 50a and the upper surface 50b of the terminal 50 are curved so as to be convex in the Z direction, moving away from each other. The lower surface 50a is curved so as to be convex toward the semiconductor chip 10 in the Z direction.

[0092] According to this, even if the second solder 92 contains gas, the gas will flow more easily in the direction of the white arrow shown in Figure 13. This suppresses the formation of voids in the second solder 92. Note that the lower surface 50a only needs to be curved to be convex, while the upper surface 50b does not need to be curved and can be flat.

[0093] <Eighth Embodiment> In the sixth embodiment, an example was shown in which the terminal 50 has a shape that is convex in the Z direction. In contrast, in this embodiment, as shown in Figure 14, the terminal 50 has a shape that is convex in the Z direction, and the semiconductor chip 10 is curved so as to be concave away from the terminal 50 in the Z direction. The curvature of the lower surface 50a is greater than that of the first main surface 10a and the second main surface 10b.

[0094] According to this, fluctuations in the separation distance between the semiconductor chip 10 and the terminal 50 are suppressed, and even if the second solder 92 contains gas, the gas is more likely to flow in the direction of the white arrow shown in Figure 14.

[0095] <Variation> The disclosure in this specification is not limited to the exemplary embodiments. The disclosure includes the exemplary embodiments and modifications made by those skilled in the art based on those exemplary embodiments. The disclosure is not limited to the combinations of parts and elements shown in the embodiments, but can be implemented in various modifications. The disclosure can be implemented in a variety of combinations. The disclosure may have parts that can be added to the embodiments. The disclosure includes embodiments in which parts and elements have been omitted. The disclosure includes substitutions of parts, substitutions of elements, combinations of parts, or combinations of elements between one embodiment and another. The technical scope of the disclosure is not limited to the descriptions of the embodiments. The technical scope of the disclosure is indicated by the descriptions of the claims. The technical scope of the disclosure should be understood to include the equivalents of the descriptions of the claims and all modifications within the claims. [Explanation of symbols]

[0096] 10...Semiconductor chip, 10a...First main surface, 10b...Second main surface, 50...Terminal, 50a...Bottom surface, 50b...Top surface, 50d...Center part, 50e...End, 50f...Upper center part, 50g...Upper end, 61...Lower conductive part, 61a...First connection surface, 62...Upper conductive part, 62a...Second connection surface, 91...First solder, 92...Second solder, 92a...Joint, 92b...Temporary joint, 93...Third solder, 93a...Upper joint, 93b...Upper temporary joint, 100...Semiconductor device, 101...First solder foil, 102...Second solder foil

Claims

1. A semiconductor chip (10) and The semiconductor chip and the conductor (50) aligned in the stacking direction, The assembly comprises a solder (92) interposed between the first surface (10b) of the semiconductor chip and the second surface (50a) of the conductor in the stacking direction, connecting the first surface and the second surface. The solder has a joint (92a) and a plurality of temporary joints (92b) having a higher oxygen content than the joint. The joint is located at both the central part (50d) on the central side of the region where the first surface and the second surface face each other in the stacking direction, and at the annular end (50e) around it. The temporary joint is located only at the end of the central portion and the end portion. A semiconductor device in which multiple temporary joints are arranged in a planar direction perpendicular to the stacking direction, with the central portion in between.

2. The semiconductor device according to claim 1, wherein the temporary joint portion has a void.

3. The semiconductor device according to claim 2, wherein the temporary joint portion includes the constituent material of the conductor.

4. A first frame (61) aligned with the semiconductor chip in the aforementioned stacking direction, A second frame (62) aligned with the conductor in the stacking direction, A first solder (91) is interposed between the first back surface (10a) on the back side of the first surface of the semiconductor chip and the third surface (61a) of the first frame in the stacking direction, and connects the first back surface and the third surface. A semiconductor device according to any one of claims 1 to 3, further comprising: a second back surface (50b) on the back side of the second surface of the conductor and a second solder (93) interposed between the second back surface and the fourth surface of the second frame in the stacking direction, and connecting the second back surface and the fourth surface.

5. The second solder has an upper joint portion (93a) and an upper temporary joint portion (93b) with a higher oxygen content than the upper joint portion. The upper joint portion is located at both the upper central portion (50f) on the central side of the region where the second back surface and the fourth surface face each other in the stacking direction, and the annular upper end portion (50g) around it. The aforementioned upper temporary joint is located only at the upper end of the upper central part and the upper end. The semiconductor device according to claim 4, wherein the plurality of upper temporary joints are arranged in the planar direction via the upper central portion.

6. The semiconductor device according to claim 1, wherein the second surface is curved such that it is convex toward the semiconductor chip in the stacking direction.

7. The first surface is curved such that it is concave away from the conductor in the stacking direction, The semiconductor device according to claim 6, wherein the second surface has a greater curvature than the first surface.

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