electronic machinery

Abstract

To obtain an electronic device that reduces power consumption when transitioning from normal mode to sleep mode. [Solution] The DC-DC converter 2-i supplies power to the processing unit at an output voltage Vouti corresponding to the power supply mode. The power supply control unit 11 controls the output voltage Vouti of the DC-DC converter 2-i. The power supply control unit 11 performs the following actions: (a) When the power supply mode is normal mode, the output voltage Vouti of the DC-DC converter 2-i is set to a first voltage value Vn; (b) When the power supply mode is changed from normal mode to sleep mode, the output voltage Vouti of the DC-DC converter 2-i is reduced to a second voltage value, and the output voltage Vouti of the DC-DC converter 2-i is set to the second voltage value during a specific first period; (c) When the specific first period ends, the output voltage Vouti of the DC-DC converter 2-i is reduced to a third voltage value.

Description

TECHNICAL FIELD

[0001] The present invention relates to an electronic device. BACKGROUND ART

[0002] A certain power supply device includes a normal power supply unit that supplies power to a load at a predetermined first voltage value, and a sleep power supply unit capable of supplying power to the load at a second voltage value lower than the first voltage value (see, for example, Patent Document 1). PRIOR ART DOCUMENTS PATENT DOCUMENTS

[0003] PATENT DOCUMENT 1 Japanese Unexamined Patent Application Publication No. 2012-139049 SUMMARY OF THE INVENTION PROBLEM TO BE SOLVED BY THE INVENTION

[0004] In some electronic devices, the operating voltage in the sleep mode is set lower than the voltage in the normal mode in order to reduce power consumption. In such an electronic device, when shifting from the normal mode to the sleep mode, a sleep transition process (a process such as data saving) is required. Therefore, after the sleep transition process is completed, the operating voltage is lowered from the voltage value in the normal mode to the voltage value in the sleep mode.

[0005] As described above, since the voltage drop timing at the time of transition to the sleep mode is delayed, power consumption when shifting the power mode from the normal mode to the sleep mode is not suppressed.

[0006] The present invention has been made in view of the above problems, and an object thereof is to obtain an electronic device in which power consumption is suppressed when shifting a power mode from a normal mode to a sleep mode. MEANS FOR SOLVING THE PROBLEM

[0007] The electronic device according to the present invention comprises a processing unit that performs data communication or data processing, a power supply circuit that supplies power to the processing unit at an output voltage corresponding to the power supply mode, and a power supply control unit that controls the output voltage of the power supply circuit. The power supply control unit (a) sets the output voltage of the power supply circuit to a first voltage value when the power supply mode is normal mode, (b) reduces the output voltage of the power supply circuit to a second voltage value when the power supply mode is changed from normal mode to sleep mode, and sets the output voltage of the power supply circuit to the second voltage value during a specific first period, and (c) reduces the output voltage of the power supply circuit to a third voltage value when the specific first period ends. [Effects of the Invention]

[0008] According to the present invention, an electronic device is obtained in which power consumption is suppressed when transitioning from the normal power mode to the sleep mode.

[0009] The above or other objects, features, and advantages of the present invention will become even more apparent from the following detailed description in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a block diagram showing the configuration of an electronic device according to an embodiment of the present invention. [Figure 2] Figure 2 is a diagram illustrating the power supply block of IC chip 1 in Figure 1. [Figure 3] Figure 3 shows the relationship between the power modes and the power on / off states of each power block. [Figure 4] Figure 4 shows an example of the correspondence between the internal register values ​​of the DC-DC converter 2-i and the output voltage Vouti. [Figure 5] Figure 5 is a timing chart illustrating the change in power supply voltage when the power supply mode is changed from normal mode to sleep mode. [Figure 6] Figure 6 is a timing chart illustrating the power supply voltage changes caused by the power saving priority trigger. [Figure 7] Figure 7 is a timing chart illustrating the power supply voltage changes caused by the recovery priority trigger. [Modes for carrying out the invention]

[0011] Embodiments of the present invention will be described below with reference to the figures.

[0012] Figure 1 is a block diagram showing the configuration of an electronic device according to an embodiment of the present invention. The electronic device shown in Figure 1 comprises an IC chip 1 and one or more DC-DC converters 2-1 to 2-N as power supply circuits. Here, the IC chip 1 is an ASIC (Application Specific Integrated Circuit) and is a SoC (System-on-a-Chip). For example, this electronic device is an image forming apparatus such as a multifunction printer equipped with a printing device, an image reading device, an operation panel, a human presence sensor, etc.

[0013] Figure 2 is a diagram illustrating the power supply block of IC chip 1 in Figure 1. For example, as shown in Figure 2, IC chip 1 has multiple power supply blocks configured, and the power on / off and power supply voltage settings can be individually controlled for each power supply block.

[0014] IC chip 1 comprises multiple processing units, each performing specific data communication or data processing, and each processing unit belongs to one of multiple power supply blocks. IC chip 1 includes a power supply control unit 11 as one of the aforementioned processing units. The power supply control unit 11 controls the output voltages Vout1 to VoutN of the DC-DC converters 2-1 to 2-N.

[0015] The scan / print block 21 includes a processing unit for image processing, a processing unit for printing using a printing device (not shown), and a processing unit for scanning using an image reading device (not shown).

[0016] The CPU (large core) block 22 includes a large number of cores (for example, 4) of CPUs (Central Processing Units) (arithmetic processing units), and the CPU (small core) block 23 includes a small number of cores (for example, 1) of a CPU (arithmetic processing unit).

[0017] The memory controller block 24 includes a memory controller (a processing unit for data read / write to and from RAM) for a RAM (not shown) such as DDR (Double Data Rate).

[0018] The always-on block 25 includes the above-described power supply control unit 11 and the like.

[0019] The AI block 26 includes an AI engine, an operation panel (an input device (not shown) that detects user operations and a display device (not shown) that displays various types of information to the user), an SSD (Solid State Drive) module, and the like.

[0020] The debug block 27 includes a processing unit related to debugging (such as a tracer).

[0021] The USB device block 28 includes a communication control processing unit for a USB device, and the USB host block 29 includes a communication control processing unit for a USB host.

[0022] The wired network block 30 includes a communication control processing unit (for example, a MAC layer) for a wired network such as Ethernet (registered trademark).

[0023] Figure 3 shows the relationship between power modes and the power on / off status of each power block. In Figure 3, power mode FP is the mode in which the device operates at full power (i.e., normal mode). Power modes LS2, LS1, and DS are sleep modes, which consume less power than normal mode. Here, LS2, LS1, and DS consume less power in that order. Note that for the USB host block and USB device block, the power on / off status for LS2, LS1, and DS is selected depending on the conditions.

[0024] In this case, when the power mode is changed from normal mode FP to sleep mode, the power mode changes from normal mode FP to sleep mode DS.

[0025] Furthermore, when the power mode returns from sleep mode DS to normal mode FP, the power mode is changed from sleep mode DS to normal mode FP via sleep mode LS1 or LS2, depending on the return trigger. Note that the power mode may also return to sleep mode DS after being changed from sleep mode DS to sleep mode LS1 or LS2.

[0026] The DC-DC converter 2-i (i=1,···,N) is a power supply circuit that supplies power to the processing unit of IC chip 1 with an output voltage corresponding to the power supply mode. Here, the DC-DC converter 2-i is a DC-DC converter that can be digitally controlled via the I2C bus.

[0027] The DC-DC converters 2-1 to 2-N supply power to the aforementioned multiple power supply blocks (specifically, to the processing units belonging to each power supply block). In this case, one DC-DC converter 2-i may supply power to one power supply block, or one DC-DC converter 2-i may supply power to multiple power supply blocks that have the same power on / off pattern for the power supply mode shown in Figure 3.

[0028] The power control unit 11 writes a digital value to the internal register of the DC-DC converter 2-i via the I2C bus, thereby setting the output voltage Vouti corresponding to that digital value to the DC-DC converter 2-i.

[0029] Figure 4 shows an example of the correspondence between the internal register values ​​of the DC-DC converter 2-i and the output voltage Vouti. For example, as shown in Figure 4, the output voltage Vouti is specified by a 7-bit internal register value.

[0030] Figure 5 is a timing chart illustrating the change in power supply voltage when the power supply mode is changed from normal mode to sleep mode. Specifically, as shown in Figure 5, for example, the power supply control unit 11 (a) sets the output voltages Vout1 to VoutN of the DC-DC converters 2-1 to 2-N to the normal voltage Vn (first voltage value, e.g., 0.9V) when the power supply mode is in normal mode, (b) when a sleep transition trigger (such as a predetermined period of inactivity or a predetermined user operation) is detected and the power supply mode is changed from normal mode to sleep mode, it lowers the output voltage Voutj of the DC-DC converter 2-j that supplies power to the power supply block to which the processing unit that remains powered on belongs to the normal lower limit voltage Vnmin (second voltage value, e.g., 0.84V) and sets the output voltage Voutj of the DC-DC converter 2-j to the normal lower limit voltage Vnmin during a specific first period, and (c) when the specific first period ends, it lowers the output voltage Voutj of the DC-DC converter 2-j to the sleep voltage Vs (third voltage value, e.g., 0.8V).

[0031] Here, the above-mentioned normal lower limit voltage Vnmin is the lower limit voltage at which the processing unit can operate in normal mode, and the above-mentioned specific first period is the period during which necessary data processing (such as data saving) is performed when the power supply mode is changed from normal mode to sleep mode. The sleep voltage Vs is a predetermined power supply voltage when power saving operation is performed. The normal lower limit voltage Vnmin and the sleep voltage Vs are predetermined in the specifications of the electronic device.

[0032] Thus, during a specific first period, the processing unit operates at a normal lower limit voltage Vnmin, which is lower than the normal voltage Vn, resulting in lower power consumption of the processing unit.

[0033] Specifically, the power control unit 11 identifies, from among the multiple DC-DC converters 2-1 to 2-N, DC-DC converter 2-i which supplies power to power blocks whose power supply is interrupted when the power mode is changed from normal mode FP to sleep mode DS, and DC-DC converter 2-j which supplies power to power blocks whose power supply is not interrupted when the power mode is changed from normal mode FP to sleep mode DS.

[0034] The power control unit 11 then (a) controls the DC-DC converter 2-i to cut off the power supply from the DC-DC converter 2-i to the power block, and (b) controls the DC-DC converter 2-j to lower the output voltage Voutj of the DC-DC converter 2-j to the normal lower limit voltage (second voltage value), so that the output voltage Voutj of the DC-DC converter 2-j is at the normal lower limit voltage Vnmin (second voltage value) during the specific first period, and when the specific first period ends, it lowers the output voltage Voutj of the DC-DC converter 2-j to the sleep voltage Vs (third voltage value).

[0035] For example, the power control unit 11 includes, for example, a first table showing the correspondence relationships shown in Figure 3, and a second table showing the correspondence between power supply blocks and DC-DC converters 2-k that supply power to those power supply blocks. The power control unit refers to the first table to identify power supply blocks whose power supply is interrupted and power supply blocks whose power supply is not interrupted, and refers to the second table to identify DC-DC converters 2-k that supply power to the identified power supply blocks.

[0036] The power control unit 11 then controls the DC-DC converter 2-j that supplies power to the power block that it has determined will not have its power supply interrupted, reducing the output voltage Voutj of the DC-DC converter 2-j to a second voltage value Vnmin, and during the specified first period, the output voltage Voutj of the DC-DC converter 2-j is set to the second voltage value Vnmin, and when the specified first period ends, the output voltage Voutj of the DC-DC converter 2-j is reduced to a third voltage value Vs.

[0037] Furthermore, when the power supply control unit 11 returns the output voltage Vouti from the third voltage value Vs to the first voltage value Vn according to a predetermined trigger, it raises the output voltage Vouti of the DC-DC converter 2-i from the third voltage value Vs to the second voltage value Vnmin, so that during a specific second period the output voltage Vouti of the DC-DC converter 2-i is set to the second voltage value Vnmin, and (c) when the specific second period ends, it raises the output voltage Vouti of the DC-DC converter 2-i to the first voltage value Vn.

[0038] Figure 6 is a timing chart illustrating the power supply voltage change caused by the power saving priority trigger. Figure 7 is a timing chart illustrating the power supply voltage change caused by the recovery priority trigger.

[0039] Specifically, in this embodiment, the power control unit 11 (a) when a specific trigger is detected, identifies a power block among a plurality of power blocks that corresponds to this trigger and returns the output voltage Vouti from the third voltage value Vs to the first voltage value Vn, and (b) for the identified power block, determines whether to apply the power saving priority mode or the recovery priority mode based on the type of trigger.

[0040] Here, for example, referring to the first table above, the power supply block that is powered on in the power supply mode before and after the power supply mode change corresponding to this trigger (for example, when the power supply mode before the change is sleep mode DS and the power supply mode after the change is normal mode FP) is identified as the power supply block that returns the output voltage Vouti from the third voltage value Vs to the first voltage value Vn.

[0041] Furthermore, if the aforementioned trigger is a recovery-priority trigger that requires user-involved data communication or data processing, the recovery-priority mode will be applied. If the aforementioned trigger is a power-saving-priority trigger that requires user-involved data communication or data processing, the power-saving-priority mode will be applied. Here, recovery-priority triggers include receiving a print job, user detection based on a human presence sensor (not shown), and detection of user operations (such as user operations on the control panel or opening and closing various covers), while power-saving-priority triggers include network packet processing and internal status update processing of the electronic device.

[0042] For example, when a specific trigger (such as the recovery priority trigger mentioned above) is detected, the power mode is first changed from sleep mode DS to sleep mode LS2, and then changed to normal mode FP. Also, when a specific trigger that does not involve user intervention (such as the detection of communication for status confirmation mentioned above) is detected, the power mode is first changed from sleep mode DS to sleep mode LS1, data processing and data communication are performed in sleep mode LS1, and then, depending on the conditions, the power mode is changed to one of sleep mode DS, sleep mode LS2, or normal mode FP.

[0043] Then, the power control unit 11 (a) when applying the power saving priority mode, controls the DC-DC converter 2-m that supplies power to the specified power block to raise the output voltage Voutm of the DC-DC converter 2-m from the third voltage value Vs to the second voltage value Vnmin, so that the output voltage Voutm of the DC-DC converter 2-m is set to the second voltage value Vnmin during the specified second period, and when the specified second period ends, raises the output voltage Voutm of the DC-DC converter 2-m to the first voltage value Vn, and (b) when applying the recovery priority mode, raises the output voltage Voutm to the first voltage value Vn immediately without setting a specified second period. In other words, in recovery priority mode, the output voltage Voutm reaches the first voltage value Vn faster than in power saving priority mode.

[0044] For example, in the case of network packet processing, since it is a temporary low load that does not involve the user, the power saving priority mode is applied, and after the output voltage Vouti is set to the second voltage value Vnmin, data processing and data communication are performed by the small core CPU in sleep mode LS1. In such a case, when the corresponding data processing or data communication is completed when the output voltage Vouti is the second voltage value Vnmin, the power mode returns to sleep mode DS, and the output voltage Vouti returns from the second voltage value Vnmin to the third voltage value Vs, as shown by the dashed line in Figure 6.

[0045] Next, the operation of the above-mentioned electronic device will be explained.

[0046] When the electronic device is started up, the power mode is set to normal mode FP, all processing units in IC chip 1 are powered on, and DC-DC converters 2-1 to 2-N supply power to the processing units at normal voltage (first voltage value Vn).

[0047] Subsequently, when a predetermined period of inactivity is detected or a specific user operation is detected, the power mode is changed to sleep mode DS. The power control unit 11 controls the DC-DC converter 2-i to cut off the power supply to the processing unit that is powered off in sleep mode DS, and controls the DC-DC converter 2-j that supplies power to the power block to which the processing unit that is powered on in sleep mode DS belongs. For example, as shown in Figure 5, the output voltage Voutj of the DC-DC converter 2-j is reduced to the sleep voltage (third voltage value Vs) via the normal lower limit voltage (second voltage value Vnmin) for the specific first period, as described above.

[0048] Subsequently, when a wake-up priority trigger is detected in sleep mode DS, the power mode is changed to normal mode FP via sleep mode LS2, and the power control unit 11 controls the DC-DC converter 2-n to start supplying power to the power block to which the processing unit that has changed from power-off to power-on in accordance with the change in power mode belongs, at the normal voltage Vn. It also controls the DC-DC converter 2-m that supplies power to the power block to which the processing unit that has been powered on before and after this change in power mode belongs, and immediately raises the output voltage Voutm of the DC-DC converter 2-m to the normal voltage (first voltage value Vn) in wake-up priority mode, for example as shown in Figure 7.

[0049] On the other hand, when a power saving priority trigger is detected in sleep mode DS, the power mode is changed to sleep mode LS1, and the power control unit 11 controls the DC-DC converter 2-m that supplies power to the power block to which the processing unit to be powered on after this power mode change belongs, and raises the output voltage Voutm of the DC-DC converter 2-m to the normal voltage (first voltage value Vn) via the normal lower limit voltage (second voltage value Vnmin) of a specific second period in power saving priority mode, for example as shown in Figure 6.

[0050] In this case, as shown in Figure 6, for example, during the specific second period when the output voltage Vouti is the normal lower limit voltage (second voltage value Vnmin) of the specific second period, the low-load recovery process is started in sleep mode LS1. After the specific second period ends and the output voltage Vouti is returned to the normal voltage (first voltage value Vn) (for example in normal mode FP), the high-load recovery process is started.

[0051] As described above, according to the above embodiment, the DC-DC converter 2-i supplies power to the processing unit with an output voltage Vouti corresponding to the power supply mode. The power supply control unit 11 controls the output voltage Vouti of the DC-DC converter 2-i. The power supply control unit 11 (a) sets the output voltage Vouti of the DC-DC converter 2-i to a first voltage value Vn when the power supply mode is normal mode, (b) lowers the output voltage Vouti of the DC-DC converter 2-i to a second voltage value when the power supply mode is changed from normal mode to sleep mode, and sets the output voltage Vouti of the DC-DC converter 2-i to the second voltage value during a specific first period, and (c) lowers the output voltage Vouti of the DC-DC converter 2-i to a third voltage value when the specific first period ends.

[0052] This reduces the power supply voltage when performing data processing necessary for transitioning to sleep mode, thus lowering power consumption during this period. Consequently, power consumption is suppressed when transitioning from normal mode to sleep mode.

[0053] Furthermore, various changes and modifications to the embodiments described above will be obvious to those skilled in the art. Such changes and modifications may be made without deviating from the spirit and scope of the subject matter and without diminishing the intended advantages. In other words, such changes and modifications are intended to be included in the claims. [Industrial applicability]

[0054] The present invention is applicable, for example, to electronic devices. [Explanation of Symbols]

[0055] 2. DC-DC converter (an example of a power supply circuit) 11 Power supply control unit 21. Scan / Print Block (Example of a Power Block) 22 CPU (large core) blocks (example of a power supply block) 23. CPU (small core) block (example of a power supply block) 24. Memory controller block (an example of a power supply block) 25 Always On Block (Example of a Power Block) 26 AI Blocks (Example of a Power Block) 27 Debug Block (Example of a Power Block) 28 USB device blocks (an example of a power block) 29 USB host block (an example of a power block) 30. Wired network block (an example of a power block)

Claims

1. A processing unit that performs data communication or data processing, A power supply circuit that supplies power to the processing unit at an output voltage corresponding to the power supply mode, The system includes a power control unit that controls the output voltage of the power supply circuit, The power supply control unit (a) sets the output voltage of the power supply circuit to a first voltage value when the power supply mode is normal mode, (b) reduces the output voltage of the power supply circuit to a second voltage value when the power supply mode is changed from normal mode to sleep mode, and sets the output voltage of the power supply circuit to the second voltage value during a specific first period, and (c) reduces the output voltage of the power supply circuit to a third voltage value when the specific first period ends. Electronic devices characterized by the following:

2. An IC chip including the aforementioned processing unit and a plurality of processing units that perform data communication or data processing, respectively, The system comprises a plurality of power supply circuits, including the aforementioned power supply circuit. The IC chip comprises multiple power supply blocks, The aforementioned multiple power supply circuits supply power to the aforementioned multiple power supply blocks, Each of the above-mentioned processing units belongs to one of the above-mentioned power supply blocks, The power control unit (a) identifies a power supply circuit among the plurality of power supply circuits that supplies power to a power supply block whose power supply is not interrupted when the power supply mode is changed from normal mode to sleep mode, and (b) controls the identified power supply circuit to reduce the output voltage of the power supply circuit to the second voltage value, so that the output voltage of the power supply circuit is the second voltage value during the specified first period, and when the specified first period ends, reduces the output voltage of the power supply circuit to the third voltage value. The electronic device according to claim 1, characterized by the following:

3. The second voltage value is the lower limit voltage at which the processing unit can operate in the normal mode, The specified first period is the period during which data processing is performed when the power mode is changed from the normal mode to the sleep mode. The electronic device according to claim 1 or claim 2, characterized by the above.

4. The electronic device according to claim 1, characterized in that, when the power supply control unit returns the output voltage from the third voltage value to the first voltage value in accordance with a predetermined trigger, it raises the output voltage of the power supply circuit from the third voltage value to the second voltage value, and during a specific second period the output voltage of the power supply circuit is set to the second voltage value, and (c) when the specific second period ends, it raises the output voltage of the power supply circuit to the first voltage value.

5. An IC chip including the aforementioned processing unit and a plurality of processing units that perform data communication or data processing, respectively, The system comprises a plurality of power supply circuits, including the aforementioned power supply circuit. The IC chip comprises multiple power supply blocks, The aforementioned multiple power supply circuits supply power to the aforementioned multiple power supply blocks, Each of the above-mentioned processing units belongs to one of the above-mentioned power supply blocks, The power control unit (a) when the trigger is detected, identifies a power block among the plurality of power blocks that will return the output voltage from the third voltage value to the first voltage value; (b) for the identified power block, determines whether to apply the power saving priority mode or the recovery priority mode based on the type of trigger; (c1) when the power saving priority mode is applied, controls the power supply circuit that supplies power to the identified power block to raise the output voltage of the power supply circuit from the third voltage value to the second voltage value, so that the output voltage of the power supply circuit is the second voltage value during the identified second period, and when the identified second period ends, raises the output voltage of the power supply circuit to the first voltage value; (c2) when the recovery priority mode is applied, raises the output voltage to the first voltage value immediately without providing the identified second period. The electronic device according to claim 4, characterized by the above.

6. If the trigger is a recovery priority trigger that requires user-involved data communication or data processing, the recovery priority mode is applied. The aforementioned return priority trigger is at least one of the following: receiving a print job, detecting a user based on a human presence sensor, and detecting user operation. If the trigger is a power-saving priority trigger that requires data communication or data processing without user involvement, the power-saving priority mode will be applied. The aforementioned power saving priority trigger is network packet processing or internal status update processing of the electronic device. The electronic device according to claim 4 or claim 5, characterized by the above.

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