Substrate, method for manufacturing a substrate, and method for manufacturing a substrate chip.

Abstract

The present invention provides a substrate capable of alleviating stress concentration, a method for manufacturing the substrate, and a method for manufacturing a substrate chip. [Solution] A substrate having a first region and a second region located outside the first region along the outer edge of the first region, wherein the first region has a plurality of first through holes, and the second region has a plurality of second through holes, the second through holes forming a row aligned from the outer edge of the first region toward the outer edge of the substrate, and the spacing between adjacent second through holes in the row gradually increases toward the outer edge of the substrate.

Description

TECHNICAL FIELD

[0001] The present invention relates to a substrate, a method for manufacturing the substrate, and a method for manufacturing a substrate chip. BACKGROUND ART

[0002] Conventionally, as substrates having through electrodes, organic substrates in which glass cloth is impregnated with resin, and inorganic substrates based on glass or silicon are known. Organic substrates have excellent workability and have been widely used with the development of mounting technology, but there are problems in terms of reduced reliability due to migration of metal wiring, coefficient of thermal expansion, and the like. In contrast, inorganic substrates have advantages such as high dimensional stability, low coefficient of thermal expansion, and high heat resistance, and are regarded as promising in next-generation packaging technologies especially with the development of high-density mounting technology.

[0003] Among inorganic substrates, glass substrates are lower in cost than silicon substrates, and have high electrical insulation and excellent flatness, so their applications are expanding to uses such as interposers and high-frequency substrates. For example, Patent Document 1 discloses a method for manufacturing a glass substrate having through holes for through electrodes. PRIOR ART DOCUMENTS PATENT DOCUMENTS

[0004] PATENT DOCUMENT 1 Japanese Unexamined Patent Publication No. 2018-24571 SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] Electronic component-mounted substrate chips are manufactured by separating them from a substrate where multiple substrate chips are formed together. When manufacturing substrate chips with through-holes from a substrate, the through-holes exist within the chip formation area in the substrate before separation. Furthermore, the area within the chip formation area where electronic components are mounted requires many through-electrodes, resulting in a high density of through-holes. On the other hand, the area outside the chip formation area within the substrate is not part of the substrate chip, so typically, there are no through-holes there, or if there are, they are fewer than in the chip formation area.

[0006] Thus, within the substrate, there are areas where through-holes are densely packed and areas where they are sparsely packed. Due to this distribution of through-hole density, stress tends to concentrate in chip formation areas where through-holes are numerous, especially in areas for mounting electronic components where through-holes are densely concentrated. Stress concentration can lead to defects such as cracks.

[0007] This invention has been made in view of the above-mentioned problems, and aims to provide a substrate that can alleviate stress concentration, a method for manufacturing a substrate, and a method for manufacturing a substrate chip. [Means for solving the problem]

[0008] A first aspect of the present disclosure is a substrate having a first region and a second region located outside the first region along the outer edge of the first region, wherein the first region has a plurality of first through holes, and the second region has a plurality of second through holes, the second through holes forming a row that is aligned from the outer edge of the first region toward the outer edge of the substrate, and the spacing between adjacent second through holes in the row gradually increases toward the outer edge of the substrate.

[0009] A second aspect of this disclosure is the substrate of the first aspect described above, wherein the substrate includes glass.

[0010] A third aspect of the present disclosure is a substrate according to the first or second aspect described above, wherein the substrate has a metal covering or filling the inside of the first through hole and / or the second through hole.

[0011] A fourth aspect of the present disclosure is a substrate according to any of the first to third aspects described above, wherein the substrate has a third region located on the inside of the substrate along the outer edge of the substrate and does not have a through hole.

[0012] A fifth aspect of this disclosure is a substrate according to any of the first to fourth aspects described above, wherein the spacing between adjacent second through holes in the row increases arithmetically toward the outer edge of the substrate.

[0013] A sixth aspect of this disclosure is the substrate of the fifth aspect described above, wherein the increase difference in the spacing is 30 μm or more and 100 μm or less.

[0014] A seventh aspect of the present disclosure is a substrate according to any of the first to fourth aspects described above, wherein the spacing between adjacent second through holes in the row increases proportionally toward the outer edge of the substrate.

[0015] An eighth aspect of this disclosure is the substrate of the seventh aspect described above, wherein the ratio of the increase in the spacing is 1.10 times or more and 1.30 times or less.

[0016] A ninth aspect of this disclosure is a substrate according to any of the first to eighth aspects described above, wherein the number of second through holes per row is 4 or more and 15 or less.

[0017] A tenth aspect of this disclosure is a substrate according to any of the first to ninth aspects described above, wherein the minimum spacing between adjacent second through holes in the row is 160 μm or more and 200 μm or less.

[0018] An eleventh aspect of this disclosure is a substrate according to any of the first to tenth aspects described above, wherein the maximum distance between adjacent second through holes in the row is 400 μm or more and 2000 μm or less.

[0019] A twelfth aspect of this disclosure is a substrate according to any of the first to eleventh aspects described above, wherein the average width of the second region is 3 mm or more and 10 mm or less.

[0020] A thirteenth aspect of the present disclosure is the substrate according to any one of the first to twelfth aspects described above, wherein the minimum interval between the second through-holes is larger than the minimum interval between the first through-holes.

[0021] A fourteenth aspect of the present disclosure is the substrate according to any one of the first to thirteenth aspects described above, wherein the first region includes metal wiring.

[0022] A fifteenth aspect of the present disclosure is the substrate according to any one of the first to fourteenth aspects described above, further comprising a through-electrode penetrating the interior of the first through-hole, wherein the first region includes an electronic component electrically connected to the through-electrode.

[0023] A sixteenth aspect of the present disclosure is a method for manufacturing a substrate, comprising: a step of preparing a substrate plate; and a step of forming through-holes in the substrate plate to obtain a substrate, wherein the substrate has a first region and a second region located outside the first region along an outer edge of the first region, the first region has a plurality of first through-holes, the second region has a plurality of second through-holes, the second through-holes form a row arranged from the outer edge of the first region toward an outer edge of the substrate, and an interval between the adjacent second through-holes in the row gradually increases toward the outer edge of the substrate.

[0024] A seventeenth aspect of the present disclosure is a method for manufacturing a substrate chip, comprising a cutting step of cutting the first region of the substrate according to any one of the first to fifteenth aspects described above to obtain individualized substrate chips. [Effects of the Invention]

[0025] According to the present invention, it is possible to provide a substrate, a method for manufacturing the substrate, and a method for manufacturing a substrate chip that can alleviate stress concentration. [Brief Description of the Drawings]

[0026] [Figure 1] It is a plan view of a substrate according to an embodiment of the present disclosure. [Figure 2] It is an enlarged view of a portion A in Figure 1. [Figure 3]This is a cross-sectional view of part B in Figure 2. [Figure 4] This is a cross-sectional view of part C in Figure 2. [Figure 5] This is a cross-sectional view of portion C in Figure 2 of a substrate comprising an insulating layer, metal wiring, and electronic components. [Figure 6] This is a schematic diagram showing the locations where the circuit board will be cut. [Modes for carrying out the invention]

[0027] An embodiment of this disclosure will be described below with reference to the drawings. Note that, for the sake of illustration and ease of understanding, the scale and aspect ratios of the drawings accompanying this specification may be altered and exaggerated from those of the actual objects. When the same or similar reference numerals are used for identical parts and / or parts having similar functions, the repetition of the designation may be omitted. Furthermore, some components of the embodiment may be omitted from the drawings.

[0028] Terms that refer to the basic material of a particular structure do not need to be distinguished solely by differences in name. For example, terms such as "substrate," "base material," "board," "sheet," or "film" fall under the above description.

[0029] Terms and / or numerical values ​​that refer to shape and / or geometric conditions do not need to be bound by strict meaning and may be interpreted as encompassing a range to which similar functionality can be expected. For example, "parallel" and / or "orthogonal" fall under the above terms. Similarly, "length values" and / or "angle values" fall under the above numerical values.

[0030] When describing one configuration as being "above," "below," "on the upper side," "on the lower side," "above," or "below" another configuration, this may include both configurations where one configuration is directly in contact with the other, and configurations where another configuration is located between the two configurations. Furthermore, the expressions "above," "on the upper side," or "above" are interchangeable with "below," "on the lower side," or "below." In other words, the vertical direction may be reversed.

[0031] One embodiment of this disclosure is described in the following paragraphs. This embodiment is an example of an embodiment of this disclosure. This disclosure shall not be construed as being limited to just one embodiment of this disclosure.

[0032] [substrate] Figure 1 is a plan view of a substrate 10 according to one embodiment of the present disclosure. As shown in Figure 1, the substrate 10 of the present disclosure has a first region 11. The first region 11 is a region on which substrate chips 40 are formed. Typically, multiple substrate chips 40 are formed in the first region 11 (see Figure 6). The number of substrate chips 40 formed in the first region 11 is not particularly limited, but for example, it is between 4 and 100.

[0033] The planar shapes of the substrate 10 and the first region 11 are, for example, rectangles or squares. The side length of the substrate 10 is, for example, 100 mm or more and 1000 mm or less. The planar area of ​​the substrate 10 is, for example, 10000 mm². 2 More than 1000000mm 2 The following applies: The area of ​​the first region 11 is preferably 60% to 98% and 80% to 98% of the area of ​​the substrate 10. In this disclosure, "plan view" means viewing from the normal direction (Z direction) of the plane in which the first region 11 and the second region 12 are located, and includes planar perspective.

[0034] Figure 2 is an enlarged view of part A in Figure 1. As shown in Figure 2, the first region 11 has a plurality of first through-holes 21. Typically, each region that becomes a substrate chip 40 has a plurality of first through-holes 21. Therefore, for example, in the case of a substrate 10 on which 16 substrate chips 40, each having 100,000 first through-holes 21, are formed, one substrate 10 will have 1,600,000 first through-holes 21. Within the first region 11, the first through-holes 21 are typically densely located in and around the region where electronic components 34 are mounted.

[0035] The substrate 10 has a first surface 10a and a second surface 10b located on the opposite side of the first surface 10a. The first through hole 21 may have the same diameter from the first surface 10a to the second surface 10b, or it may have a tapered shape where the diameter on the first surface 10a side is larger than the diameter on the second surface 10b side, or it may have a tapered shape where the diameter on the first surface 10a side is smaller than the diameter on the second surface 10b side. Furthermore, the diameter of the first through hole 21 may decrease as it moves from the first surface 10a toward the central part in the thickness direction, and increase as it moves from the central part toward the second surface 10b in the thickness direction. That is, the diameter of the first through hole 21 may be smallest in the central part.

[0036] As shown in Figure 1, the substrate 10 of this disclosure further has a second region 12 located outside the first region 11 along the outer edge 11e of the first region 11. As shown in Figure 2, the second region 12 has a plurality of second through holes 22. Since the second region 12 is located outside the first region 11 on which the substrate chip 40 is formed, it is a region that does not remain in the substrate chip 40 after it has been pieced. That is, the second through holes 22 in the second region 12 also do not remain in the pieced substrate chip 40.

[0037] As shown in Figure 2, the second through-holes 22 form a row 22a that is arranged from the outer edge 11e of the first region 11 toward the outer edge 10e of the substrate 10. In row 22a, the second through-holes 22 may be arranged in a straight line, a curved line, a folded line, or a staggered pattern. The spacing (pitch) between adjacent second through-holes 22 in row 22a gradually increases toward the outer edge 10e of the substrate 10.

[0038] Figure 3 is a cross-sectional view of part B in Figure 2. For example, in a row 22a consisting of eight second through holes 22, if the spacing between adjacent second through holes 22 is P1, P2, P3..., P7 in order from closest to the first region 11 as shown in Figure 3, then the spacing between the second through holes 22 is P1 <P2<···<P7となる。

[0039] If, outside the first region 11 which has multiple first through-holes 21, there is a region without through-holes and / or a region where the density of through-holes is lower than that of the first region 11, stress tends to concentrate in the first region 11, especially in regions where the first through-holes 21 are densely concentrated, due to the density distribution of the through-holes. In contrast, the substrate 10 of this disclosure has a second region 12 outside the first region 11 as described above. The second region 12 has multiple second through-holes 22. These second through-holes 22 constitute a row 22a that is aligned from the outer edge 11e of the first region 11 toward the outer edge 10e of the substrate 10. The spacing between adjacent second through-holes 22 in the row 22a gradually increases toward the outer edge 10e of the substrate 10. As a result, compared to the conventional substrate 10, the density distribution of the through-holes changes smoothly from the first region 11 toward the outside of the substrate 10. As a result, stress concentration is reduced in the substrate 10 of this disclosure, making it less likely for defects such as cracks to occur.

[0040] The substrate 10 may have through holes outside the first region 11, either on the inside (first region 11 side) or outside (outer edge 10e side) of a row 22a in which the spacing between adjacent second through holes 22 gradually increases toward the outer edge 10e of the substrate 10, where the spacing between adjacent through holes 22 is not arranged in such a way that the spacing between adjacent through holes gradually increases toward the outer edge 10e of the substrate 10. However, it is preferable that the substrate 10 does not have through holes outside the first region 11, either on the inside or outside of a row 22a in which the spacing between adjacent second through holes 22 gradually increases toward the outer edge 10e of the substrate 10.

[0041] When N1 is the total number of through holes located outside the first region 11 in which the spacing between adjacent through holes gradually increases toward the outer edge 10e of the substrate 10 (second through holes 22), and N2 is the total number of through holes in which the spacing between adjacent through holes does not gradually increase toward the outer edge 10e of the substrate 10, the larger the ratio R of the second through holes 22, which can be calculated as R = N1 / (N1+N2)×100, the greater the tendency to alleviate stress concentration. N1+N2 is the total number of through holes located outside the first region 11. Preferably, the ratio R of the second through holes 22 is 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, 95% or more, 98% or more, and 100%.

[0042] The number of rows 22a of the second through-holes 22 is not particularly limited, but it is preferable to have multiple rows. Furthermore, it is preferable that the multiple rows 22a are arranged surrounding the first region 11. This tends to further alleviate stress concentration. When there are multiple rows 22a of the second through-holes 22, it is preferable that the spacing between adjacent second through-holes 22 in all rows 22a gradually increases toward the outer edge 10e of the substrate 10, but there may be rows 22a where the spacing between adjacent through-holes does not gradually increase toward the outer edge 10e of the substrate 10.

[0043] The first region 11 and the second region 12 may be positioned with a gap between them, as shown in Figure 1, or they may be adjacent without a gap. Of these, it is preferable that the first region 11 and the second region 12 be positioned with a gap between them. This makes it easier to perform precise dicing when the substrate chip 40 formed in the first region 11 is diced, as the dicing between the first region 11 and the second region 12 is less likely to be hindered by the second through-hole 22. In particular, if the inside of the second through-hole 22 is coated or filled with metal, it is difficult to dic at the location where the second through-hole 22 exists, so the effect of leaving a gap between the first region 11 and the second region 12 becomes significant. The distance between the first region 11 and the second region 12 is, for example, 100 μm to 3000 μm, 150 μm to 2000 μm, or 200 μm to 1000 μm.

[0044] As shown in Figure 1, the substrate 10 may have a third region 13. The third region 13 is located inside the substrate 10 along the outer edge 10e of the substrate 10 and does not have through holes. The third region 13 functions, for example, as a region to be gripped by a jig to fix the substrate 10 in the manufacturing process of the substrate 10 and the process of separating substrate chips 40 from the substrate 10. Such a third region 13 is also called a keep-out zone (KOZ). The presence of a third region 13 without through holes along the outer edge 10e of the substrate 10 makes it easier for the difference in the density distribution of through holes to become larger throughout the substrate 10, thus making the effect of mitigating stress concentration by this disclosure more effective. The average width of the third region 13 is, for example, 1 mm or more and 20 mm or less, and 3 mm or more and 10 mm or less. "Average width of the third region 13" is the arithmetic mean of the widths of the third region 13. "The width of the third region 13" refers to the dimension of the third region 13 in the direction from the outer edge 11e of the first region 11 toward the outer edge 10e of the substrate 10.

[0045] The method of gradually increasing the spacing between adjacent second through holes 22 is not particularly limited, but for example, it may be increased arithmetically toward the outer edge 10e of the substrate 10, or it may be increased geometrically toward the outer edge 10e of the substrate 10.

[0046] "Arithmetic progression" means increasing at a constant rate. When the spacing of the second through-holes 22 increases arithmetically toward the outer edge 10e of the substrate 10, the "difference in increase" of the spacing becomes constant. For example, when the spacing of the second through-holes 22 increases arithmetically toward the outer edge 10e of the substrate 10, if the difference in increase from P1 to P2 is 50 μm, then the difference in increase from P2 to P3, the difference in increase from P3 to P4, etc., will also be 50 μm.

[0047] On the other hand, "ratio-metric increase" means an increase at a constant ratio. When the spacing of the second through holes 22 increases ratio-metrically toward the outer edge 10e of the substrate 10, the "increase ratio" of the spacing becomes constant. For example, when the spacing of the second through holes 22 increases ratio-metrically toward the outer edge 10e of the substrate 10, if the increase ratio from P1 to P2 is 1.20 times, then the increase ratio from P2 to P3, the increase ratio from P3 to P4, etc., will also be 1.20 times.

[0048] When the spacing between adjacent second through-holes 22 increases arithmetically toward the outer edge 10e of the substrate 10, the difference in the increase in spacing is preferably 30 μm or more, 40 μm or more, and 50 μm or more. Furthermore, the difference in spacing is preferably 150 μm or less, 100 μm or less, and 70 μm or less. When the difference in spacing is within the above range, stress concentration tends to be further reduced. The numerical range for the difference in spacing between adjacent second through-holes 22 may be defined by combining any one of several upper limit candidate values ​​and any one of several lower limit candidate values. Specifically, the difference in spacing between adjacent second through-holes 22 may be, for example, 30 μm or more and 150 μm or less, 40 μm or more and 100 μm or less, and 50 μm or more and 70 μm or less.

[0049] When the spacing between adjacent second through-holes 22 increases proportionally toward the outer edge 10e of the substrate 10, the ratio of increase in spacing is preferably 1.10 times or more, 1.15 times or more, and 1.17 times or more. Alternatively, the ratio of increase in spacing is preferably 1.30 times or less, 1.23 times or less, and 1.20 times or less. When the ratio of increase in spacing is within the above range, stress concentration tends to be further reduced. The numerical range for the ratio of increase in spacing between adjacent second through-holes 22 may be defined by combining any one of a plurality of candidate upper limits and any one of a plurality of candidate lower limits. Specifically, the ratio of increase in spacing between adjacent second through-holes 22 may be, for example, 1.10 times or more and 1.30 times or less, 1.15 times or more and 1.23 times or less, and 1.17 times or more and 1.20 times or less.

[0050] The number of second through-holes 22 per row is preferably 4 or more, 6 or more, or 8 or more. The number of second through-holes 22 per row is preferably 20 or less, 17 or less, or 15 or less. When the number of second through-holes 22 per row is within the above range, stress concentration tends to be further reduced. The numerical range for the number of second through-holes 22 per row may be defined by combining any one of a plurality of upper limit candidate values ​​and any one of a plurality of lower limit candidate values. Specifically, the number of second through-holes 22 per row may be, for example, 4 or more and 20 or less, 6 or more and 17 or less, or 8 or more and 15 or less.

[0051] In row 22a, the minimum spacing between adjacent second through-holes 22 is preferably 140 μm or more, 160 μm or more, and 170 μm or more. This reduces the possibility that the second through-holes 22 may be too densely packed, causing stress to concentrate in the second region 12. Alternatively, the minimum spacing is preferably 220 μm or less, 200 μm or less, and 190 μm or less. This makes it less likely for the difference in density of through-holes between the first region 11 and the second region 12 to become large, and stress concentration tends to be further mitigated. The numerical range for the minimum spacing between adjacent second through-holes 22 in row 22a may be defined by combining any one of several upper limit candidate values ​​and any one of several lower limit candidate values. Specifically, the minimum spacing between adjacent second through-holes 22 in row 22a may be, for example, 140 μm or more and 220 μm or less, 160 μm or more and 200 μm or less, or 170 μm or more and 190 μm or less.

[0052] It is preferable that the minimum spacing of the second through-holes 22 is greater than the minimum spacing of the first through-holes 21. This reduces the possibility that the second through-holes 22 may be too densely packed, which could lead to stress concentration in the second region 12.

[0053] The maximum spacing between adjacent second through-holes 22 in row 22a is preferably 400 μm or more, 500 μm or more, and 600 μm or more. Furthermore, the maximum spacing is preferably 2000 μm or less, 1500 μm or less, and 1000 μm or less. When the maximum spacing between adjacent second through-holes 22 in row 22a is within the above range, stress concentration tends to be further reduced. The numerical range for the maximum spacing between adjacent second through-holes 22 in row 22a may be defined by combining any one of a plurality of upper limit candidate values ​​and any one of a plurality of lower limit candidate values. Specifically, the maximum spacing between adjacent second through-holes 22 in row 22a may be, for example, 400 μm or more and 2000 μm or less, 500 μm or more and 1500 μm or less, and 600 μm or more and 1000 μm or less.

[0054] The average width of the second region 12 is preferably 2 mm or more, 3 mm or more, 4 mm or more, and 5 mm or more. This tends to further alleviate stress concentration. The average width of the second region 12 is preferably 11 mm or less, 10 mm or less, 9 mm or less, and 8 mm or less. This allows the first region 11 and / or the third region 13 to be enlarged. "Average width of the second region 12" is the arithmetic mean of the widths of the second region 12. "Width of the second region 12" is the dimension of the second region 12 in the direction from the outer edge 11e of the first region 11 toward the outer edge 10e of the substrate 10. The width of the second region 12 is approximately equal to the sum of the spacing between adjacent second through holes 22. If the width of the second region 12 is constant, that constant width becomes the average width. The average width of the second region 12 may be defined as a numerical range by combining any one of a plurality of upper limit candidate values ​​and any one of a plurality of lower limit candidate values. Specifically, the average width of the second region 12 may be, for example, 2 mm or more and 11 mm or less, 3 mm or more and 10 mm or less, or 4 mm or more and 9 mm or less.

[0055] The diameters of the first through-hole 21 and the second through-hole 22 are preferably 10 μm or more, 30 μm or more, and 50 μm or more. Also, the diameters of the first through-hole 21 and the second through-hole 22 are preferably 200 μm or less, 160 μm or less, and 100 μm or less. The diameters of the first through-hole 21 and the second through-hole 22 may be the same or different. The diameters of multiple first through-holes 21 may be the same or different. The diameters of multiple second through-holes 22 may be the same or different. The numerical range of the diameters of the first through-hole 21 and the second through-hole 22 may be defined by combining any one of a plurality of upper limit candidate values ​​and any one of a plurality of lower limit candidate values. Specifically, the diameters of the first through-hole 21 and the second through-hole 22 may be, for example, 10 μm or more and 200 μm or less, 30 μm or more and 160 μm or less, or 50 μm or more and 100 μm or less.

[0056] The substrate 10 may have a metal covering or filling the inside of the first through-hole 21 and / or the second through-hole 22. Examples of such embodiments include filled vias and conformal vias.

[0057] A filled via is a through-electrode in which the interior of the first through-hole 21 and the second through-hole 22, as shown in Figures 3-5, is filled with metal. As a result, filled vias tend to have relatively low electrical resistance and higher conductivity.

[0058] On the other hand, in the case of conformal vias, the inside of the first through-hole 21 and / or the second through-hole 22 is coated with metal, and the center does not necessarily have to be filled with metal. Compared to filled vias, conformal vias tend to have a simpler plating process and do not require a filling process, thus reducing manufacturing costs. In addition, in the case of conformal vias, the inside of the coated metal may be, for example, hollow or filled with resin. Furthermore, a cap plating may be formed on top of the filled resin. Filling the hollow with resin prevents processing solutions such as developer and cleaning solutions from entering the hollow during the manufacturing process.

[0059] The metal covering or filling the inside of the first through-hole 21 functions as a through-electrode. That is, the substrate 10 may have a through-electrode that penetrates the inside of the first through-hole 21. The inside of the second through-hole 22 may be covered or filled with metal at the same time as the inside of the first through-hole 21 is covered or filled with metal. Note that both the inside of the first through-hole 21 and the inside of the second through-hole 22 may be covered or filled with metal. Alternatively, the inside of the first through-hole 21 may be covered or filled with metal, while the inside of the second through-hole 22 may not be covered or filled with metal.

[0060] Examples of metals used to coat or fill the interior of the first through-hole 21 and / or the second through-hole 22 include copper (Cu), gold (Au), silver (Ag), platinum (Pt), iron (Fe), tin (Sn), zinc (Zn), nickel (Ni), chromium (Cr), palladium (Pd), ruthenium (Ru), rhodium (Rh), aluminum (Al), tungsten (W), and alloys containing these materials.

[0061] Figure 4 is a cross-sectional view of portion C in Figure 2. As shown in Figures 3 and 4, the substrate 10 may have a core layer 20 having a core substrate 23. In this case, the first through-hole 21 and the second through-hole 22 penetrate the core substrate 23 in the thickness direction (Z direction). The thickness of the core substrate 23 is preferably 300 μm or more, and 400 μm or more. This makes the core substrate 23 less prone to bending, facilitating handling during the manufacturing process, and tends to reduce warping of the substrate 10 due to internal stress in the insulating layer 31. The thickness of the core substrate 23 is preferably 700 μm or less, and 600 μm or less. This shortens the time required to form the through-holes.

[0062] Examples of materials that the core substrate 23 may contain include glass, quartz, sapphire, resin, silicon, and silicon carbide. The core substrate 23 preferably contains glass from the viewpoint of low dielectric loss, excellent high-frequency characteristics, and a low coefficient of thermal expansion. When the core substrate 23 is a glass core containing glass, the through-electrode that penetrates the inside of the first through-hole 21 is also called a through-glass via (TGV).

[0063] Examples of glass used in the core substrate 23 include alkali-free glass. Alkali-free glass is glass that does not contain alkaline components such as sodium or potassium. By using alkali-free glass, corrosion of the terminals of the connected semiconductor chip is prevented in principle. Alkali-free glass may contain boric acid instead of alkaline components, or it may contain alkaline earth metal oxides such as calcium oxide or barium oxide.

[0064] Figure 5 is a cross-sectional view of portion C in Figure 2 of a substrate 10 comprising an insulating layer 31, metal wiring 33, and electronic components 34. As shown in Figure 5, the substrate 10 may have one or more insulating layers 31 laminated on a core layer 20. The insulating layers 31 may be laminated on both sides of the core layer 20. The insulating layers 31 may contain, for example, a resin and further contain inorganic fillers such as glass fibers.

[0065] Examples of materials for the vias 32 and metal wiring 33 include copper (Cu), gold (Au), silver (Ag), platinum (Pt), iron (Fe), tin (Sn), zinc (Zn), nickel (Ni), chromium (Cr), palladium (Pd), ruthenium (Ru), rhodium (Rh), aluminum (Al), tungsten (W), and alloys containing these materials.

[0066] As shown in Figure 5, the first region 11 may include vias 32 and metal wiring 33. The metal wiring 33 may be located on the core layer 20 and / or on the insulating layer 31. On the core layer 20 may be between the core layer 20 and the insulating layer 31. On the insulating layer 31 may be between insulating layers 31. The vias 32 can penetrate the insulating layer 31 in the thickness direction and electrically connect the metal wirings 33 to each other.

[0067] As shown in Figure 5, the first region 11 may include electronic components 34. The electronic components 34 may be electrically connected to through electrodes penetrating the interior of the first through hole 21 via metal wiring 33 by flip-chip bonding, wire bonding, etc. In the case of flip-chip bonding, as shown in Figure 5, the electronic components 34 may be connected to the metal wiring 33 via, for example, solder balls 35. When multiple substrate chips 40 are formed in the first region 11, each region that becomes a substrate chip 40 may include one or more electronic components 34. The electronic components 34 are not particularly limited, but are semiconductor chips such as logic chips and memory chips.

[0068] [Manufacturing method for circuit boards] An example of a method for manufacturing the substrate 10 of this disclosure will be described below. The specific means for carrying out each of the steps shown below are not particularly limited, and known means can be applied, for example. The manufacturing method shown below is illustrative, and other steps not disclosed may be carried out between the disclosed steps, and the order of the steps is not limited to the extent that it does not cause inconsistencies.

[0069] The method for manufacturing the substrate 10 of this disclosure comprises the steps of preparing a substrate board and obtaining the substrate 10 by forming through holes in the substrate board. The substrate board is, for example, a board that will become a core substrate 23. The through holes formed here include the first through hole 21 and the second through hole 22 described above. There are no particular limitations on the method for forming through holes in the substrate board, but examples include laser processing, etching, and a combination of etching and laser processing.

[0070] In laser processing, a laser is irradiated onto a substrate to form through-holes. In this case, a resist layer is not required. Excimer lasers, Nd:YAG lasers, femtosecond lasers, etc., can be used for laser processing. When using an Nd:YAG laser, the fundamental wave with a wavelength of 1064 nm, the second harmonic with a wavelength of 532 nm, the third harmonic with a wavelength of 355 nm, etc., can be used.

[0071] In the etching method, first, a resist layer is provided on at least one of the first surface 10a or the second surface 10b, and an opening is made in the resist layer at a position corresponding to the through-hole to form a resist mask. Next, through-holes are formed in the substrate by processing the core substrate 23 at the openings in the resist layer using a dry etching method such as reactive ion etching (RIE) or deep reactive ion etching (DRIE), or a wet etching method.

[0072] Furthermore, in the combined etching and laser processing method, first, a modified layer is formed in the region of the substrate where through-holes are to be formed by laser irradiation. Subsequently, the substrate is immersed in hydrogen fluoride or the like to etch the modified layer. This allows through-holes to be formed in the substrate. Alternatively, through-holes may be formed in the core substrate 23 by blasting, which involves spraying an abrasive material onto the substrate.

[0073] The through-hole may be formed from one side, or from both the first side 10a and the second side 10b.

[0074] The manufacturing method of the substrate 10 of this disclosure may include a step of coating or filling the inside of the first through-hole 21 and / or the second through-hole 22 with metal. For example, a seed layer (not shown) may be formed on the first surface 10a, the second surface 10b and the inner walls of the through-holes of the substrate 10 by PVD (Physical Vapor Deposition), sol-gel method, electroless plating, etc. The seed layer is a conductive layer that serves as a base for growing through-electrodes by depositing metal ions in the plating solution during the electroplating process in which through-electrodes are formed by the plating treatment. This allows the through-electrodes to adhere firmly to the first surface 10a, the second surface 10b and the inner walls of the through-holes of the substrate 10.

[0075] Next, a resist layer is formed in the portion of the seed layer where through electrodes are not provided. The resist layer may be made of a photosensitive material, such as a dry film resist containing acrylic resin. Then, through electrodes are formed on the seed layer that is not covered by the resist layer using an electroplating method. For example, the substrate 10 is immersed in an electroplating solution containing copper, and an electric current is passed through the seed layer. This allows through electrodes to be deposited on the seed layer.

[0076] Subsequently, the resist layer is removed, and then the portion of the seed layer that was covered by the resist layer—in other words, the portion of the seed layer exposed from the through electrode—is removed, for example, by wet etching. This allows the through electrode to be formed. Alternatively, if a conformal type through electrode is formed, the inside of the through electrode may be filled with resin, and a cap plating may be formed on top of the resin.

[0077] The above describes an example of conformal via formation, but filled vias may be formed instead. For example, filled vias may be formed by plating until the through-holes are filled.

[0078] The manufacturing method of the substrate 10 of this disclosure may include, as necessary, steps such as forming an insulating layer 31, forming metal wiring 33, and mounting electronic components 34.

[0079] [Manufacturing method for substrate chips] The manufacturing method for the substrate chip 40 of this disclosure includes a cutting step of cutting the first region 11 of the substrate 10 described above to obtain individual substrate chips 40. The cutting is so-called dicing, and conventional methods using blades, lasers, etc., can be applied. Figure 6 is a schematic diagram showing the locations where the substrate 10 is cut, and the dashed lines in Figure 6 indicate the dicing streets. In the cutting step, as shown in Figure 6, the first region 11 is cut so that each substrate chip 40 formed in the first region 11 is made into an individual piece. The electronic component 34 may be mounted on the first region 11 after the cutting step. [Examples]

[0080] The present disclosure will be described in more detail below with reference to examples and comparative examples. The present disclosure is not limited in any way by the following examples.

[0081] A substrate was manufactured by forming multiple first through-holes and multiple second through-holes in a substrate board. A glass plate was used as the substrate board. The diameter of the first and second through-holes was 80 μm. There were 13 second through-holes in one row. The spacing of the second through-holes was as shown in Tables 1 to 5 below. The spacing of adjacent second through-holes shown in Tables 1 to 5 below is P1, P2, P3..., P13 in order from closest to the first region. The minimum spacing of the first through-holes was 100 μm. The interiors of the first and second through-holes were filled with metal.

[0082] In Examples 1 to 14, the spacing between adjacent second through-holes in a row was gradually increased arithmetically toward the outer edge of the substrate so that the increase difference was as shown in the table. In Examples 15 to 28, the spacing between adjacent second through-holes in a row was gradually increased proportionally toward the outer edge of the substrate so that the increase ratio was as shown in the table.

[0083] In Examples 1-7 and 15-21, the distance P1 between the second through-hole closest to the first region and the adjacent second through-hole was set to 200 μm. In Examples 8-14 and 22-28, the distance P1 was set to 160 μm.

[0084] In Comparative Example 1, the spacing between adjacent second through-holes in a row was kept constant at 300 μm without increasing. In Comparative Example 2, the spacing between adjacent second through-holes in a row was kept constant at 500 μm without increasing. In Comparative Example 3, the spacing between adjacent second through-holes in a row was kept constant at 700 μm without increasing. In Comparative Example 4, no second through-holes were formed.

[0085] Ten of each type of circuit board were manufactured. Next, the presence or absence of cracks during the manufacturing process was checked. Based on the number of boards with cracks, the resistance to cracking was evaluated according to the following criteria. A: 0 pieces B: 1~2 pieces C: 3~4 pieces D: 5~7 pieces E: 8-10 sheets

[0086] [Table 1]

[0087] [Table 2]

[0088] [Table 3]

[0089] [Table 4]

[0090] [Table 5]

[0091] From the above results, it can be confirmed that the substrate of this disclosure is less prone to cracking. Therefore, it is considered that the substrate of this disclosure can alleviate stress concentration. [Industrial applicability]

[0092] This disclosure has industrial applicability as a substrate capable of alleviating stress concentration, a method for manufacturing the substrate, and a method for manufacturing the substrate chip. [Explanation of symbols]

[0093] 10...Substrate, 10a...First surface, 10b...Second surface, 10e...Outer edge of the substrate, 11...First region, 11e...Outer edge of the first region, 12...Second region, 13...Third region, 20...Core layer, 21...First through hole, 22...Second through hole, 22a...Row of second through holes, 23...Core substrate, 31...Insulating layer, 32...Via, 33...Metal wiring, 34...Electronic component, 35...Solder ball, 40...Substrate chip.

Claims

1. It is a substrate, The first area and, It comprises a second region located outside the first region along the outer edge of the first region, The first region has a plurality of first through holes, The aforementioned second region has a plurality of second through holes, The second through-holes form a row that extends from the outer edge of the first region toward the outer edge of the substrate, In the row, the spacing between adjacent second through holes gradually increases toward the outer edge of the substrate. substrate.

2. The aforementioned substrate includes glass, The substrate according to claim 1.

3. Having a metal that covers or fills the inside of the first through hole and / or the second through hole, The substrate according to claim 1.

4. A third region is located on the inside of the substrate along the outer edge of the substrate and has no through holes, The substrate according to claim 1.

5. In the row, the spacing between adjacent second through holes increases gradually and arithmetically toward the outer edge of the substrate. The substrate according to claim 1.

6. The increase in the aforementioned interval is 30 μm or more and 100 μm or less. The substrate according to claim 5.

7. In the row, the spacing between adjacent second through holes increases proportionally toward the outer edge of the substrate. The substrate according to claim 1.

8. The increase ratio of the aforementioned interval is 1.10 times or more and 1.30 times or less. The substrate according to claim 7.

9. The number of the second through-holes per row is 4 or more and 15 or less. The substrate according to claim 1.

10. In the row, the minimum distance between adjacent second through-holes is 160 μm or more and 200 μm or less. The substrate according to claim 1.

11. In the row, the maximum distance between adjacent second through-holes is 400 μm or more and 2000 μm or less. The substrate according to claim 1.

12. The average width of the second region is 3 mm or more and 10 mm or less. The substrate according to claim 1.

13. The minimum spacing of the second through-hole is greater than the minimum spacing of the first through-hole. The substrate according to claim 1.

14. The first region comprises metal wiring, The substrate according to claim 1.

15. The device includes a through electrode that penetrates the interior of the first through hole, The first region comprises an electronic component electrically connected to the through electrode. The substrate according to claim 1.

16. The process of preparing the circuit board, The process includes forming through holes in the substrate plate to obtain a substrate, The aforementioned substrate, The first area and, It comprises a second region located outside the first region along the outer edge of the first region, The first region has a plurality of first through holes, The aforementioned second region has a plurality of second through holes, The second through-holes form a row that extends from the outer edge of the first region toward the outer edge of the substrate, In the row, the spacing between adjacent second through holes gradually increases toward the outer edge of the substrate. A method for manufacturing a circuit board.

17. The invention comprises a cutting step of cutting the first region of the substrate described in claim 1 to obtain individual substrate chips, A method for manufacturing substrate chips.

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